Nanowire manufacturing method

Abstract

A method for manufacturing nanowires, particularly semiconductor materials such as InAs or InSb, comprises the steps of providing a sacrificial substrate, providing a patterned mask layer thereon, providing a nanowire through an opening in the patterned mask layer, and removing the sacrificial substrate. The material of the sacrificial substrate may be selected to lattice-match with the nanowire material regardless of its electrical properties. A superconducting layer may be formed on the nanowire before removing the sacrificial substrate, and an additional superconducting layer may be formed on the bottom side of the nanowire after removing the sacrificial substrate.

Description

Technology Field

[0001] The present disclosure relates to nanowires, and in particular to an improved method for manufacturing nanowires. Background Technology

[0002] Nanowires represent great potential for applications in quantum computing. Unfortunately, manufacturing high-quality nanowires with precise device geometries is difficult. Conventional processes for manufacturing nanowires involve selective-area-growth (SAG), where nanowires are selectively grown directly onto a substrate through a patterned mask layer. For many nanowire devices to function properly, the nanowires must be made of conductive semiconductor materials such as indium arsenide (InAs), indium antimonide (InSb), or indium arsenide antimonide (InAsSb). The substrate on which the nanowires are grown must be an electrically insulating material at all relevant device operating frequencies, including RF. Examples of substrate materials that meet these criteria include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), silicon (Si), and germanium (Ge). There is often a significant difference between the crystal lattice constants of the substrate and the nanowires. Such crystal lattice mismatches induce crystal defects in nanowires, such as dislocations and stacking faults, during growth. Crystal defects can penetrate the nanowires and consequently reduce the performance of the resulting nanowires.

[0003] In this regard, nanowires with reduced crystal defects and methods for manufacturing the same are required.

[0004] In one embodiment, a method for manufacturing a nanowire comprises the steps of providing a sacrificial substrate, providing a patterned mask layer on the sacrificial substrate, providing a nanowire on the sacrificial substrate through an opening in the patterned mask layer, and removing the sacrificial substrate. Since the sacrificial substrate is used to grow the nanowire and is subsequently removed, the material of the sacrificial substrate can be selected to be lattice-matched with the material of the nanowire regardless of its electrical properties. Thus, high-quality nanowires can be grown and operated without the performance degradation typically experienced when using a lattice-matched substrate.

[0005] In one embodiment, the sacrificial substrate is removed by a mechanical process such as polishing or grinding. In another embodiment, the sacrificial substrate is removed by a selective etching process. In some embodiments, a sacrificial layer may be provided between the sacrificial substrate and the nanowire to facilitate the selective etching process.

[0006] Those skilled in the art will understand the scope of the present disclosure and realize additional embodiments after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. Brief explanation of the drawing

[0007] The accompanying drawings, incorporated into and forming part of this specification, serve to illustrate various aspects of the present disclosure and, together with the description, explain the principles of the present disclosure. FIG. 1 is a flowchart illustrating a method for manufacturing one or more nanowires according to one embodiment of the present disclosure. FIGS. 2a to 2gb are diagrams illustrating the method of FIG. 1 according to one embodiment of the present disclosure. FIG. 3 is a flow diagram illustrating a method for manufacturing one or more nanowires according to one embodiment of the present disclosure. FIGS. 4a to 4hb are diagrams illustrating the method of FIG. 3 according to one embodiment of the present disclosure. Specific details for implementing the invention

[0008] The embodiments described below provide information necessary for those skilled in the art to carry out the embodiments and to describe the best mode of carrying out the embodiments. When reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and recognize the applications of such concepts not specifically addressed herein. Such concepts and applications should be understood as falling within the scope of the present disclosure and the appended claims.

[0009] It will be understood that while terms such as first, second, etc. may be used in this specification to describe various elements, these elements should not be limited by such terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be named a second element, and similarly, a second element may be named a first element. As used in this specification, the term "and / or" includes all combinations of one or more of the related listed items.

[0010] When an element, such as a layer, region, or substrate, is referred to as extending "on" or "on" another element, it may extend directly on or directly above the other element, or an intervening element may exist. In contrast, when an element is referred to as extending "directly on" or "directly on" another element, no intervening element exists. Likewise, when an element, such as a layer, region, or substrate, is referred to as extending "on" or "on" another element, it will be understood that it may extend directly or immediately above the other element or intervening elements, or may exist therein. In contrast, when an element is referred to as extending "directly on" or "immediately above" another element, no intervening element exists. Furthermore, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that it may be directly connected or coupled to the other element, or that an intervening element may exist. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening element exists.

[0011] Relative terms such as "below," "above," "above," "below," "horizontal," or "vertical" may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as illustrated in the drawings. It will be understood that these terms and the terms discussed above are intended to include different orientations of the device in addition to the orientation illustrated in the drawings.

[0012] The terms used in this disclosure are used merely to describe specific embodiments and are not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms “includes,” “including,” “comprises,” and / or “comprising,” when used herein, specify the presence of the mentioned features, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0013] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant technical field, and should be further understood that they should not be interpreted in an idealized or overly formal sense unless explicitly defined in this specification.

[0014] FIG. 1 is a flowchart illustrating a method for manufacturing nanowires according to one embodiment of the present disclosure. FIGS. 2a through 2g illustrate each of the steps in FIG. 1, and FIGS. 1 and FIGS. 2 are discussed together below. First, a sacrificial substrate (10) is provided (Block 100 and FIG. 2a). The sacrificial substrate (10) provides a support for growing high-quality nanowires. Thus, the sacrificial substrate (10) is a material that is lattice-matched with the material of the nanowire to be grown. As defined herein, the lattice-matched material has a difference in lattice constant of less than 2%. As discussed above, a material that provides good lattice matching for growing nanowires is often incompatible with the operation of the nanowire. This is because a material that provides good lattice matching is often not an electrical insulating material. As described below, in a subsequent step, the sacrificial substrate (10) is removed, and accordingly, the electrical properties of the sacrificial substrate are irrelevant. Accordingly, the material of the sacrificial substrate (10) can be selected based solely on mechanical properties, namely, the lattice constant to provide an ideal growth surface for one or more nanowires. Depending on the material of the nanowire grown on the sacrificial substrate (10), the sacrificial substrate may include indium arsenide (InAs), indium antimonide (InSb), or gallium antimonide (GaSb).

[0015] A patterned mask layer (12) is provided on a sacrificial substrate (10) (Block 102 and FIG. 2b). The patterned mask layer (12) may comprise an oxide material such as silicon dioxide or any suitable material for providing a mask layer. Providing the patterned mask layer (12) includes providing a blanket mask layer and patterning the blanket mask layer using a lithography process. One or more openings within the patterned mask layer (12) expose a surface of the sacrificial substrate (10) on which one or more nanowires can be grown.

[0016] Nanowires (14) are provided on a sacrificial substrate (10) through an opening in a patterned mask layer (12) (Block 104 and FIG. 2c). Providing nanowires (14) may involve growing the nanowires (14) using a selective area growth (SAG) process. Although the nanowires (14) are illustrated as an integrated structure, the nanowires (14) may comprise any number of nanowire layers that can be grown together or separately and may contain the same or different materials. The nanowires (14) may comprise, for example, indium arsenide (InAs), indium antimonide (InSb), and indium arsenide antimonide (InAsSb). The nanowires may have a thickness of 5 nm to 300 nm. Additionally, the nanowires (14) may have a diameter of about nanometers (10⁻⁹ m) or a length-to-width ratio greater than 1000. Since the material of the sacrificial substrate (10) is selected to be lattice-matched with the material of the nanowire (14), the quality of the nanowire (14) obtained can be very high. That is, even if the nanowire (14) has defects such as dislocations and stacking faults, the nanowire (14) has very few defects, so the performance of the nanowire (14) can be improved.

[0017] A superconducting layer (16) is provided on a nanowire (14) (Block 106 and FIG. 2d). A superconducting layer (16) may also be provided on a portion of a patterned mask layer (12). The superconducting layer (16) may be provided by any suitable film deposition process. The superconducting layer (16) may comprise one of aluminum, lead, niobium, indium, tin, and vanadium. The thickness of the superconducting layer (16) may be 3 nm to 30 nm.

[0018] A support structure (18) is provided on the superconducting layer (16) and the nanowire (14) (Block 108 and FIG. 2e). The support structure (18) may comprise a dielectric material such as silicon nitride (SiN) or silicon dioxide (SiC), or may comprise an organic polymer film. As described below, the support structure (18) is provided to provide mechanical support to the nanowire (14) so ​​that the sacrificial substrate (10) can be removed. The support structure (18) may be provided by any suitable film deposition process for the dielectric, including both an in-situ process and an ex-situ process.

[0019] The sacrificial substrate (10) is removed (Block 110 and FIG. 2f). The sacrificial substrate (10) can be removed by any suitable process, such as a mechanical process (e.g., polishing / grinding) or a chemical process (e.g., selective etching). Although not shown in FIG. 2f, the patterned mask layer (12) may also be removed. As discussed above, since the material of the sacrificial substrate (10) is selected to be lattice-matched with the material of the nanowire (14), the sacrificial substrate (10) provides an ideal growth substrate for the nanowire (14). However, the sacrificial substrate (10) does not have the desired electrical properties for the operation of the nanowire (14). By providing the sacrificial substrate (10) as a growth substrate and removing it later, high-quality nanowires (14) can be grown without interfering with the subsequent operation of the nanowire (14). Additionally, in some cases, the sacrificial substrate (10) can be reused, which can reduce waste and manufacturing costs.

[0020] Optionally, a back layer (20) may be provided on the nanowire (14) (Block 112 and FIGS. 2ga and 2gb). In some embodiments, the back layer (20) is an additional superconducting layer or a single capping layer, as shown in FIGS. 2ga. In other embodiments, the back layer (20) is a gate structure comprising a gate contact (24) on a dielectric layer (22) and the dielectric layer (22), as shown in FIGS. 2b. In particular, the back layer (20) may include any number of additional layers configured to perform any desired function without departing from the principles of the present disclosure. In Block 108, the superconducting layer (16) is provided on the upper surface of the nanowire (14), but the back layer (20) may be provided on the back surface of the nanowire (14) exposed after the sacrificial substrate (10) is removed. Accordingly, the nanowire (14) can be effectively sandwiched between the superconducting layer (16) and the back layer (20). The back layer (20) may allow for the creation of additional electrostatic gates that enable further control over the position of the electron wave function and / or the electron density within the nanowire (14). Accordingly, the performance of the nanowire (14) can be improved.

[0021] FIG. 3 is a flowchart illustrating a method for manufacturing nanowires according to additional embodiments of the present disclosure. FIGS. 4a through 4h illustrate each of the steps in FIG. 3, and FIGS. 3 and FIGS. 4 are discussed together below. The method discussed in relation to FIG. 3 is largely the same as that discussed in FIG. 1 and begins by providing a sacrificial substrate (10) (Block 200 and FIG. 4a). The sacrificial substrate (10) provides a support for growing high-quality nanowires. Thus, the sacrificial substrate (10) is a material that is lattice-matched with the material of the nanowire to be grown. Depending on the material of the nanowire grown on the sacrificial substrate (10), the sacrificial substrate may comprise indium arsenide (InAs), indium antimonide (InSb), indium phosphide (InP), or gallium antimonide (GaSb). In some embodiments, the sacrificial substrate (10) may comprise multiple layers, such as a graded buffer layer.

[0022] A sacrificial layer (22) is provided on a sacrificial substrate (10) (Block 202 and FIG. 4b). The sacrificial layer (22) provides a barrier between the sacrificial substrate (10) and the nanowire to be grown thereon. The material of the sacrificial layer (22) is selected to be selectively etchable with respect to the material of the nanowire (14) so ​​that the sacrificial substrate (10) can be easily removed in a subsequent etching process described below. In many embodiments, the sacrificial layer (22) may comprise aluminum antimonide (AlSb), aluminum arsenide (AlAs), and aluminum gallium arsenide (AlGaSb), including an aluminum arsenide etch stop layer. The sacrificial layer (22) may also provide lattice matching with the material of the nanowire.

[0023] A patterned mask layer (12) is provided on a sacrificial layer (22) (Block 204 and FIG. 4c). The patterned mask layer (12) may comprise an oxide material such as silicon dioxide or any suitable material for providing a mask layer. Providing the patterned mask layer (12) includes providing a blanket mask layer and patterning the blanket mask layer using a lithography process. One or more openings within the patterned mask layer (12) expose the surface of the sacrificial substrate (10) on which one or more nanowires can be grown. Although the sacrificial layer (22) is illustrated as a blanket layer on the sacrificial substrate so that the patterned mask layer (12) is provided on the sacrificial layer (22), in some embodiments, only the sacrificial layer (22) may be provided within the openings of the patterned mask layer (12) so that the patterned mask layer (12) is provided on the sacrificial substrate (10) prior to the sacrificial layer (22).

[0024] Nanowires (14) are provided on a sacrificial layer (22) through an opening in a patterned mask layer (12) (Block 206 and FIG. 4d). Providing nanowires (14) may involve growing the nanowires (14) using a selective area growth (SAG) process. Although the nanowires (14) are illustrated as an integrated structure, the nanowires (14) may comprise any number of nanowire layers that can be grown together or separately and may contain the same or different materials. The nanowires (14) may comprise, for example, indium arsenide (InAs), indium antimonide (InSb), and indium arsenide antimonide (InAsSb). The nanowires may have a thickness of 5 nm to 300 nm. Additionally, the nanowires (14) may have a diameter of about nanometers (10⁻⁹ m) or a length-to-width ratio greater than 1000. Since the materials of the sacrificial substrate (10) and the sacrificial layer (22) are selected to be lattice-matched with the material of the nanowire (14), the quality of the nanowire (14) obtained can be very high. In other words, the nanowire (14) has very few defects such as dislocations and stacking faults, so the performance of the nanowire (14) can be improved.

[0025] A superconducting layer (16) is provided on a nanowire (14) (Block 208 and FIG. 4e). A superconducting layer (16) may also be provided on a portion of a patterned mask layer (12). The superconducting layer (16) may be provided by any suitable film-forming process. The superconducting layer (16) may comprise one of aluminum, lead, niobium, indium, tin, and vanadium. The thickness of the superconducting layer (16) may be 3 nm to 30 nm.

[0026] A support structure (18) is provided on the superconducting layer (16) and the nanowire (14) (Block 210 and FIG. 4f). The support structure (18) may comprise a dielectric material such as silicon nitride (SiN) or silicon dioxide (SiC), or an organic polymer film. As described below, the support structure (18) is provided to provide mechanical support to the nanowire (14) so ​​that the sacrificial substrate (10) can be removed. The support structure (18) may be provided by any suitable film deposition process for the dielectric, including both an in-situ process and an ex-situ process.

[0027] The sacrificial substrate (10) and the sacrificial layer (22) are removed (Block 212 and FIG. 4g). Although not shown in FIG. 4g, the patterned mask layer (12) may also be removed. As discussed above, removing the sacrificial substrate (10) may include selectively etching the sacrificial layer (22), and the material of the sacrificial layer (22) is selected to be selectively etched with respect to the material of the nanowire (14). By providing the sacrificial substrate (10) as a growth substrate and later removing it, high-quality nanowires (14) can be grown without interfering with the subsequent operation of the nanowire (14).

[0028] Optionally, a back layer (20) may be provided on the nanowire (14) (Block 214 and FIG. 4ha and FIG. 4hb). As discussed above, the back layer (20) may include a single capping layer or additional superconducting layer as shown in FIG. 4ga or a gate control structure including a dielectric layer (22) and a gate contact (24) on the dielectric layer (22) as shown in FIG. 4gb. In particular, the back layer (20) may include any number of additional layers configured to perform any desired function without departing from the principles of the present disclosure. In particular, while the superconducting layer (16) is provided on the upper surface of the nanowire (14) in Block 210, the back layer (20) may be provided on the back surface of the nanowire (14) exposed after the sacrificial substrate (10) is removed. Accordingly, the nanowire (14) can be effectively sandwiched between the superconducting layer (16) and the back layer (20). The back layer (20) may allow for the creation of additional electrostatic gates that enable further control over the position of the electron wave function and / or the electron density within the nanowire (14). Thus, the performance of the nanowire (14) can be improved.

[0029] In particular, the process discussed above is merely an example. Generally, the present disclosure considers growing one or more nanowires on a lattice-matched sacrificial substrate and then subsequently removing the sacrificial substrate so as not to interfere with the operation of the one or more nanowires. Those skilled in the art will understand that any suitable process for achieving this purpose is considered herein.

[0030] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

Claim 1 A method for manufacturing a nanowire, comprising the steps of: providing a sacrificial substrate; providing a patterned mask layer on the sacrificial substrate; providing the nanowire on the sacrificial substrate through an opening in the patterned mask layer; providing a superconducting layer on the upper side of the nanowire; providing a support structure on the nanowire, the superconducting layer, and the patterned mask layer; removing the sacrificial substrate after providing the support structure; and providing an additional superconducting layer on the bottom side of the nanowire after removing the sacrificial substrate. Claim 2 A method according to claim 1, wherein the step of providing the nanowire on the sacrificial substrate comprises the step of growing one or more nanowire layers through a selective area growth process. Claim 3 A method according to claim 2, wherein the one or more nanowire layers comprise one or more of indium arsenide, indium antimonide, and indium arsenide antimonide. Claim 4 A method according to paragraph 3, wherein the sacrificial substrate is lattice-matched with the one or more nanowire layers. Claim 5 A method according to paragraph 3, wherein the sacrificial substrate comprises one of indium arsenide, gallium arsenide, and indium antimonide. Claim 6 A method according to claim 1, wherein the sacrificial substrate is mechanically removed. Claim 7 A method according to claim 1, wherein the step of providing the support structure comprises the step of providing a dielectric layer on the nanowire and the patterned mask layer. Claim 8 delete Claim 9 A method according to claim 1, wherein the superconducting layer and the additional superconducting layer comprise one or more of aluminum, lead, niobium, indium, tin, and vanadium. Claim 10 A method according to claim 1, further comprising the step of providing a sacrificial layer between the nanowire and the sacrificial substrate. Claim 11 A method according to claim 10, wherein the sacrificial layer is a blanket layer on the sacrificial substrate. Claim 12 A method according to claim 10, wherein the step of removing the sacrificial substrate includes the step of selectively etching the sacrificial layer. Claim 13 A method according to claim 12, wherein the sacrificial layer comprises one of aluminum antimonide, aluminum arsenide, and aluminum gallium arsenide. Claim 14 A method according to claim 12, wherein the step of providing nanowires on the sacrificial layer comprises the step of growing one or more nanowire layers through a selective region growth process. Claim 15 A method according to claim 14, wherein the one or more nanowire layers comprise one or more of indium arsenide, indium antimonide, and indium arsenide antimonide. Claim 16 In claim 15, the method wherein the sacrificial substrate is lattice-matched with the one or more nanowire layers. Claim 17 A method according to claim 15, wherein the sacrificial substrate comprises one of indium arsenide, indium antimonide, and gallium antimonide. Claim 18 delete Claim 19 A method according to claim 12, wherein the superconducting layer and the additional superconducting layer comprise one or more of aluminum, lead, niobium, indium, tin, and vanadium.

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