Low roughness EUV lithography

Abstract

Methods and related apparatus for smoothing the edges of patterned features using EUV (extreme ultraviolet) lithography are provided herein. In some embodiments, at least one cycle is performed to smooth the feature by depositing a passivation layer that preferentially accumulates in the gaps of the feature with the protrusions left exposed, and then etching the feature to remove the exposed protrusions. The passivation material may preferentially accumulate in the gaps due to a ratio of surface to volume higher in the gaps than in the protrusions. In some embodiments, the local critical dimension uniformity (LCU) is reduced, and the roughness measurement in the contact holes is reduced. In some embodiments, at least one cycle is performed to deposit a thin layer in a plurality of holes having different CDs formed in the photoresist, the thin layer is preferentially deposited in the larger CD holes, and the thin layer is removed anisotropically to remove the thin layer from the bottom ends of the holes.

Description

Background Technology

[0001] Patterning methods are extremely important in semiconductor processing. In particular, extreme ultraviolet (EUV) lithography has been explored to expand lithography technology beyond its optical limits and to replace current photolithography methods for patterning small critical dimension (CD) features. Current EUV lithography methods produce weak patterns and poor edge roughness that can eventually render the substrate unusable.

[0002] Aspects of the present disclosure relate to methods and related apparatus for smoothing the edges of patterned features using EUV lithography. In some embodiments, at least one cycle is performed to smooth the feature by depositing a passivation layer that preferentially accumulates within the gaps of the feature with the protrusions exposed, and then etching the feature to remove the exposed protrusions. The passivation material may preferentially accumulate within the gaps due to a higher ratio of surface area to volume within the gaps than within the protrusions. In some embodiments, the local critical dimension uniformity (LCU) is reduced, and the roughness measurement within the contact holes is reduced. In some embodiments, a thin layer is deposited within a plurality of holes having different CDs formed in the photoresist, the thin layer is preferentially deposited within the larger CD holes, and at least one cycle is performed to anisotropically remove the thin layer to remove the thin layer from the bottom ends of the holes.

[0003] In some embodiments, the method comprises the step of receiving a substrate having a plurality of holes including sidewalls and bottom portions patterned within one or more layers on the substrate, wherein the holes are patterned with a nominal CD (critical dimension) and have a first LCDU (local critical dimension uniformity) (3 sigma); and the step of performing a multi-cycle deposition-etching operation within one or more layers, wherein each cycle includes (a) an operation of depositing a first material in the holes and (b) an operation of removing the first material from the bottom portions of the holes, wherein the chamber pressure of the chamber on which the substrate is placed is higher during operation (b) than during operation (a), and the holes have a second LCDU (3 sigma) after multi-cycle deposition, and the second LCDU (3 sigma) is less than the first LCDU (3 sigma).

[0004] In some embodiments, the holes are patterned with an EUV (extreme ultraviolet) dose of less than about 40 mJ / cm². In some embodiments, the second LCDU (3 sigma) is less than 3 nm. In some of these embodiments, the first LCDU (3 sigma) is greater than 5 nm. In some embodiments, the difference between the first LCDU (3 sigma) and the second LCDU (3 sigma) is at least 1 nm.

[0005] In some embodiments, the multi-cycle deposition-etching operation is a plasma-assisted operation. In some embodiments, the multi-cycle deposition-etching operation is performed within a single chamber, and the transition between deposition and etching involves changing the chamber pressure. In some embodiments, one or more layers are polymeric or non-polymeric resists, and step (a) includes the step of exposing a pattern of holes to methane (CH4). In some embodiments, step (b) includes the step of exposing a pattern of holes to a plasma generated from nitrogen (N2) gas.

[0006] In some embodiments, during step (a), the first material is preferentially deposited in the larger of the plurality of holes. In some embodiments, the holes have a second CD after multi-cycle deposition, and the second CD is less than the first CD. In some embodiments, the holes have a second CD after multi-cycle deposition, and the second CD is greater than the first CD.

[0007] Another aspect of the present disclosure comprises methods including: receiving a substrate having a feature selected from lines or holes patterned by EUV in one or more layers on a substrate, wherein the feature comprises sidewalls having gaps and protrusions; depositing a passivation layer on the feature sidewalls such that the passivation layer is preferentially deposited in the gaps while exposing the protrusions; and etching the feature to remove the exposed protrusions.

[0008] In some embodiments, one or more layers comprise an amorphous carbon film, and the step of depositing a passivation layer comprises exposing the feature to a plasma generated from sulfur oxide. In some embodiments, one or more layers comprise an amorphous silicon film, and the step of depositing a passivation layer comprises exposing the feature to a plasma generated from carbon fluoride. In some embodiments, one or more layers comprise a resist polymer, and the step of depositing a passivation layer comprises exposing the feature to a plasma generated from methane. In some embodiments, the step of removing protrusions comprises an atomic layer etching (ALE) process.

[0009] Another aspect of the present disclosure relates to a method comprising the steps of: providing a contact hole array patterned by EUV of a dose of 40 mJ / cm² or less, wherein the holes are patterned with a nominal CD and have a first LCDU (3 sigma); and performing one or more smoothing operations to reduce the LCDU (3 sigma) by at least 2 nm.

[0010] These and other aspects of the present disclosure are described below with reference to the drawings. Brief explanation of the drawing

[0011] Figure 1 is a schematic example of a multilayer stack on a semiconductor substrate. Figure 2 is a graph schematically illustrating the relationship between EUV dose and LCDU. FIG. 3 is an example of a feature schematically illustrating protrusions to be etched and gaps including passivation material. FIG. 4a illustrates a schematic example of a reduction and growth process performed on a line to reduce roughness. FIG. 4b illustrates a schematic example of a shrinking process and a growing process performed on a hole to reduce roughness and critical dimensions. Figure 5 illustrates a schematic example of preferential passivation of a rough contact hole. Figure 6 illustrates a schematic example of smoothing during the tone inversion patterning process. FIG. 7 is a schematic illustration of examples of plasma etching chambers according to various embodiments. Figure 8 illustrates the effect of the electrostatic chuck (ESC) temperature on a multi-cycle deposition-removal process performed to reduce the CD on the contact hole pattern in the resist. Figure 9 shows the LCDU for two different pressures as a function of deposition time and removal time for a multi-cycle deposition-removal process performed to reduce CD on a contact hole pattern in a resist. Specific details for implementing the invention

[0012] In the following description, numerous specific details are presented to provide a complete understanding of the provided embodiments. The disclosed embodiments may be practiced with or without some or all of these specific details. In other examples, well-known process operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described together with specific embodiments, it will be understood that this is not intended to limit the disclosed embodiments.

[0013] In semiconductor processing, the patterning of thin films is typically a critical step in the fabrication and manufacturing of semiconductors. Conventional stacks for lithography usually comprise a photoresist layer on top of a lower layer, which is typically deposited on a hard mask by spin-on methods. The hard mask is usually made of a single composition, and the hard mask itself is deposited on a target layer. Conventional patterning involves photolithography, such as 193 nm lithography. In photolithography, patterns are printed by emitting photons from a photon source onto a mask and printing the pattern onto a photosensitive photoresist, thereby inducing a chemical reaction in the photoresist that removes specific portions of the photoresist to form the pattern. In conventional lithography, the number of photons that may strike the photoresist can be variable. In many instances, a large number of photons strike the photoresist, and each photon carries low energy. Since a large number of photons may be used, errors caused by some stray photons do not substantially affect the defined pattern that occurs.

[0014] As devices become smaller, the need to print smaller features increases. While multiple patterning techniques have been developed for use with conventional photolithography, multiple patterning utilizes multiple layer deposition and etching processes. The scaling of features in advanced semiconductor ICs (integrated circuits) and other devices drives lithography to improve resolution by always shifting to smaller imaging source wavelengths.

[0015] EUV lithography is developed to print smaller patterns on photoresist using EUV light sources at a wavelength of approximately 13.5 nm within leading-edge lithography tools, also referred to as scanners. EUV radiation is strongly absorbed by a wide range of materials, including quartz and water, and therefore operates in a vacuum.

[0016] In EUV lithography, fewer photons are emitted from the source and strike the photoresist to form a pattern. Each photon carries higher energy than the photons used in conventional lithography. Furthermore, in EUV lithography, fewer higher-energy photons strike the photoresist, and thus some stray photons that miss the photosensitive locations can cause larger errors within the defined pattern. Compared to conventional lithography, where more lower-energy photons are used and some stray photons may not substantially affect the pattern, photoresist shot noise and stochastic effects attributed to these photons are of particular concern in EUV lithography.

[0017] Techniques for smoothing the edges of features patterned using EUV techniques are provided herein. Techniques with any EUV patterning scheme, including schemes in which a single stack or a multilayer stack is used, may be applied. For example, in some embodiments, a multilayer stack may be used to form lines or spaces or contacts and holes within integrated circuits and to form features for advanced technology nodes as defined by the International Technology Roadmap for Semiconductors. Examples of these advanced technology nodes include 22 nm nodes, 16 nm nodes, 10 nm nodes, and nodes greater than or equal to 16 nm nodes. At the 16 nm node, the width of a typical via or line within a Damascene structure is not greater than about 30 nm. Although the following techniques primarily describe EUV, the techniques provided herein may also be effectively used in other current and future generative patterning techniques to smooth feature edges and tune the critical dimensions of features.

[0018] As mentioned above, the techniques disclosed herein may be used with single stack or multilayer patterning schemes. FIG. 1 is a schematic example of an example of a multilayer stack on a semiconductor substrate. A wafer (100) comprises a target layer (110), a multilayer stack (120), a selectable underlayer (130), and a photoresist (140). The target layer (110) may be any target layer or substrate, such as a metal, oxide, dielectric material, or an ultra-low-k (ULK) substrate. In many embodiments, the target layer (110) is a silicon substrate.

[0019] The multilayer stack (120) comprises a layer (120a) and sublayers (120b and 120c). According to various embodiments, the multilayer stack (120) comprises only two sublayers (as illustrated in the multilayer stack (120)), or more than two sublayers, or three or more sublayers, or four or more sublayers, or five or more sublayers. In some embodiments, an optional sublayer (130) is included as part of the multilayer stack (120). The optional sublayer (130) may be a spin-on layer or a layer deposited by PECVD (plasma-enhanced chemical vapor deposition). As an example, FIG. 1 illustrates two sublayers (120b and 120c) as well as layer (120a). In some embodiments, layer (120a) may be an atomically smooth layer. Multilayer stacks including atomically smooth layers are described in U.S. Patent Application No. 14 / 185,757, filed February 20, 2014, and titled "PECVD FILMS FOR EUV LITHOGRAPHY," which is incorporated herein by reference.

[0020] In various embodiments, the lower layer adjacent to the target layer (110) (i.e., the lower layer (120c) of the example in FIG. 1) is a rigid hard mask layer having rigidity characterized by the stress and modulus of the layer. For example, the rigid hard mask layers may have a modulus of at least 100 MPa and a stress of less than about 500 MPa. In many embodiments, the lower layer (120c), or another lower layer adjacent to the target layer (110), is an amorphous carbon layer. In some embodiments, the modulus to stress ratio of the amorphous carbon lower layer (120c) is at least about 1:1. Examples of rigid hard mask layers used for the lower layer (110) may also include DLC (diamond-like carbon), doped amorphous carbon, and SoC (spin-on carbon).

[0021] In various embodiments, the lower layers (120b and 120c) may be removable after transferring a pattern to the next layer. For example, the lower layer (120b) may be removed after the pattern is transferred to the lower layer (120c). In some embodiments, the lower layers (120b and 120c) may reflect, refract, or absorb a leveling beam emitted onto a substrate to measure the flatness of the wafer.

[0022] The composition of the lower layers (120b and 120c) may be selected from one of many classes of compositions, e.g., oxides, metals (e.g., hafnium, cobalt, tungsten, titanium) or conductive films (e.g., titanium nitride, titanium silicide, cobalt silicide), dielectric materials (e.g., silicon oxide, silicon nitride, SOG (spin-on-glass)), hard mask materials (e.g., amorphous carbon, amorphous silicon), or others, e.g., silicon oxynitride (SiON), NFARL (nitrogen-free anti-reflective layer), or SiARC (silicon anti-reflective coating). In one example, the lower layer (120b) is an amorphous silicon layer and the lower layer (120c) is an amorphous carbon layer. In many embodiments, the lower layer (120b) and the lower layer (120c) may each have a thickness of about 100 Å to about 900 Å.

[0023] The lower layers (120b and 120c) are selected based on the etching contrast of the lower layers (120b and 120c) relative to adjacent layers. In many embodiments, the lower layer (120b) has high etching contrast for the lower layer (120c) and also has high etching contrast for 120a. In various embodiments, the lower layer (120c) has high etching contrast for both the lower layer (120b) and the target layer (110). For example, if the lower layer (120c) is an amorphous carbon layer, the lower layer (120b) may have high etching contrast for both the atomically smooth layer (120a) and the amorphous carbon lower layer (120c).

[0024] The sublayers (120b and 120c) may also be selected based on other optimizable properties such as physical properties, chemical properties, and optical properties. Examples of these properties may include surface energy, bonding structure, hydrophobicity, refractive index, and absorption coefficient.

[0025] Layer (120a) may be a thin layer deposited within a layer near the top of a multilayer stack, such as a first or second layer under the photoresist (140). Layer (120a) may be an atomically smooth layer characterized by very low roughness. "Atomically smooth" is defined as having a monolayer roughness of less than 1, or a deviation of about 1 / 2 monolayer from the average line. "Local" roughness is 1 μm of the wafer surface area. 2It is defined as roughness. The roughness of the layer may be numerically determined by observation and by atomic force microscopy (AFM). Roughness may also be measured by the average of the vertical deviations of the roughness profile from the mean line. In one example, the atomically smooth layer (120a) may have an average roughness of less than about 2 Å. Roughness may also be measured by the root mean square (RMS) of the vertical deviations of the roughness profile from the mean line.

[0026] In some embodiments, the thickness of the layer (120a) may be about 30 Å to about 60 Å. The layer (120a) may have high etching contrast with respect to adjacent layers and may also be removable after transferring the pattern to the next layer. In various embodiments, the layer (120a) is an oxide layer. In some examples, the layer (120a) is a thin layer of silicon oxide.

[0027] A multilayer stack as illustrated in FIG. 1 may also be used in EUV lithography by utilizing a reduction effect. When larger features are printed on a photoresist using EUV lithography and each layer is etched under the multilayer stack, the features are reduced to decrease the photoresist shot noise and photon-induced roughness described above. In many embodiments, the features printed on the photoresist are reduced so that the patterned features within the target layer have a critical dimension of about 70% or less of the width or size of the critical dimension of the pattern within the photoresist. The percentage of reduction may be optimized by various etching processes. The percentage of reduction may also be limited by the pitch.

[0028] Thinner photoresist films may be used with multilayer stacks to reduce the exposure dose used to pattern the photoresist. For example, reducing the photoresist thickness from approximately 1000 Å to approximately 300 Å significantly reduces the dose required to expose the photoresist, thereby improving scanner throughput. The photoresist may also function as a mask during the reactive ion etching (RIE) of the underlying films to transfer a mask pattern onto a target layer. When the photoresist functions as a mask for this purpose, a lower limit on the photoresist thickness may be determined by the minimum thickness of the photoresist to enable its use as a mask.

[0029] In addition to the reduction effect described above, various techniques for smoothing EUV-patterned features are provided herein. While these techniques may be used for multilayer stacks with relatively thin photoresist layers, they may also be advantageously used for stacks and single layers containing thick photoresist layers. Furthermore, as mentioned above, the techniques are not limited to 13.5 nm EUV, but may be used with other wavelengths of EUV and other next-generation patterning techniques when roughness is an issue.

[0030] The techniques provided herein produce low roughness. For example, features patterned using EUV may have low line edge roughness (LER) using the techniques disclosed herein. LER may be defined as the deviation of the feature edge (when viewed from top to bottom) from a smooth, ideal shape—that is, the edge deviations of the feature occurring at a dimensional scale smaller than the resolution limit of the imaging tool used to print the feature. The magnitude of the LER may be influenced by a number of factors, including photon shot noise of the exposure radiation, the stochastic nature of the dissolution of the photoresist within the developer, measurement noise introduced by the scanning electron microscope (SEM), and chemical interactions between the photoresist and the underlying film. The sidewall roughness on the patterned photoresist may be highly anisotropic, and the roughness may propagate from the photoresist-substrate interface over the photoresist pattern sidewalls. In ultrathin photoresist films that may have a thickness of about 100 nm or less, roughness may be correlated from the photoresist-substrate interface to the photoresist-air interface for a plurality of different photoresist material platforms. In EUV lithography, particularly for high-volume fabrication, the photoresist LER is targeted to be less than about 1 nm (3σ). Since each layer is etched downward within a multilayer stack, the walls of the features are smoothed and the LER may be optimized to be close to less than 1 nm. Patterned features may also feature local critical dimension (CD) uniformity (LCU). LCDU is a hole-to-hole CD variation on a local scale defined as the 3-sigma value of the CD distribution. According to various embodiments, features with an LCDU of 2.5 nm or less (3σ) may be provided.In some embodiments, LCDU is a field LCDU (3σ), which is 3 sigma of all contact holes (or other features) within the field of view. LCDU is a common divisor of the roughness within the contact holes and may be the result of shot noise, masks, and metrology components.

[0031] In some embodiments, the techniques provided herein smooth patterned features using low-dose EUV. FIG. 2 is a graph schematically illustrating the relationship between EUV dose and LCDU. The dots represent the dose / LCDU for various representative resists. As can be seen from FIG. 2, very high doses (e.g., greater than 60 mJ / cm²) are used to obtain an LCDU of about 3 nm. As the dose decreases, the roughness increases, and an LCDU of greater than 5 nm is produced from doses of 30 mJ / cm² or less. An exemplary dose / LCDU target zone (201) with an EUV dose of about 40 mJ / cm² or less and an LCDU of about 3 nm or less is shown in FIG. 2. To date, resists could not be patterned within the target zone.

[0032] Although the smoothing techniques disclosed herein may be used with any resist and EUV dose, in some embodiments, a low EUV dose is used to intentionally create coarse features that are smoothed by the techniques disclosed herein. In this way, a dose / LCDU within the target zone may be obtained. In the example illustrated in FIG. 2, an LCDU (205) of about 2.5 nm may be obtained by low dose patterning of 15 mJ / cm² to obtain relatively coarse features (203), followed by one or more smoothing techniques as described herein. Depending on various embodiments, the methods disclosed herein may include receiving features patterned by EUV at doses of 40 mJ / cm² or less, 30 mJ / cm² or less, or 5 mJ / cm² or less, or much lower doses. An exemplary LCDU may be about 5 nm or 6 nm at these doses. Methods further include reducing roughness. Examples of techniques for reducing roughness and smoothing features are described below.

[0033] The various techniques described below may be applied at any appropriate stage when transferring a pattern within an EUV resist exposed to a target layer. This includes smoothing features within the resist layer or one or more intermediate layers. In some embodiments, one or more techniques may be performed in multiple pattern transfer steps. In some embodiments, the amorphous hard mask layer (e.g., the lower layer (120c) in FIG. 1) may be the thickest part of the stack and may provide the best opportunity for smoothing.

[0034] As further discussed below, various techniques involve the deposition of a passivation layer that reduces the etching rate. The passivation chemical may be applied during the etching operation or in an alternating sequence with the etchant. If applied during the etching operation, the passivation chemical may be supplied within a compound identical to or different from the main etchant. For example, in the fluorocarbon plasma etching of dielectrics, C x F y A polymer passivation layer may also be deposited. In another example, sulfur and carbon may form a passivation layer during SO2 / O2 etching of a carbonaceous layer. Passivating chemicals may depend on the material to be passivated as well as the etching chemicals. Any suitable passivation chemical may be used, including examples such as sulfur-containing compounds like sulfur dioxide (SO2) compounds for passivating amorphous carbon (aC) films, fluorocarbons like C4F6 and C4F8 for passivating amorphous silicon (a-Si) and oxide films, and methane (CH4) for passivating resist polymers or non-polymer resists. Hydrogen bromide (HBr) may also be used to passivate carbon-containing films and silicon-containing films.

[0035] Priority removal of protrusions

[0036] The roughness of a feature, such as a line or hole, may be characterized by protrusions and gaps along different edges or sides of the feature. In some embodiments, one or more cycles are performed to smooth the feature by 1) applying a thin passivation layer that preferentially accumulates within the gaps while exposing the protrusions, and 2) etching the feature to remove the exposed protrusions. The passivation layer is thinner than at least the largest protrusions. The passivation material may preferentially accumulate within the gaps due to a higher surface-to-volume ratio within the gaps than within the protrusions. Because the passivation is preferential and the gaps are passivated to a greater extent than the protrusions, subsequent etching preferentially removes the protrusions. In this way, the protrusions are shaved down, and the roughness is reduced. FIG. 3 illustrates an example of a feature schematically illustrating the protrusions to be etched and the gaps containing the passivation material. It should be noted that the technique may be applied to positive features such as pillars and negative features such as holes, and that the reduction of protrusions accordingly decreases or increases the CD.

[0037] In some embodiments, an ALE process may be used to etch protrusions. ALE processes are described in "Overview of Atomic Layer Etching in the Semiconductor Industry" by Kanarik et al., J. Vac. Sci. Technol. A 33(2), Mar / Apr 2015, which is incorporated herein by reference for the purpose of describing ALE. In an ALE process, the surface of a feature may be exposed to a surface modification chemical to form a thin reactive surface layer. Examples of surface modification chemicals include chloride chemicals such as Cl2 for etching silicon and oxides, fluorocarbons for etching dielectrics, and oxidizing chemicals such as O2. After surface modification, a removal operation removes the reactive surface layer without removing the underlying material. Low-energy ion bombardment may be used. In the example of FIG. 3, gaps are preferentially passivated while exposing protrusions to be preferentially etched in one or more cycles of ALE. A thin passivation layer may be deposited from surface modification chemicals or in individual operations prior to surface modification. Other etching processes, including continuous etching processes, may be used instead of ALE.

[0038] Examples of process sequences include: deposition of a passivation layer → one or more etching cycles; deposition of a passivation layer → one or more etching cycles → deposition of a passivation layer → one or more etching cycles.

[0039] In one example, the patterned EUV resist may be exposed to an inductively coupled plasma (ICP) generated from CH4 / H2 to preferentially passivate the gaps of the patterned features. This may be followed by an O2 (modification) / Ar (removal) ALE process.

[0040] In some embodiments, an ALE process is used in which a surface-modified layer is preferentially deposited on the protrusions. Since the removal operation removes only the surface-modified layer, the protrusions are preferentially removed.

[0041] Reduction plus growth smoothing

[0042] In some embodiments, reduction and growth processes are performed on the feature, and roughness is reduced by each reduction operation and each growth operation. This is shown in FIG. 4a for the line. FIG. 4b illustrates a rough schematic example of top-down views of a reduction + trimming + reduction + trimming sequence to obtain a smooth contact hole with a target CD. First, an etched hole is provided at (A). The hole may be formed, for example, within the resist or within one or more intermediate layers. The hole is reduced to reach (B), and the process reduces the roughness. Reducing the hole and reducing the roughness may involve using an appropriate passivation chemical reaction in an ALE or continuous process to preferentially deposit a passivation layer within the gaps. Next, the resist or other material surrounding the hole is trimmed to increase the CD and reduce the roughness. See (C). As described above, trimming may involve an appropriate passivation chemical reaction in ALE or continuous etching. Subsequently, the hole may be returned from (D) to the target CD and reduced again to decrease roughness. The reduction + growth cycle may be repeated multiple times to reduce roughness (step down). By cycling back and forth between the reduction and growth of the feature, roughness can be reduced without requiring more space on the substrate for the feature. For example, a 40 nm feature may be printed at 40 nm and smoothed by reduction and growth between 36 nm and 41 nm. This can be useful when there is not more space to print on the substrate due to dense features.

[0043] Accelerated smoothing by feature radius

[0044] In some embodiments, a passivation layer thicker than the smallest radius of curvature of the critical features is deposited. This results in new rough features that are preferentially rounded by pinching off within corners with high volume-to-surface ratios. FIG. 5 illustrates a schematic example of preferential passivation of a rough contact hole. In 505, a rough resist image for a circular hole is shown. As can be seen from the image, the nominal circular feature has squared-off edges. During the etching process, the passivation layer (502) is preferentially deposited at the corners. The hole (501) is etched into the material (503), which may be the resist or the underlying layer, as described above. Because the passivation material is preferentially deposited within regions with a high volume-to-surface ratio, the process can preferentially smooth the roughest regions of the features. The features become progressively smoother as etching progresses. For example, C4F8 or C4F6 fluorocarbon may also be used to preferentially deposit a passivation layer within the corners during the etching of a dielectric. In another example, a sulfur-containing compound may also be used to preferentially deposit a passivation layer within the corners during the etching of a carbon hard mask.

[0045] Tone inversion based on EUV resist smoothing

[0046] In some embodiments, tone inversion is used to increase roughness reduction. As illustrated in FIG. 6, two smoothing opportunities are provided by using tone inversion (602). Without tone inversion (601), one smoothing opportunity is provided. In 602, features may be selectively smoothed using one or more techniques, for example, as described above during the first smoothing opportunity. Protrusions are reduced, but recessed roughness may be protected. The effectiveness of this technique may be limited by the target CD, which limits total removal. However, after the reduction of protrusions in the first smoothing operation, a planarization deposition is performed and the initial mandrel is removed. This causes the previously concave features to become protrusions in the inverted tone images and inverts the CD of the feature. The newly formed protrusions may be reduced as described above.

[0047] Examples of processes for implementing tone inversion are described in U.S. Patent Application No. 14 / 101,901, filed December 10, 2013, titled “IMAGE REVERSAL WITH AHM GAP FILL FOR MULTIPLE PATTERNING,” which is incorporated herein by reference. The smoothing techniques described herein may be applied at any suitable step of the image inversion processes described herein.

[0048] In a tone inversion or image inversion process, a combination of positive and negative resists may be used. In the example of FIG. 6, a masked negative photoresist layer may be placed on a substrate including a layer to be patterned. The masked negative photoresist layer is exposed to EUV and developed to create an opening for the pattern. Smoothing by one or more of the techniques described herein may be performed during or after the development of the negative photoresist layer. Subsequently, the positive photoresist may be exposed to EUV to pattern the holes. Smoothing by one or more of the techniques described above may be performed during or after the development of the negative photoresist layer.

[0049] Modification of pattern transfer layers

[0050] As described above with respect to FIG. 1, in some embodiments, there may be one or more layers between the resist and the target layer. In some embodiments, these layers are configured to improve smoothing during the etching process. Modification may be performed to adjust the adhesion coefficient of the layers and / or the etching rate. The layers may be modified when deposited or by injecting dopants. For example, an n-dopant may be included in the silicon layer to modify the etching selectivity. Additional examples of dopants include Co, W, Ti, Ta, Hf, Sn, As, B, Ge, and P.

[0051] LCDU reduction within the array of holes

[0052] In some embodiments, the LCDU may be reduced within an array of other features or holes formed in the photoresist after lithography and before etching of the underlying material. The LCDU may feature variations in hole size (e.g., diameter) over a relatively small area of ​​the region, e.g., a 200 nm × 200 nm portion. In some embodiments, 1) a thin layer is deposited in a plurality of holes having different CDs formed in the photoresist, the thin layer is preferentially deposited in the larger CD holes, and 2) one or more cycles are performed to remove the thin layer anisotropically from the bottom portions of the holes.

[0053] The layer will be deposited on the bottoms of the holes and on the sidewalls, but will be removed from the bottoms of the holes. Because the layer is deposited preferentially in the larger holes, the sidewall thickness will grow preferentially in the larger holes over the smaller holes, making the CD more uniform.

[0054] Deposition chemicals may depend not only on etching chemicals but also on the material on which the film is deposited. Any suitable chemical with examples including sulfur-containing compounds such as sulfur dioxide (SO2) compounds to be deposited on amorphous carbon (aC) films, fluorocarbons such as C4F6 and C4F8 to be deposited on amorphous silicon (a-Si) and oxide films, and methane (CH4) or other alkanes to be deposited on resist polymers may be used. Hydrogen bromide (HBr) may also be used to passivate carbon-containing and silicon-containing films. Removal chemicals may also depend not only on deposition chemicals but also on the material on which the film is deposited. In one example, a CH4 / N2 deposition chemical follows an N2 removal chemical.

[0055] The above operations may be used to improve the LCDU, but it should be noted that they lower the CD of the lithography-defined holes. In some embodiments, the substrate temperature may be controlled to tune the LCDU and CD independently. Refer to Fig. 8, which illustrates the effect of the electrostatic chuck (ESC) temperature on a multi-cycle deposition-removal process performed to reduce the CD for the contact hole pattern in the resist. The ESC temperature is correlated with the substrate temperature. As can be seen from Fig. 8, the LCDU is relatively insensitive to the ESC temperature, but the CD is sensitive to the ESC temperature. This allows for the independent tuning of the LCDU and CD.

[0056] In some embodiments, deposition and removal operations are performed at different pressures, with the pressure being higher during removal. FIG. 9 illustrates the LCDU for two different pressures as a function of deposition time and removal time. At lower pressures, longer deposition improves the LCDU. At higher pressures, removal time has minimal effect on the LCDU. Deposition is advantageous at low pressures, but removal is advantageous at high pressures.

[0057] Examples

[0058] Examples of multilayer stacks to which smoothing techniques may be applied are as follows: The target layer may be a silicon oxide-based layer, such as a TEOS layer, with a thickness of about 1500 Å. On top of the target layer, there may be a first sublayer of amorphous carbon, which may be an ashable hardmask. The amorphous carbon layer may be rigid and may have a high modulus to maintain a fine pattern, particularly when the amorphous carbon layer is patterned in subsequent steps. Exemplary thicknesses of the amorphous carbon layer may be about 400 Å or about 900 Å. On top of the amorphous layer, there may be a second sublayer of amorphous silicon having a high etching contrast with respect to the amorphous carbon. In some embodiments, the amorphous silicon is doped. In some embodiments, the amorphous silicon is not doped. This layer may be about 100 Å thick. On top of the amorphous silicon layer, there may be an atomically smooth layer. The amorphous silicon layer may have high etching contrast with respect to the atomically smooth layer. The atomically smooth layer may be a silicon oxide layer with a thickness of about 30 Å to about 60 Å, and may be deposited such that the film roughness is less than that of a monolayer. For example, the average roughness of the atomically smooth layer may be about 2 Å. A photoresist layer may be present on top of the atomically smooth layer.

[0059] As described above, an example of transferring a smoothing pattern of a contact hole into a silicon oxide layer using a multilayer stack is as follows:

[0060] Oxide / a-Si Etching: 600 W TCP / 120 Vb (200 Hz, 50 % DC) / SF6 / CH2F2 / N2 / He

[0061] aC Hardmask Open: 440 W TCP / 150 Vb / SO2 / O2

[0062] Biased pulsed TCP (transformer coupled plasma) may also be used to etch oxide and a-Si layers using CH2F2, which provides a passivation layer that preferentially deposits within the corners of the contact holes during etching as described above with respect to FIG. 5. During the opening of the aC hard mask, sulfur may preferentially form a passivation layer within the corners of the contact holes.

[0063] As described above, an example of smoothing during pattern transfer of a grating pattern into a silicon oxide layer using a multilayer stack is as follows:

[0064] Resist Growth / Shrinkage: x times [Oxidation (O250 W TCP / 0 Bias Voltage (Vb), 1 sec) + Argon Elimination (Ar 300 W TCP / 20 Vb / 2 sec) + Polymer Passivation Layer (CH4 / H2700 W TCP / 4 sec]

[0065] The above example is an example of shrinkage / growth smoothing as described above for FIGS. 4a and 4b. During oxidation and argon operations, the contact hole is grown (using trimmed resist) and during passivation, the contact hole is shrunk. In one example, a polymer passivation layer may be preferentially formed within the recesses of the feature so that O2 / Ar etching removes the passivated material less quickly.

[0066] Oxide etching / a-Si etching and aC hardmask opening may also be performed as described above.

[0067] Examples of improving LCDU within an array of holes are described. As described above, 10 cycles of deposition (3 seconds) and etching (5 seconds) of a multi-cycle deposition / removal process were performed to improve LCDU within the resist. The chamber pressure was 120 mT. A pulsed TCP plasma was employed with 200 W / 50 W pulsing. A nominal CD of 22 nm was used. The deposition chemical was CH4 / N2 and the removal chemical was N2. LCDU and CD were measured as a function of temperature, and the results are shown in Fig. 8.

[0068] As described above, multiple cycles of 10 seconds of deposition and 3 seconds of etching in a multi-cycle deposition / removal process were performed to improve the LCDU in the resist. The chamber pressure was varied. The temperature was 30 °C. The pulsed TCP plasma was employed at 200 W / 50 W pulsing. A nominal CD of 22 nm was used. The deposition chemical was CH4 / N2 and the removal chemical was N2. The LCDU was measured as a function of pressure for deposition and etching, and the results are shown in Fig. 9.

[0069] device

[0070] The disclosed embodiments may be carried out in a process chamber such as a plasma etching chamber. For example, the methods described above may be carried out in an ICP (inductively coupled plasma) or CCP (capacitively coupled plasma) chamber, or in a downstream plasma chamber.

[0071] FIG. 7 is a schematic illustration of an example of a plasma etching chamber according to various embodiments. The plasma etching chamber (700) includes an upper electrode (702) and a lower electrode (704) in which plasma may be generated.

[0072] As described above, the substrate (799) having EUV patterning on its upper surface may be positioned on the lower electrode (704) and held in place by an ESC. Other clamping mechanisms may also be employed. The plasma etching chamber (700) includes plasma confining rings (706) that maintain the plasma over the substrate and are spaced apart from the chamber walls. Other plasma confining structures, such as a shroud or dome acting as an inner wall, may be employed. In some embodiments, the plasma etching chamber (700) may not include any of these plasma confining structures.

[0073] In the example of FIG. 7, the plasma etching chamber (700) comprises two RF sources, an RF (radio frequency) source (710) connected to the upper electrode (702) and an RF source (712) connected to the lower electrode (704). Each of the RF sources (710 and 712) may comprise one or more sources of any suitable frequency, including 2 MHz, 13.56 MHz, 27 MHz, and 60 MHz. Gas may be introduced into the chamber (700) from one or more gas sources (714, 716, and 718). For example, the gas source (714) may comprise an inert gas, the gas source (716) may comprise an etchant, and the gas source (718) may comprise a passivating gas. Gases may be introduced into the chamber through the inlet (720) using excess gas and reaction byproducts exhausted through the exhaust pump (722). An example of a plasma etching chamber that may be employed is the 2300® Flex™ reactive ion etching tool available from Lam Research Corp., Fremont, California. Further technology for plasma etching chambers may be found in U.S. Patents No. 6,841,943 and No. 8,552,334, which are incorporated herein by reference in their entirety.

[0074] Returning to FIG. 7, the controller (730) is connected to valves associated with the RF sources (710 and 712) as well as the gas sources (714, 716, and 718) and the exhaust pump (722). In some embodiments, the controller (730) controls all activities of the plasma etching chamber (700). The controller (730) may execute control software (738) that is stored in a mass storage device (740), loaded into a memory device (742), and executed on a processor (744). Alternatively, the control logic may be hardcoded within the controller (730). ASICs (Applications Specific Integrated Circuits), PLDs (Programmable Logic Devices) (e.g., FPGAs (field-programmable gate arrays)), etc., may be used for these purposes. In the following discussion, where "software" or "code" is used, functionally comparable hard-coded logic may be used at that location. The control software (738) may include instructions for controlling timing, mixtures of gases, gas flow rates, chamber pressure, chamber temperature, wafer or pedestal temperature, RF frequency, RF power levels, substrate pedestal, chuck and / or susceptor position, and other parameters of a specific process performed by the plasma etching chamber (700). The control software (738) may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of process tool components used to perform various process tool processes. The control software (738) may be coded in any suitable computer-readable programming language.

[0075] In some embodiments, the control software (738) may include IOC (input / output control) sequencing instructions for controlling the various parameters described above. Other computer software and / or programs stored in a mass storage device (740) and / or memory device (742) associated with the controller (730) may be employed in some embodiments. Examples of programs or sections of programs for this purpose include process gas control programs, pressure control programs, and RF source control programs.

[0076] A process gas control program may include code for controlling gas composition (e.g., fluorinated gases, fluid silicon sources, oxidizers as described herein) and flow rates, and for flowing gas into the chamber before etching to selectably stabilize the pressure within the chamber. A pressure control program may include code for controlling the pressure within the chamber by, for example, controlling a throttle valve in the chamber's exhaust system, the gas flow into the chamber, etc. An RF source control program may include code for setting RF power levels applied to the electrodes according to the embodiments of this specification.

[0077] In some embodiments, there may be a user interface associated with a controller (730). The user interface may include a display screen, graphical software displays of device and / or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

[0078] In some embodiments, parameters adjusted by the controller (730) may be related to process conditions. Non-limiting examples include process gas composition and flow rates, pedestal temperature, solid silicon source temperature, pressure, plasma conditions (such as RF bias power levels, current in zones of a multi-zone coil), etc. These parameters may be provided to the user in the form of a recipe, which may be entered using a user interface.

[0079] Signals for monitoring the process may be provided from various process tool sensors by the analog input and / or digital input connections of the system controller (730). Signals for controlling the process may be output on the analog output and digital output connections of the plasma etching chamber (700). Non-limiting examples of sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0080] The controller (730) may provide program instructions for implementing the optional etching processes described above. The program instructions may control various process parameters such as RF bias power levels, currents within the zones of a multi-zone coil, pressures, pedestal temperatures, solid silicon source temperatures, gas flow rates, etc. The instructions may also control parameters to selectively etch silicon nitride films according to various embodiments described herein.

[0081] The controller (730) will typically include one or more memory devices and one or more processors configured to execute instructions to perform the method according to the disclosed embodiments. A machine-readable medium containing instructions for controlling process operations according to the disclosed embodiments may be coupled with the controller (730), for example, as described above.

[0082] In some embodiments, the controller (730) may be part of or form part of a system controller that is part of a system that may be part of the examples described above. These systems may include semiconductor processing equipment, including processing tools or tools, chambers or chambers, a platform or platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated into an electronic device for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronic device may be referred to as a "controller" that may control various components or subcomponents of the system or systems. The system controller may be programmed to control any of the processes disclosed herein, depending on the processing conditions and / or type of the system, for example, the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, tools and other delivery tools and / or wafer transfer into and out of load locks connected to or interfacing with a specific system.

[0083] Generally speaking, a system controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs (application-specific integrated circuits), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions transmitted to the system controller or the system in the form of various individual settings (or program files) that define operation parameters for executing a specific process on or for a semiconductor wafer. In some embodiments, the operation parameters may be part of a recipe defined by a process engineer to achieve one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a substrate.

[0084] In some embodiments, the system controller may be integrated into the system, coupled to the system, otherwise networked to the system, or coupled to or part of a computer that is a combination thereof. For example, the system controller may be all or part of a factory (fab) host computer system capable of enabling remote access to substrate processing, or it may be located within the “cloud.” The computer may enable remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, examine trends or performance measurements from multiple manufacturing operations, change parameters of the current processing, set processing steps following the current processing, or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a local network or a network that may include the Internet. The remote computer may include a user interface that enables the input or programming of parameters and / or settings to be subsequently transmitted from the remote computer to the system. In some examples, the system controller receives instructions in the form of data that specify parameters for each of the process steps to be performed during one or more operations. It should be understood that these parameters may be specific to the type of tool configured to be controlled or interfaced by the system controller and the type of process to be performed. Accordingly, as described above, the system controller may be distributed by including one or more individual controllers that are networked together and cooperate for a common purpose, for example, for the processes and controls described herein.An example of a distributed controller for this purpose may be one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) that are combined to control a process on the chamber.

[0085] Exemplary systems may include, without limitation, a plasma etching chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etching chamber or module, a PVD (physical vapor deposition) chamber or module, a CVD (chemical vapor deposition) chamber or module, an ALD (atomic layer deposition) chamber or module, an ALE (atomic layer etch) chamber or module, an ion implantation chamber or module, a track chamber or module, a strip chamber or module, and any other semiconductor processing systems that may be used or associated in the manufacture and / or fabrication of semiconductor wafers.

[0086] As described above, depending on the process steps or steps to be performed by the tool, the system controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a main computer, other controllers, or tools used in material transfer for moving containers of wafers from / to tool locations and / or load ports within the semiconductor manufacturing plant.

[0087] conclusion

[0088] Although the embodiments described above are described in some detail for the sake of clarity of understanding, it will be apparent that specific changes and modifications may be made within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and devices of the embodiments. Accordingly, the embodiments are illustrative and not to be considered restrictive, and the embodiments are not limited to the details provided herein.

Claims

Claim 1 A step of receiving said substrate including a plurality of features including sidewalls and bottom portions patterned within one or more layers on the substrate, wherein said features are patterned with a nominal CD (critical dimension) and have a first LCDU (local critical dimension uniformity) (3 sigma), said plurality of features include features of different sizes, and the LCDU (3 sigma) is characterized by a variation in the feature sizes of said plurality of features; A method comprising the step of performing a multi-cycle deposition-etching operation within one or more layers, wherein each of the cycles comprises: (a) an operation of depositing a first material within the features, including on the sidewalls and bottom portions of the features; and (b) anisotropically removing the first material from the features to remove the first material from the bottom portions of the features, wherein the features have a second LCDU (3 sigma) after the multi-cycle deposition-etching, and the second LCDU (3 sigma) is less than the first LCDU (3 sigma). Claim 2 A method according to claim 1, wherein the features are patterned with an EUV (extreme ultraviolet) dose of less than 40 mJ / ㎠. Claim 3 In claim 1, the method wherein the second LCDU (3 sigma) is less than 3 nm. Claim 4 In claim 3, the method wherein the first LCDU (3 sigma) is greater than 5 nm. Claim 5 A method according to claim 1, wherein the difference between the first LCDU (3 sigma) and the second LCDU (3 sigma) is at least 1 nm. Claim 6 In claim 1, the method wherein the multi-cycle deposition-etching operation is a plasma-assisted operation. Claim 7 A method according to claim 1, wherein one or more layers comprise a polymeric or non-polymeric resist and the operation (a) comprises exposing the sidewalls and bottom portions of the features to methane (CH4). Claim 8 A method according to claim 1, wherein the operation (b) comprises exposing the sidewalls and bottom portions of the features to a plasma generated from nitrogen (N2) gas. Claim 9 A method according to claim 1, wherein the features have a second CD after the multi-cycle deposition-etching, and the second CD is less than the first CD. Claim 10 A method according to claim 1, wherein the features have a second CD after the multi-cycle deposition-etching, and the second CD is greater than the first CD. Claim 11 A method according to claim 1, wherein the operation (a) comprises preferentially depositing the first material on the larger features among the plurality of features. Claim 12 In claim 1, the above features are a line or hole-in, a method. Claim 13 A method comprising: receiving a substrate including a feature selected from a line or feature hole patterned by EUV within one or more layers on the substrate, wherein the feature includes sidewalls; depositing a passivation layer on the feature sidewalls; and removing at least a portion of the passivation layer from the feature sidewalls and reducing the sidewall roughness. Claim 14 In claim 13, the step of depositing the passivation layer comprises the step of exposing the feature to a plasma generated from sulfur oxide. Claim 15 In claim 13, the step of depositing the passivation layer comprises the step of exposing the feature to a plasma generated from carbon fluoride. Claim 16 In claim 13, the step of depositing the passivation layer comprises the step of exposing the feature to a carbon-containing chemical. Claim 17 In claim 16, the carbon-containing chemical comprises a plasma generated from a gas containing methane. Claim 18 In claim 13, the method wherein one or more layers comprise a resist. Claim 19 In claim 13, the step of removing at least a portion of the passivation layer and reducing the sidewall roughness comprises an atomic layer etching (ALE) process. Claim 20 A method according to claim 13, further comprising the step of repeating the deposition step and the removal step one or more times. Claim 21 A method comprising the step of providing a multilayer stack on a target layer, wherein the multilayer stack comprises a first layer and one or more underlayers below the first layer; and the step of providing a resist layer on the multilayer stack, wherein the multilayer stack reduces roughness when a pattern is transferred from the resist layer to the target layer, and the roughness is reduced by (a) depositing a passivation layer on a feature transferred to the multilayer stack, and (b) removing at least a portion of the passivation layer from the sidewalls of the feature. Claim 22 In claim 21, the method wherein the resist layer is EUV patterned. Claim 23 In claim 21, the method wherein the first layer is a carbon layer. Claim 24 A method according to claim 21, wherein one or more lower layers comprise an oxide layer or a nitride layer. Claim 25 In claim 21, the method wherein one or more sublayers comprise a carbon layer. Claim 26 In claim 21, the one or more lower layers include an upper lower layer and a lower lower layer, and the upper lower layer is disposed between the first layer and the lower lower layer. Claim 27 In claim 26, the method wherein the upper and lower layers comprise an oxide. Claim 28 In claim 26, the method wherein the lower layer comprises carbon.

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