Semiconductor Device Having an NMOS Transistor and a PMOS Transistor and Methods of Manufacturing the Semiconductor Device

Abstract

A semiconductor device is described. The semiconductor device includes an NMOS transistor structure formed on an NMOS region of a substrate; and a PMOS transistor structure formed on a PMOS region of the substrate. The NMOS transistor structure includes NMOS source / drain regions formed on the substrate and a plurality of NMOS channel patterns and a plurality of NMOS gate structures alternately and repeatedly stacked between the NMOS source / drain regions. The PMOS transistor structure includes a plurality of PMOS channel patterns and a plurality of PMOS gate structures alternately and repeatedly stacked between the PMOS source / drain regions formed on the substrate and the PMOS transistor regions. Each of the NMOS channel patterns includes a single layer of silicon. Each of the PMOS channel patterns includes a silicon layer and a silicon germanium layer.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device having an NMOS transistor and a PMOS transistor and a method for manufacturing the same. Background Technology

[0003] A semiconductor device having multi-bridge channels with multiple nanosheets has been studied and proposed for high performance. Prior art literature

[65535] 1. U.S. Patent Application Publication No. 2014-0197377 2. Republic of Korea Patent Publication No. 10-2015-0051445 3. U.S. Patent Application Publication No. 2020-0294865 The problem to be solved

[0005] The problem that the embodiments of the present disclosure aim to solve is to provide a semiconductor device having an NMOS transistor and a PMOS transistor having a plurality of nanosheets.

[0006] The problem that the embodiments of the present disclosure aim to solve is to provide methods for manufacturing semiconductor devices having NMOS transistors and PMOS transistors having a plurality of nanosheets. means of solving the problem

[0008] A semiconductor device according to one embodiment of the present disclosure for solving the above problem comprises: an NMOS transistor structure formed on an NMOS region of a substrate; and a PMOS transistor structure formed on a PMOS region of the substrate. The NMOS transistor structure comprises NMOS source / drain regions formed on the substrate and a plurality of NMOS channel patterns and a plurality of NMOS gate structures alternately and repeatedly stacked between the NMOS source / drain regions. The PMOS transistor structure comprises PMOS channel patterns and a plurality of PMOS gate structures alternately and repeatedly stacked between the PMOS source / drain regions formed on the substrate and the PMOS transistor regions. Each of the NMOS channel patterns comprises a single layer of silicon. Each of the PMOS channel patterns comprises a silicon layer and a silicon germanium layer.

[0009] A semiconductor device according to one embodiment of the present disclosure for solving the above problem includes an NMOS transistor structure formed on an NMOS region of a substrate and a PMOS transistor structure formed on a PMOS region of the substrate. The NMOS transistor structure includes NMOS source / drain regions formed on the substrate and a plurality of NMOS channel patterns and a plurality of NMOS gate structures alternately and repeatedly stacked between the NMOS source / drain regions. The PMOS transistor structure includes a plurality of PMOS channel patterns and a plurality of PMOS gate structures alternately and repeatedly stacked between the PMOS source / drain regions formed on the substrate and the PMOS transistor regions. The vertical thickness of each NMOS channel pattern is smaller than the vertical thickness of each PMOS channel pattern. The vertical thickness of each NMOS gate structure is larger than the vertical thickness of each NMOS gate structure.

[0010] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure for solving the above problem comprises: stacking pre-channel patterns including a sacrificial layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on a substrate having an NMOS region and a PMOS region; removing the sacrificial layers of the pre-channel patterns within the PMOS region to form first spaces; forming PMOS gate structures within the first spaces; removing the sacrificial layers and the silicon germanium layers of the pre-channel patterns within the NMOS region to form second spaces; oxidizing the surfaces of the first silicon layers and the second silicon layers to form first silicon oxide layers and second silicon oxide layers; removing the first silicon oxide layers and the second silicon oxide layers to expand the second spaces into third spaces; and forming NMOS gate structures within the third spaces.

[0011] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure for solving the above problem comprises: stacking pre-channel patterns including a sacrificial layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on a substrate having an NMOS region and a PMOS region; removing the sacrificial layers and the silicon germanium layer of the pre-channel patterns within the NMOS region to form first spaces; oxidizing the surfaces of the first silicon layers and the second silicon layers exposed within the first spaces to form first silicon oxide layers and second silicon oxide layers; removing the first silicon oxide layers and the second silicon oxide layers to expand the first spaces into second spaces; forming NMOS gate structures within the second spaces; removing the sacrificial layers of the pre-channel patterns within the PMOS region to form third spaces; and forming PMOS gate structures within the third spaces.

[0012] A method for manufacturing a semiconductor device according to an embodiment of the present disclosure for solving the above problem comprises: forming preliminary channel patterns including a sacrificial layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on a substrate having an NMOS region and a PMOS region; removing the sacrificial layer within the PMOS region to form a first space, wherein the lower surface of the first silicon layer, the upper surface of the second silicon layer, and a first partial surface of the substrate are exposed within the first space; removing the sacrificial layer and the silicon germanium layer within the NMOS region to form a second space, wherein the lower and upper surfaces of the first silicon layer, the lower and upper surfaces of the second silicon layer, and a second partial surface of the substrate are exposed within the second space; and oxidizing the lower and upper surfaces of the first silicon layer, the lower and upper surfaces of the second silicon layer, and the second partial surface of the substrate exposed within the second space within the NMOS region to form a first silicon oxide layer, a second silicon oxide layer, and a substrate oxide layer. The method includes the step of removing the first silicon oxide layer, the second silicon oxide layer, and the substrate oxide layer to expand the second space into a third space; and the step of forming gate structures within the first space and the third space. Effects of the invention

[0014] According to embodiments of the present disclosure, the semiconductor device may have NMOS transistors and PMOS transistors having improved performance. Brief explanation of the drawing

[0016] FIG. 1 is a top view showing transistor structures of a semiconductor device according to one embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along lines II' and II-II' of FIG. 1 to show transistor structures of a semiconductor device according to one embodiment of the present disclosure. FIG. 3 to 16 are cross-sectional views taken along lines II' and II-II' of FIG. 1 to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIG. 17 to 27 are cross-sectional views taken along lines II' and II-II' of FIG. 1 to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIG. 28 to 33 are cross-sectional views taken along lines II' and II-II' of FIG. 1 to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIG. 34 to 37 are cross-sectional views taken along lines II' and II-II' of FIG. 1 to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. These are longitudinal sections. Specific details for implementing the invention

[0017] FIG. 1 is a top view showing transistor structures (100, 200) of a semiconductor device according to one embodiment of the present disclosure. Referring to FIG. 1, a semiconductor device according to one embodiment of the present disclosure may include an NMOS transistor structure (100) disposed within an NMOS region (NA) and a PMOS transistor structure (200) disposed within a PMOS region (PA). The NMOS transistor structure (100) may include an NMOS active region (ACTn) extending in a first horizontal direction (X) and an NMOS gate structure (GSn) extending in a second horizontal direction (Y). The NMOS active region (ACTn) may include an NMOS channel (CHn) overlapping with the NMOS gate structure (GSn) and NMOS source / drain regions (SDn) not overlapping with the NMOS gate structure (GSn). A PMOS transistor structure (200) may include a PMOS active region (ACTp) extending in a first horizontal direction (X) and a PMOS gate structure (GSp) extending in a second horizontal direction (Y). The PMOS active region (ACTp) may include a PMOS channel structure (CHp) that overlaps with the PMOS gate structure (GSp) and PMOS source / drain regions (SDp) that do not overlap with the PMOS gate structure (GSp). The first horizontal direction (X) and the second horizontal direction (Y) may be perpendicular.

[0018] FIG. 2 is a series of cross-sectional views taken along the lines II' and II-II' of FIG. 1 to show transistor structures (100, 200) of a semiconductor device according to one embodiment of the present disclosure.

[0019] Referring to FIG. 2, a semiconductor device according to one embodiment of the present disclosure may include an NMOS transistor structure (100) disposed within an NMOS region (NA) of a substrate (10) and a PMOS transistor structure (200) disposed within a PMOS region (PA).

[0020] The NMOS transistor structure (100) may include NMOS source / drain regions (SDn) formed on a substrate (10) of an NMOS region (NA), a plurality of NMOS channel patterns (20n), and a plurality of NMOS gate structures (40).

[0021] The NMOS source / drain regions (SDn) may include an N-type semiconductor layer. For example, the NMOS source / drain regions (SDn) may include silicon (Si:P) containing phosphorus (P).

[0022] A plurality of NMOS channel patterns (20n) and a plurality of NMOS gate structures (40) can be alternately and repeatedly stacked.

[0023] A plurality of NMOS channel patterns (20n) may each include a semiconductor pattern such as silicon.

[0024] A plurality of NMOS gate structures (40) may each include an NMOS interface insulating layer (41), an NMOS gate insulating layer (42), an NMOS gate barrier layer (43), an NMOS external gate electrode (44), and an NMOS internal gate electrode (45). The NMOS external gate electrode (44) may surround the top, bottom, and sides of the NMOS internal gate electrode (45). The NMOS gate barrier layer (43) may surround the top, bottom, and sides of the NMOS external gate electrode (44). The NMOS gate insulating layer (42) may surround the top, bottom, and sides of the NMOS gate barrier layer (43). The NMOS interface insulating layer (41) may surround the top, bottom, and sides of the NMOS gate insulating layer (42). The NMOS external gate electrode (44) of the topmost NMOS gate structure (40) can surround the bottom surface and sides of the NMOS internal gate electrode (45) in a U-shape. The NMOS gate barrier layer (43) of the topmost NMOS gate structure (40) can surround the bottom surface and sides of the NMOS external gate electrode (44) in a U-shape. The NMOS gate insulating layer (42) of the topmost NMOS gate structure (40) can surround the bottom surface and sides of the NMOS gate barrier layer (43) in a U-shape.

[0025] The NMOS interface insulating layer (41) may include oxidized silicon. For example, the NMOS interface insulating layer (41) may be formed by oxidizing the surfaces of the MOS channel patterns (20n) and the surfaces of the substrate (10).

[0026] The NMOS gate insulating layer (42) may include an insulating material containing hafnium (Hf) or zirconium (Zr), such as hafnium oxide (HfO), hafnium nitride oxide (HfON), hafnium silicon oxide (HfSiO), hafnium silicon nitride oxide (HfSiON), zirconium oxide (ZrO), zirconium nitride oxide (ZrON), zirconium silicon oxide (ZrSiO), zirconium silicon nitride oxide (ZrSiON), hafnium zirconium oxide (HfZrO), hafnium zirconium nitride oxide (HfZrON), hafnium zirconium silicon oxide (HfZrSiO), and hafnium zirconium silicon nitride oxide (HfZrSiON).

[0027] The NMOS gate barrier layer (43) may include a barrier metal such as titanium nitride (TiN).

[0028] The NMOS external gate electrode (44) may include a metal, a metal alloy, or a metal compound for controlling the work function of the NMOS. For example, the NMOS external gate electrode (44) may include titanium aluminum (TiAl).

[0029] The NMOS internal gate electrode (45) may include a metal or a metal compound. For example, the NMOS internal gate electrode (45) may include titanium nitride (TiN), tungsten (W), or various metal alloys.

[0030] The central part of the upper surface of the NMOS channel pattern (20n) in contact with the NMOS interface insulating layer (41) of the NMOS channel pattern (20n) located at the top, and the upper surface of the substrate (10) in contact with the NMOS interface insulating layer (41) of the NMOS channel pattern (20n) located at the bottom can be recessed.

[0031] The PMOS transistor structure (200) may include PMOS source / drain regions (SDp) formed on a substrate (10) of a PMOS region (PA), a plurality of PMOS channel patterns (20p), and a plurality of PMOS gate structures (50).

[0032] PMOS source / drain regions (SDp) may include a P-type semiconductor layer. For example, PMOS source / drain regions (SDp) may include silicon germanium (SiGe:B) containing boron (B).

[0033] A number of PMOS channel patterns (20p) and a number of PMOS gate structures (50) can be stacked alternately and repeatedly.

[0034] A plurality of PMOS channel patterns (20p) may each include a first silicon layer (22), a silicon germanium layer (23), and a second silicon layer (24) that are sequentially stacked.

[0035] A plurality of PMOS gate structures (50) may each include a PMOS interface insulating layer (51), a PMOS gate insulating layer (52), and a PMOS gate electrode (54). The PMOS gate insulating layer (52) may surround the top, bottom, and sides of the PMOS gate electrode (54). The PMOS interface insulating layer (51) may surround the top, bottom, and sides of the PMOS gate insulating layer (52). The PMOS gate insulating layer (52) of the topmost PMOS gate structure (50) may surround the bottom and sides of the PMOS gate electrode (54) in a U-shape.

[0036] The PMOS interface insulating layer (51) may include oxidized silicon. For example, the PMOS interface insulating layer (51) may be formed by oxidizing the lower surface of the first silicon layer (22) of each PMOS channel pattern (20p), the upper surface of the second silicon layer (24), the inner sides of the PMOS source / drain regions (SDp), and the upper surface of the substrate (10).

[0037] The PMOS gate insulating layer (52) may include a high dielectric insulating material containing hafnium (Hf) or zirconium (Zr), such as hafnium oxide (HfO), hafnium nitride oxide (HfON), hafnium silicon oxide (HfSiO), hafnium silicon nitride oxide (HfSiON), zirconium oxide (ZrO), zirconium nitride oxide (ZrON), zirconium silicon oxide (ZrSiO), zirconium silicon nitride oxide (ZrSiON), hafnium zirconium oxide (HfZrO), hafnium zirconium nitride oxide (HfZrON), hafnium zirconium silicon oxide (HfZrSiO), and hafnium zirconium silicon nitride oxide (HfZrSiON).

[0038] The PMOS gate electrode (54) may include a barrier metal such as titanium nitride (TiN). Since the PMOS gate electrode (54) includes a barrier metal, the gate barrier layer may be omitted. In another embodiment, the PMOS gate electrode (54) may include a PMOS gate barrier layer and a PMOS gate electrode. In yet another embodiment, the PMOS gate electrode (54) may include a PMOS gate barrier layer, a PMOS external gate electrode, and a PMOS internal gate electrode. The PMOS gate barrier layer may include a barrier metal layer. The PMOS external gate electrode may include a metal layer, a metal alloy layer, or a metal compound layer for controlling the work function of the PMOS.

[0039] The central portion of the upper surface of the second silicon layer (24) of the PMOS channel pattern (20p) in contact with the PMOS interface insulating layer (51) of the topmost PMOS gate structure (50) may be recessed. The surface of the substrate (10) in contact with the PMOS interface insulating layer (51) of the bottommost PMOS gate structure (50) may not be recessed.

[0040] The NMOS gate structure (40) may have a first gate thickness (TG1) in the vertical direction. The PMOS gate structure (50) may have a second gate thickness (TG2) in the vertical direction. The first gate thickness (TG1) may be thicker than the second gate thickness (TG2). Therefore, the resistance of the NMOS gate structure (40) may be lower than the resistance of the PMOS gate structure (50). Since the NMOS gate structure (40) includes more multilayer conductive layers than the PMOS gate structure (50), the first gate thickness (TG1) of the NMOS gate structure (40) may be thicker than the second gate thickness (TG2) of the PMOS gate structure (50).

[0041] The NMOS channel pattern (20n) may have a first channel thickness (TC1) in the vertical direction. The PMOS channel pattern (20p) may have a second channel thickness (TC2) in the vertical direction. The first channel thickness (TC1) may be thinner than the second channel thickness (TC2). The NMOS channel pattern (20n) may be single-layer. The PMOS channel pattern (20p) may be multi-layer. Accordingly, the second channel thickness (TC2) of the PMOS channel pattern (20p) may be thicker than the first channel thickness (TC1) of the NMOS channel pattern (20n). For example, the second silicon layer (24) of the NMOS channel pattern (20n) and the PMOS channel pattern (20p) may be formed at the same level. The first channel thickness (TC1) of the NMOS channel pattern (20n) may be smaller than the vertical thickness of the second silicon layer (24) of the PMOS channel pattern (20p). In the manufacturing process, the surface of the NMOS channel pattern (20n) may be oxidized and removed. The surface of the second silicon layer (24) of the PMOS channel pattern (20p) may not be removed.

[0042] The PMOS channel pattern (20p) may include silicon layers (22, 24) and a silicon germanium layer (23) interposed between the silicon layers (22, 24). Accordingly, the silicon layers (22, 24) of the PMOS channel pattern (20p) may be subjected to two-dimensional lattice stress by the silicon germanium layer (23). Thus, the carrier mobility of the PMOS channel pattern (20p) may be improved.

[0043] FIGS. 3 to 16 are cross-sectional views taken along the lines II' and II-II' of FIG. 1 to illustrate a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0044] Referring to FIG. 3, a method for manufacturing a semiconductor device according to one embodiment of the present disclosure may include performing deposition processes to repeatedly stack pre-channel layers (20a) on a substrate (10) having an NMOS region (NA) and a PMOS region (PA), the pre-channel layers (20a) comprising a sacrificial layer (21), a first silicon layer (22), a silicon germanium layer (23), and a second silicon layer (24) as a set. In this embodiment, three layers of pre-channel layers (20a) are shown, but four or more layers of pre-channel layers (20a) may be stacked. The sacrificial layer (21) may include germanium-rich silicon germanium. For example, the sacrificial layer (21) may include SixGey (0 < x < y, x + y = 1, where x and y are real numbers). That is, the sacrificial layer (21) may contain more germanium than silicon. In one embodiment, the sacrificial layer (21) may comprise 50% or more germanium (50% or less silicon). The first silicon layer (22) may comprise single-crystal silicon. The silicon germanium layer (23) may comprise silicon-rich silicon germanium. For example, the silicon germanium layer (23) may comprise SivGez (v > z > 0, v + z = 1, v and z are real numbers). In one embodiment, the silicon germanium layer (23) may comprise 75% or more silicon (25% or less germanium). The second silicon layer (24) may comprise single-crystal silicon. The sacrificial layer (21), the first silicon layer (22), the silicon germanium layer (23), and the second silicon layer (24) may each be formed by performing an epitaxial growth process. The sacrificial layer (21) may have a first thickness (t1) in the vertical direction. The first silicon layer (22) may have a second thickness (t2) in the vertical direction. The silicon germanium layer (23) may have a third thickness (t3) in the vertical direction. The second silicon layer (24) may have a fourth thickness (t4) in the vertical direction. The first thickness (t1) may be the thickest.The second thickness (t2) and the third thickness (t3) may be the thinnest. The second thickness (t2) and the third thickness (t3) may be similar. The fourth thickness (t4) may be intermediate between the first thickness (t1) and the second thickness (t2) (or the third thickness (t3)). In one embodiment, the first thickness (t1) may be about 8 to 12 nm, the second thickness (t2) and the third thickness (t3) may be about 2 to 5 nm, and the fourth thickness (t4) may be 6 to 10 nm.

[0045] Referring to FIG. 4, the method may further include performing a deposition process and an etching process to form dummy gate structures (30n, 30p) and spacers (34) on preliminary channel layers (20a), and performing a patterning process using the dummy gate structures (30n, 30p) and spacers (34) as an etching mask to form preliminary channel patterns (20b). The dummy gate structures (30n, 30p) may each include dummy gate electrodes (31n, 31p) and dummy gate capping layers (32n, 32p). The dummy gate electrodes (31n, 31p) may include polycrystalline silicon. The dummy gate capping layers (32n, 32p) and spacers (34) may have an etch selectivity ratio with silicon oxide. For example, the dummy gate capping layers (32n, 32p) and spacers (34) may comprise silicon nitride. In one embodiment, a buffer insulating layer may be further formed between the second silicon layer (24) of the top-most preliminary channel patterns (20b) and the dummy gate electrodes (30n, 30p). The buffer insulating layer may comprise silicon oxide, silicon nitride, or a combination thereof.

[0046] Referring to FIG. 5, the method may further include performing an epitaxial growth process and a deposition process to form source / drain regions (SDn, SDp) and an interlayer insulating layer (35). The source / drain regions (SDn, SDp) may include NMOS source / drain regions (SDn) and PMOS source / drain regions (SDp). The NMOS source / drain regions (SDn) may include silicon (Si:P) containing phosphorus (P). The PMOS source / drain regions (SDp) may include silicon germanium (SiGe:B) containing boron (B). The interlayer insulating layer (35) may include silicon oxide, silicon nitride, or a combination thereof. Forming the interlayer insulating layer (35) may include performing a deposition process or a spin coating process.

[0047] Referring to FIG. 6, the method may further include performing photolithography and etching processes to form a first mask pattern (M1) that covers an NMOS region (NA) and exposes a PMOS region (PA), and removing a PMOS dummy gate structure (30p) within the PMOS region (PA) to form a first gate trench (GT1) between spacers (34). The upper surface of the second silicon layer (24) of the top-most pre-channel pattern (20b) may be exposed within the first gate trench (GT1). The first mask pattern (M1) may comprise silicon oxide, silicon nitride, or a combination thereof. In another embodiment, the first mask pattern (M1) may comprise a polymeric organic material.

[0048] Referring to FIG. 7, the method may further include performing an etching process to remove a sacrificial layer (21) within a PMOS region (PA) to form first spaces (S1). Since the sacrificial layer (21) and the silicon germanium layer (23) have different silicon and germanium content ratios, they may have an etching selectivity ratio. Within the first spaces (S1), the upper surface of the substrate (10), the lower surface of the first silicon layer (22), the upper surface of the second silicon layer (24), and the inner surfaces of the PMOS source / drain regions (SDp) may be exposed. As the sacrificial layer (21) is removed, the preliminary channel pattern (20b) may be formed into a PMOS channel pattern (20p) comprising the first silicon layer (22), the silicon germanium layer (23), and the second silicon layer (24). The first spaces (S1) may have a first vertical width (W1) corresponding to the vertical thickness (t1) of the sacrificial layer (21) between the upper surface of the second silicon layer (24) and the lower surface of the first silicon layer (22).

[0049] Referring to FIG. 8, the method may further include performing an oxidation process to form a PMOS interface insulating layer (51) on the upper surface of the substrate (10) exposed within the first gate trench (GT1) and first spaces (S1) in the PMOS region (PA), the lower surface of the first silicon layer (22), the upper surface of the second silicon layer (24), and the inner surfaces of the PMOS source / drain regions (SDp). Accordingly, the PMOS interface insulating layer (51) may include an oxidized silicon layer.

[0050] Referring to FIG. 9, the method may further include performing deposition processes to form a PMOS gate insulating layer (52) and a PMOS gate electrode (54) on a PMOS interface insulating layer (51) in a first gate trench (GT1) and first spaces (S1) within a PMOS region (PA) to form a PMOS gate electrode structure (50). Forming the PMOS gate insulating layer (52) may include conformally forming a high dielectric insulating layer on the PMOS interface insulating layer (51). The high dielectric insulating layer may include an insulating material containing hafnium (Hf) or zirconium (Zr), such as hafnium oxide (HfO), hafnium nitride oxide (HfON), hafnium silicon oxide (HfSiO), hafnium silicon nitride oxide (HfSiON), zirconium oxide (ZrO), zirconium nitride oxide (ZrON), zirconium silicon oxide (ZrSiO), zirconium silicon nitride oxide (ZrSiON), hafnium zirconium oxide (HfZrO), hafnium zirconium nitride oxide (HfZrON), hafnium zirconium silicon oxide (HfZrSiO), and hafnium zirconium silicon nitride oxide (HfZrSiON). Forming the PMOS gate electrode (54) may involve performing a deposition process to form a metal compound, such as titanium nitride (TiN), on the PMOS gate insulating layer (52). The PMOS gate electrode (54) may completely fill the first spaces (S1). In another embodiment, forming the PMOS gate electrode (54) may include forming a multilayer metal layer, a metal alloy layer, or a metal compound layer. Within the NMOS region (NA), the PMOS gate insulating layer (52) and the PMOS gate electrode (54) may also be formed on the first mask pattern (M1).

[0051] Referring to FIG. 10, the method may further include performing an etching or planarization process to remove the PMOS gate insulating layer (52) and the PMOS gate electrode (54) on the interlayer insulating layer (35) within the PMOS region (PA), and performing a photolithography process to form a second mask pattern (M2) that covers the PMOS region (PA) and exposes the NMOS region (NA). The second mask pattern (M2) may include silicon oxide, silicon nitride, or a combination thereof. In another embodiment, the second mask pattern (M2) may include a polymeric organic material.

[0052] Referring to FIG. 11, the method may further include removing an NMOS dummy gate structure (30n) within an NMOS region (NA) to form a second gate trench (GT2). The upper surface of the second silicon layer (24) of the uppermost reserve channel pattern (20b) located within the second gate trench (GT2) may be exposed.

[0053] Referring to FIG. 12, the method may further include removing the sacrificial layer (21) and the silicon germanium layer (23) within the NMOS region (NA) to form second spaces (S2). The second spaces (S2) may be formed between the upper surface of the substrate (10) and the lower surface of the first silicon layer (22), between the upper surface of the first silicon layer (22) and the lower surface of the second silicon layer (24), and between the upper surface of the second silicon layer (24) and the lower surface of the first silicon layer (22). The upper surface of the substrate (10), the upper and lower surfaces of the first silicon layer (22), the upper and lower surfaces of the second silicon layer (24), and the inner surfaces of the NMOS source / drain regions (SDn) may be exposed within the second spaces (S2). The second spaces (S2) may also have a first vertical width (W1) corresponding to the vertical thickness (t1) of the sacrificial layer (21), in the same way as the first spaces (S1), between the upper surface of the second silicon layer (24) and the lower surface of the first silicon layer (22).

[0054] Referring to FIG. 13, the method may further include performing an oxidation process to form oxidized silicon layers (26, 27, 28, 29) on the surface of the substrate (10) exposed within the second spaces (S2) and the second gate trench (GT2), the surface of the first silicon layer (22), the surface of the second silicon layer (24), and the inner surfaces of the NMOS source / drain regions (SDn). For example, the first silicon layer (22) may be completely oxidized to form a first silicon oxide layer (26), a second silicon oxide layer (27) may be formed on the surface of the second silicon layer (24), a source / drain oxide layer (28) may be formed on the inner surfaces of the NMOS source / drain regions (SDn), and a substrate oxide layer (29) may be formed on the surface of the substrate (10).

[0055] Referring to FIG. 14, the method may further include performing an oxide removal process to remove all of the first silicon oxide layer (26), the second silicon oxide layer (27), the source / drain oxide layer (28), and the substrate oxide layer (29). As the first silicon oxide layer (26) is removed, the second spaces (S2) may be formed into third spaces (S3). Within the third spaces (S3), the surfaces of the second silicon layer (24), the inner surfaces of the NMOS source / drain regions (SDn), and the surface of the substrate (10) may be exposed. Referring again to FIG. 12, the second spaces (S2) may have a first vertical width (W1) corresponding to the thickness (t1) of the sacrificial layer (21), and the third spaces (S3) may have a second vertical width (W2) corresponding to the sum of the thickness (t1) of the sacrificial layer (21), the thickness (t2) of the first silicon layer (22), and the thickness (t3) of the silicon germanium layer (23). Thus, the second vertical width (W2) may be larger than the first vertical width (W1).

[0056] Referring to FIG. 15, the method may further include performing an oxidation process to form an NMOS interface insulating layer (41) on the surface of the second silicon layer (24) exposed within the third spaces (S3) of the NMOS region (NA), the surfaces of the NMOS source / drain regions (SDn), and the surface of the substrate (10). Accordingly, the NMOS interface insulating layer (41) may comprise an oxidized silicon layer.

[0057] Referring to FIG. 16, the method may further include performing deposition processes to form an NMOS gate insulating layer (42), an NMOS gate barrier layer (43), an NMOS external gate electrode (44), and an NMOS internal gate electrode (45) on an NMOS interface insulating layer (41) in a second gate trench (GT2) and third spaces (S3) within an NMOS region (NA). Forming the NMOS gate insulating layer (42) may include performing a deposition process to conformally form a high dielectric insulating layer on the NMOS interface insulating layer (41). The high dielectric insulating layer may comprise the same material as the PMOS gate insulating layer (52). Accordingly, the NMOS gate insulating layer (42) may include at least one of insulating materials containing hafnium (Hf) or zirconium (Zr), such as hafnium oxide (HfO), hafnium nitride oxide (HfON), hafnium silicon oxide (HfSiO), hafnium silicon nitride oxide (HfSiON), zirconium oxide (ZrO), zirconium nitride oxide (ZrON), zirconium silicon oxide (ZrSiO), zirconium silicon nitride oxide (ZrSiON), hafnium zirconium oxide (HfZrO), hafnium zirconium nitride oxide (HfZrON), hafnium zirconium silicon oxide (HfZrSiO), and hafnium zirconium silicon nitride oxide (HfZrSiON). Forming the NMOS gate barrier layer (43) may include performing a deposition process to conformally form a barrier metal layer, such as titanium nitride (TiN), on the NMOS gate surface insulating layer (42). Forming the NMOS external gate electrode (44) may include performing a deposition process to conformally form a work function controlling metal layer on the NMOS gate barrier layer (43). For example, the work function controlling metal layer may include a metal alloy such as titanium aluminum (TiAl).Forming the NMOS internal gate electrode (45) may include performing a deposition process to form a metal layer or a metal compound layer on the NMOS external gate electrode (44). For example, the NMOS internal gate electrode (45) may include titanium nitride (TiN) or tungsten (W), or various metal alloys. The NMOS internal gate electrode (45) may completely fill the third spaces (S3).

[0058] Subsequently, with reference to FIG. 2, the method may further include performing an etching process or a planarization process to remove the NMOS gate insulating layer (42), NMOS gate barrier layer (43), NMOS external gate electrode (44), and NMOS internal gate electrode (45) on the interlayer insulating layer (35) in the NMOS region (NA), removing the NMOS gate insulating layer (42), NMOS gate barrier layer (43), NMOS external gate electrode (44), NMOS internal gate electrode (45), and a second mask pattern (M2) on the interlayer insulating layer (35) in the PMOS region (PA), and performing a deposition process to form a gate capping layer (36) in the NMOS region (NA) and the PMOS region (PA). The gate capping layer (36) may include a silicon nitride-based material.

[0059] FIGS. 17 to 27 are cross-sectional views taken along lines II' and II-II' of FIG. 1 to illustrate a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0060] Referring to FIG. 17, a method for manufacturing a semiconductor device according to one embodiment of the present disclosure may further include performing the processes described with reference to FIGS. 3 to 5, performing photolithography and etching processes to form a first mask pattern (M1) that covers a PMOS region (PA) and exposes an NMOS region (NA), and removing an NMOS dummy gate structure (30n) within the NMOS region (NA) to form a first gate trench (GT1) between spacers (34). The upper surface of a second silicon layer (24) of a top-most pre-channel pattern (20b) may be exposed within the first gate trench (GT1). The first mask pattern (M1) may comprise silicon oxide, silicon nitride, or a combination thereof. In another embodiment, the first mask pattern (M1) may comprise a polymeric organic material.

[0061] Referring to FIG. 18, the method may further include performing an etching process to remove both the sacrificial layer (21) and the silicon germanium layer (23) within the NMOS region (NA) to form first spaces (S1). The first spaces (S1) may be formed between the upper surface of the substrate (10) and the lower surface of the first silicon layer (22), between the upper surface of the first silicon layer (22) and the lower surface of the second silicon layer (24), and between the upper surface of the second silicon layer (24) and the lower surface of the first silicon layer (22). Between the upper surface of the second silicon layer (24) and the lower surface of the first silicon layer (22), the first spaces (S1) may have a first vertical width (W1) corresponding to the vertical thickness (t1) of the sacrificial layer (21).

[0062] Referring to FIG. 19, the method may further include performing an oxidation process to oxidize a first silicon layer (22) exposed within the second spaces (S2) to form a first silicon oxide layer (26), forming a second silicon oxide layer (27) on the surface of the second silicon layer (24), oxidizing the surface of the NMOS source / drain regions (SDn) to form a source / drain oxide layer (28), and oxidizing the surface of the substrate (10) to form a substrate oxide layer (29).

[0063] Referring to FIG. 20, the method may further include performing an oxide removal process to remove all of the first silicon oxide layer (26), the second silicon oxide layer (27), the source / drain oxide layer (28), and the substrate oxide layer (29). Referring again to FIG. 18, the first spaces (S1) may have a first vertical width (W1) corresponding to the thickness (t1) of the sacrificial layer (21), and the second spaces (S2) may have a second vertical width (W2) corresponding to the sum of the thickness (t1) of the sacrificial layer (21), the thickness (t2) of the first silicon layer (22), and the thickness (t3) of the silicon germanium layer (23). Thus, the second vertical width (W2) may be larger than the first vertical width (W1).

[0064] Referring to FIG. 21, the method may further include performing an oxidation process to form an NMOS interface insulating layer (41) on the surface of the first silicon layer (22) exposed within the second spaces (S2) of the NMOS region (NA), the surfaces of the NMOS source / drain regions (SDn), and the surface of the substrate (10). The NMOS interface insulating layer (41) may comprise an oxidized silicon layer.

[0065] Referring to FIG. 22, the method may further include performing deposition processes to form an NMOS gate insulating layer (42), an NMOS gate barrier layer (43), an NMOS external gate electrode (44), and an NMOS internal gate electrode (45) on an NMOS interface insulating layer (41) in a first gate trench (GT1) and in second spaces (S2) within an NMOS region (NA). The NMOS gate insulating layer (42), the NMOS gate barrier layer (43), the NMOS external gate electrode (44), and the NMOS internal gate electrode (45) may also be formed on a first mask pattern (M1) within a PMOS region (PA).

[0066] Referring to FIG. 23, the method may further include performing a planarization process to remove the NMOS gate insulating layer (42), NMOS gate barrier layer (43), NMOS external gate electrode (44), and NMOS internal gate electrode (45) on the interlayer insulating layer (35) in the NMOS region (NA), the NMOS gate insulating layer (42), NMOS gate barrier layer (43), NMOS external gate electrode (44), and NMOS internal gate electrode (45) on the interlayer insulating layer (35) in the PMOS region (PA), and the first mask pattern (M1), and forming a second mask pattern (M2) that covers the NMOS region (NA) and exposes the PMOS region (PA).

[0067] Referring to FIG. 24, the method may further include removing a PMOS dummy gate structure (30p) within a PMOS region (PA) to form a second gate trench (GT2) between spacers (34). The upper surface of the second silicon layer (24) of the top-most reserve channel pattern (20n) may be exposed within the second gate trench (GT2).

[0068] Referring to FIG. 25, the method may further include performing an etching process to remove the sacrificial layer (21) within the PMOS region (PA) to form third spaces (S3). The third spaces (S3) may have a first vertical width (W1) corresponding to the vertical thickness (t1) of the sacrificial layer (21) between the upper surface of the second silicon layer (24) and the lower surface of the first silicon layer (22).

[0069] Referring to FIG. 26, the method may further include performing an oxidation process to form a PMOS interface insulating layer (51) on the surface of the first silicon layer (22), the surface of the second silicon layer (24), and the surfaces of the NMOS source / drain regions (SDn) exposed within the second gate trench (GT2) and the third spaces (S3) within the PMOS region (PA).

[0070] Referring to FIG. 27, the method may further include forming a PMOS gate structure (50) by performing deposition processes to form a PMOS gate insulating layer (52) and a PMOS gate electrode (54) on a PMOS interface insulating layer (51) in a second gate trench (GT2) and in third spaces (S3) within a PMOS region (PA). The PMOS gate insulating layer (52) and the PMOS gate electrode (54) may also be formed on a second mask pattern (M2) within an NMOS region (NA).

[0071] Subsequently, referring further to FIG. 2, the method may further include performing an etching process or a planarization process to remove the PMOS gate insulating layer (52) and PMOS gate electrode (54) on the interlayer insulating layer (35) in the PMOS region (PA), removing the PMOS gate insulating layer (52), PMOS gate electrode (54), and the second mask pattern (M2) on the interlayer insulating layer (35) in the NMOS region (NA), and performing a deposition process to form a gate capping layer (36) in the NMOS region (NA) and the PMOS region (PA). The gate capping layer (36) may include a silicon nitride-based material.

[0072] FIGS. 28 to 33 are cross-sectional views taken along the lines II' and II-II' of FIG. 1 to illustrate a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0073] Referring to FIG. 28, a method for manufacturing a semiconductor device according to one embodiment of the present disclosure may include performing processes described with reference to FIGS. 3 to 7 and FIGS. 17 to 20 to form a first gate trench (GT1) and second spaces (S2) within an NMOS region (NA), and forming a second gate trench (GT2) and third spaces (S3) within a PMOS region (PA).

[0074] Referring to FIG. 29, the method may further include forming interface insulating layers (41, 51) and gate insulating layers (42, 52) within second spaces (S2) and third spaces (S3). The interface insulating layers (41, 51) may include an NMOS interface insulating layer (41) formed within second spaces (S2) in an NMOS region (NA) and a PMOS interface insulating layer (51) formed within third spaces (S3) in a PMOS region (PA). The gate insulating layers (42, 52) may include an NMOS gate insulating layer (42) formed on an NMOS interface insulating layer (41) in an NMOS region (NA) and a PMOS gate insulating layer (52) formed on a PMOS interface insulating layer (51) in a PMOS region (PA). The NMOS interface insulating layer (41) and the PMOS interface insulating layer (51) can be formed by performing the same process simultaneously. The NMOS gate insulating layer (42) and the PMOS gate insulating layer (52) can also be formed by performing the same process simultaneously.

[0075] Referring to FIG. 30, the method may further include forming a PMOS gate structure (50) by performing the processes described with reference to FIG. 9. Forming the PMOS gate structure (50) may include forming a PMOS gate electrode (54). Within the NMOS region (NA), the PMOS gate electrode (54) may be formed on the NMOS gate insulating layer (42).

[0076] Referring to FIG. 31, the method may further include performing a planarization process to remove gate insulating layers (42, 52) and a PMOS gate electrode (54) on an interlayer insulating layer (35), and forming a third mask pattern (M3) that covers a PMOS region (PA) and exposes an NMOS region (NA). The third mask pattern (M3) may contain the same material as the first mask pattern (M1) and the second mask pattern (M2). The PMOS gate electrode (54) may be exposed within the NMOS region (NA).

[0077] Referring to FIG. 32, the method may further include removing the PMOS gate electrode (54) within the NMOS region (NA). By removing the PMOS gate electrode (54) within the NMOS region (NA), the second spaces (S2) may be formed into fourth spaces (S4).

[0078] Referring to FIG. 33, the method may further include forming an NMOS gate structure (40) within a first gate trench (GT1) and fourth spaces (S4) within an NMOS region (NA). Forming the NMOS gate structure (40) may include performing deposition processes to form an NMOS gate barrier layer (43), an NMOS external gate electrode (44), and an NMOS internal gate electrode (45).

[0079] Then, referring to FIG. 2, the method may further include performing a planarization process to remove a third mask pattern (M3), an NMOS gate barrier layer (43), an NMOS external gate electrode (44), and an NMOS internal gate electrode (45) on an interlayer insulating layer (35), and forming a gate capping layer (36).

[0080] FIGS. 34 to 37 are cross-sectional views taken along the lines II' and II-II' of FIG. 1 to illustrate a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0081] Referring to FIG. 34, a method for manufacturing a semiconductor device according to one embodiment of the present disclosure may further include performing processes described with reference to FIG. 2 to 7, FIG. 17 to 20, and FIG. 28 to 29 to form a first gate trench (GT1) and second spaces (S2) within an NMOS region (NA), and forming a second gate trench (GT2) and third spaces (S3) within a PMOS region (PA), and further performing processes described in FIG. 16 or FIG. 22 to form an NMOS gate barrier layer (43), an NMOS external gate electrode (44), and an NMOS internal gate electrode (45) on an NMOS gate insulating layer (42) within the first gate trench (GT1) and second spaces (S2) within the NMOS region (NA).

[0082] Referring to FIG. 35, the method may further include performing a planarization process to remove the NMOS gate insulating layer (42), NMOS gate barrier layer (43), NMOS external gate electrode (44), and NMOS internal gate electrode (45) on the interlayer insulating layer (35) in the NMOS region (NA), and the PMOS gate insulating layer (52), NMOS gate insulating layer (42), NMOS gate barrier layer (43), NMOS external gate electrode (44), NMOS internal gate electrode (45), and the third mask pattern (M3) on the interlayer insulating layer (35) in the PMOS region (PA), and forming a fourth mask pattern (M4) that covers the NMOS region (NA) and exposes the PMOS region (PA).

[0083] Referring to FIG. 36, the method may further include removing the NMOS gate barrier layer (43), the NMOS external gate electrode (44), and the NMOS internal gate electrode (45) within the PMOS region (PA) to form fourth spaces (S4).

[0084] Referring to FIG. 37, the method may further include forming a PMOS gate electrode (54) in fourth spaces (S4) within a PMOS region (PA). The PMOS gate electrode (54) may also be formed on a fourth mask pattern (M4) within an NMOS region (NA).

[0085] Then, referring to FIG. 2, the method may further include performing a planarization process to remove the fourth mask pattern (M4), NMOS gate barrier layer (43), NMOS external gate electrode (44), and NMOS internal gate electrode (45) on the interlayer insulating layer (35), and forming a gate capping layer (36).

[0086] Although the technical concept of the present invention has been specifically described according to the preferred embodiments above, it should be noted that the above-mentioned embodiments are for illustrative purposes only and are not intended to be limiting. Furthermore, a person skilled in the art will understand that various embodiments are possible within the scope of the technical concept of the present invention. Explanation of the symbols

[0088] 100: NMOS transistor structure 200: PMOS transistor structure 10: Substrate 20a: Pre-channel layer 20b: Pre-channel pattern 20n: NMOS channel pattern 20p: PMOS channel pattern 21: Sacrificial layer 22: First silicon layer 23: Silicon germanium layer 24: Second silicon layer 26: First silicon oxide layer 27: Second silicon oxide layer 28: Source / drain oxide layer 29: Substrate oxide layer 30n, 30p: Dummy gate structure 31: Dummy gate electrode 32: Dummy gate capping layer 34: Spacer 35: Interlayer insulating layer 36: Gate capping layer 40: NMOS gate structure 41: NMOS interface insulating layer 42: NMOS gate insulating layer 43: NMOS gate barrier layer 44: NMOS external gate electrode 45: NMOS internal gate electrode 50: PMOS gate structure 51: PMOS interface insulating layer 54: PMOS gate electrode SDn: NMOS source / drain region SDp: PMOS source / drain region M1-M4: 1st-4th mask patterns GT1, GT2: Gate trench S1, S2, S3, S4: Space

Claims

Claim 1 A semiconductor device comprising: an NMOS transistor structure formed on an NMOS region of a substrate; and a PMOS transistor structure formed on a PMOS region of the substrate, wherein the NMOS transistor structure comprises: NMOS source / drain regions formed on the substrate; and NMOS channel patterns and NMOS gate structures alternately and repeatedly stacked on the substrate between the NMOS source / drain regions; and wherein the PMOS transistor structure comprises: PMOS source / drain regions formed on the substrate; and PMOS channel patterns and PMOS gate structures alternately and repeatedly stacked on the substrate between the PMOS source / drain regions, wherein each of the NMOS channel patterns comprises a single silicon layer, and each of the PMOS channel patterns comprises silicon layers and a silicon germanium layer, wherein the silicon layers of each of the PMOS channel patterns comprise a first silicon layer and a second silicon layer, and the silicon germanium layer of each of the PMOS channel patterns is interposed between the first silicon layer and the second silicon layer. Claim 2 delete Claim 3 A semiconductor device according to claim 1, wherein the silicon layer of each NMOS channel pattern and the second silicon layer of each PMOS channel pattern are located at the same level, and the vertical thickness of the silicon layer of each NMOS channel pattern is thinner than the vertical thickness of the second silicon layer of each PMOS channel pattern. Claim 4 A semiconductor device according to claim 1, wherein each of the above NMOS gate structures comprises an NMOS interface insulating layer, an NMOS gate insulating layer, an NMOS gate barrier layer, an NMOS external gate electrode, and an NMOS internal gate electrode, and each of the above PMOS gate structures comprises a PMOS interface insulating layer, a PMOS gate insulating layer, and a PMOS gate electrode. Claim 5 A semiconductor device according to claim 4, wherein the NMOS interface insulating layer and the PMOS interface insulating layer comprise the same material, the NMOS gate insulating layer and the PMOS gate insulating layer comprise the same material, the NMOS gate barrier layer and the PMOS gate electrode comprise the same material, and the NMOS external gate electrode comprises an NMOS work function controlling metal. Claim 6 In claim 4, each of the above NMOS interface insulating layers is conformally formed on the upper and lower surfaces of the NMOS channel patterns, the inner surfaces of the NMOS source / drain regions, and the first surface of the substrate, and each of the above PMOS interface insulating layers is conformally formed on the upper and lower surfaces of the PMOS channel patterns, the inner surfaces of the PMOS source / drain regions, and the second surface of the substrate, and the first surface of the substrate on which the NMOS interface insulating layer is formed is recessed compared to the second surface of the substrate on which the PMOS interface insulating layer is formed. Claim 7 A semiconductor device according to claim 1, wherein the vertical thickness of each of the NMOS channel patterns is smaller than the vertical thickness of each of the PMOS channel patterns. Claim 8 A semiconductor device according to claim 1, wherein the vertical thickness of each of the NMOS gate structures is greater than the vertical thickness of each of the PMOS gate structures. Claim 9 A semiconductor device comprising: an NMOS transistor structure formed on an NMOS region of a substrate; and a PMOS transistor structure formed on a PMOS region of the substrate, wherein the NMOS transistor structure comprises: NMOS source / drain regions formed on the substrate; and a plurality of NMOS channel patterns and a plurality of NMOS gate structures alternately and repeatedly stacked between the NMOS source / drain regions, and the PMOS transistor structure comprises: PMOS source / drain regions formed on the substrate; and a plurality of PMOS channel patterns and a plurality of PMOS gate structures alternately and repeatedly stacked between the PMOS source / drain regions, wherein the vertical thickness of each NMOS channel pattern is smaller than the vertical thickness of each PMOS channel pattern, and the vertical thickness of each NMOS gate structure is larger than the vertical thickness of each PMOS gate structure. Claim 10 A semiconductor device according to claim 9, wherein each of the above NMOS channel patterns comprises a single layer of silicon, and each of the above PMOS channel patterns comprises a silicon layer and a silicon germanium layer. Claim 11 In claim 10, the silicon layer of each of the above PMOS channel patterns comprises a first silicon layer and a second silicon layer, and the silicon germanium layer is interposed between the first silicon layer and the second silicon layer. Claim 12 In claim 9, each of the above NMOS gate structures comprises an NMOS interface insulating layer, an NMOS gate insulating layer, an NMOS gate barrier layer, an NMOS external gate electrode, and an NMOS internal gate electrode, and each of the above PMOS gate structures comprises a PMOS interface insulating layer, a PMOS gate insulating layer, and a PMOS gate electrode, a semiconductor device. Claim 13 A semiconductor device according to claim 12, wherein the NMOS interface insulating layer and the PMOS interface insulating layer comprise an oxidized silicon layer, the NMOS gate insulating layer and the PMOS gate insulating layer comprise an insulating layer comprising hafnium or zirconium, the NMOS gate barrier layer and the PMOS gate electrode comprise titanium nitride (TiN), and the NMOS internal gate electrode comprises a metal alloy or metal compound comprising aluminum. Claim 14 In claim 12, each of the above NMOS interface insulating layers is conformally formed on the upper and lower surfaces of the NMOS channel patterns, the inner surfaces of the NMOS source / drain regions, and a first surface of the substrate, and each of the above PMOS interface insulating layers is conformally formed on the upper and lower surfaces of the PMOS channel patterns, the inner surfaces of the PMOS source / drain regions, and a second surface of the substrate, and the first surface of the substrate on which the NMOS interface insulating layer is formed is recessed compared to the second surface of the substrate on which the PMOS interface insulating layer is formed. Claim 15 A method for manufacturing a semiconductor device comprising: stacking pre-channel patterns including a sacrificial layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on a substrate having an NMOS region and a PMOS region; removing the sacrificial layers of the pre-channel patterns within the PMOS region to form first spaces; forming PMOS gate structures within the first spaces; removing the sacrificial layers and the silicon germanium layer of the pre-channel patterns within the NMOS region to form second spaces; oxidizing the surfaces of the first silicon layers and the second silicon layers to form first silicon oxide layers and second silicon oxide layers; removing the first silicon oxide layers and the second silicon oxide layers to expand the second spaces into third spaces; and forming NMOS gate structures within the third spaces. Claim 16 A method for manufacturing a semiconductor device according to claim 15, wherein each of the above sacrificial layers comprises silicon germanium, and each of the above sacrificial layers has a germanium content higher than that of the silicon germanium layer. Claim 17 A method for manufacturing a semiconductor device according to claim 16, wherein each of the above sacrificial layers contains more germanium than silicon, and each of the above silicon germanium layers contains more silicon than germanium. Claim 18 A method for manufacturing a semiconductor device according to claim 15, wherein the step of forming the preliminary channel patterns comprises: stacking preliminary channel layers including the sacrificial layer, the first silicon layer, the silicon germanium layer, and the second silicon layer on the substrate; forming an NMOS dummy gate structure and a PMOS dummy gate structure on the stacked preliminary channel layers; and patterning the stacked preliminary channel layers using the NMOS dummy gate structure and the PMOS dummy gate structure as an etching mask. Claim 19 A method for manufacturing a semiconductor device according to claim 18, wherein the step of forming the first spaces comprises: forming a first mask pattern that covers the NMOS region and exposes the PMOS region; performing an etching process using the first mask pattern as an etching mask to remove the PMOS dummy gate structure; and removing the sacrificial layers. Claim 20 A method for manufacturing a semiconductor device according to claim 19, wherein the step of forming the second spaces further comprises: forming a second mask pattern that covers the PMOS region and exposes the NMOS dummy gate structure; and performing an etching process using the second mask pattern as an etching mask to remove the NMOS dummy gate structure. Claim 21 A method for manufacturing a semiconductor device according to claim 20, wherein the step of extending the second spaces into the third spaces comprises: oxidizing the surfaces of the first silicon layers, the surfaces of the second silicon layers, and the surface of the substrate exposed within the second spaces to form the first silicon oxide layers, the second silicon oxide layers, and the substrate oxide layer, respectively; and removing the first silicon oxide layers, the second silicon oxide layers, and the substrate oxide layer. Claim 22 A method for manufacturing a semiconductor device according to claim 15, wherein the step of forming the PMOS gate structures comprises: conformally forming PMOS interface insulating layers on the surfaces of the first silicon layers exposed within the first spaces, the surfaces of the second silicon layers, and the surface of the substrate; conformally forming PMOS gate insulating layers on the PMOS interface insulating layers; and forming PMOS gate electrodes that fill the first spaces on the PMOS gate insulating layers. Claim 23 A method for manufacturing a semiconductor device according to claim 22, wherein the step of forming the PMOS interface insulating layers comprises performing an oxidation process to oxidize the surfaces of the first silicon layers, the surfaces of the second silicon layers, and the surface of the substrate, the step of forming the PMOS gate insulating layers comprises performing a deposition process to conformally form an insulating layer comprising hafnium or zirconium, and the step of forming the PMOS gate electrodes comprises performing a deposition process to fill the first spaces with a metal or metal oxide comprising titanium. Claim 24 A method for manufacturing a semiconductor device according to claim 22, wherein the step of forming the NMOS gate structures comprises: forming NMOS interface insulating layers on the surfaces of the second silicon layers exposed within the third spaces and on the surface of the substrate; conformally forming NMOS gate insulating layers on the NMOS interface insulating layers; conformally forming NMOS gate barrier layers on the NMOS gate insulating layers; conformally forming NMOS external gate electrodes on the NMOS gate barrier layers; and forming NMOS internal gate electrodes on the NMOS external gate electrodes to fill the third spaces. Claim 25 A method for manufacturing a semiconductor device according to claim 24, wherein the step of forming the NMOS interface insulating layers comprises performing an oxidation process to oxidize the surfaces of the second silicon layers and the surface of the substrate, the step of forming the NMOS gate insulating layers comprises performing a deposition process to conformally form an insulating layer comprising hafnium or zirconium, and the step of forming the PMOS gate electrodes comprises performing a deposition process to fill the third spaces with a metal comprising titanium or a metal oxide. Claim 26 A method for manufacturing a semiconductor device comprising: stacking pre-channel patterns including a sacrificial layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on a substrate having an NMOS region and a PMOS region; removing the sacrificial layers and the silicon germanium layer of the pre-channel patterns within the NMOS region to form first spaces; oxidizing the surfaces of the first silicon layers and the second silicon layers exposed within the first spaces to form first silicon oxide layers and second silicon oxide layers; removing the first silicon oxide layers and the second silicon oxide layers to expand the first spaces into second spaces; forming NMOS gate structures within the second spaces; removing the sacrificial layers of the pre-channel patterns within the PMOS region to form third spaces; and forming PMOS gate structures within the third spaces. Claim 27 A method for manufacturing a semiconductor device according to claim 26, wherein each of the above sacrificial layers comprises silicon germanium, and each of the above sacrificial layers has a germanium content higher than that of the silicon germanium layer. Claim 28 A method for manufacturing a semiconductor device according to claim 27, wherein each of the above sacrificial layers contains more germanium than silicon, and each of the above silicon germanium layers contains more silicon than germanium. Claim 29 A method for manufacturing a semiconductor device according to claim 26, wherein the step of forming the preliminary channel patterns comprises: stacking preliminary channel layers including the sacrificial layer, the first silicon layer, the silicon germanium layer, and the second silicon layer on the substrate; forming an NMOS dummy gate structure and a PMOS dummy gate structure on the stacked preliminary channel layers; and patterning the stacked preliminary channel layers using the NMOS dummy gate structure and the PMOS dummy gate structure as an etching mask. Claim 30 A method for manufacturing a semiconductor device according to claim 29, wherein the step of forming the first spaces comprises: forming a first mask pattern that covers the PMOS region and exposes the NMOS region; performing an etching process using the first mask pattern as an etching mask to remove the NMOS dummy gate structure; and removing the sacrificial layers and the silicon germanium layers. Claim 31 A method for manufacturing a semiconductor device according to claim 30, wherein the step of expanding the first spaces into the second spaces comprises: oxidizing the surfaces of the first silicon layers, the surfaces of the second silicon layers, and the surface of the substrate exposed within the first spaces to form the first silicon oxide layers, the second silicon oxide layers, and the substrate oxide layer, respectively; and performing the step of removing the first silicon oxide layers, the second silicon oxide layers, and the substrate oxide layer. Claim 32 A method for manufacturing a semiconductor device according to claim 30, wherein the step of forming the third spaces further comprises: forming a second mask pattern that covers the NMOS region and exposes the PMOS dummy gate structure; performing an etching process using the second mask pattern as an etching mask to remove the NMOS dummy gate structure; and removing the sacrificial layers. Claim 33 A method for manufacturing a semiconductor device according to claim 26, wherein the step of forming the PMOS gate structures comprises: conformally forming PMOS interface insulating layers on the surfaces of the first silicon layers exposed within the first spaces, the surfaces of the second silicon layers, and the surface of the substrate; conformally forming PMOS gate insulating layers on the PMOS interface insulating layers; and forming PMOS gate electrodes that fill the first spaces on the PMOS gate insulating layers. Claim 34 A method for manufacturing a semiconductor device according to claim 33, wherein the step of forming the PMOS interface insulating layers comprises performing an oxidation process to oxidize the surfaces of the first silicon layers, the surfaces of the second silicon layers, and the surface of the substrate; the step of forming the PMOS gate insulating layers comprises performing a deposition process to conformally form an insulating layer comprising hafnium or zirconium; and the step of forming the PMOS gate electrodes comprises performing a deposition process to fill the first spaces with a metal or metal oxide comprising titanium. Claim 35 A method for manufacturing a semiconductor device according to claim 33, wherein the step of forming the NMOS gate structures comprises: forming NMOS interface insulating layers on the surfaces of the second silicon layers exposed within the third spaces and on the surface of the substrate; conformally forming NMOS gate insulating layers on the NMOS interface insulating layers; conformally forming NMOS gate barrier layers on the NMOS gate insulating layers; conformally forming NMOS external gate electrodes on the NMOS gate barrier layers; and forming NMOS internal gate electrodes on the NMOS external gate electrodes to fill the third spaces. Claim 36 A method for manufacturing a semiconductor device according to claim 35, wherein the step of forming the NMOS interface insulating layers comprises performing an oxidation process to oxidize the surfaces of the second silicon layers and the surface of the substrate, the step of forming the NMOS gate insulating layers comprises performing a deposition process to conformally form an insulating layer comprising hafnium or zirconium, and the step of forming the PMOS gate electrodes comprises performing a deposition process to fill the third spaces with a metal comprising titanium or a metal oxide. Claim 37 A step of forming preliminary channel patterns including a sacrificial layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on a substrate having an NMOS region and a PMOS region; a step of removing the sacrificial layer within the PMOS region to form a first space, wherein the lower surface of the first silicon layer, the upper surface of the second silicon layer, and a first partial surface of the substrate are exposed within the first space; a step of removing the sacrificial layer and the silicon germanium layer within the NMOS region to form a second space, wherein the lower and upper surfaces of the first silicon layer, the lower and upper surfaces of the second silicon layer, and a second partial surface of the substrate are exposed within the second space; a step of oxidizing the lower and upper surfaces of the first silicon layer, the lower and upper surfaces of the second silicon layer, and the second partial surface of the substrate exposed within the second space within the NMOS region to form a first silicon oxide layer, a second silicon oxide layer, and a substrate oxide layer; and a step of removing the first silicon oxide layer, the second silicon oxide layer, and the substrate oxide layer to make the second space a third space. A method for manufacturing a semiconductor device comprising: a step of expanding; and a step of forming gate structures within the first space and the third space. Claim 38 A method for manufacturing a semiconductor device according to claim 37, wherein the gate structures include an NMOS gate structure and a PMOS gate structure, and the step of forming the NMOS gate structure comprises: forming an NMOS interface insulating layer conformally on the lower and upper surfaces of the second silicon layer exposed within the third space and on the second partial surface of the substrate; forming an NMOS gate insulating layer conformally on the NMOS interface insulating layer; forming an NMOS gate barrier layer conformally on the NMOS gate insulating layer; and forming an NMOS gate electrode that fills the third space on the NMOS gate barrier layer. Claim 39 A method for manufacturing a semiconductor device according to claim 38, wherein the step of forming the NMOS gate electrode comprises: forming an NMOS external gate electrode conformally on the NMOS gate barrier layer; and forming an NMOS internal gate electrode that fills the third space on the NMOS external gate electrode. Claim 40 A method for manufacturing a semiconductor device according to claim 38, wherein the step of forming the PMOS gate structure comprises: forming a PMOS interface insulating layer conformally on the lower surface of the first silicon layer exposed within the first space, the upper surface of the second silicon layer, and the first partial surface of the substrate; forming a PMOS gate insulating layer conformally on the PMOS interface insulating layer; and forming a PMOS gate electrode that fills the first space on the PMOS gate insulating layer. Claim 41 A method for manufacturing a semiconductor device according to claim 37, wherein each of the above sacrificial layers comprises silicon germanium, and each of the above sacrificial layers has a germanium content higher than that of the silicon germanium layer. Claim 42 A method for manufacturing a semiconductor device according to claim 41, wherein each of the above sacrificial layers contains more germanium than silicon, and each of the above silicon germanium layers contains more silicon than germanium. Claim 43 delete

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