Memory and operation method of memory

Abstract

A method of operating memory may include the steps of: receiving an active command and a row address; confirming that a part of a column of a first row corresponding to the row address has been replaced with a part of a second row; activating the first row and the second row; confirming the activation of a random pulse; and, in response to the activation of the random pulse, randomly selecting one of the row address corresponding to the first row and the row address corresponding to the second row and sampling it to a sampling address.

Description

Technology Field

[0001] This patent document relates to memory. Background Technology

[0003] As the density of memory increases, the spacing between multiple word lines contained in memory is decreasing. As the spacing between word lines decreases, the coupling effect between adjacent word lines is increasing.

[0004] Meanwhile, whenever data is input or output to a memory cell, the word line toggles between an active state and an inactive state. As described above, as the coupling effect between adjacent word lines increases, data in memory cells connected to word lines adjacent to frequently active word lines is being corrupted. This phenomenon is called row hammering, and it is becoming a problem because data in memory cells is corrupted before the memory cells are refreshed due to word line disturbance.

[0006] Figure 1 is a drawing for explaining row hammering and shows a part of a cell array included in a memory device.

[0007] In FIG. 1, 'WLL' corresponds to a word line with a high number of activations, and 'WLL-1' and 'WLL+1' correspond to word lines placed adjacent to 'WLL', i.e., word lines adjacent to the word line in terms of activation count. Also, 'CL' represents a memory cell connected to 'WLL', 'CL-1' represents a memory cell connected to 'WLL-1', and 'CL+1' represents a memory cell connected to 'WLL+1'. Each memory cell includes a cell transistor (TL, TL-1, TL+1) and a cell capacitor (CAPL, CAPL-1, CAPL+1).

[0008] In Figure 1, when 'WLL' is activated or deactivated, the voltage of 'WLL-1' and 'WLL+1' rises or falls due to the coupling phenomenon occurring between 'WLL' and 'WLL-1' and 'WLL+1', which also affects the charge amount of the cell capacitors (CL-1, CL+1). Therefore, if the activation of 'WLL' occurs frequently and 'WLL' toggles between the activated state and the deactivated state, the change in the amount of charge stored in the cell capacitors (CAPL-1, CAPL+1) included in 'CL-1' and 'CL+1' increases, and the data of the memory cell may degrade.

[0009] In addition, electromagnetic waves generated as the word line toggles between the active and inactive states damage data by causing electrons to flow into or out of the cell capacitor of a memory cell connected to an adjacent word line.

[0010] Row hammering is primarily caused by attacks from outside of memory, such as those by hackers. As a countermeasure against row hammering attacks, a method is used to randomly sample active rows and refresh adjacent rows of the sampled rows. This method is used because randomly sampled rows are likely to be excessively active. The problem to be solved

[0012] Embodiments of the present invention can provide a technique to counter row hammering attacks applied to memory. means of solving the problem

[0014] A method of operating a memory according to an embodiment of the present invention may include: receiving an active command and a row address; confirming that a part of a column of a first row corresponding to the row address has been replaced with a part of a second row; activating the first row and the second row; confirming the activation of a random pulse; and in response to the activation of the random pulse, randomly selecting one of the row address corresponding to the first row and the row address corresponding to the second row and sampling it as a sampling address.

[0015] A method of operating a memory according to another embodiment of the present invention may include: a cell array comprising a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a repair circuit that stores information regarding one or more defective rows in which some columns among the plurality of rows have defects, and if an active address corresponds to one of the one or more defective rows, activates a repair signal and provides an additional active address that specifies a row to be additionally activated; a random pulse generation circuit that generates a randomly activated random pulse signal; and a sampling circuit that samples and stores the active address when the active signal and the random pulse signal are activated and the repair signal is deactivated, and randomly samples and stores one of the active address and the additional active address when the active signal, the random pulse signal, and the repair signal are activated. Effects of the invention

[0017] According to embodiments of the present invention, it is possible to efficiently respond to low hammering attacks. Brief explanation of the drawing

[0019] FIG. 1 is a drawing for explaining low hammering. FIGS. 2 and FIGS. 3 are diagrams for explaining the repair operation of memory. FIG. 4 is a configuration diagram of a memory (400) according to an embodiment of the present invention. FIG. 5 is a configuration diagram of an exemplary embodiment of the sampling circuit (445) of FIG. 4. FIG. 6 is a timing diagram illustrating the operation of the memory (400) of FIG. 4. Specific details for implementing the invention

[0020] Hereinafter, in order to provide a detailed explanation that enables a person skilled in the art to easily implement the technical concept of the present invention, the most preferred embodiment of the present invention will be described with reference to the accompanying drawings. In describing the present invention, known components unrelated to the gist of the invention may be omitted. It should be noted that in assigning reference numbers to the components of each drawing, identical components are assigned the same number as much as possible, even if they are shown in different drawings.

[0022] Figures 2 and 3 are diagrams for explaining the repair operation of memory.

[0023] Figure 2 illustrates a general row repair scheme. In the case where some memory cells of row 50 (wordline) in the cell array are defective, row 50 can be replaced with row 2130. In this case, since row 50 is completely replaced by row 2130, row 50 is not activated during the active operation, and row 2130 is activated in place of row 50. If the memory controller commands the active operation for row 50 multiple times, row 2130 is activated multiple times in memory, and row 2129 and row 2130, which are adjacent rows to row 2130, are subjected to row hammering attacks. Therefore, during the smart refresh operation to prepare for row hammering attacks, a refresh operation for the adjacent rows of row 2130 is performed.

[0024] Figure 3 illustrates a paired row repair scheme. In the case where there is a defect in the memory cells (indicated by hatching) of columns 255 through 511 of row 50 in the cell array, the memory cells of columns 255 through 511 of row 50 can be replaced with the memory cells of columns 255 through 511 of row 2130. In this case, since only some columns of row 50 are replaced with some columns of row 2130, row 50 and row 2130 can be activated simultaneously during the active operation of row 50. During a read or write operation after activation, if columns 255 through 511 are selected, the memory cells of row 2130 are accessed, and if the remaining columns are selected, the memory cells of row 50 are accessed. For example, after row 50 and row 2130 are simultaneously active, if a write operation for column 3 is commanded, data is written to the memory cell of column 3 of row 50, and if a read operation for column 270 is commanded, data can be read from the memory cell of column 270 of row 2130.

[0025] When using a paired row repair scheme, if the memory controller commands an active operation for row 50 multiple times, rows 49 and 51, which are adjacent to row 50, and rows 2129 and 2131, which are adjacent to row 2130, will be subjected to row hammering attacks in memory. Therefore, it may be difficult to respond to row hammering attacks.

[0027] FIG. 4 is a configuration diagram of a memory (400) according to an embodiment of the present invention.

[0028] Referring to FIG. 4, the memory (400) may include a command address receiving circuit (401), a data transmission and reception circuit (403), a command decoder (410), an address control circuit (421), an address counter (423), a repair circuit (430), a random pulse generation circuit (441), a counter circuit (443), a sampling circuit (445), a smart refresh circuit (450), a cell array (460), a row circuit (470), and a column circuit (480).

[0029] The command address receiving circuit (401) can receive a command and an address (CA). Depending on the type of memory (400), the command and the address may be input to the same input terminals or to separate input terminals; however, the case where the command and the address are input to the same input terminals is exemplified here. The command and the address (CA) may be multi-bit.

[0030] The data transmission and reception circuit (403) can receive data (DATA) or transmit data (DATA). During a write operation, the data transmission and reception circuit (403) can receive data (DATA) to be written to the cell array (460) from the memory controller, and during a read operation, transmit data (DATA) read from the cell array (460) to the memory controller.

[0031] The command decoder (410) can decode the command and address (CA) to determine the type of operation that the memory controller instructs the memory (400) to generate internal command signals (ACT, PCG, REF, WR, RD, SR). The active signal (ACT) is a signal that is activated when an active operation is instructed, and the precharge signal (PCG) may be a signal that is activated when a precharge operation is instructed. The refresh signal (REF) may be a signal that is activated when an (auto) refresh operation is instructed. The write signal (WR) may be a signal that is activated when a write operation is instructed, and the read signal (RD) may be a signal that is activated when a read operation is instructed. And the smart refresh signal (SR) may be a signal that is activated when a smart refresh operation is instructed. Here, the smart refresh signal (SR) is exemplified as being activated when the memory controller instructs a smart refresh operation, but the smart refresh signal (SR) may also be activated when the memory (400) itself determines that a smart refresh operation is necessary.

[0032] The address control circuit (421) can classify the address received from the command decoder (410) into a row address (R_ADD) and a column address (C_ADD). The address control circuit (421) can classify the received address into a row address (R_ADD) when an active operation is indicated as a decoding result of the command decoder (410), and classify the received address into a column address (C_ADD) when a read and write operation is indicated. The row address (R_ADD) is also called an active address because it is an address that specifies the row to which the active operation will be performed.

[0033] The address counter (423) can generate a refresh address (REF_ADD) to be used for a refresh operation. The address counter (423) can change the refresh address (REF_ADD) by +1 each time the refresh signal (REF) is activated. Since the refresh address (REF_ADD) is changed each time the refresh signal (REF) is activated, the rows of the cell array (460) can be refreshed sequentially.

[0034] The repair circuit (430) can store information regarding defective rows among the rows of the cell array (460). Here, the information regarding defective rows may include (1) a list of defective rows, (2) which columns in the defective rows are defective, and (3) which row is to be additionally activated to replace some columns of the defective rows.

[0035] The repair circuit (430) can check whether the row corresponding to the row address (R_ADD) is a defective row during an active operation in which the active signal (ACT) is activated, and can activate the repair signal (REP) if the row corresponding to the row address (R_ADD) is a defective row. Additionally, when the repair signal (REP) is activated, it can provide an additional active address (ADDITIONAL_ADD) to the row circuit (470) to specify additional rows to be activated. Additionally, when the repair signal (REP) is activated, it can provide information (DEFECT_COL) regarding which columns are defective in the defective row to the column circuit (480).

[0036] The random pulse generation circuit (441) can generate a randomly activated random pulse signal (RANDOM). The activation period and the length of the activation interval (pulse width) of the random pulse signal (RANDOM) can be changed randomly. The random pulse generation circuit (441) may be a PRBS generator (Pseudorandom Binary Sequence Generator).

[0037] The counter circuit (443) can count the number of times the active signal (ACT) is activated during the period in which the random pulse signal (RANDOM) is activated. The counter circuit (443) generates an even / odd signal (EVEN / ODD), which may be a signal whose level changes whenever the active signal (ACT) is activated during the period in which the random pulse signal (RANDOM) is activated. The even / odd signal (EVEN / ODD) may be a signal indicating whether the active signal (ACT) is activated an even number of times or an odd number of times during the activation period of the random pulse signal (RANDOM). Since the logic level of the even / odd signal (EVEN / ODD) is influenced by the activation timing and number of times the random pulse signal (RANDOM) and the active signal (ACT) have random periods and pulse widths, the logic level of the even / odd signal (EVEN / ODD) can be considered to be determined randomly. The counter circuit (443) may be a 1-bit counter that is activated by a random pulse signal (RANDOM) and counts the number of times the active signal (ACT) is activated.

[0038] The sampling circuit (445) can sample and store a row address (R_ADD) when the repair signal (REP) is disabled and the active signal (ACT) and random pulse signal (RANDOM) are enabled. Since the random pulse signal (RANDOM) is a signal that is randomly enabled, one of the row addresses where active operations have been performed can be randomly selected and sampled. The address (SAMPLE_ADD) sampled by the sampling circuit (445) can be determined to be an address where active operations have been performed excessively many times.

[0039] When the repair signal (REP) is activated, the sampling circuit (445) can randomly select and sample one of the row address (R_ADD) and the additional active address (ADDITIONAL_ADD) when the active signal (ACT) and the random pulse signal (RANDOM) are activated. When the repair signal (REP) is activated, the row corresponding to the row address (R_ADD) and the row corresponding to the additional active address (ADDITIONAL_ADD) in the cell array (460) are activated. Therefore, if the row corresponding to the row address (R_ADD) is activated excessively many times, the row corresponding to the additional active address (ADDITIONAL_ADD) may also be activated excessively many times. For this reason, when the repair signal (REP) is activated, the sampling circuit (445) can randomly select and sample one of the row address (R_ADD) and the additional active address (ADDITIONAL_ADD) when the active signal (ACT) and the random pulse signal (RANDOM) are activated. An even / odd signal having random characteristics (EVEN / ODD) may be used for the sampling circuit (445) to randomly select one of the row address (R_ADD) and the additional active address (ADDITIONAL_ADD).

[0040] The smart refresh circuit (450) can provide a smart refresh address (SR_ADD) to the row circuit (470) so that adjacent rows of the row corresponding to the address (SAMPLE_ADD) sampled by the sampling circuit (334) can be refreshed when the smart refresh signal (SR) is activated. The smart refresh address (SR_ADD) may be an address corresponding to an adjacent row of the row corresponding to the sampled address (SAMPLE_ADD). Since the sampled address (SAMPLE_ADD) is an address that is highly likely to be an address that has been activated excessively many times, the adjacent row of the row corresponding to the sampled address (SAMPLE_ADD) may be the row that has been hit by a row hammer attack. That is, the smart refresh circuit (450) can provide a row address (SR_ADD) corresponding to the row that has been hit by a row hammer attack to the row circuit (470) during the smart refresh operation so that the row that has been hit by a row hammer attack can be refreshed.

[0041] The cell array (460) may include a plurality of memory cells arranged in a plurality of rows and a plurality of columns. Each of the memory cells may include a cell capacitor and a cell transistor. In the cell array (460), row lines arranged in the row direction are called word lines, and column lines arranged in the column direction are called bit lines. Each of the memory cells may be connected to one of the row lines and one of the column lines.

[0042] The row circuit (470) can activate a row selected by the row address (R_ADD) among the rows of the cell array (460) when the active signal (ACT) is activated and the repair signal (REP) is deactivated. That is, the row circuit (470) can activate a word line selected by the row address (R_ADD) among the word lines of the cell array (460). When the active signal (ACT) and the repair signal (REP) are activated, the row circuit (470) can activate a row selected by the row address (R_ADD) and a row selected by the additional active address (ADDITIONAL_ADD) among the rows of the cell array (460). And when the precharge signal (PCG) is activated, the row circuit (470) can precharge the activated row.

[0043] The row circuit (470) can refresh a row selected by the refresh address (REF_ADD) among the rows of the cell array (460) when the refresh signal (REF) is activated. That is, the memory cells of the row selected by the refresh address (REF_ADD) can be refreshed. Additionally, the row circuit (470) can refresh a row selected by the smart refresh address (SR_ADD) when the smart refresh signal (SR) is activated. Through the smart refresh operation, rows in the cell array (460) that are likely to lose data due to a row hammer attack can be refreshed.

[0044] The column circuit (480) can write data to the memory cells of the columns selected by the column address (C_ADD) among the columns of the cell array (460) when the write signal (WR) is activated. Additionally, the column circuit (480) can read data from the memory cells of the columns selected by the column address (C_ADD) among the columns of the cell array (460) when the read signal (RD) is activated. When the repair signal (REP) is activated, that is, when two rows are active, the column circuit (480) can determine which of the two active rows' memory cells to access using the defective column information (DEFECT_COL). For example, as shown in FIG. 3, when row 50 and row 2130 are active, if some of columns 255 through 511 are selected by the column address (C_ADD) during a read or write operation, the memory cells of the columns selected by the column address (C_ADD) in row 2130 can be accessed. Additionally, if some of the columns other than columns 255 through 511 are selected by the column address (C_ADD) during a read or write operation, the memory cells of the columns selected by the column address (C_ADD) in row 50 can be accessed.

[0046] FIG. 5 is a configuration diagram of an exemplary embodiment of the sampling circuit (445) of FIG. 4.

[0047] Referring to FIG. 5, the sampling circuit (445) may include a first selection circuit (510), a second selection circuit (520), and a latch circuit (530).

[0048] The first selection circuit (510) can select and output either an additional active address (ADDITIONAL_ADD) or a low address (R_ADD) in response to the even / odd signal (EVEN / ODD). When the even / odd signal (EVEN / ODD) is at a high level, it can select and output an additional active address (ADDITIONAL_ADD), and when the even / odd signal (EVEN / ODD) is at a low level, it can select and output a low address (R_ADD). Alternatively, the first selection circuit (510) may perform the selection operation in the opposite way. Since the level of the even / odd signal (ODD) is determined randomly, the first selection circuit (510) can also randomly select and output either a low address (R_ADD) or an additional active address (ADDITIONAL_ADD).

[0049] The second selection circuit (520) can select and output one of the address (ADD_SEL1) and the row address (R_ADD) selected by the first selection circuit (510) in response to the repair signal (REP). When the repair signal (REP) is activated, it selects and outputs the address (ADD_SEL1) selected by the first selection circuit (510), and when the repair signal (REP) is deactivated, it selects and outputs the row address (R_ADD). Accordingly, the output address (ADD_SEL2) of the second selection circuit (520) becomes the row address (R_ADD) when the repair signal (REP) is deactivated, and when the repair signal (REP) is activated, it may be the address (ADD_SEL1) randomly selected from the row address (R_ADD) and the additional active address (ADDITIONAL_ADD).

[0050] The latch circuit (530) can receive and store the address (ADD_SEL2) selected by the second selection circuit (520) while the active signal (ACT) and the random pulse signal (RANDOM) are active, that is, while the output signal of the AND gate (531) is at a high level.

[0052] FIG. 6 is a timing diagram illustrating the operation of the memory (400) of FIG. 4.

[0053] Referring to FIG. 6, the active signal (ACT) can be activated three times while the random pulse signal (RANDOM) is activated at a high level. Referring to the row address (R_ADD), row 123 is activated during the first active operation, row 243 is activated during the second active operation, and row 340 is activated during the third active operation. Also, since the repair signal (REP) is activated during the third active operation, row 2040 can be activated along with row 340 by the additional active address (ADDITONAL_ADD).

[0054] In addition, it can be observed that whenever the active signal (ACT) is activated during the activation period of the random pulse signal (RANDOM), the level of the even / odd signal (EVEN / ODD) changes to high, low, and high levels.

[0055] It can be confirmed that the address (SAMPLE_ADD) sampled by the latch circuit (530) of the sampling circuit (445) becomes row 123 during the first active operation and row 243 during the second active operation. Additionally, during the third active operation, since the repair signal (REP) is at a high level and the even / odd signal (EVEN / ODD) is at a high level, it can be confirmed that row 2040, corresponding to the additional active address (ADDITIONAL_ADD), becomes the sampled address (SAMPLE_ADD). Since the random pulse signal (RANDOM) is deactivated to a low level during the third active operation, the sampled address (SAMPLE_ADD) can be determined to be row 2040.

[0056] Finally, since row 2040 is sampled by the sampling circuit (445), if a smart refresh operation is performed thereafter, adjacent rows of row 2040 can be refreshed.

[0058] According to embodiments of the present invention, even when two rows are simultaneously activated by a paired row repair scheme at the time of random sampling, more efficient defense against row hammering attacks may be possible by randomly selecting and sampling one of the two activated rows.

[0059] Although the technical concept of the present invention has been specifically described according to the preferred embodiments above, it should be noted that the aforementioned embodiments are for illustrative purposes only and are not intended to be limiting. Furthermore, a person skilled in the art will understand that various embodiments are possible within the scope of the technical concept of the present invention. Explanation of the symbols

[0061] 400: Memory 401: Command Address Receiving Circuit 403: Data transmission and reception circuit 410: Command Decoder 421: Address control circuit 423: Address Counter 430: Repair circuit 441: Random pulse generation circuit 443: Counter circuit 445: Sampling circuit 450: Smart Refresh Circuit 460: Cell array 470: Low circuit 480: Column circuit

Claims

Claim 1 A method of operating a memory comprising: receiving a row address and an active command for a first row; confirming that a portion of a column of the first row has been replaced by a portion of a column of the second row; activating the first row and the second row in response to the active command for the first row; confirming the activation of a random pulse signal; and randomly selecting one of a first row address corresponding to the first row and a second row address corresponding to the second row in response to the activation of the random pulse and sampling it as a sampling address, wherein the sampling step comprises: selecting a first address corresponding to the first row when the number of times the first row is activated during the interval in which the random pulse signal is activated is either odd or even; and selecting a row address corresponding to the second row when the number is the other of odd or even. Claim 2 A method of operating a memory according to claim 1, further comprising: a step of determining to perform a smart refresh operation; and a step of refreshing adjacent rows of a row corresponding to the sampling address. Claim 3 A method of operating a memory comprising: receiving a row address and an active command for a first row; confirming that a part of a column of the first row has been replaced by a part of a column of the second row; activating the first row and the second row in response to the active command for the first row; confirming the activation of a random pulse signal; and randomly selecting one of a first row address corresponding to the first row and a second row address corresponding to the second row in response to the activation of the random pulse and sampling it as a sampling address, wherein the sampling step comprises: counting the number of active commands applied during the activation interval of the random pulse; selecting a row address corresponding to the first row address if the counting result is even and selecting a row address corresponding to the second row address if the counting result is odd; and storing the selected row address as the sampling address. Claim 4 A memory comprising: a cell array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a repair circuit that stores information regarding one or more defective rows in which some columns among the plurality of rows have defects, and if an active address corresponds to one of the one or more defective rows, activates a repair signal and provides an additional active address that specifies a row to be additionally activated; a random pulse generation circuit that generates a randomly activated random pulse signal; and a sampling circuit that samples and stores the active address when the active signal and the random pulse signal are activated and the repair signal is deactivated, and randomly samples and stores one of the active address and the additional active address when the active signal, the random pulse signal, and the repair signal are activated. Claim 5 In claim 4, the memory further includes a counter circuit for counting the number of times the active signal is activated during the activation period of the random pulse signal, and the sampling circuit samples the additional active address if the counting result of the counter circuit is even when the active signal, the random pulse signal, and the repair signal are activated, and samples the active address if the counting result of the counter circuit is odd. Claim 6 In claim 4, the memory further includes a counter circuit for counting the number of times the active signal is activated during the activation period of the random pulse signal, and the sampling circuit samples the additional active address if the counting result of the counter circuit is odd when the active signal, the random pulse signal, and the repair signal are activated, and samples the active address if the counting result of the counter circuit is even. Claim 7 A memory according to claim 4, further comprising a row circuit that activates a row corresponding to the active address among the rows of the cell array when the active signal is activated, and further activates a row corresponding to the additional active address among the rows of the cell array when the repair signal is activated. Claim 8 In claim 7, when the row corresponding to the active address and the row corresponding to the additional active address are activated in the cell array, a memory in which one of the two rows activated according to the column address is accessed during a read and write operation. Claim 9 In claim 7, a memory further comprising a smart refresh circuit for controlling the row circuit such that adjacent rows of a row corresponding to an address stored in the sampling circuit are refreshed during a smart refresh operation.

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