Image sensing device

Abstract

An embodiment of the present invention comprises: first to fourth column lines extending in a column direction and arranged sequentially in a row direction; first and third unit pixel circuits arranged in a first row and connected to the first and third column lines, respectively; second and fourth unit pixel circuits arranged in a second row and connected to the second and fourth column lines, respectively; first and second readout circuits provided corresponding to the first and second unit pixel circuits; third and fourth readout circuits provided corresponding to the third and fourth unit pixel circuits; and a first path changing circuit for changing first and second paths between the first and second column lines and the first and second readout circuits so that, based on a first control signal, the first and second unit pixel circuits and the first and second readout circuits are connected according to a first correspondence relationship during the first unit time. An image sensing device is provided that includes a second path changing circuit for changing the third and fourth paths between the third and fourth column lines and the third and fourth readout circuits, such that, based on the second control signal, the third and fourth unit pixel circuits and the third and fourth readout circuits are connected according to a second correspondence relationship different from the first correspondence relationship during the first unit time.

Description

Technology Field

[0001] The present invention relates to semiconductor design technology, and more specifically to an image sensing device. Background Technology

[0003] An image sensing device is a device that captures images by utilizing the light-responsive properties of semiconductors. Image sensing devices can be broadly classified into image sensing devices using CCDs (Charge Coupled Devices) and image sensing devices using CMOS (Complementary Metal Oxide Semiconductor). Recently, image sensing devices using CMOS are widely used due to the advantage of being able to directly implement analog and digital control circuits on a single integrated circuit (IC). The problem to be solved

[0005] An embodiment of the present invention provides an image sensing device capable of attenuating mismatch occurring between readout circuits. means of solving the problem

[0007] According to one aspect of the present invention, an image sensing device may include: first to fourth column lines extending in a column direction and arranged sequentially in a row direction; a first unit pixel circuit arranged in a first row and connected to the first column line; a second unit pixel circuit arranged in a second row and connected to the second column line; a third unit pixel circuit arranged in the first row and connected to the fourth column line; a fourth unit pixel circuit arranged in the second row and connected to the third column line; first to fourth readout circuits provided in correspondence with the first to fourth unit pixel circuits; a first path changing circuit for changing first paths between the first and second column lines and the first and third readout circuits based on a control signal; and a second path changing circuit for changing second paths between the third and fourth column lines and the second and fourth readout circuits in the same manner as the first path changing circuit based on the control signal. Effects of the invention

[0009] An embodiment of the present invention has the effect of reducing row fixed pattern noise (RFPN) by attenuating mismatch occurring between readout circuits. Brief explanation of the drawing

[0011] FIG. 1 is a block diagram of an image sensing device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the internal configuration of each of the pixel array, path change area, first readout area, and second readout area illustrated in FIG. 1. FIGS. 3 and FIGS. 4 are block diagrams for further explaining the first and second path changing circuits illustrated in FIGS. 2. FIGS. 5 and 6 are diagrams for explaining how pixel signals of the first to fourth pixel circuits shown in FIG. 2 are read out through which readout regions. FIG. 7 is a block diagram of an image sensing device according to a second embodiment of the present invention. FIG. 8 is a block diagram showing the internal configuration of each of the pixel array, path change area, first readout area, and second readout area illustrated in FIG. 7. FIGS. 9 and FIGS. 10 are block diagrams for elaborating on the first and second path changing circuits illustrated in FIGS. 8. FIGS. 11 and FIGS. 12 are diagrams for explaining how pixel signals of the first to fourth pixel circuits shown in FIG. 8 are read out through which readout regions. Specific details for implementing the invention

[0012] Hereinafter, in order to explain in detail enough so that a person skilled in the art to which the present invention pertains can easily implement the technical concept of the present invention, embodiments of the present invention will be described with reference to the accompanying drawings.

[0013] Furthermore, throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected" but also cases where they are "electrically connected" with other components interposed between them. Additionally, when a part is described as "including" or "equipped" with a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include or be equipped with additional components. Moreover, it will be understood that even if some components are described in the singular form throughout the specification, the present invention is not limited thereto, and such components may be composed of multiple units.

[0014] Figure 1 shows an image sensing device according to a first embodiment of the present invention in a block diagram.

[0015] Referring to FIG. 1, the image sensing device (100) may include a row decoder (110), a pixel array (120), a first readout area (130), a second readout area (140), a path change area (150), and a controller (160).

[0016] The row decoder (110) can control the operation of the pixel array (120). For example, the row decoder (110) can control the pixel array (120) in units of two rows.

[0017] The pixel array (120) may include a plurality of pixel circuits arranged at the intersections of a plurality of rows and a plurality of columns. The plurality of pixel circuits are described below (see FIG. 2). The pixel array (120) may generate pixel signals under the control of the row decoder (110). For example, the pixel array (120) may generate pixel signals from pixel circuits arranged in the first and second rows during a first row line time, and may generate pixel signals from pixel circuits arranged in the 2n-1 and 2n rows during the nth row line time (where n is a natural number).

[0018] The first readout area (130) can read out half of the pixel signals generated from the pixel array (120). For example, the first readout area (130) can read out pixel signals generated from half of the pixel circuits among the pixel circuits arranged in the first row during the first row line time and pixel signals generated from half of the pixel circuits among the pixel circuits arranged in the second row.

[0019] The second readout area (140) can read out the remaining half of the pixel signals among the pixel signals generated from the pixel array (120). For example, the second readout area (140) can read out the pixel signals generated from the remaining half of the pixel circuits among the pixel circuits arranged in the first row during the first row line time and the pixel signals generated from the remaining half of the pixel circuits among the pixel circuits arranged in the second row.

[0020] The path change area (150) can transmit half of the pixel signals generated from the pixel array (120) to the first readout area (130) and transmit the remaining half of the pixel signals generated from the pixel array (120) to the second readout area (140).

[0021] A first readout area (130), a second readout area (140), and a path change area (150). The first and second readout areas (130, 140) may be placed on one side of the pixel array (120). In particular, the path change area (150) may be placed between the pixel array (120) and the readout areas (130, 140).

[0022] The controller (160) can control the overall operation of the row decoder (110), the first readout area (130), the second readout area (140), and the path change area (150). For example, the controller (160) may include a timing controller.

[0023] FIG. 2 shows a block diagram showing parts of each of the pixel array (120), the first readout area (130), the second readout area (140), and the path change area (150) illustrated in FIG. 1.

[0024] Referring to FIG. 2, the pixel array (120) may include first to fourth pixel circuits (PX00, PX01, PX10, PX11). The first and second pixel circuits (PX00, PX01) may be arranged in a first column, and the third and fourth pixel circuits (PX10, PX11) may be arranged in a second column. The first and third pixel circuits (PX00, PX10) may be arranged in a first row, and the second and fourth pixel circuits (PX01, PX11) may be arranged in a second row.

[0025] The first to fourth pixel circuits (PX00, PX01, PX10, PX11) may each include at least one pixel. For example, the first to fourth pixel circuits (PX00, PX01, PX10, PX11) may each include a single pixel or a plurality of pixels. The plurality of pixels may have a structure that shares a column line.

[0026] The first pixel circuit (PX00) can be connected to the first odd-numbered column line (CL00). The second pixel circuit (PX01) can be connected to the first even-numbered column line (CL01). The third pixel circuit (PX10) can be connected to the second even-numbered column line (CL11). The fourth pixel circuit (PX11) can be connected to the second odd-numbered column line (CL10). It can be seen that the connection structure between the first pixel circuit (PX00), the second pixel circuit (PX01), the first odd-numbered column line (CL00), and the first even-numbered column line (CL01) is different from the connection structure between the third pixel circuit (PX10), the fourth pixel circuit (PX11), the second odd-numbered column line (CL10), and the second even-numbered column line (CL11). For example, the connection structures may be opposite to each other.

[0027] The first pixel circuit (PX00) can output at least one pixel signal to the first odd-numbered column line (CL00) during the first row line time. The second pixel circuit (PX01) can output at least one pixel signal to the first even-numbered column line (CL01) during the first row line time. The third pixel circuit (PX10) can output at least one pixel signal to the second even-numbered column line (CL11) during the first row line time. The fourth pixel circuit (PX11) can output at least one pixel signal to the second odd-numbered column line (CL10) during the first row line time.

[0028] The first odd-numbered column line (CL00), the first even-numbered column line (CL01), the second odd-numbered column line (CL10), and the second even-numbered column line (CL11) can be extended in the column direction and arranged in order in the row direction.

[0029] The first readout area (130) may include first and third readout circuits (ADC00, ADC01). The first readout circuit (ADC00) may read out a pixel signal generated from the first pixel circuit (PX00) or a pixel signal generated from the second pixel circuit (PX01). For example, the first readout circuit (ADC00) may read out a pixel signal generated from the first pixel circuit (PX00) during a first frame time, and may read out a pixel signal generated from the second pixel circuit (PX01) during a second frame time. The third readout circuit (ADC01) may read out a pixel signal generated from the third pixel circuit (PX10) or a pixel signal generated from the fourth pixel circuit (PX11). For example, the third readout circuit (ADC01) can read out a pixel signal generated from the fourth pixel circuit (PX11) during the first frame time and can read out a pixel signal generated from the third pixel circuit (PX10) during the second frame time.

[0030] The second readout area (140) may include second and fourth readout circuits (ADC10, ADC11). The second readout circuit (ADC10) may read out a pixel signal generated from the first pixel circuit (PX00) or a pixel signal generated from the second pixel circuit (PX01). For example, the second readout circuit (ADC10) may read out a pixel signal generated from the second pixel circuit (PX01) during the first frame time, and may read out a pixel signal generated from the first pixel circuit (PX00) during the second frame time. The fourth readout circuit (ADC11) may read out a pixel signal generated from the third pixel circuit (PX10) or a pixel signal generated from the fourth pixel circuit (PX11). For example, the fourth readout circuit (ADC11) can read out a pixel signal generated from the third pixel circuit (PX10) during the first frame time and can read out a pixel signal generated from the fourth pixel circuit (PX11) during the second frame time.

[0031] The first and second readout circuits (ADC00, ADC10) may be provided corresponding to the first and second pixel circuits (PX00, PX01) and may read out pixel signals generated from the first and second pixel circuits (PX00, PX01). The third and fourth readout circuits (ADC01, ADC11) may be provided corresponding to the third and fourth pixel circuits (PX10, PX11) and may read out pixel signals generated from the third and fourth pixel circuits (PX10, PX11).

[0032] The path change area (150) may include first and second path change circuits (SW00, SW01). The first path change circuit (SW00) can change the first and second paths between the first odd-numbered column line (CL00) and the first even-numbered column line (CL01), and between the first readout circuit (ADC00) and the second readout circuit (ADC10), based on the first control signal (SEL1). For example, the first path change circuit (SW00) can change the first and second paths every unit time. The second path change circuit (SW01) can change the third and fourth paths between the second odd-numbered column line (CL10) and the second even-numbered column line (CL11), and between the third readout circuit (ADC01) and the fourth readout circuit (ADC11), based on the second control signal (SEL2). For example, the second path changing circuit (SW01) can change the third and fourth paths every unit time.

[0033] The first and second control signals (SEL1, SEL2) may be generated from a controller (160). According to one example of the present invention, the first and second control signals (SEL1, SEL2) may be generated in a non-inverted state relative to each other at the unit time interval. For example, the first and second control signals (SEL1, SEL2) may be the same signal. According to another example of the present invention, either of the first and second control signals (SEL1, SEL2) may be transitioned at the unit time interval, and the other may be generated randomly. According to yet another example of the present invention, the first and second control signals (SEL1, SEL2) may each be generated randomly. The unit time may include one of two or more row line times and one or more frame times.

[0034] FIGS. 3 and 4 show block diagrams for further explaining the first and second path changing circuits (SW00, SW01) illustrated in FIG. 2.

[0035] For example, FIGS. 3 and 4 illustrate a block diagram for explaining the operation of the first and second path changing circuits (SW00, SW01) when the first and second control signals (SEL1, SEL2) are in a non-inverted state. FIG. 3 illustrates an example of the first to fourth paths formed through the first and second path changing circuits (SW00, SW01) when the first and second control signals (SEL1, SEL2) are at a first logic level (e.g., "0"), and FIG. 4 illustrates an example of the first to fourth paths formed through the first and second path changing circuits (SW00, SW01) when the first and second control signals (SEL1, SEL2) are at a second logic level (e.g., "1").

[0036] As illustrated in FIG. 3, if the first and second control signals (SEL1, SEL2) are at a logic low level (i.e., "0"), the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) is connected to the first readout circuit (ADC00) and the first even-numbered column line (CL01) is connected to the second readout circuit (ADC10), and the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the third readout circuit (ADC01) and the second even-numbered column line (CL11) is connected to the fourth readout circuit (ADC11). For example, the first and second paths can be formed parallel to the column direction, and the third and fourth paths can also be formed parallel to the column direction.

[0037] As illustrated in FIG. 4, if the first and second control signals (SEL1, SEL2) are at a logic high level (i.e., "1"), the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) is connected to the second readout circuit (ADC10) and the first even-numbered column line (CL01) is connected to the first readout circuit (ADC00), and the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the fourth readout circuit (ADC11) and the second even-numbered column line (CL11) is connected to the third readout circuit (ADC01). For example, the first and second paths can be formed to intersect each other, and the third and fourth paths can also be formed to intersect each other.

[0038] Hereinafter, the operation of an image sensing device (100) according to the first embodiment of the present invention having the above configuration will be described.

[0039] In an embodiment of the present invention, the first and second paths and the third and fourth paths are changed at each single frame time, as an example.

[0040] First, the operation of the image sensing device (100) during the first frame time is described.

[0041] During the first frame time, the controller (160) can generate first and second control signals (SEL1, SEL1) having a logic low level (i.e., "0"). The first path changing circuit (SW00) can change the first and second paths between the first odd-numbered column line (CL00) and the first even-numbered column line (CL01) and the first readout circuit (ADC00) and the second readout circuit (ADC10) based on the first control signal (SEL1) so that the first and second pixel circuits (PX00, PX01) and the first and second readout circuits (ADC00, ADC10) are connected according to a first correspondence relationship. For example, the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) and the first readout circuit (ADC00) are connected and the first even-numbered column line (CL01) and the second readout circuit (ADC10) are connected (see FIG. 3). In addition, the second path changing circuit (SW01) can change the third and fourth paths between the second odd-numbered column line (CL10) and the second even-numbered column line (CL11) and the third readout circuit (ADC01) and the fourth readout circuit (ADC11) so that the third and fourth pixel circuits (PX10, PX11) and the third and fourth readout circuits (ADC01, ADC11) are connected according to a second correspondence relationship different from the first correspondence relationship, based on the second control signal (SEL2). For example, the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the third readout circuit (ADC01) and the second even-numbered column line (CL11) is connected to the fourth readout circuit (ADC11) (see FIG. 3).

[0042] During the first row line time in the first frame time, the first pixel circuit (PX00) can output at least one pixel signal through the first odd-numbered column line (CL00), the second pixel circuit (PX01) can output at least one pixel signal through the first even-numbered column line (CL01), the third pixel circuit (PX10) can output at least one pixel signal through the second even-numbered column line (CL11), and the fourth pixel circuit (PX11) can output at least one pixel signal through the second odd-numbered column line (CL10).

[0043] Accordingly, the first readout circuit (ADC00) can read out the pixel signal of the first pixel circuit (PX00), the second readout circuit (ADC10) can read out the pixel signal of the second pixel circuit (PX01), the third readout circuit (ADC01) can read out the pixel signal of the fourth pixel circuit (PX11), and the fourth readout circuit (ADC11) can read out the pixel signal of the third pixel circuit (PX10).

[0044] The operation of the image sensing device (100) during the first frame time is summarized as follows with reference to FIG. 5.

[0045] FIG. 5 is a diagram for explaining which of the first and second readout regions (130, 140) pixel signals generated from the first to fourth pixel circuits (PX00, PX01, PX10, PX11) illustrated in FIG. 2 are readouted.

[0046] Referring to FIG. 5, during the first row line time in the first frame time, half of the pixel signals generated from the first and third pixel circuits (PX00, PX10) arranged in the first row can be read out through the first readout circuit (ADC00) included in the first readout area (130), and the remaining half of the pixel signals can be read out through the fourth readout circuit (ADC11) included in the second readout area (140). Similarly, during the first row line time in the first frame time, half of the pixel signals generated from the second and fourth pixel circuits (PX01, PX11) arranged in the second row can be read out through the second readout circuit (ADC10) included in the second readout area (140), and the remaining half of the pixel signals can be read out through the third readout circuit (ADC01) included in the first readout area (130).

[0047] Accordingly, pixel signals can be read out in a mixed form with some of the readout circuits included in the first readout area (130) and some of the readout circuits included in the second readout area (140) based on the same low line.

[0048] Next, the operation of the image sensing device (100) during the second frame time is described.

[0049] During the second frame time, the controller (160) can generate first and second control signals (SEL1, SEL2) having a logic high level (i.e., "1"). The first path changing circuit (SW00) can change the first and second paths between the first odd-numbered column line (CL00) and the first even-numbered column line (CL01) and the first readout circuit (ADC00) and the second readout circuit (ADC10) based on the first control signal (SEL1) so that the first and second pixel circuits (PX00, PX01) and the first and second readout circuits (ADC00, ADC10) are connected according to the second correspondence relationship. For example, the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) and the second readout circuit (ADC10) are connected and the first even-numbered column line (CL01) and the first readout circuit (ADC00) are connected (see FIG. 4). In addition, the second path changing circuit (SW01) can change the third and fourth paths between the second odd-numbered column line (CL10) and the second even-numbered column line (CL11) and the third readout circuit (ADC01) and the fourth readout circuit (ADC11) based on the second control signal (SEL2) so that the third and fourth pixel circuits (PX10, PX11) and the third and fourth readout circuits (ADC01, ADC11) are connected according to the first corresponding relationship. For example, the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the fourth readout circuit (ADC11) and the second even-numbered column line (CL11) is connected to the third readout circuit (ADC01) (see FIG. 4).

[0050] During the first row line time in the second frame time, the first pixel circuit (PX00) can output at least one pixel signal through the first odd-numbered column line (CL00), the second pixel circuit (PX01) can output at least one pixel signal through the first even-numbered column line (CL01), the third pixel circuit (PX10) can output at least one pixel signal through the second even-numbered column line (CL11), and the fourth pixel circuit (PX11) can output at least one pixel signal through the second odd-numbered column line (CL10).

[0051] Accordingly, the first readout circuit (ADC00) can read out the pixel signal of the second pixel circuit (PX01), the second readout circuit (ADC10) can read out the pixel signal of the first pixel circuit (PX00), the third readout circuit (ADC01) can read out the pixel signal of the third pixel circuit (PX10), and the fourth readout circuit (ADC11) can read out the pixel signal of the fourth pixel circuit (PX11).

[0052] The operation of the image sensing device (100) during the second frame time is summarized as follows with reference to FIG. 6.

[0053] FIG. 6 is a diagram for explaining which of the first and second readout regions (130, 140) pixel signals generated from the first to fourth pixel circuits (PX00, PX01, PX10, PX11) illustrated in FIG. 2 are readouted.

[0054] Referring to FIG. 6, during the first row line time in the second frame time, half of the pixel signals generated from the first and third pixel circuits (PX00, PX10) arranged in the first row can be read out through the second readout circuit (ADC10) included in the second readout area (140), and the remaining half of the pixel signals can be read out through the third readout circuit (ADC01) included in the first readout area (130). Similarly, during the first row line time in the second frame time, half of the pixel signals generated from the second and fourth pixel circuits (PX01, PX11) arranged in the second row can be read out through the first readout circuit (ADC00) included in the first readout area (130), and the remaining half of the pixel signals can be read out through the fourth readout circuit (ADC11) included in the second readout area (140).

[0055] Accordingly, pixel signals can be read out from pixel circuits arranged in each row in a mixed form, with some of the readout circuits included in the first readout area (130) and some of the readout circuits included in the second readout area (140).

[0056] In addition, each readout circuit included in the first readout area (130) and each readout circuit included in the second readout area (140) can alternately read out pixel signals from two corresponding pixel circuits during the first and second frame times.

[0057] The first embodiment of the present invention describes, as an example, changing the first to fourth paths at each single frame time, but is not necessarily limited thereto. For example, the first embodiment of the present invention may change the first to fourth paths at two or more row line times or two or more frame times. Furthermore, the first embodiment of the present invention describes, as an example, continuously changing (i.e., regularly changing) the first to fourth paths during the first and second frame times, but is not necessarily limited thereto. For example, the first embodiment of the present invention may randomly change the first to fourth paths during the first and second frame times.

[0058] Figure 7 shows an image sensing device according to a second embodiment of the present invention in a block diagram.

[0059] Referring to FIG. 7, the image sensing device (200) may include a row decoder (210), a pixel array (220), a first readout area (230), a second readout area (240), a path change area (250), and a controller (260).

[0060] The row decoder (210) can control the operation of the pixel array (220). For example, the row decoder (210) can control the pixel array (220) in units of two rows.

[0061] The pixel array (220) may include a plurality of pixel circuits arranged at the intersections of a plurality of rows and a plurality of columns. The plurality of pixel circuits are described below (see FIG. 8). The pixel array (220) may generate pixel signals under the control of the row decoder (210). For example, the pixel array (220) may generate pixel signals from pixel circuits arranged in the first and second rows during a first row line time, and may generate pixel signals from pixel circuits arranged in the 2n-1 and 2n rows during the nth row line time (where n is a natural number).

[0062] The first readout area (230) can read out half of the pixel signals generated from the pixel array (220). For example, the first readout area (230) can read out pixel signals generated from half of the pixel circuits arranged in the first row during the first row line time and pixel signals generated from half of the pixel circuits arranged in the second row.

[0063] The second readout area (240) can read out the remaining half of the pixel signals among the pixel signals generated from the pixel array (220). For example, the second readout area (240) can read out the pixel signals generated from the remaining half of the pixel circuits among the pixel circuits arranged in the first row during the first row line time and the pixel signals generated from the remaining half of the pixel circuits among the pixel circuits arranged in the second row.

[0064] The path change area (250) can transmit half of the pixel signals generated from the pixel array (220) to the first readout area (230) and transmit the remaining half of the pixel signals generated from the pixel array (220) to the second readout area (240).

[0065] A first readout area (230), a second readout area (240), and a path change area (250). The first and second readout areas (230, 240) may be placed on one side of the pixel array (220). In particular, the path change area (250) may be placed between the pixel array (220) and the readout areas (230, 240).

[0066] The controller (260) can control the overall operation of the row decoder (210), the first readout area (230), the second readout area (240), and the path change area (250). For example, the controller (260) may include a timing controller.

[0067] FIG. 8 shows a block diagram showing parts of each of the pixel array (220), the first readout area (230), the second readout area (240), and the path change area (250) illustrated in FIG. 7.

[0068] Referring to FIG. 8, the pixel array (220) may include first to fourth pixel circuits (PX00, PX01, PX10, PX11). The first and second pixel circuits (PX00, PX01) may be arranged in a first column, and the third and fourth pixel circuits (PX10, PX11) may be arranged in a second column. The first and third pixel circuits (PX00, PX10) may be arranged in a first row, and the second and fourth pixel circuits (PX01, PX11) may be arranged in a second row.

[0069] The first to fourth pixel circuits (PX00, PX01, PX10, PX11) may each include at least one pixel. For example, the first to fourth pixel circuits (PX00, PX01, PX10, PX11) may each include a single pixel or a plurality of pixels. The plurality of pixels may have a structure that shares a column line.

[0070] The first pixel circuit (PX00) can be connected to the first odd-numbered column line (CL00). The second pixel circuit (PX01) can be connected to the first even-numbered column line (CL01). The third pixel circuit (PX10) can be connected to the second odd-numbered column line (CL10). The fourth pixel circuit (PX11) can be connected to the second even-numbered column line (CL11). It can be seen that the connection structure between the first pixel circuit (PX00), the second pixel circuit (PX01), the first odd-numbered column line (CL00), and the first even-numbered column line (CL01) is the same as the connection structure between the third pixel circuit (PX10), the fourth pixel circuit (PX11), the second odd-numbered column line (CL10), and the second even-numbered column line (CL11).

[0071] The first pixel circuit (PX00) can output at least one pixel signal to the first odd-numbered column line (CL00) during the first row line time. The second pixel circuit (PX01) can output at least one pixel signal to the first even-numbered column line (CL01) during the first row line time. The third pixel circuit (PX10) can output at least one pixel signal to the second odd-numbered column line (CL10) during the first row line time. The fourth pixel circuit (PX11) can output at least one pixel signal to the second even-numbered column line (CL11) during the first row line time.

[0072] The first odd-numbered column line (CL00), the first even-numbered column line (CL01), the second odd-numbered column line (CL10), and the second even-numbered column line (CL11) can be extended in the column direction and arranged in order in the row direction.

[0073] The first readout area (230) may include first and third readout circuits (ADC00, ADC01). The first readout circuit (ADC00) may read out a pixel signal generated from the first pixel circuit (PX00) or a pixel signal generated from the second pixel circuit (PX01). For example, the first readout circuit (ADC00) may read out a pixel signal generated from the first pixel circuit (PX00) during a first frame time, and may read out a pixel signal generated from the second pixel circuit (PX01) during a second frame time. The third readout circuit (ADC01) may read out a pixel signal generated from the third pixel circuit (PX10) or a pixel signal generated from the fourth pixel circuit (PX11). For example, the third readout circuit (ADC01) can read out a pixel signal generated from the fourth pixel circuit (PX11) during the first frame time and can read out a pixel signal generated from the third pixel circuit (PX10) during the second frame time.

[0074] The second readout area (240) may include second and fourth readout circuits (ADC10, ADC11). The second readout circuit (ADC10) may read out a pixel signal generated from the first pixel circuit (PX00) or a pixel signal generated from the second pixel circuit (PX01). For example, the second readout circuit (ADC10) may read out a pixel signal generated from the second pixel circuit (PX01) during the first frame time, and may read out a pixel signal generated from the first pixel circuit (PX00) during the second frame time. The fourth readout circuit (ADC11) may read out a pixel signal generated from the third pixel circuit (PX10) or a pixel signal generated from the fourth pixel circuit (PX11). For example, the fourth readout circuit (ADC11) can read out a pixel signal generated from the third pixel circuit (PX10) during the first frame time and can read out a pixel signal generated from the fourth pixel circuit (PX11) during the second frame time.

[0075] The first and second readout circuits (ADC00, ADC10) may be provided corresponding to the first and second pixel circuits (PX00, PX01) and may read out pixel signals generated from the first and second pixel circuits (PX00, PX01). The third and fourth readout circuits (ADC01, ADC11) may be provided corresponding to the third and fourth pixel circuits (PX10, PX11) and may read out pixel signals generated from the third and fourth pixel circuits (PX10, PX11).

[0076] The path change area (250) may include first and second path change circuits (SW00, SW01). The first path change circuit (SW00) can change the first and second paths between the first odd-numbered column line (CL00) and the first even-numbered column line (CL01), and between the first readout circuit (ADC00) and the second readout circuit (ADC10), based on the first control signal (SEL1). The first path change circuit (SW00) can change the first and second paths per unit time. The second path change circuit (SW01) can change the third and fourth paths between the second odd-numbered column line (CL10) and the second even-numbered column line (CL11), and between the third readout circuit (ADC01) and the fourth readout circuit (ADC11), based on the second control signal (SEL2). The second path change circuit (SW01) can change the third and fourth paths at the unit time interval.

[0077] The first and second control signals (SEL1, SEL2) may be generated from a controller (260). According to one example of the present invention, the first and second control signals (SEL1, SEL2) may be generated in a state inverted from each other at the unit time. According to another example of the present invention, either of the first and second control signals (SEL1, SEL2) may be transitioned at the unit time and the other may be generated randomly. According to yet another example of the present invention, the first and second control signals (SEL1, SEL2) may each be generated randomly. The unit time may include any one of two or more row line times and one or more frame times.

[0078] FIGS. 9 and FIGS. 10 show block diagrams for further explaining the first and second path changing circuits (SW00, SW01) illustrated in FIG. 8.

[0079] For example, FIGS. 9 and 10 illustrate a block diagram for explaining the operation of the first and second path changing circuits (SW00, SW01) when the first and second control signals (SEL1, SEL1) are in an inverted state. FIG. 9 illustrates an example of the first to fourth paths formed through the first and second path changing circuits (SW00, SW01) when the first control signal (SEL1) is at a first logic level (e.g., "0") and the second control signal (SEL2) is at a second logic level (e.g., "1"), FIG. 4 illustrates an example of the first to fourth paths formed through the first and second path changing circuits (SW00, SW01) when the first control signal (SEL1) is at a second logic level (e.g., "1") and the second control signal (SEL2) is at a first logic level (e.g., "0").

[0080] As illustrated in FIG. 9, if the first control signal (SEL1) is a logic low level (i.e., "0") and the second control signal (SEL2) is a logic high level (i.e., "1"), the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) is connected to the first readout circuit (ADC00) and the first even-numbered column line (CL01) is connected to the second readout circuit (ADC10), and the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the fourth readout circuit (ADC11) and the second even-numbered column line (CL11) is connected to the third readout circuit (ADC01). For example, the first and second paths can be formed parallel to the column direction, and the third and fourth paths can be formed intersecting each other.

[0081] As illustrated in FIG. 10, if the first control signal (SEL1) is a logic high level (i.e., "1") and the second control signal (SEL2) is a logic low level (i.e., "0"), the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) is connected to the second readout circuit (ADC10) and the first even-numbered column line (CL01) is connected to the first readout circuit (ADC00), and the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the third readout circuit (ADC01) and the second even-numbered column line (CL11) is connected to the fourth readout circuit (ADC11). For example, the first and second paths can be formed to intersect each other, and the third and fourth paths can be formed parallel to the column direction.

[0082] Hereinafter, the operation of an image sensing device (200) according to a second embodiment of the present invention having the above configuration will be described.

[0083] In an embodiment of the present invention, the first and second paths and the third and fourth paths are changed at each single frame time, as an example.

[0084] First, the operation of the image sensing device (200) during the first frame time is described.

[0085] During the first frame time, the controller (260) can generate a first control signal (SEL1) having a logic low level (i.e., "0") and a second control signal (SEL2) having a logic high level (i.e., "1"). The first path changing circuit (SW00) can change the first and second paths between the first odd-numbered column line (CL00) and the first even-numbered column line (CL01) and the first readout circuit (ADC00) and the second readout circuit (ADC10) based on the first control signal (SEL1) so that the first and second pixel circuits (PX00, PX01) and the first and second readout circuits (ADC00, ADC10) are connected according to a first correspondence relationship. For example, the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) and the first readout circuit (ADC00) are connected and the first even-numbered column line (CL01) and the second readout circuit (ADC10) are connected (see FIG. 9). In addition, the second path changing circuit (SW01) can change the third and fourth paths between the second odd-numbered column line (CL10) and the second even-numbered column line (CL11) and the third readout circuit (ADC01) and the fourth readout circuit (ADC11) so that the third and fourth pixel circuits (PX10, PX11) and the third and fourth readout circuits (ADC01, ADC11) are connected according to a second correspondence relationship different from the first correspondence relationship, based on the second control signal (SEL2). For example, the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the fourth readout circuit (ADC11) and the second even-numbered column line (CL11) is connected to the third readout circuit (ADC01) (see FIG. 9).

[0086] During the first row line time in the first frame time, the first pixel circuit (PX00) can output at least one pixel signal through the first odd-numbered column line (CL00), the second pixel circuit (PX01) can output at least one pixel signal through the first even-numbered column line (CL01), the third pixel circuit (PX10) can output at least one pixel signal through the second odd-numbered column line (CL10), and the fourth pixel circuit (PX11) can output at least one pixel signal through the second even-numbered column line (CL11).

[0087] Accordingly, the first readout circuit (ADC00) can read out the pixel signal of the first pixel circuit (PX00), the second readout circuit (ADC10) can read out the pixel signal of the second pixel circuit (PX01), the third readout circuit (ADC01) can read out the pixel signal of the fourth pixel circuit (PX11), and the fourth readout circuit (ADC11) can read out the pixel signal of the third pixel circuit (PX10).

[0088] The operation of the image sensing device (100) during the first frame time is summarized as follows with reference to FIG. 11.

[0089] FIG. 11 is a diagram for explaining which of the first and second readout regions (230, 240) pixel signals generated from the first to fourth pixel circuits (PX00, PX01, PX10, PX11) illustrated in FIG. 8 are readouted.

[0090] Referring to FIG. 11, during the first row line time in the first frame time, half of the pixel signals generated from the first and third pixel circuits (PX00, PX10) arranged in the first row can be read out through the first readout circuit (ADC00) included in the first readout area (230), and the remaining half of the pixel signals can be read out through the fourth readout circuit (ADC11) included in the second readout area (240). Similarly, during the first row line time in the first frame time, half of the pixel signals generated from the second and fourth pixel circuits (PX01, PX11) arranged in the second row can be read out through the second readout circuit (ADC10) included in the second readout area (240), and the remaining half of the pixel signals can be read out through the third readout circuit (ADC01) included in the first readout area (230).

[0091] Accordingly, pixel signals can be read out in a mixed form with some of the readout circuits included in the first readout area (230) and some of the readout circuits included in the second readout area (240) based on the same low line.

[0092] Next, the operation of the image sensing device (200) during the second frame time is described.

[0093] During the second frame time, the controller (260) can generate a first control signal (SEL1) having a logic high level (i.e., "1") and a second control signal (SEL2) having a logic low level (i.e., "0"). The first path changing circuit (SW00) can change the first and second paths between the first odd-numbered column line (CL00) and the first even-numbered column line (CL01) and the first readout circuit (ADC00) and the second readout circuit (ADC10) based on the first control signal (SEL1) so that the first and second pixel circuits (PX00, PX01) and the first and second readout circuits (ADC00, ADC10) are connected according to the second correspondence relationship. For example, the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) and the second readout circuit (ADC10) are connected and the first even-numbered column line (CL01) and the first readout circuit (ADC00) are connected (see FIG. 10). In addition, the second path changing circuit (SW01) can change the third and fourth paths between the second odd-numbered column line (CL10) and the second even-numbered column line (CL11) and the third readout circuit (ADC01) and the fourth readout circuit (ADC11) based on the second control signal (SEL2) so that the third and fourth pixel circuits (PX10, PX11) and the third and fourth readout circuits (ADC01, ADC11) are connected according to the first corresponding relationship. For example, the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the third readout circuit (ADC01) and the second even-numbered column line (CL11) is connected to the fourth readout circuit (ADC11) (see FIG. 10).

[0094] During the first row line time in the second frame time, the first pixel circuit (PX00) can output at least one pixel signal through the first odd-numbered column line (CL00), the second pixel circuit (PX01) can output at least one pixel signal through the first even-numbered column line (CL01), the third pixel circuit (PX10) can output at least one pixel signal through the second odd-numbered column line (CL10), and the fourth pixel circuit (PX11) can output at least one pixel signal through the second even-numbered column line (CL11).

[0095] Accordingly, the first readout circuit (ADC00) can read out the pixel signal of the second pixel circuit (PX01), the second readout circuit (ADC10) can read out the pixel signal of the first pixel circuit (PX00), the third readout circuit (ADC01) can read out the pixel signal of the third pixel circuit (PX10), and the fourth readout circuit (ADC11) can read out the pixel signal of the fourth pixel circuit (PX11).

[0096] The operation of the image sensing device (200) during the second frame time is summarized as follows with reference to FIG. 12.

[0097] FIG. 12 is a diagram for explaining which of the first and second readout regions (230, 240) pixel signals generated from the first to fourth pixel circuits (PX00, PX01, PX10, PX11) illustrated in FIG. 8 are readouted.

[0098] Referring to FIG. 12, during the first row line time in the second frame time, half of the pixel signals generated from the first and third pixel circuits (PX00, PX10) arranged in the first row can be read out through the second readout circuit (ADC10) included in the second readout area (240), and the remaining half of the pixel signals can be read out through the third readout circuit (ADC01) included in the first readout area (230). Similarly, during the first row line time in the second frame time, half of the pixel signals generated from the second and fourth pixel circuits (PX01, PX11) arranged in the second row can be read out through the first readout circuit (ADC00) included in the first readout area (230), and the remaining half of the pixel signals can be read out through the fourth readout circuit (ADC11) included in the second readout area (240).

[0099] Accordingly, pixel signals can be read out from pixel circuits arranged in each row in a mixed form, with some of the readout circuits included in the first readout area (230) and some of the readout circuits included in the second readout area (240).

[0100] In addition, each readout circuit included in the first readout area (230) and each readout circuit included in the second readout area (240) can alternately read out pixel signals from two corresponding pixel circuits during the first and second frame times.

[0101] The second embodiment of the present invention describes, as an example, changing the first to fourth paths at each single frame time, but is not necessarily limited thereto. For example, the second embodiment of the present invention may change the first to fourth paths at two or more row line times or two or more frame times. Furthermore, the second embodiment of the present invention describes, as an example, continuously changing (i.e., regularly changing) the first to fourth paths during the first and second frame times, but is not necessarily limited thereto. For example, the second embodiment of the present invention may randomly change the first to fourth paths during the first and second frame times.

[0102] FIG. 13 shows an image sensing device according to a third embodiment of the present invention in a block diagram.

[0103] Referring to FIG. 13, the image sensing device (300) may include a row decoder (310), a pixel array (320), a first readout area (330), a second readout area (340), a path change area (350), and a controller (360).

[0104] The row decoder (310) can control the operation of the pixel array (320). For example, the row decoder (310) can control the pixel array (320) in units of two rows.

[0105] The pixel array (320) may include a plurality of pixel circuits arranged at the intersections of a plurality of rows and a plurality of columns. The plurality of pixel circuits are described below (see FIG. 14). The pixel array (320) may generate pixel signals under the control of the row decoder (310). For example, the pixel array (320) may generate pixel signals from pixel circuits arranged in the first and second rows during a first row line time, and may generate pixel signals from pixel circuits arranged in the 2n-1 and 2n rows during the nth row line time (where n is a natural number).

[0106] The first readout area (330) can read out half of the pixel signals generated from the pixel array (320). For example, the first readout area (330) can read out pixel signals generated from half of the pixel circuits among the pixel circuits arranged in the first row during the first row line time and pixel signals generated from half of the pixel circuits among the pixel circuits arranged in the second row.

[0107] The second readout area (340) can read out the remaining half of the pixel signals among the pixel signals generated from the pixel array (320). For example, the second readout area (340) can read out the pixel signals generated from the remaining half of the pixel circuits among the pixel circuits arranged in the first row during the first row line time and the pixel signals generated from the remaining half of the pixel circuits among the pixel circuits arranged in the second row.

[0108] The path change area (350) can transmit half of the pixel signals generated from the pixel array (320) to the first readout area (330) and transmit the remaining half of the pixel signals generated from the pixel array (320) to the second readout area (340).

[0109] The first readout area (330), the second readout area (340), and the path change area (350) may be placed on one side of the pixel array (320). In particular, the path change area (350) may be placed between the pixel array (320) and the readout areas (330, 340).

[0110] The controller (360) can control the overall operation of the row decoder (310), the first readout area (330), the second readout area (340), and the path change area (350). For example, the controller (360) may include a timing controller.

[0111] FIG. 14 shows a block diagram showing parts of each of the pixel array (320), the first readout area (330), the second readout area (340), and the path change area (350) illustrated in FIG. 13.

[0112] Referring to FIG. 14, the pixel array (320) may include first to fourth pixel circuits (PX00, PX01, PX10, PX11). The first and second pixel circuits (PX00, PX01) may be arranged in a first column, and the third and fourth pixel circuits (PX10, PX11) may be arranged in a second column. The first and third pixel circuits (PX00, PX10) may be arranged in a first row, and the second and fourth pixel circuits (PX01, PX11) may be arranged in a second row.

[0113] The first to fourth pixel circuits (PX00, PX01, PX10, PX11) may each include at least one pixel. For example, the first to fourth pixel circuits (PX00, PX01, PX10, PX11) may each include a single pixel or a plurality of pixels. The plurality of pixels may have a structure that shares a column line.

[0114] The first pixel circuit (PX00) can be connected to the first odd-numbered column line (CL00). The second pixel circuit (PX01) can be connected to the first even-numbered column line (CL01). The third pixel circuit (PX10) can be connected to the second odd-numbered column line (CL10). The fourth pixel circuit (PX11) can be connected to the second even-numbered column line (CL11). It can be seen that the connection structure between the first pixel circuit (PX00), the second pixel circuit (PX01), the first odd-numbered column line (CL00), and the first even-numbered column line (CL01) is the same as the connection structure between the third pixel circuit (PX10), the fourth pixel circuit (PX11), the second odd-numbered column line (CL10), and the second even-numbered column line (CL11).

[0115] The first pixel circuit (PX00) can output at least one pixel signal to the first odd-numbered column line (CL00) during the first row line time. The second pixel circuit (PX01) can output at least one pixel signal to the first even-numbered column line (CL01) during the first row line time. The third pixel circuit (PX10) can output at least one pixel signal to the second odd-numbered column line (CL10) during the first row line time. The fourth pixel circuit (PX11) can output at least one pixel signal to the second even-numbered column line (CL11) during the first row line time.

[0116] The first odd-numbered column line (CL00), the first even-numbered column line (CL01), the second odd-numbered column line (CL10), and the second even-numbered column line (CL11) can be extended in the column direction and arranged in order in the row direction.

[0117] The first readout area (330) may include first and third readout circuits (ADC00, ADC01). The first readout circuit (ADC00) may read out a pixel signal generated from the first pixel circuit (PX00) or a pixel signal generated from the second pixel circuit (PX01). For example, the first readout circuit (ADC00) may read out a pixel signal generated from the first pixel circuit (PX00) during a first frame time, and may read out a pixel signal generated from the second pixel circuit (PX01) during a second frame time. The third readout circuit (ADC01) may read out a pixel signal generated from the third pixel circuit (PX10) or a pixel signal generated from the fourth pixel circuit (PX11). For example, the third readout circuit (ADC01) can read out a pixel signal generated from the fourth pixel circuit (PX11) during the first frame time and can read out a pixel signal generated from the third pixel circuit (PX10) during the second frame time.

[0118] The second readout area (340) may include second and fourth readout circuits (ADC10, ADC11). The second readout circuit (ADC10) may read out a pixel signal generated from the first pixel circuit (PX00) or a pixel signal generated from the second pixel circuit (PX01). For example, the second readout circuit (ADC10) may read out a pixel signal generated from the second pixel circuit (PX01) during the first frame time, and may read out a pixel signal generated from the first pixel circuit (PX00) during the second frame time. The fourth readout circuit (ADC11) may read out a pixel signal generated from the third pixel circuit (PX10) or a pixel signal generated from the fourth pixel circuit (PX11). For example, the fourth readout circuit (ADC11) can read out a pixel signal generated from the third pixel circuit (PX10) during the first frame time and can read out a pixel signal generated from the fourth pixel circuit (PX11) during the second frame time.

[0119] The first and second readout circuits (ADC00, ADC10) may be provided corresponding to the first and second pixel circuits (PX00, PX01) and may read out pixel signals generated from the first and second pixel circuits (PX00, PX01). The third and fourth readout circuits (ADC01, ADC11) may be provided corresponding to the third and fourth pixel circuits (PX10, PX11) and may read out pixel signals generated from the third and fourth pixel circuits (PX10, PX11).

[0120] The path change area (350) may include a path control circuit (PS), a first path change circuit (SW00), and a second path change circuit (SW01). The path control circuit (PS) may generate a third control signal (SEL3) based on first and second control signals (SEL1, SEL2). The first path change circuit (SW00) may change the first and second paths between the first odd-numbered column line (CL00) and the first even-numbered column line (CL01), and between the first readout circuit (ADC00) and the second readout circuit (ADC10), based on the first control signal (SEL1). The first path change circuit (SW00) may change the first and second paths per unit time. The second path changing circuit (SW01) can change the third and fourth paths between the second odd-numbered column line (CL10) and the second even-numbered column line (CL11), and between the third readout circuit (ADC01) and the fourth readout circuit (ADC11), based on the second control signal (SEL2). The second path changing circuit (SW01) can change the third and fourth paths at the unit time interval.

[0121] The first and second control signals (SEL1, SEL2) may be generated from a controller (360). According to one example of the present invention, the first and second control signals (SEL1, SEL2) may be generated in a state inverted from each other at the unit time. According to another example of the present invention, either of the first and second control signals (SEL1, SEL2) may be transitioned (i.e., generated regularly) at the unit time, and the other may be generated randomly. According to yet another example of the present invention, the first and second control signals (SEL1, SEL2) may each be generated randomly. The unit time may include any one of two or more row line times and one or more frame times.

[0122] In FIG. 15, the path control circuit (PS) illustrated in FIG. 14 is shown as a circuit diagram.

[0123] Referring to FIG. 15, the path control circuit (PS) may include a first switching element (SC0) and a second switching element (SC1).

[0124] The first switching element (SC0) can output a first inverted control signal ( / SEL1) as a third control signal (SEL3) based on the second control signal (SEL2). The first inverted control signal ( / SEL1) may be a signal obtained by inverting the first control signal (SEL).

[0125] The second switching element (SC1) can output the first control signal (SEL1) as the third control signal (SEL3) based on the second inversion control signal ( / SEL2). The second inversion control signal ( / SEL2) may be a signal obtained by inverting the second control signal (SEL2).

[0126] FIGS. 16 to 19 show block diagrams for further explaining the first and second path changing circuits (SW00, SW01) illustrated in FIG. 14.

[0127] As illustrated in FIG. 16, the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) is connected to the first readout circuit (ADC00) and the first even-numbered column line (CL01) is connected to the second readout circuit (ADC10), and the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the fourth readout circuit (ADC11) and the second even-numbered column line (CL11) is connected to the third readout circuit (ADC01). For example, the first and second paths can be formed parallel to the column direction, and the third and fourth paths can be formed intersecting each other.

[0128] As illustrated in FIG. 17, the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) is connected to the first readout circuit (ADC00) and the first even-numbered column line (CL01) is connected to the second readout circuit (ADC10), and the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the third readout circuit (ADC01) and the second even-numbered column line (CL11) is connected to the fourth readout circuit (ADC11). For example, the first and second paths can be formed parallel to the column direction, and the third and fourth paths can also be formed parallel to the column direction.

[0129] As illustrated in FIG. 18, the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) is connected to the second readout circuit (ADC10) and the first even-numbered column line (CL01) is connected to the first readout circuit (ADC00), and the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the third readout circuit (ADC01) and the second even-numbered column line (CL11) is connected to the fourth readout circuit (ADC11). For example, the first and second paths can be formed to intersect each other, and the third and fourth paths can be formed parallel to the column direction.

[0130] As illustrated in FIG. 19, the first path changing circuit (SW00) can change the first and second paths so that the first odd-numbered column line (CL00) is connected to the second readout circuit (ADC10) and the first even-numbered column line (CL01) is connected to the first readout circuit (ADC00), and the second path changing circuit (SW01) can change the third and fourth paths so that the second odd-numbered column line (CL10) is connected to the fourth readout circuit (ADC11) and the second even-numbered column line (CL11) is connected to the third readout circuit (ADC01). For example, the first and second paths can be formed to intersect each other, and the third and fourth paths can also be formed to intersect each other.

[0131] In the third embodiment of the present invention, the first to fourth paths may be formed at each unit time as illustrated in any one of FIGS. 16 to 19. That is, in the third embodiment of the present invention, the first to fourth paths may be randomly changed at each unit time.

[0132] According to embodiments of the present invention, by reading out pixel signals in a mixed form with respect to the same row line, some readout circuits included in the first readout area and some readout circuits included in the second readout area, there is an advantage of being able to reduce the mismatch between the readout circuits included in the first readout area and the readout circuits included in the second readout area. Furthermore, according to embodiments of the present invention, when changing the first to fourth paths randomly compared to changing them regularly, there is an advantage of being able to further reduce the mismatch between the readout circuits included in the first readout area and the readout circuits included in the second readout area.

[0133] Although the technical concept of the present invention has been specifically described according to the above embodiments, it should be noted that the embodiments described above are for illustrative purposes only and are not intended to be limiting. Furthermore, a person skilled in the art will understand that various embodiments are possible through various substitutions, modifications, and changes within the scope of the technical concept of the present invention. Explanation of the symbols

[0135] 100: Image sensing device 110: Row decoder 120: Pixel array 130: First readout area 140: Second Readout Area 150: Path Change Area 160 : Controller

Claims

Claim 1 delete Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 delete Claim 8 delete Claim 9 delete Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete Claim 21 First to fourth column lines extending in the column direction and arranged sequentially in the row direction; a first unit pixel circuit arranged at the intersection of the first row and the first column and connected to the first column line; a second unit pixel circuit arranged at the intersection of the second row and the first column and connected to the second column line; a third unit pixel circuit arranged at the intersection of the first row and the second column and connected to the third column line; a fourth unit pixel circuit arranged at the intersection of the second row and the second column and connected to the fourth column line; first and second readout circuits provided corresponding to the first and second unit pixel circuits; third and fourth readout circuits provided corresponding to the third and fourth unit pixel circuits; and a first and second column line and the first and second readout circuits and the first and second readout circuits such that, based on a first control signal, the first and second unit pixel circuits and the first and second readout circuits are connected according to a first corresponding relationship during a first unit time. A first path changing circuit for changing a second path; and a second path changing circuit for changing a third and fourth path between the third and fourth column lines and the third and fourth readout circuits such that, based on a second control signal, the third and fourth unit pixel circuits and the third and fourth readout circuits are randomly connected according to either a first correspondence relationship or a second correspondence relationship—different from the first correspondence relationship—during the first unit time, and further comprising a path control circuit for generating the second control signal based on the first control signal and the third control signal, wherein the path control circuit comprises a first switching element for outputting a first inverted control signal—which is a signal obtained by inverting the first control signal—as the second control signal based on the third control signal;An image sensing device comprising a second switching element for outputting the first control signal as the second control signal based on the third inverted control signal—which is the inverted signal of the third control signal.; Claim 22 An image sensing device according to claim 21, wherein the first path changing circuit changes the first and second paths so that the first and second unit pixel circuits and the first and second readout circuits are connected according to the second corresponding relationship during the second unit time based on the first control signal, and the second path changing circuit changes or maintains the third and fourth paths so that the third and fourth unit pixel circuits and the third and fourth readout circuits are connected randomly according to either the first corresponding relationship or the second relationship during the second unit time based on the second control signal. Claim 23 delete Claim 24 An image sensing device according to claim 21, wherein the first control signal is controlled regularly at each unit time, the third control signal is controlled randomly at each unit time, and the second control signal is controlled randomly at each unit time. Claim 25 delete Claim 26 delete Claim 27 An image sensing device according to claim 21, wherein the first and second readout circuits are placed in the first column and the third and fourth readout circuits are placed in the second column.

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