Data processiong system including host with reliability management of memory systems and method for the same

Abstract

The host handles the reliability management of memory systems. The host analyzes the characteristics of the data associated with the selected memory system among the memory systems. Based on these characteristics, the host determines one or more reliability schemes and a reliability control mode from among a plurality of reliability schemes to be applied to the selected memory system. The host provides reliability management information indicating the reliability control mode to the selected memory system. The plurality of reliability schemes include Error Correction Code (ECC) schemes, read retry schemes, intra redundancy schemes, and refresh schemes.

Description

Technology Field

[0001] Embodiments of the present disclosure relate to a scheme for managing the reliability of memory systems. Background Technology

[0002] The paradigm of the computing environment is shifting toward ubiquitous computing systems that can be used anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and laptop computers is increasing rapidly. These portable electronic devices generally utilize memory systems equipped with memory device(s), that is, data storage device(s). Data storage devices are used as primary or secondary memory devices for portable electronic devices.

[0003] Memory systems utilizing memory devices offer excellent stability, durability, high information access speeds, and low power consumption because they have no moving parts. Examples of memory systems with such advantages include USB (Universal Serial Bus) memory devices, memory cards with various interfaces such as UFS (Universal Flash Storage), and SSDs (Solid State Drives).

[0004] System reliability is one of the most critical aspects of memory systems. If the ability to handle the reliability of data stored in memory systems is improved, the performance and Quality of Service (QoS) of such memory systems can be enhanced. Therefore, memory systems with improved reliability management are desired. In this context, embodiments of the present invention are devised. The problem to be solved

[0005] Aspects of the present invention include a data processing system comprising a host capable of handling reliability management of memory systems, and a method for managing reliability thereof. means of solving the problem

[0006] In one aspect, a data processing system comprises a host including a plurality of memory systems and a reliability manager coupled to the plurality of memory systems. The reliability manager is configured to analyze the characteristics of data associated with a selected memory system among the plurality of memory systems, determine one or more reliability measures and a reliability control mode among a plurality of reliability measures to be applied to the selected memory system based on the characteristics, and provide reliability management information indicating the reliability control mode to the selected memory system. The plurality of reliability measures include an Error Correction Code (ECC) measure, a read retry measure, an intra redundancy measure, and a refresh measure.

[0007] Further aspects of the present invention will become apparent from the following description. Brief explanation of the drawing

[0008] FIG. 1 is a block diagram illustrating a data processing system according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a memory system according to an embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a data processing system including a host that manages the reliability of memory systems according to an embodiment of the present invention. FIG. 5 is a diagram illustrating the architecture of a data processing system according to an embodiment of the present invention. FIG. 6 is a diagram illustrating the Application Programming Interfaces (APIs) of a reliability manager according to an embodiment of the present invention. FIG. 7 is a diagram illustrating coverage units of a Solid State Drive (SSD) controlled by a reliability manager according to an embodiment of the present invention. FIG. 8 is a flowchart illustrating a reliability management method according to an embodiment of the present invention. FIGS. 9a and 9b are drawings illustrating examples of reliability management information by APIs of a reliability manager according to an embodiment of the present invention. Specific details for implementing the invention

[0009] Various embodiments are described in more detail below with reference to the attached drawings. However, the present invention may be embodied in other forms and should not be interpreted as being limited to the embodiments described herein. Rather, by providing these embodiments, the present disclosure is made thorough and the scope of the invention is fully and sufficiently conveyed to those skilled in the art. Furthermore, references to "exemplars," "other embodiments," etc., in this specification do not necessarily refer to a single embodiment, nor do any other reference to such expressions refer to the same embodiment. Throughout the entire disclosure, similar reference numbers indicate similar parts in the drawings and embodiments of the present invention.

[0010] The present invention may be embodied in various ways, including as a process, device, system, computer program product embedded in a computer-readable storage medium, and / or as a processor (e.g., a processor suitable for executing instructions stored in and / or provided by memory coupled to the processor). In this specification, such implementations or any other forms taken by the present invention will be referred to as descriptions. Overall, the order of steps of the disclosed processes may be changed within the scope of the present invention. Unless otherwise noted, a component such as a processor or memory described as suitable for executing a task may be embodied as a general-purpose component temporarily configured to perform a task at a given time or as a specific component manufactured to perform the task. As used herein, the term 'processors' refers to one or more devices, circuits and / or processing cores suitable for processing data such as computer program instructions.

[0011] Hereinafter, a detailed description of embodiments of the present invention is provided together with the accompanying drawings illustrating aspects of the present invention. Although the present invention is described in relation to such embodiments, the present invention is not limited to any of the embodiments. The scope of the present invention is limited only by the claims. The present invention encompasses many alternatives, modifications, and equivalents within the scope of the claims. To provide a general understanding of the present invention, many specific details are provided in the following description. These details are provided for illustrative purposes, and the present invention may be practiced according to the claims even without some or all of these specific details. For clarity, technical elements known in the art related to the present invention have not been described in detail so as not to make the present invention unnecessarily ambiguous.

[0012] FIG. 1 is a block diagram illustrating a data processing system (2) according to an embodiment of the present invention.

[0013] Referring to FIG. 1, the data processing system (2) may include a host device (5) and a memory system (10). The memory system (10) may receive a request from the host device (5) and operate in response to the received request. For example, the memory system (10) may store data to be accessed by the host device (5).

[0014] The host device (5) may be implemented as any one of various types of electronic devices. In various embodiments, the host device (5) may include electronic devices such as a desktop computer, a workstation, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player and / or a digital video recorder and a digital video player. In various embodiments, the host device (5) may include portable electronic devices such as a mobile phone, a smart phone, an e-book player, an MP3 player, a PMP (Portable Multimedia Player) and / or a portable game player.

[0015] The memory system (10) can be implemented as any one of various types of storage devices, such as an SSD (Solid State Drive) and a memory card. In various embodiments, the memory system (10) is provided as one of various components within an electronic device such as a computer, UMPC (Ultra-Mobile Personal Computer), workstation, net-book computer, PDA (Personal Digital Assistant), portable computer, web tablet PC, cordless phone, mobile phone, smart phone, e-book reader, PMP (Portable Multimedia Player), portable game device, navigation device, black box, digital camera, DMB (Digital Multimedia Broadcasting) player, 3D television, smart television, digital audio recorder, digital audio player, digital photo recorder, digital photo player, digital video recorder, digital video player, storage device of a data center, a device capable of receiving and transmitting information in a wireless environment, and an RFID (Radio-Frequency Identification) device, and is provided as one of various electronic devices in a home network, one of various electronic devices in a computer network, and of a telematics network. It can be provided as one of the various components within an electronic device, such as one of the electronic devices or one of the various electronic devices of a computing system.

[0016] The memory system (10) may include a memory controller (100) and a semiconductor memory device (200). The memory controller (100) can control the overall operation of the semiconductor memory device (200).

[0017] A semiconductor memory device (200) can execute one or more erase operations, program operations, and read operations under the control of a memory controller (100). The semiconductor memory device (200) can receive commands (command, CMD), addresses (ADDR), and data (DATA) through input / output lines. The semiconductor memory device (200) can receive power (PWR) through power lines and receive control signals (CTL) through control lines. Depending on the design and configuration of the memory system (10), the control signals (CTL) may include a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, and other operation signals.

[0018] The memory controller (100) and the semiconductor memory device (200) can be integrated into a single semiconductor device such as an SSD. The SSD may include a storage device for storing data. When the semiconductor memory system (10) is used in an SSD, the operating speed of the host device (e.g., the host device (5) of FIG. 1) coupled to the memory system (10) can be significantly improved.

[0019] The memory controller (100) and the semiconductor memory device (200) can be integrated into a single semiconductor device such as a memory card. For example, the memory controller (100) and the semiconductor memory device (200) can be integrated to configure a PC (Personal Computer), CF (Compact Flash) card, SM (Smart Media) card, Memory Stick, MMC (Multimedia Card), RS-MMC (Reduced-Size Multimedia Card), MMCmicro (micro-size version of MMC), SD (Secure Digital) card, miniSD (mini Secure Digital) card, microSD (micro Secure Digital) card, SDHC (Secure Digital High Capacity) and / or UFS (Universal Flash Storage) of the PCMCIA (Personal Computer Memory Card International Association).

[0020] FIG. 2 is a block diagram illustrating a memory system according to an embodiment of the present invention. For example, the memory system of FIG. 2 may represent the memory system (10) illustrated in FIG. 1.

[0021] Referring to FIG. 2, the memory system (10) may include a memory controller (100) and a semiconductor memory device (200). The memory system (10) may operate in response to a request from a host device (e.g., the host device (5) of FIG. 1), and in particular, may store data to be accessed by the host device.

[0022] The memory device (200) can store data to be accessed by the host device.

[0023] The memory device (200) may be implemented as a volatile memory device such as DRAM (Dynamic Random Access Memory) and / or SRAM (Static Random Access Memory), or as a non-volatile memory such as ROM (Random Access Memory), MROM (Mask ROM), PROM (Programmable ROM), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), FRAM (Ferroelectric RAM), PRAM (Phase change RAM), MRAM (Magnetoresistive RAM), and / or RRAM (Resistive RAM).

[0024] The controller (100) can control the storage of data in the memory device (200). For example, the controller (100) can control the memory device (200) in response to a request from a host device. The controller (100) can provide data read from the memory device (200) to the host device and store the data provided from the host device in the memory device (200).

[0025] The controller (100) includes a storage unit (110), a control component (120) that can be implemented as a processor such as a CPU (Central Processing Unit), an ECC (Error Correction Code) component (130), a host interface (Host Interface, 140), and a memory interface (Memory Interface, 150), all of which are connected via a bus (160).

[0026] The storage unit (110) functions as a working memory for the memory system (10) and the controller (100) and can store data for operating the memory system (10) and the controller (100). When the controller (100) controls the operations of the memory device (200), the storage unit (110) can store data used by the controller (100) and the memory device (200) for operations such as reading, writing, programming, and erasing.

[0027] The storage unit (110) may be implemented as a volatile memory such as SRAM or DRAM. As described above, the storage unit (110) may store data used by a host device in the memory device (200) for read and write operations. For data storage, the storage unit (110) may include a program memory, a data memory, a write buffer, a read buffer, a map buffer, etc.

[0028] The control component (120) can control the overall operation of the memory system (10), in particular, write and read operations for the memory device (200) in response to a corresponding request from a host device. The control component (120) can control the overall operations of the memory system (10) by driving firmware referred to as a flash translation layer (FTL). For example, the FTL can perform operations such as Logical-To-Physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. L2P mapping is known as Logical Block Addressing (LBA).

[0029] The ECC component (130) detects and corrects errors in the data read from the memory device (200) during a read operation. If the number of error bits is greater than or equal to the threshold number of correctable error bits, the ECC component (130) cannot correct the error bits and instead can output an error correction failure signal indicating a failure to correct the error bits.

[0030] In various embodiments, the ECC component (130) may perform error correction operations based on coded modulation such as LDPC (low density parity check) code, BCH (Bose-Chaudhuri-Hocquenghem) code, turbo code, TPC (turbo product code), RS (Reed-Solomon) code, convolution code, RSC (recursive systematic code), TCM (trellis-coded modulation), or BCM (Block coded modulation). However, error correction is not limited to these techniques. As such, the ECC component (130) may include any and all circuits, systems, or devices for suitable error correction operations.

[0031] The host interface (140) can communicate with the host device through one or more different interface protocols such as USB (universal serial bus), MMC (multi-media card), PCI-e or PCIe (peripheral component interconnect express), SCSI (small computer system interface), SAS (serial-attached SCSI), SATA (serial advanced technology attachment), PATA (parallel advanced technology attachment), ESDI (enhanced small disk interface), and / or IDE (integrated drive electronics).

[0032] The memory interface (150) can provide an interface between the controller (100) and the memory device (200) so that the controller (100) can control the memory device (200) in response to a request from the host device. The memory interface (150) can generate control signals for the memory device (200) and process data under the control of the control component (120).

[0033] A memory device (200) may include a memory cell array (210), a control circuit (220), a voltage generation circuit (230), a row decoder (240), a page buffer (250) which may be in the form of an array of page buffers, a column decoder (260), and an input / output circuit (270). The memory cell array (210) may include a plurality of memory blocks (211) capable of storing data. The voltage generation circuit (230), the row decoder (240), the page buffer array (250), the column decoder (260), and the input / output circuit (270) may form a peripheral circuit for the memory cell array (210). The peripheral circuit may perform a program operation, a read operation, or an erase operation on the memory cell array (210). The control circuit (220) may control the peripheral circuit.

[0034] The voltage generation circuit (230) can generate various levels of operating voltages. For example, in an erasure operation, the voltage generation circuit (230) can generate various levels of operating voltages, such as an erasure voltage and a pass voltage.

[0035] The row decoder (240) may be in an electrical communication state with the voltage generation circuit (230) and a plurality of memory blocks (211). The row decoder (240) may select at least one memory block among the plurality of memory blocks (211) in response to a row address generated by the control circuit (220) and transmit operating voltages supplied from the voltage generation circuit (230) to the selected memory blocks.

[0036] The page buffer (250) can be coupled to the memory cell array (210) via bit lines (BL) (illustrated in FIG. 3). The page buffer (250) can precharge the bit lines (BL) with a positive voltage in response to page buffer control signal(s) generated by the control circuit (220), transfer data to a selected memory block during program and read operations, receive data from a selected memory block, or temporarily store the transferred data.

[0037] The column decoder (260) can transmit data to the page buffer (250) and receive data from the page buffer (250), or transmit data to the input / output circuit (270) and receive data from the input / output circuit (270).

[0038] The input / output circuit (270) can transmit instructions and addresses received from an external device (e.g., the memory controller (100) of FIG. 1) to the control circuit (220), transmit data from the external device to the column decoder (260), or output data from the color device (260) to the external device.

[0039] The control circuit (220) can control peripheral circuits in response to instructions and addresses.

[0040] FIG. 3 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, the memory block of FIG. 3 may be any memory block among the memory blocks (211) of the memory cell array (210) illustrated in FIG. 2.

[0041] Referring to FIG. 3, an exemplary memory block (211) may include a plurality of word lines (WL0 to WLn-1) coupled to a row decoder (240), a drain select line (DSL), and a source select line (SSL). These lines may be arranged in parallel, and a plurality of word lines are arranged between the DSL and the SSL.

[0042] An exemplary memory block (211) may further include a plurality of cell strings (221) each coupled to bit lines (BL0 to BLm-1). A cell string in each column may include one or more drain select transistors (DST) and one or more source select transistors (SST). In the illustrated embodiment, each cell string has one DST and one SST. In a cell string, a plurality of memory cells or memory cell transistors (MC0 to MCn-1) may be serially coupled between the select transistors (DST and SST). Each of the memory cells may be formed as a Single Level Cell (SLC) storing 1 bit of data, a Multi-Level Cell (MLC) storing 2 bits of data, a Triple-Level Cell (TLC) storing 3 bits of data, or a Quadruple-Level Cell (QLC) storing 4 bits of data.

[0043] The source of each SST in each cell string can be coupled to a common source line (CSL), and the drain of each DST can be coupled to a corresponding bit line. The gates of the SSTs in the cell string can be coupled to an SSL, and the gates of the DSTs in the cell string can be coupled to a DSL. The gates of memory cells across the cell strings can be coupled to each word line. That is, the gates of memory cells (MC0) are coupled to a corresponding word line (WL0), and the gates of memory cells (MC1) are coupled to a corresponding word line (WL1). A group of memory cells coupled to a specific word line can be referred to as a physical page. Therefore, the number of physical pages in a memory block (211) can correspond to the number of word lines.

[0044] The page buffer array (250) may include a plurality of page buffers (251) coupled to bit lines (BL0 to BLm-1). The page buffers (251) may operate in response to page buffer control signals. For example, the page buffers (251) may temporarily store data received through the bit lines (BL0 to BLm-1) or detect voltages or currents of the bit lines during a read or verification operation.

[0045] In some embodiments, the memory blocks (211) may include NAND-type flash memory cells. However, the memory blocks (211) are not limited to such cell types and may include NOR-type flash memory cells. The memory cell array (210) may be implemented as a hybrid flash memory in which two or more types of memory cells are combined, or as a one-NAND flash memory in which a controller is embedded inside the memory chip.

[0046] As described above, memory systems such as SSDs can store data. SSD replacement can be caused by different reasons. Subsystems in the storage layer can detect problems that cause drive replacement. For example, problems may be reported by the drive itself, or by the storage layer or file system. The inventors have found that SSD replacement is caused by various types of reasons, namely, predictive failures, threshold exceeded, recommended failures, aborted commands, disk ownership I / O errors, command timeouts, lost writes, SCSI (Small Computer System Interface) errors, and unresponsive drives, as shown in Table 1.

[0047] Category category percentage(%) SL1 Disaster prediction 12.78 Exceeding threshold 12.73 Disability recommendation 8.93 SL2 Stop instructions 13.56 Disk ownership I / O errors 3.27 Instruction timeouts 1.81 SL3 Entry loss 13.54 SL4 SCSI errors 32.78 Drive unresponsive 0.60

[0048] Referring to Table 1 above, it can be seen that SCSI errors are the most common. SCSI errors are associated with bit errors in the data stored on SSDs. Therefore, it is desirable to provide a method to manage the reliability of memory systems (e.g., SSDs) so that the performance (e.g., tail latency, write amplification) and Quality of Service (QoS) of memory systems can be improved.

[0049] Embodiments provide a data processing system including a host capable of managing the reliability of memory systems, and a method for managing the reliability thereof. According to the embodiments, the hosts determine whether to apply one or more reliability measures to associated memory systems based on the characteristics of the data, and can apply the reliability measures(s) deemed appropriate to the memory systems based on the determination.

[0050] FIG. 4 is a drawing illustrating a data processing system (2) according to an embodiment of the present invention.

[0051] Referring to FIG. 4, the data processing system (2) may include a host (5) and SSDs (401-40k) as memory systems (400) coupled to the host (5). The host (5) may include a reliability manager (500) that performs reliability management for the SSDs (401-40k). The SSDs (401-40k) may be host manageable and reliable (HMR) SSDs.

[0052] The reliability manager (500) can analyze the characteristics of data associated with a select memory system among a number of memory systems (i.e., SSDs (401-40k)).

[0053] In some embodiments, the characteristics include data patterns and / or data priorities. For example, a data pattern indicates the frequency of data access of a specific data relative to other data and the type of data (e.g., read or write). Data accessed at a high frequency may be considered hot data, while data accessed at a low frequency may be considered cold data. Regarding data priorities, metadata may have a relatively high priority, and general data (i.e., non-meta data) may have a relatively low priority.

[0054] The reliability manager (500) can determine a reliability control mode that controls at least one of a plurality of reliability methods based on the characteristics of the data of the selected memory system. In some embodiments, one or more reliability methods are determined based on the reliability control mode. The reliability manager (500) can provide reliability management information indicating the reliability control mode to the selected memory system.

[0055] In some embodiments, a number of reliability measures may include Error Correction Code (ECC) measures, read retry measures, intra redundancy measures, and refresh measures. In the ECC measures, the on / off status of an ECC algorithm (e.g., Bose-Chaudhuri-Hocquenghem (BCH), Low Density Parity Check (LDPC)) and code strength (i.e., low strength, high strength) may be controlled. The read retry measures may control the maximum retry count and the retry scale factor. The intra redundancy measures may control the on / off status of intra redundancy (e.g., Redundant Arrays of Inexpensive Disks (RAID)) and the stripe size (i.e., strength) associated with the RAID. The refresh method can control the on / off of data refresh and the refresh frequency (or maximum frequency). The refresh method may include one or more of remapping-based refresh, in-place refresh, or read reclaim.

[0056] In some embodiments, any mode among various reliability control modes including a default mode, a detection mode (or detection only mode), an archiving mode, and a read many mode (or WORM (Write Once Read Many) mode) may be applied.

[0057] In default mode, one or more of the ECC method, read re-execution method, intra-redundancy method and refresh method may be used. In default mode, the reliability manager (500) may notify the SSDs (401-40k) which of these default reliability methods is used.

[0058] The detection-only mode may involve enabling error detection and disabling error correction. In the detection-only mode, the reliability manager (500) may notify the user of the error(s) occurring in the data and the data associated with the error detection.

[0059] In storage mode, intra-redundancy and refresh methods may be utilized. In storage mode, the reliability manager (500) may increase the stripe size associated with the RAID or decrease the strength associated with the RAID. Additionally, the reliability manager (500) may increase the period during which the refresh is executed.

[0060] In the multiple reading mode, a refresh method may be used. In the multiple reading mode, the reliability manager (500) may increase the refresh period and decrease the maximum retry count of the reading retry.

[0061] As described above, the reliability manager (500) determines a reliability control mode based on the characteristics of the data of the selected memory system as shown in Table 2, and determines one or more reliability methods among a plurality of reliability methods based on the reliability control mode. In some embodiments, the host (5) or the user may determine an appropriate reliability control mode based on the user's workload associated with the selected memory system. For example, as illustrated in FIGS. 9a and 9b, the host (5) provides APIs (Application Program Interfaces), and the user may use the APIs of the host (5) to select a specific mode.

[0062] Data characteristics Reliability control mode Intra-redundancy Refresh Cold data Storage Mode Stripe size (+) Strength (-) Refresh(+) read heavy data Multiple reading mode Refresh(+) Max Retry Count(-)

[0063] Referring to Table 2, when the data of the selected memory system is cold data, the reliability manager (500) determines a management mode as a reliability control mode. In the management mode, the reliability manager (500) selects an intra-redundancy plan and a refresh plan, controls the values ​​for the intra-redundancy plan (e.g., increase the stripe size (+) and decrease the intensity (-)), and controls the values ​​for the refresh plan (e.g., increase the refresh frequency (+)). When the data of the selected memory system is read-heavy data, the reliability manager (500) determines a multiple read mode as a reliability control mode. In the multiple read mode, the reliability manager (500) selects a refresh plan and controls the values ​​for the refresh plan (e.g., increase the refresh frequency (+) and decrease the maximum read retry count (-)).

[0064] In some embodiments, the reliability management information may include coverage information indicating the extent to which reliability management is applied to the selected memory system. In an embodiment, the coverage may indicate that the entire selected memory system is subject to reliability management. In another embodiment, the coverage may indicate that only specific parts of the selected memory system, such as one or more NS (Namespaces), NVMe sets, zones, dies, and channels in the selected memory system, are subject to reliability management. The reliability manager (500) may select two or more memory systems and apply the same coverage to all selected memory systems, i.e., SSDs (401-40k). Alternatively, if multiple memory systems are selected, the reliability manager (500) may apply different coverages to different memory systems. That is, the coverage of each SSD (401-40k) may be different.

[0065] As described above, the reliability manager (500) of the host (5) determines whether to apply one or more reliability measures to the SSDs (401-40k) based on the characteristics of the data, and can apply the reliability measure(s) determined to be appropriate to the SSDs (401-40k).

[0066] For metadata having a higher priority than general data, the reliability manager (500) determines appropriate reliability measures associated with the metadata for memory systems and controls the values ​​or parameters of the appropriate reliability measures, such as adjusting (e.g. increasing) the values ​​of ECC and RAID, thereby reducing the occurrence of errors in the metadata and increasing the integrity of the metadata. Accordingly, the embodiments can improve the performance and QoS of the memory systems.

[0067] FIG. 5 is a diagram illustrating the architecture of a data processing system (2) according to an embodiment of the present invention.

[0068] Referring to FIG. 5, the data processing system (2) may include a user space (510), a kernel space (520), and hardware (530). The user space (510) and the kernel space (520) may represent software components of the host (5) and / or SSDs (401-40k) in FIG. 4. In a typical manner, the user space (510) may include applications and standard libraries, and the kernel space (520) may include a file system, a block layer, and a device driver (e.g., an NVMe driver). The hardware (530) may represent hardware components of the SSDs (401-40k) in FIG. 4. Each of the SSDs may support reliability management.

[0069] In an embodiment, the user space (510) may include reliability management libraries. For reliability management of the hardware (530) (i.e., SSDs (401-40k)), an application associated with the reliability manager (500) in FIG. 4 may call APIs (Application Programming Interfaces), and the APIs may be provided to the hardware (530) through an NVMe driver.

[0070] FIG. 6 is a diagram illustrating the APIs (Application Programming Interfaces) of a reliability manager (500) according to an embodiment of the present invention.

[0071] Referring to FIG. 6, the reliability manager (500) may include a plurality of reliability management APIs (510-1 to 510-k). Each of the reliability management APIs (510-1 to 510-k) may correspond to SSDs (401-40k). In other words, the reliability management API (510-1) corresponds to SSD (401), the reliability management API (510-2) corresponds to SSD (402), the reliability management API (510-3) corresponds to SSD (403), and the reliability management API (510-k) corresponds to SSD (40k).

[0072] Each SSD may support one or more of the multiple reliability methods. In other words, each SSD may be an HMR SSD. In some embodiments, the multiple reliability methods may include an ECC (F1) method, a read retry (F2) method, an intra-redundancy (e.g., RAID) (F3) method, and a refresh (F4) method. The ECC and intra-redundancy methods (F1 and F3) are associated with the hardware reliability management of the SSD. The read retry and refresh methods (F2 and F4) are associated with the software reliability management of the SSD.

[0073] FIG. 7 is a drawing illustrating coverage units of a Solid State Drive (SSD) that are covered by operations executed by a reliability manager according to an embodiment of the present invention.

[0074] Referring to FIG. 7, the reliability manager (500) can manage which components / parts of each memory system (i.e., SSD) are covered in terms of reliability operations. In an embodiment, the coverage may extend to the entire SSD (710). In another embodiment, the coverage may extend to only a part of the SSD, such as, for example, one or more NS (Namespaces), one or more NVMe sets, one or more zones, one or more dies, and one or more channels (CHs). In some embodiments, the reliability manager (500) may cover all SSDs to the same degree, or cover different SSDs differently. In the latter case, specific components / parts of one SSD may be covered, but the same components / parts of another SSD may not be covered.

[0075] FIG. 8 is a flowchart illustrating a reliability management method (800) according to an embodiment of the present invention.

[0076] Referring to FIG. 8, the reliability management method (800) can be executed by the reliability manager (500) in FIG. 4 to 6 and can be used for a number of memory systems (e.g., SSDs).

[0077] In operation 810, the reliability manager (500) can analyze the characteristics of data associated with a selected memory system among a number of memory systems.

[0078] In some embodiments, the characteristics include data patterns and / or data priorities. For example, in terms of data patterns, the reliability manager (500) may analyze the frequency of access to specific data relative to other data and / or the type of data (e.g., read or write), for example, the ratio of read data to write data. Additionally, data may be analyzed in terms of priority. Specific data may have a relatively high priority, and other data may have a relatively low priority, and the relative amount of these two types of data may be analyzed.

[0079] In operation 820, the reliability manager (500) can determine a reliability control mode that controls at least one of a plurality of reliability methods based on the characteristics. In operation 830, the reliability manager (500) can provide reliability management information indicating a reliability control mode to be used in a selected memory system.

[0080] In some embodiments, a number of reliability measures may include an ECC measure, a read re-execution measure, an intra-redundancy measure, and a refresh measure.

[0081] In some embodiments, the reliability control mode may include a default mode, a detection mode (or detection-only mode), a storage mode, and a multiple read mode (or WORM mode). In some embodiments, the reliability management information may include coverage information indicating which part of the selected memory system the reliability control mode is applied to. In an embodiment, the reliability control mode may be applied to the entire selected memory system. In another embodiment, the reliability control mode may be applied to only a part of the selected memory system, such as one or more Namespaces (NS), NVMe sets, zones, dies, and channels in the selected memory system.

[0082] FIGS. 9a and 9b show examples of reliability management information implemented by APIs used by a reliability manager (500) to perform reliability management according to an embodiment of the present invention. In some embodiments, as illustrated in FIGS. 9a and 9b, a host (5) provides APIs, and a user may use the APIs to select a specific mode. Each API may provide a selected memory system (e.g., SSD) on which reliability management will be performed, along with coverage information, along with information regarding which reliability control mode will be applied. If the coverage is less than the entire SSD, additional information regarding the part(s) to be subject to reliability management may be provided.

[0083] Referring to FIG. 9a, the reliability management information may include mode information and coverage information. In the illustrated example, the mode information may represent a default mode ("1"), a detection mode (or detection-only mode) ("2"), a storage mode ("3"), or a multiple read mode (or WORM mode) ("4"). In the illustrated example, the coverage information may represent the coverage of the selected SSD, i.e., the entire selected SSD ("1"), or part(s) of the selected SSD, such as one or more NSs ("2"), NVMe sets ("3"), and zones ("4") in the selected SSD.

[0084] If the reliability plan is applied to only part(s) of the selected SSD, the reliability management information may additionally include titles or identifiers (IDs) for part(s) of the selected SSD, such as NS("2"), NVMe set("3"), and zone("4").

[0085] Referring to FIG. 9b, reliability management information can be manually generated by the user. Reliability management information may include mode information and coverage information.

[0086] In the illustrated example, a default mode ("1") is set, and ECC schemes, read retry schemes (i.e., RETRY), intra-redundancy schemes (i.e., RAID), and refresh schemes can be set.

[0087] In the default mode ("1"), the coverage information indicates how much of the selected SSD is under reliability management, ranging from the entire selected SSD ("1") to a portion(s) of the selected SSD identified by one or more NSs ("2"), NVMe sets ("3"), zones ("4"), dies ("5"), and channels ("6").

[0088] If the reliability scheme is used for only a portion of the selected SSD, the reliability management information may additionally include identifiers (IDs) for the portion(s) of the selected SSD, such as NSs ("2"), NVMe sets ("3"), zones ("4"), dies ("5"), and channels ("6").

[0089] In the case of the ECC scheme, the ECC algorithm's On / Off status and code strength can be set. "0" indicates that the ECC algorithm is Off. "1" indicates that the ECC algorithm is On. "2" indicates that the ECC (BCH, low parity) is at a low strength. "3" indicates that the ECC (LDPC, high parity) is at a high strength.

[0090] In the case of a read retry (i.e., retry) method, the maximum number of retries, i.e., the maximum retry count, can be set.

[0091] For intra-redundancy (i.e., RAID) schemes, the on / off status of the intra-redundancy (e.g., RAID) and the stripe size (i.e., strength) associated with the RAID can be set. "0" indicates that the RAID scheme is off. "1" indicates that the RAID scheme is on. A numerical value representing the stripe size can be set.

[0092] For the refresh plan, the on / off status and the duration (or maximum frequency) of the refresh plan can be set. "0" indicates that the refresh plan is off. "1" indicates that the refresh plan is on. The maximum frequency at which the refresh plan is applied can be set in terms of numerical values.

[0093] As described above, embodiments provide a host capable of managing the reliability of memory systems and a method for managing the reliability thereof. The host determines appropriate reliability measures associated with data for the memory systems and controls the values ​​of the appropriate reliability measures. Accordingly, the embodiments can improve the performance and QoS of the memory systems.

[0094] Although the present invention has been illustrated and described in the context of various embodiments, the invention is not limited to any of the embodiments, nor is it limited to any specific details provided. As those skilled in the art will be aware from the foregoing disclosure, many alternative methods of implementing the invention exist. The disclosed embodiments are illustrative and not limiting. The intent of the invention is to encompass all modifications and alternatives that fall within the scope of the claims.

Claims

Claim 1 A data processing system comprising a plurality of memory systems; and a host including a reliability manager coupled to the plurality of memory systems, wherein the reliability manager is configured to analyze data characteristics associated with a selected memory system among the plurality of memory systems, determine one or more reliability measures and a reliability control mode among a plurality of reliability measures to be applied to the selected memory system based on the characteristics, and provide reliability management information indicating the reliability control mode to the selected memory system, wherein the plurality of reliability measures include an Error Correction Code (ECC) measure, a read retry measure, an intra redundancy measure, and a refresh measure, and wherein the reliability manager includes a plurality of reliability management APIs (Application Programming Interfaces) corresponding to each of the plurality of memory systems. Claim 2 A data processing system according to claim 1, wherein the characteristics include at least one of a data pattern and a data priority. Claim 3 In claim 2, the data pattern is a data processing system including data access frequency and data type. Claim 4 In claim 1, the ECC method comprises a data processing system that controls the on and off of an ECC algorithm and code strength. Claim 5 A data processing system according to claim 1, wherein the read retry method comprises controlling a maximum retry count and a retry scale factor. Claim 6 In claim 1, the intra-redundancy method comprises a data processing system that controls the on and off of RAID (Redundant Arrays of Inexpensive Disks) and the stripe size associated with RAID. Claim 7 In claim 1, the refresh method comprises a data processing system that controls the on and off of data refresh and the refresh period. Claim 8 A data processing system according to claim 1, wherein the reliability control mode includes a default mode, a detection mode, an archiving mode, and a read-many mode, wherein in the default mode, one or more of an ECC method, a read retry method, an intra-redundancy method, and a refresh method are set and applied, in the detection mode, error detection is controlled, in the archiving mode, an intra-redundancy method and a refresh method are controlled and applied, and in the read-many mode, a refresh method is controlled and applied. Claim 9 In claim 1, the reliability management information includes coverage information indicating the portion of the selected memory system to which the reliability control mode is to be applied, wherein the portion to which the reliability control mode is to be applied includes the entire selected memory system, and the data processing system. Claim 10 In claim 9, if the coverage information indicates that a part of the selected memory system is covered, the coverage information further comprises information on which of one or more parts of the selected memory system is covered. Claim 11 A method for operating a host coupled to multiple memory systems, wherein a reliability manager of the host analyzes the characteristics of data associated with a selected memory system among the multiple memory systems, determines one or more reliability measures and a reliability control mode among multiple reliability measures to be applied to the selected memory system based on the characteristics, and provides reliability management information indicating the reliability control mode to the selected memory system, wherein the multiple reliability measures include an Error Correction Code (ECC) measure, a read retry measure, an intra redundancy measure, and a refresh measure, and the reliability manager includes multiple reliability management APIs (Application Programming Interfaces) corresponding to each of the multiple memory systems. Claim 12 In claim 11, the method wherein the characteristics include at least one of a data pattern and a data priority. Claim 13 In claim 12, the data pattern comprises a method including the access frequency of the data and the type of the data. Claim 14 In claim 11, the ECC method comprises controlling the on and off of an ECC algorithm and the code strength. Claim 15 In claim 11, the read retry method comprises controlling the maximum retry count and the retry scale factor. Claim 16 In claim 11, the intra-redundancy method comprises controlling the on and off of RAID (Redundant Arrays of Inexpensive Disks) and the stripe size associated with RAID. Claim 17 In claim 11, the refresh method comprises controlling the on and off of data refresh and the refresh period. Claim 18 In claim 11, the reliability control mode comprises a default mode, a detection mode, an archiving mode, and a read-many mode, wherein in the default mode, one or more of an ECC scheme, a read retry scheme, an intra-redundancy scheme, and a refresh scheme are set and applied, in the detection mode, error detection is controlled, in the archiving mode, an intra-redundancy scheme and a refresh scheme are controlled and applied, and in the read-many mode, a refresh scheme is controlled and applied. Claim 19 In claim 11, the reliability management information includes coverage information indicating the portion of the selected memory system to which the reliability control mode is to be applied, wherein the portion to which the reliability control mode is to be applied includes the entire selected memory system. Claim 20 In claim 19, if the coverage information indicates that a part of the selected memory system is covered, the coverage information further includes information on which of one or more parts of the selected memory system is covered.

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