Backside power rail architecture

Abstract

Various embodiments described herein refer to a device having back power rails, including first back power rails that supply core voltage to memory logic and second back power rails that supply peripheral voltage to control logic. In some embodiments, at least one first back power rail may have a rail break that interrupts continuity so that at least one second back power rail can supply peripheral voltage to control logic.

Description

Background Technology

[0001] This section is intended to provide information regarding the understanding of the various technologies described in this specification. As the title of this section implies, this is a discussion of related technologies that by no means constitute prior art. Generally, related technologies may or may not be considered prior art. Accordingly, any references in this section should be read in this light and understood as not being an acknowledgment of any prior art.

[0002] In some memory architecture designs, conventional power rails can be embedded in the memory, where metal power lines are embedded in the substrate and used as power rails for voltage distribution from backside circuitry. However, in these conventional memory designs, memory cells typically use front power rails for voltage distribution to the frontside circuitry containing the memory cells. Unfortunately, conventional memory designs are inefficient in that the use of front power rails for memory cells incurs an area penalty during manufacturing. Therefore, it is necessary to improve conventional memory designs to enhance the area efficiency of modern memory architectures. Brief explanation of the drawing

[0003] Embodiments of various techniques are described herein with reference to the accompanying drawings. However, it should be understood that the accompanying drawings are intended to illustrate only the various embodiments described herein and are not intended to limit the embodiments of the various techniques described herein. FIG. 1 illustrates a schematic diagram of a buried power rail (BPR) architecture according to various embodiments described in this specification. FIG. 2 illustrates a schematic diagram of a power distribution network (PDN) according to various embodiments described in this specification. FIG. 3 illustrates a schematic diagram of a voltage domain network (VDN) according to various embodiments described in this specification. FIG. 4 illustrates a diagram of a method for providing a buried power rail (BPR) architecture according to the embodiments described in this specification. Specific details for implementing the invention

[0004] Various embodiments described herein refer to back power rail architectures for control and wordline decoder circuits in various memory applications. Additionally, various schemes and techniques described herein may provide power distribution architectures that operate to provide a back power distribution network for memory applications. Various schemes and techniques described herein may provide front / back power rails that supply core voltage to memory control circuits and front / back power rails that supply peripheral voltage thereto. For example, a back power rail architecture may have first back power rails that supply core voltage to memory logic and second back power rails that supply peripheral voltage to control logic. Additionally, in this example, at least one first back power rail may have a rail break that interrupts continuity to allow at least one second back power rail to supply peripheral voltage to control logic. Additionally, in some cases, the continuous single-line section may provide a spatial opening, thereby allowing coupling of at least one second back power rail to the memory control circuit section.

[0005] In various embodiments, the backside power distribution schemes and techniques described herein may provide random access memory (RAM) applications, including static random access memory (SRAM). For example, regarding backside power domains for SRAM technology, metallization may be provided as embedded power rails on the front (e.g., above the device) and also on the back (e.g., below the device). In the logic domain, the embedded power rails may power memory components within a core memory array, thereby allowing a number of different power domains to be used to avoid area penalties. Various embodiments described herein may also provide overall power domain schemes for memory applications, including various uses of frontside-to-backside transition cells having transition vias, for example. These aspects, along with various other features, are described in more detail herein.

[0006] Various embodiments of back power rail architectures, along with various back power distribution schemes and related techniques, will be described in more detail in this specification with reference to FIGS. 1 through 4.

[0007] FIG. 1 illustrates a drawing (100) of a buried power rail (BPR) architecture (104) according to various embodiments described in this specification.

[0008] In various embodiments, the BPR architecture (104) may be implemented as a system or device having various integrated circuit (IC) components arranged and coupled together as a combination or assembly of parts providing physical circuit designs and / or related structures. In some cases, the method of designing, providing, and constructing the BPR architecture (104) as an integrated system or device may involve the use of various IC circuit components described herein, thereby enabling various back-side power distribution schemes and techniques associated therewith. The BPR architecture (104) may be integrated with computing circuits and related components on a single chip, and the BPR architecture (104) may be implemented in some embedded systems for automotive, electronic, mobile, server, and Internet-of-things (IoT) applications.

[0009] As illustrated in FIG. 1, the BPR architecture (104) may include a frontside power network (FSPN) (108) configured for a memory architecture, such as a backside power section for a memory control circuit section. In some cases, the frontside power network (FSPN) (108) may include front metal layers that supply core voltage in a plurality of voltage domains, wherein one or more voltage domains of the core voltage may refer to an internal core voltage domain (VDDC) and / or an external core voltage domain (VDDCE).

[0010] In some embodiments, the front power network (FSPN) (108) may include various types of components, circuits, and metal layers. For example, the front power network (FSPN) (108) may include front power rails coupled to a memory circuit having an array of bit cells arranged in columns and rows, for example, header logic and power-gating control logic. Also, in some cases, the front power network (FSPN) (108) may include a plurality (N) of front metal layers (e.g., FM0, FM1, FM2, ..., FMN) along with frontside inter-layer vias (FSV).

[0011] The BPR architecture (104) may include a back power network (BSPN) (118) that provides power distribution for memory control circuits, such as a column multiplexer circuit (COLMUX), a sense amplifier circuit (SA), a power gate input / output (PG I / O) circuit, and a power gate controller (PG_CNTL). Additionally, the back power network (BSPN) (118) may be configured to provide power in various different voltage domains for memory control logic placed at the front. Thus, the back power distribution network (BSPN) (118) may be configured to supply core voltages, peripheral voltages, and / or ground.

[0012] In some embodiments, the back power network (BSPN) (118) may include one or more embedded metal layers supplying ambient voltage in a plurality of domains, and the plurality of domains of ambient voltage are referred to as the internal ambient voltage domain (VDDP) and the external ambient voltage domain (VDDPE). Additionally, the plurality of domains of ambient voltage may refer to the internal core voltage domain (VDDC) and the external core voltage domain (VDDCE). Additionally, in various cases, the ground supply may refer to the external ground (VSSE).

[0013] In some embodiments, the backside power network (BSPN) (118) may include backside metal layers (e.g., BM0). For example, the backside power network (BSPN) (118) may include a backside power network having backside power rails. Additionally, the backside power network (BSPN) (118) may have backside metal layers (e.g., BM0, BM1, BM2, ..., BMN) together with backside interlayer vias (BSV). The backside power network (BSPN) (118) may also include backside power connection bumps (BSB).

[0014] The BPR architecture (104) may have a front-to-back transition architecture (114) with buried transition vias (BTVs) used to couple the buried back power network (BSPN) to the front power network (FSPN). The buried transition vias (BTVs) (124) may be configured to provide power transitions between the back power network (BSPN) (118) and the front power network (FSPN) (108). Thus, in some cases, the BPR architecture (104) may be configured to transition the back power rails of the back power network to the front power rails of the front power network, thereby providing power taps from the back power network (BSPN) to the memory circuit. Additionally, the front-to-back transition section (114) may be referred to as a buried transition architecture that can have back-to-front transition cells with buried transition vias (124) that provide coupling transitions between the back power network (BSPN) (118) and the front power network (FSPN) (108).

[0015] In some embodiments, the back power rail (BPR) architecture (104) may be configured to operate as a power distribution network architecture that utilizes back buried metal in the back power network (BSPN) for the back power rails and also utilizes front metal in the front power network (FSPN) for the front power rails. Additionally, the front power network (FSPN) may use front metal, and the back power network (BSPN) may use back buried metal placed under the front metal of the front power network (FSPN). Additionally, the transition architecture may refer to a buried transition architecture placed between the back buried metal of the back power network (BSPN) and the front metal of the front power network (FSPN).

[0016] In some embodiments, the buried transition architecture may be configured to use back-to-front transition cells having transition vias that couple the back buried metal of the back power network (BSPN) to the front metal of the front power network (FSPN). The front power network (FSPN) may use front metal layers to supply core voltage in one or more voltage domains, such as an internal core voltage domain (VDDC) and / or an external core voltage domain (VDDCE). Additionally, the back power network (BSPN) may use one or more buried metal layers to supply peripheral voltage in multiple domains, such as an internal peripheral voltage domain (VDDP) and an external peripheral voltage domain (VDDPE). In some embodiments, the BSPN may be configured to provide, supply, and utilize the internal core voltage domain (VDDC) and / or the external core voltage domain (VDDCE).

[0017] In various embodiments, the various schemes and techniques described herein may provide a power distribution network architecture for transferring power from the back to the front using buried power rails. Additionally, the power distribution network architecture may be configured to use back-buried metal for the back power rails and front metal for the front power rails. Additionally, in some cases, the power distribution network architecture may use header-based power tapping circuitry in multiple different voltage domains, such as VDDC, VDDCE, VDDP, and VDDPE, along with a single ground, such as external ground (VSSE). These embodiments and various other features and characteristics are described in more detail below with reference to FIGS. 2 and FIGS. 3.

[0018] FIG. 2 illustrates a schematic diagram (200) related to a power distribution network (PDN) architecture (204) according to various embodiments described in this specification.

[0019] In various embodiments, the PDN architecture (204) may be implemented as a system or device having various integrated circuit (IC) components arranged and coupled together as a combination or assembly of parts providing physical circuit designs and related structures. In some cases, the method of designing, providing, and / or constructing the PDN architecture (204) as an integrated system or device may involve the use of various IC circuit components described herein, thereby enabling various back-side power distribution techniques associated therewith. Additionally, in some cases, the PDN architecture (204) may be integrated with computing circuits and related components on a single chip, and the PDN architecture (204) may be implemented in various embedded systems for automotive, electronic, mobile, server, and Internet of Things (IoT) applications.

[0020] As illustrated in FIG. 2, the power distribution network (PDN) (204) may include a power distribution architecture having a front power network having front power rails (e.g., M0) and a back power network having back power rails (e.g., BM0). The front power rails may be configured to supply core voltage to memory circuits in various core voltage domains (e.g., VDDC, VDDCE), and the back power rails may also be configured to supply peripheral voltage to memory control circuits in various peripheral voltage domains (e.g., VDDP, VDDPE). Additionally, the power distribution architecture may use transition vias that provide coupling transitions from the back power rails of the back power network to the front power rails of the front power network. The transition vias may refer to buried transition vias (BTV) (214) configured to provide coupling transitions between the back power network and the front power network.

[0021] The front power network of the power distribution network (PDN) (204) may have various types of components, circuits, and metal layers coupled to the core voltage domains (VDDC, VDDCE). For example, the front power network (FSPN) may include various memory-related circuits and / or components on the top and bottom (bot) and on the right and left sides operating in the core voltage domains (VDDC, VDDCE). In some cases, the term top may be referred to as upper, and the term bottom (bot) may be referred to as lower, where the top (or upper) layer may be placed on the bottom (or lower) layer, which may be their respective relative positions within a multi-layer memory stack in various memory applications.

[0022] The back power network (BSPN) of the power distribution network (PDN) (204) may have various buried metal layers coupled to one or more core voltage and / or peripheral voltage domains (VDDCE, VDDP, VDDPE). For example, the back power network (BSPN) may be coupled to various memory circuits and / or components that may be configured to operate in the internal peripheral voltage domain (VDDP) and / or the external peripheral voltage domain (VDDPE). The transition architecture may include buried transition vias (BTVs) that provide power taps for transitionally coupling the back metals (BM0) of the back power rails to the front metals (M0) of the front power rails. Additionally, in some cases, the back power rail architecture may be configured to provide BTVs between the back power rails and the front power rails as coupling transitions (and / or power transfer transitions) to provide back-to-front power taps from the back power network to the front power network.

[0023] In some embodiments, the front power network may be configured to use a front metal (e.g., M0) for the front power rails, and the back power network may also be configured to use a back buried metal (e.g., BM0) for the back power rails placed under the front metal of the front power network. Additionally, in some cases, the back power rail architecture may be configured to operate as a power distribution network architecture providing buried transition vias (BTVs), which may be placed between the front metal of the front power network and the back buried metal of the back power network.

[0024] In some embodiments, the back power rail schemes and techniques described herein may provide a power distribution network (PDN) architecture that uses a mixture of back-to-front power rails. As described herein, the power distribution network architecture may be configured to use back buried metal for the back power rails and also to use front metal for the front power rails. Additionally, the power distribution network architecture may use control circuits in a number of different voltage domains, such as VDDC, VDDCE, VDDP, VDDPE, along with a single ground, such as VSSE. Additionally, the power distribution network architecture may incorporate the use of buried power rails equipped with buried transition vias (BTVs) and buried metal layers (BM0).

[0025] As illustrated in FIG. 2, a power distribution network (PDN) (204) may have one or more power rails (R1, R2), for example, including a first power rail (R1) and a second power rail (R2). In the power rails (R1, R2), a front metal (M0) may be formed over a back metal (BM0), and a BTV metal may be used to couple the front metal (M0) to the back metal (BM0). In some embodiments, parts of the power rails (R1, R2) may be coupled to different power supplies in different power domains. For example, as illustrated in FIG. 2, parts of the power rails (R1, R2) may be used to couple the FS metal (M0) and the BS metal (BM0) to a ground, such as an external ground (VSSE). Additionally, as shown in FIG. 2, other parts of the power rails (R1, R2) can be used to couple the front metal (M0) and back metal (BM0) to various different peripheral domains, such as internal and external peripheral domains (VDDP, VDDPE).

[0026] In some embodiments, the back power rail (BPR) architecture may include a first row (R1) having first back power rails in first regions (210) that supply core voltage (VDDC) to memory logic and second back power rails in second regions (214) that supply peripheral voltage (VDDP) to control logic. As illustrated in FIG. 2, at least one first back power rail may be configured to have one or more rail breaks (RB) that interrupt continuity, thereby enabling at least one second back power rail in second regions (214) to supply peripheral voltage (VDDP) to control logic. The first back power rails may provide a first net (VDDC) that supplies core voltage (VDDC) to memory logic, and the second back power rails may provide a second net (VDDP) that supplies peripheral voltage (VDDP) to control logic. A rail single-line section (RB) may provide a spatial opening within at least one first back power rail to allow coupling of at least one second back power rail to control logic. In some cases, the core voltage may refer to the internal core voltage (VDDC), and the peripheral voltage may refer to the internal peripheral voltage (VDDP).

[0027] In some embodiments, the back power rail (BPR) architecture may include a second row (R2) having first back power rails that supply a core voltage (VDDCE) to memory logic, second back power rails that supply an ambient voltage (VDDPE) to control logic, and third back power rails that couple the memory logic and control logic to an external ground (VSSE). As illustrated in FIG. 2, at least one first back power rail may have a plurality of rail breaks (RB) that interrupt continuity, thereby enabling at least one second back power rail to supply an ambient voltage (VDDPE) to control logic and thereby enabling at least one third back power rail to couple the memory logic and control logic to ground (VSSE). The first back power rails may provide a first net (VDDCE) that supplies a core voltage (VDDCE) to the memory logic, and the second back power rails may also provide a second net (VDDPE) that supplies an ambient voltage (VDDPE) to the control logic. A plurality of rail open sections (RB) provide a plurality of spatial openings within at least one first back power rail to allow coupling of at least one second back power rail to the control logic and to allow at least one third back power rail to couple the memory logic and the control logic to ground (VSSE). In some cases, the core voltage may refer to an external core voltage (VDDCE), and the ambient voltage may refer to an external ambient voltage (VDDPE).

[0028] In some embodiments, as illustrated in FIG. 2, the first power rail (R1) may use a front power rail (M0) having rail breaks (RB) that provide a break in continuity, thereby enabling one or more corresponding back power rails (BTV / BM0) to supply an ambient voltage (VDDP) to a memory control circuit placed on the front. Additionally, the second power rail (R2) may have a continuous front power rail (M0), and the second power rail (R2) may be coupled to ground (VSSE). However, various other configurations having different voltage domains may be used to support discontinuous rails having one or more continuous breaks and / or continuous rails. Accordingly, various embodiments described herein may use back metal having substantially low resistance for power distribution. In this way, the PDN (204) may be configured to use a novel architecture of back power distribution for the memory control and wordline driver circuits having back power rails to improve the current-resistance (IR) drop, performance, and area of ​​the memory control circuit.

[0029] In some embodiments, as illustrated in FIG. 2, the PDN architecture (204) may provide a back power rail (BPR) architecture having a plurality of rows of back power rails configured to supply various different core and peripheral voltage domains (e.g., VDDC, VDDCE, VDP, VDDPE). For example, the rows of back power rails may be used to supply power to a memory circuit having, for example, memory logic and control logic. The rows of back power rails (R1, R2) may have one or more rail open sections (RB) that enable a plurality of different nets (VDDC, VDDCE, VDP, VDDPE, VSSE) to supply power to the memory logic and control logic. Additionally, the alignment of rail disconnections (RBs) in one or more first regions (210) may allow core voltages in multiple domains (e.g., VDDC, VDDCE) to be supplied from different rows (R1, R2) of the back power rails. Additionally, the alignment of rail disconnections (RBs) in one or more second regions (214) may allow peripheral voltages in multiple domains (e.g., VDDP, VDDPE) to be supplied from different rows (R1, R2) of the back power rails. As illustrated in FIG. 2, a plurality of rows (R1, R2) of back power rails may include a first row (R1) of back power rails and a second row (R2) of back power rails, wherein the first row (R1) of back power rails may have one or more rail single-line sections (RB) that enable a plurality of different nets (VDDC, VDDP) to supply power to memory logic and control logic, and the second row (R2) of back power rails may also have one or more rail single-line sections (RB) that enable a plurality of different nets (VDDCE, VDDPE, VSSE) to supply power to memory logic and control logic.

[0030] Additionally, in some embodiments, portions of the first row (R1) of the back power rails within one or more first regions (210) may be vertically aligned with corresponding portions of the second row (R2) of the back power rails within one or more first regions (210). Additionally, portions of the first row (R1) of the back power rails within one or more second regions (214) may be vertically aligned with corresponding portions of the second row (R2) of the back power rails within one or more second regions (214). As illustrated in FIG. 2, one or more rail single-line sections (RB) may provide spatial openings within the back power rails, thereby enabling a number of different nets (VDDC, VDDCE, VDP, VDDPE, VSSE) to supply power to memory logic and control logic. As described in this specification, a plurality of domains of core voltage may include an internal core voltage domain (VDDC) and an external core voltage domain (VDDCE), and a plurality of domains of peripheral voltage may include an internal peripheral voltage domain (VDDP) and an external peripheral voltage domain (VDDPE), and one or more back power rails are coupled to external ground (VSSE).

[0031] In some embodiments, the PDN (204) may provide and couple power rails (R1, R2) to a memory control circuit formed on the front and back power rails. Further details regarding a voltage domain network (VDN) (304) including a memory architecture (e.g., core array, decoders, drivers, headers, control unit, etc.) are described below with reference to FIG. 3. Also, referring to FIG. 2 and FIG. 3, the alignment lines (B1 to B10) of FIG. 2 correspond to the same alignment lines (B1 to B10) of FIG. 3.

[0032] FIG. 3 illustrates a schematic diagram of a voltage domain network (VDN) (304) according to various embodiments described in this specification.

[0033] In various embodiments, the voltage domain network (VDN) architecture (304) may be implemented as a system or device having various integrated circuit (IC) components arranged and coupled together as a combination or assembly of parts providing physical circuit designs and related structures. In some cases, the method of designing, providing, and constructing the VDN architecture (304) as an integrated system or device may involve the use of various IC circuit components described herein to implement various associated back-side power distribution schemes and techniques. Additionally, in some cases, the VDN (304) may be integrated with computing circuits and related components on a single chip, and the VDN (304) may be implemented in various embedded systems for automotive, electronic, mobile, server, and Internet of Things (IoT) applications.

[0034] As illustrated in FIG. 3, the voltage domain network (VDN) (304) may include memory control logic and / or circuitry having various circuits and / or components, including a wordline decoder / controller (324), wordline drivers (308A, 308B), and wordline headers (312A, 312B) configured to operate as power-gating headers for power-gating the wordline drivers (308A, 308B). In some cases, the wordline drivers (308A, 308B) may have a lower wordline driver (WLD_bot (308B)) for a lower core array and an upper wordline driver (WLD_top (308A)) for an upper core array. Wordline headers (312A, 312B) may include an upper wordline header (WLH_top (312A)) that can operate as an upper power-gating header for an upper wordline driver (WLD_top (308A)), and a lower wordline header (WLH_bot (312B)) that also operates as a lower power-gating header for a lower wordline driver (WLD_bot (308B)). Memory control logic and / or circuitry may include an upper controller (CNTL_top (318A)) for an upper wordline driver (WLD_top (308A)) and a lower controller (CNTL_bot (318B)) for a lower wordline driver (WLD_bot (308B)). Additionally, the memory control logic and / or circuit may include a power-gating controller (PG_CNTL (328)) that can be configured to power gate the wordline controller (CNTL (324)).

[0035] In some embodiments, the circuits and / or components of the memory control circuitry may be configured to operate in various different voltage domains. For example, as illustrated in FIG. 3, the wordline drivers (WLD_top (308A), WLD_bot (308B)) may be configured to operate in the VDDC domain, and the wordline headers (WLH_top (312A), WLH_bot (312B)) may be configured to operate in the VDDCE domain. Additionally, in some embodiments, the wordline controller (CNTL (324)) may be configured to operate in the VDDPE domain, and the upper controller (CNTL_top (318A)) and lower controller (CNTL_bot (318B)) may be configured to operate in the VDDP domain. Additionally, in some embodiments, the power-gating controller (PG_CNTL (328)) may be configured to operate in the VDDPE domain.

[0036] As illustrated with reference to FIGS. 2 and 3, a combination of the power distribution network (PDN) (204) of FIG. 2 and the voltage domain network (VDN) of FIG. 3 can be configured to provide a power rail architecture for memory control applications. Accordingly, in some embodiments, as illustrated in FIGS. 2 and 3, the power rail architecture may include a front power distribution network (FPDN) having front power rails coupled to the memory control circuitry and a back power distribution network (BPDN) having back power rails. Additionally, as illustrated in FIG. 2, at least one of the front power rails may have one or more rail breaks in continuity that provide spatial openings to allow coupling of at least one corresponding back power rail to the memory control logic. In some embodiments, the front power rails may be formed of front metal, and the back power rails may be formed of embedded metal placed beneath the front metal.

[0037] In some embodiments, a front power distribution network (FPDN) may supply core voltage to the memory control circuit via front power rails, and a back power distribution network (BPDN) may supply peripheral voltage via back power rails. Additionally, back power rails may refer to buried power rails placed beneath the front power rails. The power rail architecture may also include transition cells that provide front-to-back power distribution from the back power distribution network to the front distribution network, and the transition cells may also include buried transition vias configured to couple at least one corresponding back power rail to the memory control circuit.

[0038] Furthermore, the core voltage may be supplied to one or more different core voltage domains, such as an internal core voltage domain (VDDC) and an external core voltage domain (VDDCE). Additionally, the peripheral voltage may be supplied to different peripheral voltage domains, such as an internal peripheral voltage domain (VDDP) and / or an external peripheral voltage domain (VDDPE). Additionally, one or more front power rails and / or one or more back power rails may be coupled to external ground (VSSE).

[0039] In some embodiments, as illustrated in FIG. 3, the VDN architecture (304) provides a plurality of regions (310, 314) corresponding to and aligned with the plurality of regions (210, 214) of FIG. 2. The plurality of regions (310, 314) refer to memory logic within the first regions (310) having wordline headers (312A, 312B) and wordline drivers (308A, 308B), and the plurality of regions (310, 314) refer to control logic within the second regions (314) having a wordline controller (324) along with various other control logic. The wordline drivers (308A, 308B) include an upper wordline driver (308A) for an upper core array and a lower wordline driver (308B) for a lower core array. Wordline headers (312A, 312B) may include a lower wordline header (312B) that operates as a lower power-gating header for a lower wordline driver (308B) and an upper wordline header (312A) that operates as an upper power-gating header for an upper wordline driver (308A). The control logic may include a lower controller (318B) for a lower wordline driver (308B) and an upper controller (318A) for an upper wordline driver (308A), and the control logic may also include a power gate controller (328) configured to power-gate the wordline controller (324).

[0040] FIG. 4 illustrates a process flow diagram of a method (400) for providing a buried power rail (BPR) architecture according to the embodiments described in this specification.

[0041] It should be understood that even though the method (400) represents the execution of operations in a specific order, in some cases, various specific parts of the operations may be executed in a different order and on different systems. In other cases, additional operations and / or steps may be added to the method (400) and / or omitted therefrom. Additionally, the method (400) may be implemented in hardware and / or software. If implemented in hardware, the method (400) may be implemented as various components and / or circuits as described herein with reference to FIGS. 1 through 3. Additionally, if implemented in software, the method (400) may be implemented as a program and / or software instruction process configured to provide various back power distribution schemes and techniques as described herein. Additionally, if implemented in software, various instructions related to implementing the method (400) may be stored in memory and / or a database. For example, various types of computing devices having a processor and memory can be configured to perform the method (400).

[0042] In various embodiments, the method (400) may refer to a method of designing, providing, building, fabricating, and / or manufacturing a back power rail architecture as an integrated system, device, and / or circuit capable of implementing the associated back power distribution schemes and techniques by involving the use of various IC circuit components described herein. In some embodiments, the back power rail architecture may be integrated with computing circuits and other related components on a single chip, and the back power distribution circuits may be implemented in various embedded systems for automotive, electronic, mobile, server, and Internet of Things (IoT) applications, including remote sensor nodes.

[0043] In block (410), the method (400) may supply (or provide) core voltage to memory logic using first back power rails. The first back power rails provide a first net that supplies core voltage to memory logic. Core voltage may refer to internal core voltage (VDDC) or external core voltage (VDDCE). Memory logic may have wordline headers and wordline drivers. Wordline drivers may include an upper wordline driver for an upper core array and a lower wordline driver for a lower core array, and wordline headers may include an upper wordline header acting as an upper power-gating header for the upper wordline driver and a lower wordline header acting as a lower power-gating header for the lower wordline driver.

[0044] In block (420), the method (400) may supply (or provide) an ambient voltage to the control logic using second back power rails. The second back power rails provide a second network that supplies the ambient voltage to the control logic. The ambient voltage may refer to an internal ambient voltage (VDDP) or an external ambient voltage (VDDPE). Additionally, the control logic may have a wordline controller. The control logic includes an upper controller for an upper wordline driver and a lower controller for a lower wordline driver, and the control logic also includes a power gate controller for power-gating the wordline controller.

[0045] In block (430), the method (400) can interrupt the continuity of at least one first back power rail with at least one rail break so that at least one second back power rail can supply ambient voltage to the control logic. At least one rail break may provide a spatial opening within at least one first back power rail to allow coupling of at least one second back power rail to the control logic.

[0046] In some embodiments, the method (400) may provide a front power distribution network providing front power rails, and the method (400) may provide a back power distribution network providing first back power rails and second back power rails positioned below the front power rails. Additionally, the method (400) may provide transition cells configured for front-to-back power distribution. The first back power rails and second back power rails may refer to buried power rails positioned below the front power rails, and the transition cells may also refer to buried transition vias, which are used to couple the buried power rails to memory logic and control logic. The front power rails may be formed of front metal, and the back power rails may be formed of buried back metal.

[0047] The subject matter of the claims is not intended to be limited to the embodiments and examples provided herein, but to include combinations of elements of different embodiments according to the claims and modified forms of these embodiments including parts of the embodiments. It should be understood that in the development of any such embodiment, many implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints that may vary from embodiment to embodiment, as in any engineering or design project. Furthermore, it should be understood that while such development efforts may be complex and time-consuming, they will nevertheless be the routine work of design, fabrication, and manufacturing for those skilled in the art who have an interest in the present invention.

[0048] Various embodiments of a device having first back power rails that supply core voltage to memory logic are described herein, and the device may include second back power rails that supply peripheral voltage to control logic. At least one first back power rail may have a rail break that interrupts continuity so that at least one second back power rail can supply peripheral voltage to control logic.

[0049] Various embodiments of a device having first back power rails that supply core voltage to memory logic are described herein, and the device may include second back power rails that supply ambient voltage to control logic. Additionally, the device may include third back power rails that couple memory logic and control logic to ground. In some cases, at least one first back power rail has a plurality of rail breaks that interrupt continuity so that at least one second back power rail can supply ambient voltage to control logic and at least one third back power rail can couple memory logic and control logic to ground.

[0050] Various embodiments of a device having a memory circuit portion having memory logic and control logic are described herein. The device may include rows of back power rails having one or more rail disconnects that enable a plurality of different nets to supply power to the memory logic and control logic. In some cases, alignment of the rail disconnects in one or more first regions enables core voltage in a plurality of domains to be supplied from different rows of back power rails. In some cases, alignment of the rail disconnects in one or more second regions enables peripheral voltage in a plurality of domains to be supplied from different rows of back power rails.

[0051] References to various embodiments are made in detail, and examples thereof are illustrated in the accompanying drawings. In the following detailed description, many specific details are described to provide a complete understanding of the disclosures provided herein. However, the disclosures provided herein may be practiced without these specific details. In some other cases, well-known methods, procedures, components, circuits, and networks are not described in detail so as not to unnecessarily obscure the details of the embodiments.

[0052] While terms such as first, second, etc. may be used herein to describe various elements, it should also be understood that these elements are not to be limited by these terms. These terms are used only to distinguish one element from another. For example, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. Although the first element and the second element are both elements, they are not considered to be the same element.

[0053] The terms used in describing the disclosures provided herein are intended to describe specific embodiments and are not intended to limit the disclosures provided herein. As used in describing the disclosures provided herein and in the appended claims, singular forms (“a,” “an,” and “the”) are intended to include plural forms as well, unless the context clearly indicates otherwise. As used herein, the term “and / or” refers to and encompasses any of one or more of the associated enumerated items and all possible combinations thereof. As used herein, the terms “includes,” “including,” “comprises,” and / or “comprising” specify the presence of the mentioned features, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0054] As used herein, the term “in the case of” may be interpreted, depending on the context, to mean “when” or “at” or “in response to determining” or “in response to detecting”. Similarly, the phrase “when it is determined” or “when [the mentioned condition or event] is detected” may be interpreted, depending on the context, to mean “when it is determined” or “in response to determining” or “when [the mentioned condition or event] is detected” or “in response to detecting [the mentioned condition or event]”. The terms “up” and “down”; “upper” and “lower”; “upward” and “downward”; “lower” and “upper”; and other similar terms indicating relative positions above or below a given point or element may be used in connection with some embodiments of the various techniques described herein.

[0055] The foregoing refers to embodiments of the various techniques described in this specification, but various other and additional embodiments may be devised in accordance with the disclosure of this specification, and these may be determined by the following claims.

[0056] Although the subject matter is described in language specific to various structural features and / or methodological operations, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations mentioned above. Rather, the specific features and operations mentioned above are disclosed as exemplary forms embodying the claims.

Claims

Claim 1 A device comprising: first back power rails supplying an internal core voltage (VDDC) to memory logic; and second back power rails supplying an internal peripheral voltage (VDDP) to control logic, wherein at least one first back power rail has a rail break that interrupts continuity to allow at least one second back power rail to supply the internal peripheral voltage (VDDP) to the control logic, and the rail break provides a spatial opening within the at least one first back power rail to allow coupling of the at least one second back power rail to the control logic. Claim 2 A device according to claim 1, wherein the first back power rails provide a first net that supplies the internal core voltage (VDDC) to the memory logic, and the second back power rails provide a second net that supplies the internal peripheral voltage (VDDP) to the control logic. Claim 3 delete Claim 4 delete Claim 5 A device according to claim 1, wherein the memory logic has wordline headers and wordline drivers, and the control logic has a wordline controller. Claim 6 A device according to claim 5, wherein the wordline drivers include an upper wordline driver for an upper core array and a lower wordline driver for a lower core array, and the wordline headers include an upper wordline header operating as an upper power-gating header for the upper wordline driver and a lower wordline header operating as a lower power-gating header for the lower wordline driver. Claim 7 A device according to claim 6, wherein the control logic comprises an upper controller for the upper wordline driver and a lower controller for the lower wordline driver, and the control logic comprises a power gate controller for power-gating the wordline controller. Claim 8 A device comprising: first back power rails supplying an internal core voltage (VDDC) to memory logic; and second back power rails supplying an internal peripheral voltage (VDDP) to control logic, wherein at least one first back power rail has a rail break that interrupts continuity so that at least one second back power rail can supply the internal peripheral voltage (VDDP) to the control logic, and a front power distribution network providing front power rails; a back power distribution network providing the first back power rails and the second back power rails disposed below the front power rails; and further comprising transition cells providing front-to-back power distribution. Claim 9 A device according to claim 8, wherein the first back power rails and the second back power rails refer to buried power rails disposed below the front power rails, and the transition cells refer to buried transition vias used to couple the buried power rails to the memory logic and the control logic. Claim 10 A device according to claim 8, wherein the front power rails are formed of front metal and the back power rails are formed of embedded metal disposed below the front metal. Claim 11 A device comprising: first back power rails supplying an external core voltage (VDDCE) to memory logic; second back power rails supplying an external peripheral voltage (VDDPE) to control logic; and third back power rails coupling the memory logic and the control logic to ground, wherein at least one first back power rail has a plurality of rail disconnections that interrupt continuity so that at least one second back power rail can supply the external peripheral voltage (VDDPE) to the control logic and at least one third back power rail can couple the memory logic and the control logic to ground. Claim 12 A device according to claim 11, wherein the first back power rails provide a first net that supplies the external core voltage (VDDCE) to the memory logic, and the second back power rails provide a second net that supplies the external peripheral voltage (VDDPE) to the control logic. Claim 13 A device according to claim 11, wherein the plurality of rail single-line sections provide spatial openings within at least one first back power rail to allow coupling of at least one second back power rail to the control logic and to allow at least one third back power rail to couple the memory logic and the control logic to ground. Claim 14 delete Claim 15 A device according to claim 11, further comprising: a front power distribution network providing front power rails; a back power distribution network providing the first back power rails, the second back power rails, and the third back power rails disposed below the front power rails; and transition cells providing front-to-back power distribution. Claim 16 A device comprising: a memory circuit portion including memory logic and control logic; and rows of back power rails having one or more rail disconnect portions that enable a plurality of different nets to supply power to the memory logic and the control logic, wherein the alignment of the rail disconnect portions in one or more first regions enables a core voltage in a plurality of domains to be supplied from different rows of the back power rails, and the alignment of the rail disconnect portions in one or more second regions enables an ambient voltage in a plurality of domains to be supplied from different rows of the back power rails, wherein the core voltage includes an internal core voltage (VDDC) and an external core voltage (VDDCE), and the ambient voltage includes an internal ambient voltage (VDDP) and an external ambient voltage (VDDPE). Claim 17 A device according to claim 16, wherein a plurality of rows of the back power rails comprises a first row of back power rails and a second row of back power rails, wherein the first row of the back power rails has one or more rail disconnections that enable the plurality of different nets to supply power to the memory logic and the control logic, and the second row of the back power rails has one or more rail disconnections that enable the plurality of different nets to supply power to the memory logic and the control logic. Claim 18 A device according to claim 17, wherein portions of a first row of the back power rails in the one or more first regions are vertically aligned with corresponding portions of a second row of the back power rails in the one or more first regions, and portions of a first row of the back power rails in the one or more second regions are vertically aligned with corresponding portions of a second row of the back power rails in the one or more second regions. Claim 19 A device according to claim 16, wherein the one or more rail single-line sections provide spatial openings within the back power rails to enable the plurality of different nets to supply power to the memory logic and the control logic. Claim 20 A device according to claim 16, wherein a plurality of domains of the core voltage include an internal core voltage domain (VDDC) and an external core voltage domain (VDDCE), a plurality of domains of the peripheral voltage include an internal peripheral voltage domain (VDDP) and an external peripheral voltage domain (VDDPE), and one or more back power rails are coupled to an external ground (VSSE).

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