Vertical channel semiconductor element, and production method for the same

Abstract

According to various embodiments, as a semiconductor device, a first structure comprising a first conductor, a first contact layer disposed in a manner in contact with the first conductor below the first conductor, and a first insulating layer disposed in a manner in contact with the first contact layer below the first contact layer; a second structure comprising a second conductor, a second contact layer disposed in a manner in contact with the second conductor above the second conductor, and a second insulating layer disposed in a manner in contact with the second contact layer above the second contact layer; and a gate structure comprising a gate, a third insulating layer surrounding the gate in contact with the gate, and a channel layer in contact with the third insulating layer. A vertical channel semiconductor device may be provided, comprising: an oxide insulator in contact with the first insulating layer, the second insulating layer, and the first region of the channel layer; wherein one of the first conductor and the second conductor is a source and the other is a drain, and the permeability of oxygen atoms in the first insulating layer and the second insulating layer is lower than the permeability of oxygen atoms in the third insulating layer, and the third insulating layer contains oxygen atoms.

Description

Technology Field

[0001] The present disclosure relates to a vertical channel semiconductor device including a multilayer structure and a method for manufacturing the same, and aims to provide a transistor with a vertical structure that includes an oxygen tunnel structure that effectively controls internal oxygen vacancies and further includes a contact layer to reduce the contact resistance of the source and drain in contact with the channel layer of the transistor. Background Technology

[0003] Due to the rapid advancement of electronic technology, the down-scaling of semiconductor devices is progressing, and accordingly, transistors equipped with a channel layer employing oxide semiconductor materials such as IGZO (InGaZnO) have been proposed to reduce leakage current through the channel region.

[0004] Transistors equipped with channels employing oxide semiconductor materials have high potential for application, particularly as memory transistors requiring low leakage current characteristics. The problem to be solved

[0006] In the case of semiconductor devices containing conventional oxide semiconductor materials, the presence of oxygen vacancies within the oxide thin film forms electron transport pathways, which can lead to low film stability. Accordingly, oxygen tunnel structures have been proposed to efficiently control internal oxygen vacancies in planar semiconductors. However, planar semiconductors have limitations in integration density.

[0007] Accordingly, in order to resolve the problems caused by oxygen vacancies and low integration density of conventional semiconductor devices, a semiconductor device including an oxygen tunnel structure according to various embodiments and a method for manufacturing the same can provide thin film stability by implementing an oxygen tunnel structure that prevents oxygen supply to the source and drain while enabling oxygen supply to the channel, and can provide a vertical structure CAA (channel all around) transistor with high integration density.

[0008] In addition, a semiconductor device including an oxygen tunnel structure according to various embodiments and a method for manufacturing the same can provide a transistor in which the material of the contact portions of the source and drain, respectively, that contact the channel to reduce contact resistance, is implemented with the same material as the channel material (or a similar material that produces the same effect).

[0009] In addition, a semiconductor device including an oxygen tunnel structure according to various embodiments and a method for manufacturing the same can provide a method for manufacturing a vertical transistor in which a channel and a gate are formed through a via hole formation process after a drain and source formation process, which is simpler compared to a horizontal transistor.

[0010] The problems that this application aims to solve are not limited to those described above, and problems not mentioned will be clearly understood by those skilled in the art from this specification and the attached drawings. means of solving the problem

[0012] According to various embodiments, as an oxide semiconductor device, a first structure comprising a first conductor, a first contact layer disposed in a manner in contact with the first conductor below the first conductor, and a first insulating layer disposed in a manner in contact with the first contact layer below the first contact layer; a second structure comprising a second conductor, a second contact layer disposed in a manner in contact with the second conductor above the second conductor, and a second insulating layer disposed in a manner in contact with the second contact layer above the second contact layer; and a gate structure comprising a gate, a third insulating layer surrounding the gate in contact with the gate, and an oxide semiconductor layer in contact with the third insulating layer. An oxide semiconductor device may be provided, comprising: an oxide insulator in contact with a first insulating layer, a second insulating layer, and a first region of the oxide semiconductor layer; wherein one of the first conductor and the second conductor is a source and the other is a drain, and the first insulating layer and the second insulating layer have a permeability of oxygen atoms lower than the permeability of oxygen atoms of the third insulating layer, and the third insulating layer contains oxygen atoms.

[0013] The means for solving the problem are not limited to the means described above, and unmentioned means of solving will be clearly understood by those skilled in the art to which this application pertains from this specification and the attached drawings. Effects of the invention

[0015] According to various embodiments, a vertically structured CAA (channel all around) transistor with high integration density can be provided by implementing an oxygen tunnel structure that prevents oxygen supply to the source and drain while enabling oxygen supply to the channel, thereby providing thin film stability.

[0016] In addition, according to various embodiments, a semiconductor device including an oxygen tunnel structure and a method for manufacturing the same may provide a transistor in which the material of the source and drain contact portions in contact with the channel to reduce contact resistance is implemented with IGZO, which is the same as the material of the channel.

[0017] In addition, according to various embodiments, a method for manufacturing a vertically structured transistor can be provided, in which a channel and a gate are formed through a via hole formation process following a drain and source formation process, which is simpler compared to a horizontally structured transistor. Brief explanation of the drawing

[0019] FIG. 1 is a perspective view schematically showing the structure of an oxide semiconductor device. Figure 2 is a cross-sectional view taken along the xz plane with respect to the axis of the structure of the oxide semiconductor device shown in Figure 1. FIG. 3 is a drawing for illustrating an example of an oxygen tunnel structure formed by a third insulating layer, an insulator, and first and second insulating layers according to various embodiments. FIG. 4 shows an oxygen atom (O) provided as an oxide semiconductor layer according to various embodiments. 2- This is a diagram showing an example where oxygen vacancies are suppressed by ). Figure 5 is a diagram showing the experimental results of the current intensity of oxide semiconductor devices according to the type of insulating material. Figure 6 shows the intensity (y1) and reliability (y2) of the drain current formed for each t1 / t2 while the same gate voltage and drain voltage are applied. FIG. 7 is a diagram illustrating an example of a method for manufacturing an oxide semiconductor device according to various embodiments. FIG. 8 is a drawing for illustrating an example of a manufacturing method for connecting a plurality of oxide semiconductor devices according to various embodiments. Specific details for implementing the invention

[0020] Specific structural or functional descriptions regarding various embodiments are illustrative for the purpose of explaining various embodiments, and various embodiments may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0021] Since various embodiments may be subject to various modifications and may take various forms, various embodiments are illustrated in the drawings and described in detail in this specification or application. However, the details disclosed in the drawings are not intended to specify or limit the various embodiments, and should be understood to include all modifications, equivalents, and substitutions that fall within the spirit and technical scope of the various embodiments.

[0022] Terms such as "first" and / or "second" may be used to describe various components, but said components shall not be limited by said terms. For the sole purpose of distinguishing one component from another, for example, without departing from the scope of rights according to the concept of the present disclosure, the first component may be named the second component, and similarly, the second component may be named the first component.

[0023] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. Conversely, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between. Other expressions describing the relationship between components, such as "between" and "exactly between," or "adjacent to" and "directly adjacent to," should be interpreted in the same way.

[0024] The terms used herein are used merely to describe specific embodiments and are not intended to limit various embodiments. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “comprising” or “having” are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0025] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which this disclosure pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification.

[0026] The present disclosure will be described in detail below by explaining preferred embodiments of the present disclosure with reference to the attached drawings. Identical reference numerals in each drawing indicate identical components.

[0027] According to various embodiments, as an oxide semiconductor device, a first structure comprising a first conductor, a first contact layer disposed in a manner in contact with the first conductor below the first conductor, and a first insulating layer disposed in a manner in contact with the first contact layer below the first contact layer; a second structure comprising a second conductor, a second contact layer disposed in a manner in contact with the second conductor above the second conductor, and a second insulating layer disposed in a manner in contact with the second contact layer above the second contact layer; and a gate structure comprising a gate, a third insulating layer surrounding the gate in contact with the gate, and an oxide semiconductor layer in contact with the third insulating layer. An oxide semiconductor device may be provided, comprising: an oxide insulator in contact with a first insulating layer, a second insulating layer, and a first region of the oxide semiconductor layer; wherein one of the first conductor and the second conductor is a source and the other is a drain, and the first insulating layer and the second insulating layer have a permeability of oxygen atoms lower than the permeability of oxygen atoms of the third insulating layer, and the third insulating layer contains oxygen atoms.

[0028] According to various embodiments, an oxide semiconductor device may be provided in which the gate structure penetrates the first structure in a vertical direction and is implemented to penetrate a part of the second structure.

[0029] According to various embodiments, an oxide semiconductor device may be provided in which the first conductor and the second conductor are electrically connected by the oxide semiconductor layer.

[0030] According to various embodiments, an oxide semiconductor device may be provided in which the remaining region other than the first region of the oxide semiconductor layer is in contact with the first contact layer or the second contact layer.

[0031] According to various embodiments, an oxide semiconductor device may be provided in which the resistance of the remaining region is lower than the resistance of the first region.

[0032] According to various embodiments, an oxide semiconductor device may be provided such that the resistance of the remaining region corresponds to the resistance of the first contact layer or the resistance of the second contact layer.

[0033] According to various embodiments, an oxide semiconductor device may be provided in which the thickness of the remaining region relative to the thickness of the first region is such that...

[0034] According to various embodiments, the first insulating layer and the second insulating layer, respectively, are Si a N b An oxide semiconductor device implemented as such may be provided.

[0035] According to various embodiments, an oxide semiconductor device may be provided in which the third insulating layer is implemented as Al2O3.

[0036] According to various embodiments, an oxide semiconductor device may be provided in which the oxide insulator is implemented as SiO2.

[0038] FIG. 1 is a perspective view schematically showing the structure of an oxide semiconductor device (1). Below, FIG. 1 will be further explained with reference to FIG. 2 and FIG. 3.

[0039] FIG. 2 is a cross-sectional view taken along the xz plane with respect to the axis (c) of the structure of the oxide semiconductor device (1) shown in FIG. 1.

[0040] According to various embodiments, with reference to FIG. 1, an oxide semiconductor device (1) comprises: a source structure (100) comprising a source (110), a first contact layer (120) disposed below the source (110) in a manner in contact with the source (110), and a first insulating layer (130) disposed below the first contact layer (120) in a manner in contact with the first contact layer (120); a drain structure (200) comprising a drain (210), a second contact layer (220) disposed above the drain (210) in a manner in contact with the drain (210), and a second insulating layer (230) disposed above the second contact layer (220) in a manner in contact with the second contact layer (220); a gate (310), a third insulating layer (320) surrounding (or covering) the gate (310) in a manner in contact with the gate (310); and the It may include a gate structure (300) comprising an oxide semiconductor layer (330) in contact with a third insulating layer (320), and an insulator (400).

[0041] Meanwhile, without being limited to the described and / or illustrated examples, the source (110) may be implemented as the drain (210), and the drain (210) may be implemented as the source (110).

[0042] According to various embodiments, the source (110), the drain (210), and the gate (310) may be conductors. The source (110), the drain (210), and the gate (310) may be made of TiN, Ti, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, ITO, IZO, ZTO, Poly-Si, or a combination thereof.

[0043] According to various embodiments, with reference to FIG. 2, a gate structure (300) may be formed in a vertical direction (e.g., in the z-axis direction) to penetrate the source (110) and the insulator (400) and to penetrate a portion of the drain (210). The flow of current between the source (110) and the drain (210) may be controlled by an oxide semiconductor layer (330) that functions as a channel controlled by the gate (310) extending in the vertical direction. By the gate (310) formed in the vertical direction, the oxide semiconductor device (1) may be defined as having a vertical structure. As the channel is formed in the vertical direction, the integration density may be increased.

[0044] According to various embodiments, a third insulating layer (320) disposed between the gate (310) and the oxide semiconductor layer (330) and formed in contact with each of them may be implemented to electrically insulate the gate (310) and the channel layer (330). Additionally, the third insulating layer (320) may be an insulating layer having a relatively higher dielectric constant compared to the first insulating layer (130) and the second insulating layer (230). For example, the third insulating layer (320) may be Al2O 3, It can be realized with high-K materials such as HfO2, ZrO2, Ta2O5, and La2O3.

[0045] According to various embodiments, the channel layer (330) can electrically connect the source (110) and the drain (310). A voltage (V) applied to the gate (310) G With a channel formed in the channel layer (330) by means of ), current can be formed in the channel layer (330) by a voltage applied to the drain (310) (or the source (110)).

[0046] According to various embodiments, the channel layer (330) may be made of IGZO (InGaZnO), Sn-IGZO, IWO (InWO), IZO (InZnO), ZTO (ZnSnO), ZnO, YZO (yttrium-doped zinc oxide), IGSO (InGaSiO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, SiInZnO, GaZnSnO, ZrZnSnO, silicon material, or a combination thereof. Preferably, the channel layer (330) may be implemented with IGZO (InGaZnO), which has low leakage current and excellent electron mobility. However, oxygen vacancies may occur within the IGZO (InGaZnO) constituting the channel layer (330), and free electrons (2e-) are formed to compensate for the charge caused by the oxygen vacancies, which may reduce the resistance of the channel layer (330). However, as a movement path is formed by free electrons, the stability of the device is reduced, and the voltage (V) applied to the gate (310) G It may be difficult to control the characteristics of the channel based on ). According to the present invention, oxygen tunnel structure formed by the aforementioned third insulating layer (320), insulator (400), and first and second insulating layers (130, 230) provides oxygen abundantly to the channel layer (330), thereby suppressing oxygen vacancies and resolving the aforementioned problem. Meanwhile, the channel layer (330) can be implemented with various materials other than oxide semiconductor materials.

[0047] According to various embodiments, a contact layer (e.g., a first contact layer (120), a second contact layer (220)) may be formed at each of the source (110) and the drain (210) to reduce contact resistance with the channel layer (330). The contact layer (120, 220) may be implemented with a material identical to (or having similar characteristics capable of producing the same effect as) the channel layer (330), and preferably implemented with IGZO (InGaZnO). For example, when implemented with identical materials, there may be an example where the channel layer (330) is implemented with silicon material and the contact layer (120, 220) is also implemented with silicon material, or an example where the channel layer (330) is implemented with IGZO and the contact layer (120, 220) is also implemented with silicon material. For example, when implemented with materials having similar characteristics, the channel layer (330) and the contact layer (120, 220) may be implemented with an oxide-based material, although they are not identical. However, not limited to the examples described, the channel layer (330) can be implemented with various other materials, and accordingly, the contact layer (e.g., first contact layer (120), second contact layer (220)) may be implemented with the same material or a material capable of producing the same effect.

[0048] According to various embodiments, an insulating layer (e.g., a first insulating layer (130), a second insulating layer (230)) may be formed between the contact layer (120, 220) of the source (110) and the drain (210) and the insulator (400). The oxygen atom permeability of the insulating layer (e.g., the first insulating layer (130), the second insulating layer (230)) may be lower than the oxygen atom permeability of the third insulating layer (320) in contact with the gate (310) and the channel layer (330). That is, the insulating layer (e.g., the first insulating layer (130), the second insulating layer (230)) may prevent oxygen atoms contained in the insulator (400) from being supplied to the source structure (100) and the drain structure (200). Accordingly, an oxygen tunnel structure can be formed such that the flow of oxygen atoms contained in the insulator (400) is concentrated in a part of the channel layer (330) in contact with the insulator (400). Additionally, the resistance of the contact layer (120, 220) and the remaining part of the channel layer (330) disposed inside the contact layer (120, 220) and the source structure (100) and the drain structure (200) can be lowered by preventing the flow of oxygen atoms in the remaining part of the channel layer (330) and causing the generation of oxygen vacancies. Accordingly, the contact resistance between the source (110) (or drain (210)) and the channel layer (330) can be formed to be low.

[0049] According to various embodiments, the insulating layer (e.g., first insulating layer (130), second insulating layer (230)) may be an insulating layer that does not contain oxygen. Additionally, the insulating layer (e.g., first insulating layer (130), second insulating layer (230)) may be implemented in a material that provides thermal stability and insulation properties. For example, the insulating layer (e.g., first insulating layer (130), second insulating layer (230)) may be implemented in a silicon nitride (SiaNb)-based material. Preferably, the insulating layer (e.g., first insulating layer (130), second insulating layer (230)) may be implemented in Si3N4. Also, for example, the insulating layer (e.g., first insulating layer (130), second insulating layer (230)) may be implemented in aluminum nitride (AlN), boron nitride (BN), etc.

[0050] In other words, the resistance of the remaining portion of the channel layer (330) that is in contact with the contact layers (120, 220), the insulating layers (130, 230), and / or the conductors (e.g., source (110), drain (210)) can be formed lower than the resistance of the remaining portion of the channel layer (330) that is in contact with the insulator (400). Also, the resistance of the remaining portion of the channel layer (330) and the resistance of the contact layers (120, 220), the insulating layers (130, 230), and / or the conductors (e.g., source (110), drain (210)) can be implemented as corresponding values.

[0051] According to various embodiments, the insulator (400) may be an insulator containing oxygen atoms that is in contact with a portion of the first insulating layer (130), the second insulating layer (230), and the channel layer (330). For example, the insulator (400) may be implemented with a material containing oxygen and having thermal stability and insulating properties. As an example, the insulator (400) may be silicon oxide (SiO2). It can be implemented with hafnium oxide (HfO2) or aluminum oxide (Al2O3). Oxygen atoms contained in the insulator (400) can be provided to the remainder of the channel layer (330). Accordingly, the occurrence of oxygen vacancies in the remainder of the channel layer (330) is suppressed, and the voltage (V) applied to the gate (310) G Channel control by ) can be performed smoothly.

[0053] FIG. 3 is a drawing for illustrating an example of an oxygen tunnel structure formed by a third insulating layer (320), an insulator (400), and first and second insulating layers (130, 230) according to various embodiments. FIG. 4 is a drawing for illustrating an oxygen atom (O) provided as a channel layer (330) according to various embodiments. 2- Figure 5 is a diagram showing an example in which oxygen vacancies are suppressed by ). Figure 5 is a diagram showing the experimental results of the current intensity of an oxide semiconductor device (1) according to the type of material of the insulator (400).

[0054] According to various embodiments, FIG. 3 shows oxygen atoms (O) contained in an insulator (400). 2- It represents the flow of ). As previously mentioned, the abundant oxygen atoms (O) contained in the insulator (400) 2- The first region (A1) of the channel layer (330) may be provided by the first and second insulating layers (130, 230) as a first region (A1), and may not be provided as a remaining region (e.g., second region (A2), third region (A3)). The first region (A1) is defined as a region in contact with the insulator (400), and the remaining region (e.g., second region (A2), third region (A3)) may be defined as a region other than the first region (A1). Alternatively, the remaining region (e.g., second region (A2), third region (A3)) may be defined as a region from a point corresponding to the first and second insulating layers (130, 230) of the channel layer (330) to the end.

[0055] According to various embodiments, in the first region (A1), as shown in FIG. 4, the generation of oxygen vacancies inside the IGZO is suppressed and the generation of free electrons can also be suppressed. FIG. 5 shows the voltage (V) applied to the gate. G Current per unit length (I) formed in the drain (210) according to ) D It indicates the strength of ). FIG. 5(a) shows a case where the insulator (400) of the oxide semiconductor device (1) is implemented with an insulating material containing oxygen (e.g., SiO2) as in the present invention, and FIG. 5(b) shows a comparative example where the insulator (400) of the oxide semiconductor device (1) is implemented with an insulating material that does not contain oxygen (e.g., Si3N4). Referring to FIG. 5(a) and (b), when oxygen is included in the insulator (400) and oxygen atoms are supplied to the channel layer (330), the current (I D It can be observed that the intensity of ) is low. That is, as the generation of oxygen vacancies in the channel layer (330) is suppressed by the supply of oxygen atoms, the generation of free electrons is suppressed, and the stability of the oxide semiconductor device (1) can be improved as intended by the present invention.

[0056] At this time, the current flowing through the channel layer (330) may need to be implemented above a threshold value to ensure sufficient operating performance, separate from the stability of the oxide semiconductor device (1). Accordingly, the contact resistance between the remaining regions (A2, A3) of the channel layer (330) and the source structure (100) and drain structure (200), respectively, may need to be implemented to be low.

[0057] Accordingly, according to various embodiments, as oxygen supply to the remaining areas (e.g., second area (A2), third area (A3)) is prevented by the first and second insulating layers (130, 230), oxygen vacancies may occur in the remaining areas (e.g., second area (A2), third area (A3)) and free electrons may be generated. Based on the amount of free electrons generated, the resistance of the remaining areas (A2, A3) may be formed to be lower than the resistance of the first area (A1). In addition, oxygen supply from the insulator (400) to the contact layer (120, 220) in contact with the remaining areas (A2, A3) of the channel layer (330) may also be prevented by the first and second insulating layers (130, 230). Accordingly, the resistance of the contact layer (120, 220) implemented with the same material as the channel layer (330) (or a similar material that produces the same effect) can correspond to the resistance of the remaining area (A2, A3) of the channel layer (330) where the aforementioned oxygen is not provided. As the resistance between the contacting components is formed to be low, the contact resistance can be formed to be low.

[0058] Meanwhile, if the length of the first region (A1) of the channel layer (330) is defined as t1 and the sum of the lengths of the first and second insulating layers (130, 230) and the contact layer (120, 220) is defined as t2, then t2 / t1 may have a relationship as shown in FIG. 6.

[0059] For example, FIG. 6 shows the current intensity (y1) of the drain formed according to t2 / t1 and the reliability (y2) (or stability) of the reliability element. Referring to FIG. 6, as the lengths of the first and second insulating layers (130, 230) and the contact layer (120, 220) increase, the current intensity (Id) of the drain (210) improves, but the reliability (or stability) of the oxide semiconductor element (1) may decrease. Channel layer (330) Channel layer (330)

[0061] FIG. 7 is a drawing for explaining an example of a method for manufacturing an oxide semiconductor device (1) according to various embodiments. FIG. 8 is a drawing for explaining an example of a method for manufacturing a plurality of oxide semiconductor devices (1a, 1b) according to various embodiments.

[0062] Referring to FIG. 7(a), the manufacturing method may include the step of forming a drain (210) by depositing TiN to a specific thickness (e.g., 100 nm) on a substrate (not shown) based on a sputtering process, and forming a second contact layer (220) by depositing IGZO to a specific thickness (e.g., 10 nm) on the drain (210). Additionally, the manufacturing method may include the step of removing the remainder while leaving only a portion of the area through an exposure and etching process while the drain (210) and the second contact layer (220) are formed. Additionally, the manufacturing method may include the step of forming a second insulating layer (230) by depositing Si3N4 to a specific thickness (e.g., 10 nm) based on a PECVD process while a portion of the drain (210) and the second contact layer (220) remains.

[0063] Referring to FIG. 7(b), the manufacturing method may include the steps of forming an insulator (400) by depositing SiO2 on a second insulating layer (230) based on a PECVD process, forming a first insulating layer (130) by depositing Si3N4 on the insulator (400) to a specific thickness (e.g., 10 nm) based on a PECVD process, forming a first contact layer (120) by depositing IGZO on the first insulator (130) to a specific thickness (e.g., 10 nm) based on a sputtering process, and forming a drain (210) by depositing TiN on the first contact layer (120) to a specific thickness (e.g., 100 nm).

[0064] Referring to FIG. 7(c), the manufacturing method may include the step of forming a hole (H) that penetrates the formed source structure (100) and a part of the drain structure (200). Also, referring to FIG. 7(d), the manufacturing method may include the step of forming a channel layer (330), a third insulating layer (320), and a gate (310) by depositing IGZO, AL2O3, and TiN based on at least one process among sputtering, ALD (atomic layer deposition), PVD (physical vapor deposition), or CVD (chemical vapor deposition). Accordingly, the process can be performed simply compared to forming a semiconductor device with a horizontal structure.

[0065] Also, referring to FIG. 8, a plurality of oxide semiconductor devices (1a, 1b) can be implemented to be connected to each other. In a state where an oxide semiconductor device (1a) is formed according to the manufacturing method described above, a process of manufacturing another oxide semiconductor device (1b) is performed after forming an insulator (800) and a contact layer (810), thereby enabling a plurality of oxide semiconductor devices (1a, 1b) connected to each other to be implemented.

Claims

Claim 1 A first structure comprising a first conductor, a first contact layer disposed in a manner in contact with the first conductor below the first conductor, and a first insulating layer disposed in a manner in contact with the first contact layer below the first contact layer; a second structure comprising a second conductor, a second contact layer disposed in a manner in contact with the second conductor above the second conductor, and a second insulating layer disposed in a manner in contact with the second contact layer above the second contact layer; a gate structure comprising a gate, a third insulating layer surrounding the gate in contact with the gate, and a channel layer in contact with the third insulating layer; A vertical channel semiconductor device comprising: an oxide insulator in contact with the first insulating layer, the second insulating layer, and the first region of the channel layer; wherein one of the first conductor and the second conductor is a source and the other is a drain; wherein the first contact layer, the second contact layer, and the channel layer are implemented with the same material or a material having similar characteristics; wherein the gate structure is implemented to penetrate the first structure in a vertical direction and to penetrate a part of the second structure; and wherein the remaining region of the channel layer other than the first region is in contact with the first contact layer or the second contact layer. Claim 2 delete Claim 3 A vertical channel semiconductor device according to claim 1, wherein the first conductor and the second conductor are electrically connected by the channel layer. Claim 4 delete Claim 5 In claim 3, a vertical channel semiconductor device in which the resistance of the remaining region is lower than the resistance of the first region. Claim 6 delete Claim 7 A vertical channel semiconductor device according to claim 5, wherein the thickness of the first region is greater than the thickness of the remaining region. Claim 8 A vertical channel semiconductor device according to claim 1, wherein each of the first insulating layer and the second insulating layer does not contain oxygen atoms and is implemented in one or more of silicon nitride (Si3N4), aluminum nitride (AlN), or boron nitride (BN). Claim 9 A vertical channel semiconductor device according to claim 8, wherein the third insulating layer comprises the oxygen atom and is implemented in one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum pentoxide (Ta2O5), or lanthanum oxide (La2O3). Claim 10 A vertical channel semiconductor device according to claim 9, wherein the oxide insulator comprises the oxygen atom and is implemented in one or more of silicon oxide (SiO2), hafnium oxide (HfO2), or aluminum oxide (Al2O3).

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