Display device and manufacturing method of the same

Abstract

A display device according to one embodiment includes a base layer comprising a first surface and a second surface opposite to the first surface; a first insulating layer located on the second surface; a flattening layer located between the second surface and the first insulating layer; a back wiring located on the first insulating layer; a back pad electrode located on the back wiring; and a second insulating layer covering the back pad electrode so as to expose at least a portion of the upper surface of the back pad electrode.

Description

Technology Field

[0001] The present invention relates to a display device and a method for manufacturing the same. Background Technology

[0002] As interest in information displays intensifies and the demand for portable information media rises, the demand for and commercialization of display devices are becoming a major focus. The problem to be solved

[0003] The present invention aims to provide a display device that prevents defects such as back wiring disposed on a base layer, and a method for manufacturing the same. means of solving the problem

[0004] A display device according to one embodiment of the present invention comprises: a base layer including a first surface and a second surface opposite to the first surface; a first insulating layer located on the second surface; a flattening layer located between the second surface and the first insulating layer; a back wiring located on the first insulating layer; a back pad electrode located on the back wiring; and a second insulating layer covering the back pad electrode so as to expose at least a portion of the upper surface of the back pad electrode.

[0005] The above-mentioned flattening layer may include an organic material.

[0006] The first insulating layer may include a transparent inorganic insulating material.

[0007] The above base layer may be a rigid substrate.

[0008] The above rear wiring may extend in a first direction on the above second surface.

[0009] The above-mentioned back pad electrode can cover the back wiring so as to overlap at least a portion with the back wiring.

[0010] The above back pad electrode may include a transparent conductive oxide.

[0011] It may further include a pixel circuit layer located on the first surface; and a display element layer located on the pixel circuit layer.

[0012] The pixel circuit layer may include a first transistor located on the first surface.

[0013] The above display element layer includes a light-emitting element, and the light-emitting element may include a first semiconductor layer; a second semiconductor layer different from the first semiconductor layer; and an active layer located between the first semiconductor layer and the second semiconductor layer.

[0014] A method for manufacturing a display device according to one embodiment includes the steps of: preparing a base layer comprising a first surface and a second surface opposite to the first surface; forming a pixel circuit layer and a display element layer on the first surface; forming a planarization layer on the second surface; forming a first insulating layer on the planarization layer; and forming back wiring and back pad electrodes on the first insulating layer.

[0015] The above-mentioned flattening layer can be formed with an organic material.

[0016] The first insulating layer can be formed with a transparent inorganic insulating material.

[0017] The above base layer, which is a rigid substrate, can be prepared.

[0018] The back pad electrode can be formed with a transparent conductive oxide.

[0019] The method may further include the step of forming a second insulating layer on the back pad electrode.

[0020] The back wiring can be formed to extend in a first direction on the second surface.

[0021] The back pad electrode can be formed to cover the back wiring by overlapping at least a portion with the back wiring.

[0022] The step of forming the pixel circuit layer may include the step of forming a first transistor on the first surface.

[0023] The step of forming the above-mentioned display element layer may include the step of placing a light-emitting element on the above-mentioned pixel circuit layer. Effects of the invention

[0024] According to one embodiment, a planarization layer is formed on one side of a base layer, and back wiring, back pad electrodes, etc. can be formed, thereby preventing defects in back wiring, etc., and ensuring structural stability of the display device.

[0025] The effects according to one embodiment are not limited to those exemplified above, and various other effects are included in this specification. Brief explanation of the drawing

[0026] FIG. 1 is a schematic plan view illustrating a display device according to one embodiment. FIG. 2 is a schematic plan view of a display panel according to one embodiment. FIG. 3 is a plan view schematically illustrating the arrangement of pixels and pixel circuits in a display panel according to one embodiment. FIG. 4 is a plan view illustrating a display device including the display panel of FIG. 3. FIG. 5 is a cross-sectional view schematically illustrating a display device according to one embodiment. FIG. 6 is a drawing showing one side of a base layer in a display device according to one embodiment. Figure 7 is a cross-sectional view taken along the line VI-VI' of Figure 6. FIGS. 8 to 11 are drawings illustrating, in sequence, a manufacturing method for manufacturing the display device of FIG. 7. FIG. 12 is a perspective view illustrating a light-emitting element included in a display device according to one embodiment. FIG. 13 is a cross-sectional view illustrating a light-emitting element included in a display device according to one embodiment. FIG. 14 is a cross-sectional view schematically illustrating a pixel of a display device including the light-emitting elements of FIG. 12 and FIG. 13. FIG. 15 is a cross-sectional view illustrating another embodiment of a light-emitting element included in a display device according to one embodiment. FIG. 16 is a cross-sectional view schematically illustrating a pixel of a display device according to one embodiment. FIG. 17 is a cross-sectional view schematically illustrating a part of the non-display area of ​​a display device according to one embodiment. FIG. 18 is a cross-sectional view schematically illustrating the display area and non-display area of ​​a display device according to one embodiment. FIG. 19 is a cross-sectional view of a display device according to one embodiment. FIG. 20 is a block diagram briefly illustrating the configuration of a display device according to one embodiment. FIG. 21 is a simplified diagram illustrating a pixel circuit of a display device according to one embodiment. FIG. 22 is a circuit diagram illustrating a pixel circuit of a display device according to one embodiment. Specific details for implementing the invention

[0027] The present invention is capable of various modifications and may take various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the invention to the specific disclosed forms, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0028] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0029] In this application, terms such as "comprising" or "having" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Furthermore, when a part such as a layer, film, region, or plate is described as being "on" another part, this includes not only cases where it is "immediately above" the other part, but also cases where there is another part in between. Additionally, in this specification, when a part such as a layer, film, region, or plate is described as being formed "on" another part, the direction in which it is formed is not limited to the upward direction only, but includes cases where it is formed in the lateral or downward direction. Conversely, when a part such as a layer, film, region, or plate is described as being "below" another part, this includes not only cases where it is "immediately below" the other part, but also cases where there is another part in between.

[0030] In this application, the term “connection” between two components may mean that it encompasses both electrical and physical connections, but is not necessarily limited thereto.

[0031] Hereinafter, a display device according to an embodiment of the present invention will be described with reference to the drawings related to the embodiments of the present invention.

[0032] FIG. 1 is a schematic plan view illustrating a display device according to one embodiment, FIG. 2 is a schematic plan view of a display panel according to one embodiment, FIG. 3 is a schematic plan view illustrating a pixel and pixel circuit arrangement in a display panel according to one embodiment, and FIG. 4 is a plan view illustrating a display device including the display panel of FIG. 3. A plurality of display devices according to one embodiment may be a multi-screen display device (TDD) (also called a tiled display) including a plurality of display panels.

[0033] Referring to FIGS. 1 and 2, a multi-screen display device (TDD) according to one embodiment may include a plurality of display panels (DP1, DP2, DP3, DP4) arranged in a matrix form along a first direction (DR1) and a second direction (DR2).

[0034] A plurality of display panels (DP1, DP2, DP3, DP4) may display individual images or divide and display a single image. The plurality of display panels (DP1, DP2, DP3, DP4) may include display panels of the same type, structure, size, or method, but the present invention is not limited thereto.

[0035] A plurality of display panels (DP1, DP2, DP3, DP4) can be physically combined by a housing (not shown) located below the plurality of display panels (DP1, DP2, DP3, DP4) so ​​as to form a single multi-screen display device (TDD).

[0036] Multiple display panels (DP1, DP2, DP3, DP4) can be implemented in various shapes. Although the multiple display panels (DP1, DP2, DP3, DP4) are shown in FIG. 1 as having a rectangular plate shape, the present invention is not limited thereto, and the multiple display panels (DP1, DP2, DP3, DP4) may each have a shape such as a circle or an ellipse.

[0037] A display panel (DP) according to one embodiment may include a display area (DA) that displays an image implemented on a base layer (BSL) and a non-display area (NDA) that does not display an image. The non-display area (NDA) may be a bezel area surrounding the display area (DA).

[0038] The display area (DA) may be located on one side of the display panel (DP). For example, the display area (DA) may be located on the front of the display panel (DP), and additionally, it may be located on the side and back of the display panel (DP).

[0039] A display area (DA) may include a plurality of pixels (PXL). A plurality of pixels (PXL) may constitute a single pixel unit (PXU). Although a single pixel unit (PXU) containing three pixels (PXL) is illustrated in FIG. 2, the pixel units (PXU) may substantially be distributed across the entire front surface of the display area (DA). For example, the pixels (PXL) may be arranged in the display area (DA) in an array structure such as a matrix or stripe. However, the present invention is not limited thereto.

[0040] The non-display area (NDA) is located around the display area (DA) to surround the display area (DA). The non-display area (NDA) may optionally include wiring, pads, driving circuits, etc., connected to the pixels (PXL) of the display area (DA).

[0041] In a plurality of display panels (DP1, DP2, DP3, DP4), the image displayed on the screen of a multi-screen display device (TDD) may be partially interrupted due to a non-display area (NDA) located in the boundary area between the plurality of display panels (DP1, DP2, DP3, DP4), but the display device according to one embodiment minimizes the non-display area (NDA) so that the non-display area (NDA) may not be visible when a user views the image. For example, the spacing of the non-display area (NDA) between two adjacent display panels among the plurality of display panels (DP1, DP2, DP3, DP4) (e.g., spacing according to the first direction (DR1) and / or spacing according to the second direction (DR2)) may correspond to the distance (or spacing) between the outermost pixel units included in each of the two adjacent display panels. Here, according to an embodiment of the present invention, the distance (or spacing) between the outermost pixel units included in each of two adjacent display panels may be substantially the same as the distance (or spacing) between pixel units included in one display panel. In this case, even if the multi-screen display device (TDD) includes a plurality of display panels (DP1, DP2, DP3, DP4), the boundary area (i.e., non-display area (NDA)) between the plurality of display panels (DP1, DP2, DP3, DP4) may not be visible to the user. The non-display area (NDA) located in the boundary area between the plurality of display panels (DP1, DP2, DP3, DP4) may be referred to as a seam area, an assembly joint area, or a dead space area.

[0042] Referring to FIGS. 3 and 4, a display area (DA) of a display panel (DP) according to one embodiment may include a plurality of pixel units (PXU), a plurality of pixel circuits (PXC), at least one gate driving circuit (GDR), and a gate line (GW). The display device illustrated in FIG. 4 may correspond to a multi-screen display device (TDD) in which the display panel (DP) of FIG. 3 is arranged in a matrix form along a first direction (DR1) and a second direction (DR2).

[0043] Among the plurality of pixel units (PXU), each pixel unit (PXU) may be spaced apart from one another and arranged in a matrix array structure in a first direction (DR1) and a second direction (DR2). The plurality of pixel units (PXU) may include a first pixel (PXL1), a second pixel (PXL2), and a third pixel (PXL3). The first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) may be spaced apart from one another in the first direction (DR1). Additionally, the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) may each include a plurality of subpixels. For example, the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) may each be composed of two subpixels. In one embodiment, the first pixel (PXL1) may be a red pixel, the second pixel (PXL2) may be a green pixel, and the third pixel (PXL3) may be a blue pixel. The present invention is not limited thereto, and the first to third pixels (PXL1, PXL2, PXL3) may each be pixels that emit different light.

[0044] A pixel circuit (PXC) may be disposed between two pixel units (PXU) that are arranged adjacently in the second direction (DR2) among a plurality of pixel units (PXU). For example, when pixel units (PXU) arranged in the first row in the first direction (DR1) are referred to as the first row pixel units (PXUR1) and pixel units (PXU) arranged in the second row are referred to as the second row pixel units (PXUR2), at least one pixel circuit (PXC) may be disposed between the first row pixel units (PXUR1) and the second row pixel units (PXUR2). The pixel circuit (PXC) may include circuit elements and may drive two pixel units (PXU) arranged adjacently in the second direction (DR2). For example, the pixel circuit (PXC) may drive the first row pixel units (PXUR1) and the second row pixel units (PXUR2).

[0045] A gate driving circuit (GDR) may be positioned between two pixel units (PXU) positioned at a predetermined distance apart in a second direction (DR2) and two pixel units (PXU) positioned at a predetermined distance apart in a first direction (DR1). For example, when pixel units (PXU) positioned in a third row positioned at a predetermined distance apart from a second row pixel unit (PXUR2) are referred to as third row pixel units (PXUR3), pixel units (PXU) positioned in the first column in the second direction (DR2) are referred to as first column pixel units (PXUC1), and pixel units (PXU) positioned in the second column are referred to as second column pixel units (PXUC2), a gate driving circuit (GDR) may be positioned between the second row pixel unit (PXUR2) and the third row pixel unit (PXUR3), and between the first column pixel unit (PXUC1) and the second column pixel unit (PXUC2).

[0046] The gate line (GW) may overlap with the pixel circuit (PXC) and be positioned extending in the first direction (DR1). The gate line (GW) may include two wires, and each wire may supply a gate signal to a pixel unit (PXU) located adjacent to each other. The gate line (GW) may supply a gate signal provided from the gate driving circuit (GDR) to the pixel unit (PXU). For example, the gate line (GW) positioned between the first row pixel unit (PXUR1) and the second row pixel unit (PXUR2) may receive a gate signal from the gate driving circuit (GDR), the gate line (GW) adjacent to the first row pixel unit (PXUR1) may supply a gate signal to the first row pixel unit (PXUR1), and the gate line (GW) adjacent to the second row pixel unit (PXUR2) may supply a gate signal to the second row pixel unit (PXUR2).

[0047] Meanwhile, as described with reference to FIGS. 1 and 2, the distance (or spacing) between the outermost pixel units (PXUs) included in each of two adjacent display panels among the plurality of display panels (DP1, DP2, DP3, DP4) may be substantially the same as the distance (or spacing) between the pixel units (PXUs) included in one display panel. Accordingly, even if the multi-screen display device (TDD) includes the plurality of display panels (DP1, DP2, DP3, DP4), the boundary area (i.e., non-display area (NDA)) between the plurality of display panels (DP1, DP2, DP3, DP4) may not be visible to the user.

[0048] Below, we will examine the structure of a display device according to one embodiment with reference to FIG. 5.

[0049] FIG. 5 is a cross-sectional view schematically illustrating a display device according to one embodiment.

[0050] Referring to FIG. 5, a display device according to one embodiment may include a pixel circuit layer (PCL), a display element layer (DPL), and a cover layer (CVL) sequentially located on a base layer (BSL).

[0051] The base layer (BSL) may constitute a base member of a display device. According to an embodiment, the base layer (BSL) may be a rigid or flexible substrate or film, and its material or physical properties are not particularly limited. For example, the base layer (BSL) may be a rigid substrate made of glass or reinforced glass, a flexible substrate made of plastic or metal (or a thin film), or at least one insulating film, and its material and / or physical properties are not particularly limited.

[0052] The pixel circuit layer (PCL) is located on the base layer (BSL) and may include a plurality of transistors and signal lines connected to the plurality of transistors. For example, each transistor may include a structure in which a semiconductor pattern, a gate electrode, a source electrode, and a drain electrode are stacked sequentially with an insulating layer in between.

[0053] The display element layer (DPL) is located on the pixel circuit layer (PCL) and may include light-emitting elements. For example, the light-emitting element may be an organic light-emitting diode, an inorganic light-emitting element, or a light-emitting element that emits light by changing the wavelength of the emitted light using quantum dots.

[0054] The cover layer (CVL) may be located on the display element layer (DPL). The cover layer (CVL) may be in the form of an encapsulation substrate or an encapsulation film composed of a multilayer film. If the cover layer (CVL) is in the form of an encapsulation film, it may be in the form of an inorganic film, an organic film, and an inorganic film stacked in sequence. For example, the cover layer (CVL) may include plastics such as polycarbonate, polypropylene, polyimide, and polyethylene terephthalate, and may include materials such as glass. The cover layer (CVL) can prevent external air and moisture from penetrating into the display element layer (DPL) and the pixel circuit layer (PCL).

[0055] According to an embodiment, the cover layer (CVL) is made of a heat and / or photocurable resin and is coated onto the base layer (BSL) in a liquid form, after which it can be cured by a curing process using heat and / or light. At this time, the cover layer (CVL) can protect the light-emitting element while simultaneously stably fixing the light-emitting element.

[0056] Additionally, according to an embodiment, a window may be provided on the cover layer (CVL) to protect the display device from external impact and to provide an input surface and / or a display surface to the user. According to another embodiment, the cover layer (CVL) may be omitted.

[0057] Hereinafter, the structure of a display device according to one embodiment will be examined with reference to FIGS. 6 and FIGS. 7.

[0058] FIG. 6 is a drawing showing one side of a base layer in a display device according to one embodiment, and FIG. 7 is a cross-sectional view cut along the line VI-VI' of FIG. 6.

[0059] Referring to FIG. 6, a display device according to one embodiment may include a base layer (BSL), a back wiring (RL), and a back pad electrode (RPD).

[0060] The back wiring (RL) may be disposed on one side of the base layer (BSL). In one embodiment, the back wiring (RL) may be disposed on the back side of the base layer (BSL).

[0061] The back wiring (RL) may be extended in a second direction (DR2). Additionally, a plurality of back wirings may be extended in a second direction (DR2) so as to be spaced apart from each other in a first direction (DR1). For example, the back wiring (RL) may be a back data wiring for providing a data voltage to a pixel circuit layer (PCL, see FIG. 5). The present invention is not limited thereto, and depending on the embodiment, the back wiring (RL) may correspond to a power wiring, a gate wiring, a sensing wiring, a control wiring, etc. The back wiring (RL) may be electrically connected to a circuit element, such as a transistor of the pixel circuit layer (PCL), through a connecting wiring, etc., which may be disposed on the side of the base layer (BSL).

[0062] The back wiring (RL) may include a metallic material. For example, the back wiring (RL) may include a single layer structure composed of a single material or a mixture thereof selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof. Additionally, the back wiring (RL) may be a double layer or multilayer structure further comprising low-resistance materials such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) to reduce wiring resistance.

[0063] The back pad electrode (RPD) can be partially extended in the second direction (DR2) and can overlap at least partially with the back wiring (RL).

[0064] The back pad electrode (RPD) may include a transparent conductive oxide. For example, the back pad electrode (RPD) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc.

[0065] Referring to FIG. 7, a display device according to one embodiment may include a base layer (BSL), a flattening layer (PLL), a first insulating layer (INS1), a back wiring (RL), a back pad electrode (RPD), and a second insulating layer (INS2).

[0066] The base layer (BSL) may include a first surface (SF1) and a second surface (SF2) which is opposite to the first surface (SF1). In one embodiment, the first surface (SF1) may be referred to as the front surface, and the second surface (SF2) may be referred to as the back surface. The present invention is not limited thereto, and depending on the embodiment, the first surface (SF1) may be referred to as the back surface, and the second surface (SF2) may be referred to as the front surface.

[0067] On the first surface (SF1) of the base layer (BSL), the aforementioned pixel circuit layer (PCL, see FIG. 5) and display element layer (DPL, see FIG. 5) may be located.

[0068] A flattening layer (PLL) may be located on the second surface (SF2) of the base layer (BSL). The flattening layer (PLL) can cover the entire second surface (SF2) of the base layer (BSL) and flatten one surface of the base layer (BSL). Accordingly, the flattening layer (PLL) can stably place wiring, electrodes, etc. on one surface of the base layer (BSL) (e.g., the second surface (SF2)). That is, even if impurities are present on one surface of the base layer (BSL) or if one surface of the base layer (BSL) is not flat due to scratches, cracks, etc. of the base layer (BSL), the flattening layer (PLL) flattenes one surface of the base layer (BSL), thereby ensuring the structural stability of the display device.

[0069] The planarization layer (PLL) may be an organic insulating layer comprising an organic material (or material). For example, the planarization layer (PLL) may include polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimide resin, unsaturated polyesters resin, polyphenylene ethers resin, polyphenylene sulfides resin, and benzocyclobutene resin.

[0070] A first insulating layer (INS1) may be located on the flattening layer (PLL). The first insulating layer (INS1) may cover one side of the flattening layer (PLL) entirely.

[0071] The first insulating layer (INS1) may be an inorganic insulating layer comprising an inorganic material (or material). Additionally, the first insulating layer (INS1) may include a transparent inorganic insulating material to align wiring, etc.

[0072] A back wiring (RL) may be positioned on the first insulating layer (INS1). Since the second surface (SF2) of the base layer (BSL) is flattened by the flattening layer (PLL) and the first insulating layer (INS1), the back wiring (RL) can be stably positioned on the first insulating layer (INS1) without defects such as short circuits or step differences.

[0073] A back pad electrode (RPD) may be located on the back wiring (RL). The back pad electrode (RPD) may be located on the back wiring (RL) and the first insulating layer (INS1) to cover the back wiring (RL).

[0074] A second insulating layer (INS2) may be positioned on the back pad electrode (RPD). The second insulating layer (INS2) may cover the back pad electrode (RPD) to expose at least a portion of the upper surface of the back pad electrode (RPD) and may cover the first insulating layer (INS1). A circuit board, etc., may be attached to the upper surface of the back pad electrode (RPD) exposed by the second insulating layer (INS2).

[0075] The second insulating layer (INS2) may be an inorganic insulating layer comprising an inorganic material. For example, the second insulating layer (INS2) may be silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (AlO x It may include at least one of metal oxides such as ). According to an embodiment, a back via layer may be disposed between the first insulating layer (INS1) and the second insulating layer (INS2).

[0076] Hereinafter, a method for manufacturing a display device according to one embodiment will be examined with reference to FIGS. 8 to 11.

[0077] FIGS. 8 to 11 are drawings illustrating, in sequence, a manufacturing method for manufacturing the display device of FIG. 7.

[0078] Referring to FIG. 8, a base layer (BSL) may be prepared, and a pixel circuit layer (PCL) and a display element layer (DPL) may be sequentially formed on a first surface (SF1) of the base layer (BSL). For example, the base layer (BSL) may be a rigid substrate including a glass substrate, a quartz substrate, a glass ceramic substrate, a crystalline glass substrate, etc. Additionally, the base layer (BSL) may be a flexible substrate including a flexible material. For example, a flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the material constituting the base layer (SUB) is not limited to the embodiments described above. For example, the pixel circuit layer (PCL) can form a first transistor on the first surface (SF1), and the display element layer (DPL) can place a light-emitting element on the pixel circuit layer (PCL).

[0079] Referring to FIG. 9, a planarization layer (PLL) can be formed on a second surface (SF2) of a base layer (BSL). For example, the planarization layer (PLL) may be an organic insulating layer comprising polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimide resin, unsaturated polyesters resin, polyphenylene ethers resin, polyphenylene sulfides resin, and benzocyclobutene resin.

[0080] Referring to FIG. 10, a first insulating layer (INS1) can be formed on a flattening layer (PLL). For example, the first insulating layer (INS1) may be a transparent inorganic insulating layer.

[0081] Referring to FIG. 11, back wiring (RL) and back pad electrodes (RPD) can be formed on a first insulating layer (INS1). Specifically, two back wirings (RL) can be formed spaced apart from each other in a first direction (DR1), and two back pad electrodes (RPD) can be formed spaced apart from each other in a first direction (DR1) and to cover the two back wirings (RL). For example, the back wiring (RL) can be implemented as a single film formed from a single material or a mixture thereof selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, or as a double film or multi-film structure further comprising low-resistance materials such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) to reduce wiring resistance. The back pad electrode (RPD) may include a transparent conductive material containing conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), and conductive polymers such as PEDOT (poly(3,4-ethylenedioxythiophene)).

[0082] Referring again to FIG. 7, a second insulating layer (INS2) can be formed on the back pad electrode (RPD) and the first insulating layer (INS1) to cover the back pad electrode (RPD) and the first insulating layer (INS1). As an example, the second insulating layer (INS2) is silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (AlO xIt may be an inorganic insulating layer including ) etc.

[0083] In a display device according to one embodiment, after a pixel circuit layer (PCL) and a display element layer (DPL), etc. are formed on a first surface (SF1) of a base layer (BSL), a back wiring (RL), a back pad electrode (RPD), etc. may be formed on a second surface (SF2) of the base layer (BSL).

[0084] As a pixel circuit layer (PCL) and a display element layer (DPL), etc. are formed on the first surface (SF1) of the base layer (BSL), foreign substances may exist on the second surface (SF2) of the base layer (BSL), and scratches, cracks, etc. may occur on the second surface (SF2) of the base layer (BSL). Accordingly, in one embodiment, a planarization layer (PLL) can be formed on the second surface (SF2) of the base layer (BSL), and a back wiring (RL) and a back pad electrode (RPD), etc. can be formed, thereby preventing defects in the back wiring (RL), etc., and ensuring the structural stability of the display device.

[0085] Hereinafter, with reference to FIGS. 12 and FIGS. 13, we will examine a light-emitting element included in a display device and a pixel according to one embodiment.

[0086] FIG. 12 is a perspective view illustrating a light-emitting element included in a display device according to one embodiment, and FIG. 13 is a cross-sectional view illustrating a light-emitting element included in a display device according to one embodiment.

[0087] Referring to FIGS. 12 and 13, the light-emitting element (LD) may include a first semiconductor layer (11), an active layer (12), and a second semiconductor layer (13). For example, the light-emitting element (LD) may be composed of a light-emitting laminate (10) in which the first semiconductor layer (11), the active layer (12), and the second semiconductor layer (13) are sequentially stacked. According to an embodiment, the light-emitting element (LD) may further include a coupling electrode layer, and the coupling electrode layer may be stacked on one side of the first semiconductor layer (11) or on one side of the second semiconductor layer (13).

[0088] Along the height (h) direction of the light-emitting element (LD), the lower surface can be referred to as the first end (EP1), and the upper surface can be referred to as the second end (EP2).

[0089] The light-emitting element (LD) may have a columnar shape in which the diameter (DD1) of the first end (EP1) and the diameter (DD2) of the second end (EP2) are different from each other. For example, the light-emitting element (LD) may have a columnar shape in which the diameter (DD1) of the first end (EP1) is smaller than the diameter (DD2) of the second end (EP2). Specifically, the light-emitting element (LD) may have an elliptical columnar shape in which the diameter increases as it moves upward along the height (h) direction. The present invention is not limited thereto, and according to an embodiment, the light-emitting element (LD) may have a columnar shape in which the diameter (DD1) of the first end (EP1) is larger than the diameter (DD2) of the second end (EP2). That is, according to an embodiment, the light-emitting element (LD) may have an elliptical columnar shape in which the diameter decreases as it moves upward along the height (h) direction.

[0090] Additionally, according to an embodiment, the light-emitting element (LD) may be implemented with the shapes of the first end (EP1) and the second end (EP2) as polygons such as rectangles, squares, equilateral triangles, and regular pentagons. That is, according to an embodiment, the light-emitting element (LD) may have a truncated pyramid shape in which the area of ​​the upper surface and the area of ​​the lower surface are different.

[0091] Light-emitting diodes (LDs) can have a size ranging from nanoscale to microscale. However, the size of the light-emitting diode (LD) is not limited to this, and the size of the light-emitting diode (LD) can be varied depending on the design conditions of various devices (e.g., display devices) that utilize a light-emitting device using the light-emitting diode (LD) as a light source.

[0092] The first semiconductor layer (11) may be a semiconductor layer of the first conductivity (or type). For example, the first semiconductor layer (11) may include at least one n-type semiconductor. For example, the first semiconductor layer (11) may include any one of the semiconductor materials of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor layer doped with a first conductive dopant such as Si, Ge, Sn, etc. However, the material constituting the first semiconductor layer (11) is not limited thereto, and the first semiconductor layer (11) may be composed of various other materials.

[0093] The active layer (12) is disposed on one side of the first semiconductor layer (11). The active layer (12) may be disposed on the first semiconductor layer (11). The active layer (12) may be formed as a single or multiple quantum well structure. In one embodiment, a clad layer (not shown) doped with a conductive dopant may be formed on the upper and / or lower part of the active layer (12). For example, the clad layer may be formed as an AlGaN layer or an InAlGaN layer. According to the embodiment, materials such as AlGaN and InAlGaN may be used to form the active layer (12), and various other materials may also constitute the active layer (12).

[0094] When a voltage greater than the threshold voltage is applied to the upper and lower surfaces of the light-emitting element (LD), electron-hole pairs combine in the active layer (12), causing the light-emitting element (LD) to emit light. By controlling the light emission of the light-emitting element (LD) using this principle, it can be used as a light source for various light-emitting devices, including pixels of a display device.

[0095] The second semiconductor layer (13) is disposed on one side of the active layer (12). The second semiconductor layer (13) may be disposed on the active layer (12). The second semiconductor layer (13) may include a semiconductor layer having a different conductivity (or type) from the first semiconductor layer (11). For example, the second semiconductor layer (13) may include at least one p-type semiconductor layer. For example, the second semiconductor layer (13) may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant such as Mg, Zn, Ca, Sr, Ba, etc. However, the material constituting the second semiconductor layer (13) is not limited thereto, and various other materials may also constitute the second semiconductor layer (13).

[0096] Meanwhile, the first semiconductor layer (11) and the second semiconductor layer (13) are each depicted as being composed of a single layer, but the present invention is not limited thereto. In one embodiment, depending on the material of the active layer (12), the first semiconductor layer (11) and the second semiconductor layer (13) may each further include at least one layer, for example, a clad layer and / or a TSBR (tensile strain barrier reducing) layer. The TSBR layer may be a strain relaxation layer that acts as a buffer to reduce the difference in lattice constants by being disposed between semiconductor layers with different lattice structures. The TSBR layer may be composed of a p-type semiconductor layer such as p-GaInP, p-AlInP, p-AlGaInP, etc., but the present invention is not limited thereto.

[0097] According to an embodiment, the light-emitting element (LD) may further include an electrode disposed above the first semiconductor layer (11) and / or below the second semiconductor layer (13) in addition to the first semiconductor layer (11), active layer (12), and second semiconductor layer (13) described above. The electrode may be an ohmic contact electrode, but the present invention is not limited thereto. According to an embodiment, the electrode may be a Schottky contact electrode. The electrode may include a conductive material. For example, the electrode may include an opaque metal using chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and oxides or alloys thereof, either alone or in combination, but the present invention is not limited thereto. According to an embodiment, the electrode may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO). Additionally, the electrode may be a portion that is in direct contact with an anode or a cathode.

[0098] In one embodiment, the light-emitting element (LD) may further include an insulating film (14). Depending on the embodiment, the insulating film (14) may be omitted or provided to cover only a portion of the light-emitting laminate (10).

[0099] The insulating film (14) can prevent electrical short circuits that may occur when the active layer (12) comes into contact with a conductive material other than the first and second semiconductor layers (11, 13). Additionally, the insulating film (14) can improve the lifespan and luminous efficiency of the light-emitting element (LD) by minimizing surface defects of the light-emitting element (LD). Furthermore, when the light-emitting elements (LDs) are closely arranged, the insulating film (14) can prevent unwanted short circuits that may occur between the light-emitting elements (LDs). As long as the active layer (12) can prevent short circuits from occurring with an external conductive material, the provision of the insulating film (14) is not limited.

[0100] The light-emitting element (LD) may further include a reflective member surrounding the outer surface of the insulating film (14). The reflective member may be composed of a material having a predetermined reflectance to concentrate light emitted from the light-emitting element (LD) into a specific area while allowing it to proceed in the direction of image display. As an example, the reflective member may be composed of a conductive material (or material) having a predetermined reflectance.

[0101] Below, we will examine the structure of a display device according to one embodiment with reference to FIG. 14.

[0102] FIG. 14 is a cross-sectional view schematically illustrating a pixel of a display device including the light-emitting elements of FIG. 12 and FIG. 13.

[0103] Referring to FIG. 14, a pixel (PXL) included in a display device according to one embodiment may include a base layer (BSL), a pixel circuit layer (PCL), and a display element layer (DPL). Here, the base layer (BSL), the pixel circuit layer (PCL), and the display element layer (DPL) may correspond to the base layer (BSL), the pixel circuit layer (PCL), and the display element layer (DPL) mentioned in FIG. 5, FIG. 8 to FIG. 11.

[0104] The base layer (BSL) may be a rigid or flexible substrate. For example, if the base layer (BSL) is a rigid substrate, the base layer (BSL) may be implemented as a glass substrate, a quartz substrate, a glass ceramic substrate, a crystalline glass substrate, etc. If the base layer (BSL) is a flexible substrate, the base layer (BSL) may be implemented as a polymer organic substrate including polyimide, polyamide, etc., a plastic substrate, etc.

[0105] The pixel circuit layer (PCL) can be located on the first surface (SF1) of the base layer (BSL).

[0106] The pixel circuit layer (PCL) may include at least one transistor and a plurality of wires connected thereto. Additionally, the pixel circuit layer (PCL) may include a buffer layer (BFL), a first gate insulating layer (GI1), a second gate insulating layer (GI2), an interlayer insulating layer (ILD), a first via layer (VIA1), and a second via layer (VIA2) sequentially stacked on one side of a base layer (BSL).

[0107] The buffer layer (BFL) is positioned on the base layer (BSL) to cover the base layer (BSL). The buffer layer (BFL) can prevent impurities from diffusing from the outside into the pixel circuit layer (PCL). The buffer layer (BFL) is silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y ), and aluminum oxide (AlO x It may include at least one of metal oxides such as ). Depending on the embodiment, the buffer layer (BFL) may be omitted. Additionally, a lower metal layer may be located between the base layer (BSL) and the buffer layer (BFL).

[0108] The first transistor (T1) may include a first semiconductor pattern (ACT1), a first gate electrode (GE1), a first source electrode (S1), and a first drain electrode (D1).

[0109] A first semiconductor pattern (ACT1) is located on a buffer layer (BFL). The first semiconductor pattern (ACT1) may include a channel region and source and drain regions located on both sides of the channel region. The source region of the first semiconductor pattern (ACT1) may be electrically connected to a first source electrode (S1), and the drain region may be electrically connected to a first drain electrode (D1). That is, the source region and the drain region may be extended and electrically connected to electrodes of another layer through contact holes, respectively.

[0110] The first semiconductor pattern (ACT1) may include at least one of polycrystalline silicon, amorphous silicon, and oxide semiconductor.

[0111] The first gate insulating layer (GI1) is located on the first semiconductor pattern (ACT1) and the buffer layer (BFL). The first gate insulating layer (GI1) covers the first semiconductor pattern (ACT1) and the buffer layer (BFL).

[0112] The first gate insulating layer (GI1) may include an inorganic material. As an example, the first gate insulating layer (GI1) may be silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y ), and aluminum oxide (AlO x It may include at least one of ). According to an embodiment, the first gate insulating layer (GI1) may include an organic material.

[0113] The first gate electrode (GE1) is located on the first gate insulating layer (GI1). The first gate electrode (GE1) can be positioned to overlap with the channel region of the first semiconductor pattern (ACT1).

[0114] The driving voltage wiring (DVL) is located on the first gate insulating layer (GI1). The driving voltage wiring (DVL) may be physically and / or electrically connected to the bridge electrode (BRD) through the second contact hole (CH2). Since the bridge electrode (BRD) may be physically and / or electrically connected to the second electrode (EL2), the driving voltage wiring (DVL) can transmit the voltage of the second driving power source (e.g., VSS) to the second electrode (EL2) through the bridge electrode (BRD). Although the driving voltage wiring (DVL) is depicted as being located on the same layer as the first gate electrode (GE1), the present invention is not limited thereto.

[0115] The second gate insulating layer (GI2) is located on the first gate electrode (GE1) and the first gate insulating layer (GI1). The second gate insulating layer (GI2) covers the first gate electrode (GE1) and the first gate insulating layer (GI1).

[0116] The second gate insulating layer (GI2) may include the same material as the first gate insulating layer (GI1), and, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y ), and aluminum oxide (AlO x It may include at least one of ).

[0117] The second gate electrode (GE2) is located on the second gate insulating layer (GI2). The second gate electrode (GE2) can be positioned to overlap with the first gate electrode (GE1). Accordingly, the first gate electrode (GE1) and the second gate electrode (GE2), which overlap with the second gate insulating layer (GI2) in between, can form a single storage capacitor (Cst).

[0118] The interlayer insulating layer (ILD) is located on the second gate insulating layer (GI2). The interlayer insulating layer (ILD) covers the second gate insulating layer (GI2). The interlayer insulating layer (ILD) may be an inorganic insulating layer containing an inorganic material. For example, the interlayer insulating layer (ILD) may be silicon nitride (SiNx) or silicon oxide (SiO2). x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (AlO x It may include at least one of metal oxides such as ). The present invention is not limited thereto, and according to an embodiment, the interlayer insulating layer (ILD) may be an organic insulating layer including an organic material.

[0119] The first source electrode (S1) and the first drain electrode (D1) are located on the interlayer insulating layer (ILD).

[0120] The first drain electrode (D1) can be electrically connected to the first electrode (EL1) of the display element layer (DPL) through the first contact hole (CH1) of the passivation layer (PSV) and the second via layer (VIA2) described later. Accordingly, the first transistor (T1) can deliver the voltage of the first driving power source (e.g., VDD) to the first electrode (EL1).

[0121] The first via layer (VIA1) is located on the interlayer insulating layer (ILD). The first via layer (VIA1) covers a portion of the interlayer insulating layer (ILD). Here, the first via layer (VIA1) may be referred to as a dam structure, pixel defining film, or bank that partitions the light-emitting region.

[0122] The first via layer (VIA1) may include at least one organic insulating layer. The first via layer (VIA1) may be composed of a single layer or multiple layers and may include an inorganic insulating material or an organic insulating material. For example, the first via layer (VIA1) may include at least one of an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0123] The bridge electrode (BRD) is located on the interlayer insulating layer (ILD) and the first via layer (VIA1). The bridge electrode (BRD) may be arranged in a curved manner in the third direction (DR3) along the shape of the first via layer (VIA1). The bridge electrode (BRD) may be physically and / or electrically connected to the driving voltage wiring (DVL) through the second gate insulating layer (GI2) and the second contact hole (CH2) of the interlayer insulating layer (ILD). Although the bridge electrode (BRD) is depicted as being located on the same layer as the first source electrode (S1) and the first drain electrode (D1) of the first transistor (T1), the present invention is not limited thereto.

[0124] The passivation layer (PSV) is located on the first source electrode (S1), the first drain electrode (D1), the interlayer insulating layer (ILD), and the bridge electrode (BRD). The passivation layer (PSV) may cover the first source electrode (S1) and the first drain electrode (D1) entirely, and may cover the interlayer insulating layer (ILD) and the bridge electrode (BRD) partially.

[0125] The passivation layer (PSV) may be provided in a form comprising an organic insulating layer, an inorganic insulating layer, or an organic insulating layer disposed on an inorganic insulating layer. For example, the inorganic insulating layer may comprise at least one of metal oxides such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). For example, the organic insulating layer may comprise at least one of polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated polyesters resin, polyphenylene ethers resin, polyphenylene sulfides resin, and benzocyclobutene resin.

[0126] A second via layer (VIA2) is positioned over a passivation layer (PSV) and a bridge electrode (BRD). The second via layer (VIA2) may partially cover the passivation layer (PSV) and the bridge electrode (BRD) so as to have at least one opening (OP). That is, at the opening (OP) of the second via layer (VIA2) that partially exposes the upper surface of the bridge electrode (BRD), the second electrode (EL2) and the bridge electrode (BRD) may be physically and / or electrically connected. Here, the second via layer (VIA2) may be referred to as a dam structure, a pixel defining film, or a bank that partitions the light-emitting region together with the first via layer (VIA1).

[0127] Additionally, depending on the height of the upper surface formed along the third direction (DR3), a portion of the second via layer (VIA2) may be located in the display element layer (DPL). A second electrode (EL2) may be located on the upper surface of the second via layer (VIA2) located in the display element layer (DPL).

[0128] The second via layer (VIA2) may include at least one organic insulating layer. The second via layer (VIA2) may be composed of a single film or multiple films and may include an inorganic insulating material or an organic insulating material. For example, the second via layer (VIA2) may include at least one of an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0129] The display element layer (DPL) may include a first electrode (EL1), a coupling electrode (CP), light-emitting elements (LD), a protective layer (PVX), and a second electrode (EL2).

[0130] The first electrode (EL1) is located on the second via layer (VIA2). That is, the first electrode (EL1) can be located on the pixel circuit layer (PCL).

[0131] The first electrode (EL1) can be in contact with the first end (EP1) of each of the light-emitting elements (LDs) and can be electrically and / or physically connected. The first electrode (EL1) can be electrically connected to the first transistor (T1) of the pixel circuit layer (PCL) through the first contact hole (CH1). Here, the first electrode (EL1) may be an anode.

[0132] The first electrode (EL1) may include a transparent conductive material having a predetermined reflectance. As an example, the first electrode (EL1) may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), or conductive polymers such as PEDOT (poly(3,4-ethylenedioxythiophene)). Additionally, the first electrode (EL1) may include an opaque metal that is advantageous for reflecting light emitted from light-emitting elements (LDs) toward the image display direction of the display device (e.g., a third direction (DR3)). For example, the first electrode (EL1) may further include metals such as magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), and alloys thereof.

[0133] The coupling electrode (CP) is located on the first electrode (EL1) and is a portion that is bonded to the light-emitting elements (LD). The coupling electrode (CP) is located between the first electrode (EL1) and the light-emitting element (LD) and can be electrically connected to the first electrode (EL1) and the light-emitting element (LD). That is, the coupling electrode (CP) can directly contact the first end (EP1) of the light-emitting element (LD) to electrically and / or physically connect the first electrode (EL1) and the first end (EP1) of the light-emitting element (LD).

[0134] The coupling electrode (CP) can be utilized as a reflective member to guide light emitted from light-emitting elements (LDs) toward the image display direction of the display device (e.g., a third direction (DR3)). To this end, the coupling electrode (CP) may be composed of an opaque conductive material having a predetermined reflectivity. The coupling electrode (CP) may include the same material as the first electrode (EL1) or one or more materials selected from the materials exemplified as constituent materials of the first electrode (EL1). For example, the coupling electrode (CP) may include a metal such as copper (Cu), gold (Au), tin (Sn), and alloys thereof that can be bonded to the light-emitting elements (LD).

[0135] A light-emitting element (LD) is positioned on a coupling electrode (CP). A first end (EP1) of the light-emitting element (LD) is positioned on the coupling electrode (CP), and the first end (EP1) of the light-emitting element (LD) may be electrically and / or physically connected to the coupling electrode (CP).

[0136] The first end (EP1) of the light-emitting element (LD) may be positioned to face the coupling electrode (CP), and the second end (EP2) of the light-emitting element (LD) may be positioned to face the second electrode (EL2).

[0137] The light-emitting element (LD) can be positioned in the height (h) direction of the light-emitting element (LD) between the coupling electrode (CP) and the second electrode (EL2). The light-emitting element (LD) illustrated in FIG. 14 may correspond to the light-emitting element (LD) of FIG. 12 and FIG. 13 described above. In FIG. 14, to simplify the illustration of the light-emitting element (LD), the diameter of the first end (EP1) and the diameter of the second end (EP2) are shown as being the same.

[0138] Additionally, an insulating film (not shown) covering the surface of the light-emitting element (LD), excluding the first end (EP1) and the second end (EP2), may be further positioned on the side of the light-emitting element (LD). Due to the insulating film, the light-emitting element (LD) can be more stably fixed on the coupling electrode (CP).

[0139] A protective layer (PVX) is positioned over a portion of the second via layer (VIA2), the first electrode (EL1), the coupling electrode (CP), and the light-emitting element (LD). The protective layer (PVX) is positioned to cover a portion of the upper surface of the second via layer (VIA2) and to cover the first electrode (EL1) and the coupling electrode (CP) entirely. Additionally, the protective layer (PVX) is positioned between the light-emitting elements (LD) so that the second end (EP2) of the light-emitting element (LD) is exposed.

[0140] The protective layer (PVX) may include an inorganic insulating layer containing an inorganic material or an organic insulating layer containing an organic material. In one embodiment, the protective layer (PVX) may be utilized as a flattening layer that mitigates step differences caused by components disposed underneath it within the display element layer (DPL). To this end, the protective layer (PVX) may be composed of an organic insulating layer containing an organic material.

[0141] The second electrode (EL2) is positioned on the light-emitting element (LD), the protective layer (PVX), and the second via layer (VIA2). The second electrode (EL2) can be positioned to cover the light-emitting element (LD), the protective layer (PVX), and the second via layer (VIA2). Additionally, the second electrode (EL2) can be positioned to cover a portion of the upper surface of the passivation layer (PSV).

[0142] The second electrode (EL2) may include a transparent conductive material having a predetermined reflectance. As an example, the second electrode (EL2) may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), or conductive polymers such as PEDOT (poly(3,4-ethylenedioxythiophene)). However, the material of the second electrode (EL2) is not limited to the above description.

[0143] Below, with reference to FIG. 15, we examine the structure of another light-emitting element according to one embodiment, and with reference to FIG. 16, we examine a display device in which the light-emitting element of FIG. 15 can be arranged.

[0144] FIG. 15 is a cross-sectional view illustrating another embodiment of a light-emitting element included in a display device according to one embodiment, and FIG. 16 is a cross-sectional view schematically illustrating a pixel of a display device according to one embodiment. The part illustrated in FIG. 16 may correspond to a display area of ​​the display device.

[0145] Referring to FIG. 15, a light-emitting element (LD) according to one embodiment may include a semiconductor structure (LD'), a first electrode (EL1), and a second electrode (EL2).

[0146] A semiconductor structure (LD') can emit light through the recombination of electrons and holes by the current flowing between the first electrode (EL1) and the second electrode (EL2). By utilizing this principle to control the light emission of the semiconductor structure (LD'), the light-emitting element (LD) can be used as a light source (or light source) for various light-emitting devices.

[0147] The first semiconductor layer (11) may, for example, include at least one n-type semiconductor layer. For example, the first semiconductor layer (11) may include any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, Sn, etc. However, the material constituting the first semiconductor layer (11) is not limited thereto, and the first semiconductor layer (11) may be composed of various other materials. In one embodiment, the first semiconductor layer (11) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant).

[0148] The active layer (12) is disposed on one side of the first semiconductor layer (11) and can be implemented as a single or multiple quantum well structure. For example, when the active layer (12) is implemented as a multiple quantum well structure, the active layer (12) may have a barrier layer, a strain reinforcing layer, and a well layer periodically stacked as a single unit. The strain reinforcing layer has a smaller lattice constant than the barrier layer and can further reinforce the strain applied to the well layer, for example, compressive strain. However, the structure of the active layer (12) is not limited to the above-described embodiment.

[0149] The active layer (12) can emit light having a wavelength of 400 nm to 900 nm and may use a double hetero structure. In one embodiment, a clad layer doped with a conductive dopant may be formed on the upper and / or lower part of the active layer (12) along the third direction (DR3). For example, the clad layer may be formed as an AlGaN layer or an InAlGaN layer. According to the embodiment, materials such as AlGaN and InAlGaN may be used to form the active layer (12), and various other materials may also constitute the active layer (12). The active layer (12) may include a first surface in contact with the first semiconductor layer (11) and a second surface in contact with the second semiconductor layer (13).

[0150] The second semiconductor layer (13) is disposed on the second surface of the active layer (12) and provides holes to the active layer (12). The second semiconductor layer (13) may include a semiconductor layer of a different type from the first semiconductor layer (11). For example, the second semiconductor layer (13) may include at least one p-type semiconductor layer. For example, the second semiconductor layer (13) may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg. However, the material constituting the second semiconductor layer (13) is not limited thereto, and various other materials may also constitute the second semiconductor layer (13). In one embodiment, the second semiconductor layer (13) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant). The second semiconductor layer (13) may include a lower surface in contact with the second surface of the active layer (12) along the third direction (DR3) and an upper surface in contact with the second electrode (EL2).

[0151] Each of the aforementioned first semiconductor layer (11), active layer (12), and second semiconductor layer (13) may be provided in a structure sequentially stacked on a semiconductor substrate. Here, the semiconductor substrate may include a semiconductor material such as a sapphire substrate or a silicon substrate. After being used as a growth substrate for growing each of the first semiconductor layer (11), active layer (12), and second semiconductor layer (13), such a semiconductor substrate may be separated from the first semiconductor layer (11) by a substrate separation process. Here, the substrate separation process may be a laser lift-off or a chemical lift-off, etc. Accordingly, as the growth semiconductor substrate is removed from the semiconductor structure (LD'), the semiconductor structure (LD') may have a thin thickness. The aforementioned semiconductor structure (LD') may have a size small to the micro-scale, but the present invention is not limited thereto.

[0152] The semiconductor structure (LD') may include a mesa interface. The mesa interface may be formed by removing a portion of each of the second semiconductor layer (13), the active layer (12), and the first semiconductor layer (11) through an etching process. Here, the etching process may be, for example, a dry etching process.

[0153] A first electrode (EL1) may be provided and / or formed on a semiconductor structure (LD'). For example, the first electrode (EL1) may be provided and / or formed on a first semiconductor layer (11) so as to be electrically isolated from the active layer (12) and the second semiconductor layer (13). In one embodiment, the first electrode (EL1) may be in contact with a bump (not shown) for bonding the light-emitting element (LD).

[0154] A second electrode (EL2) may be provided and / or formed on a semiconductor structure (LD'). For example, the second electrode (EL2) may be provided and / or formed on a second semiconductor layer (13). In one embodiment, the second electrode (EL2) may be in contact with another bump (not shown) for bonding the light-emitting element (LD).

[0155] The first electrode (EL1) may be a contact electrode that makes ohmic contact with the first semiconductor layer (11), and the second electrode (EL2) may be a contact electrode that makes ohmic contact with the second semiconductor layer (13). According to an embodiment, the first and second electrodes (EL1, EL2) may be Schottky contact electrodes. Additionally, the first electrode (EL1) may be a cathode, and the second electrode (EL2) may be an anode.

[0156] The first electrode (EL1) and the second electrode (EL2) may include a conductive material. For example, the first and second electrodes (EL1, EL2) may include opaque metals such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and oxides or alloys thereof, used alone or in combination, but the present invention is not limited thereto. According to an embodiment, the first electrode (EL1) and the second electrode (EL2) may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO).

[0157] Referring to FIG. 16, a pixel (PXL) according to one embodiment may include a base layer (BSL), a pixel circuit layer (PCL) located on the base layer (BSL), and a back wiring layer (RLL). Here, the base layer (BSL) and the pixel circuit layer (PCL) may correspond to the base layer (BSL) and the pixel circuit layer (PCL) mentioned in FIG. 5.

[0158] The pixel circuit layer (PCL) may include a lower metal layer (BML) located on a first surface (SF1) of a base layer (BSL), a first transistor (T1), a storage capacitor (Cst), a first bridge electrode (BRD1), a first data electrode (SD1), a second bridge electrode (BRD2), a second data electrode (SD2), a first pixel electrode (PDE1), a second pixel electrode (PDE2), a first contact electrode (CNE1), a second contact electrode (CNE2), and a plurality of insulating layers (BFL, GI1, GI2, ILD, VIA1, VIA2, VIA3, VIA4, FIN1, FIN2, FIN3, FIN4).

[0159] The lower metal layer (BML) is located on the base layer (BSL) and may overlap at least partially with the first transistor (T1) described later. As an example, the lower metal layer (BML) may be made of a single material or a mixture thereof selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof.

[0160] The buffer layer (BFL) is located on the base layer (BSL) and the lower metal layer (BML), and can prevent impurities, etc. from diffusing into circuit elements, etc. located on the buffer layer (BFL). The buffer layer (BFL) may be an inorganic insulating layer containing an inorganic material. For example, the buffer layer (BFL) may be silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y), aluminum oxide (AlO x It may include at least one of metal oxides such as ).

[0161] The first transistor (T1) may include a first semiconductor pattern (ACT1), a first source electrode (SE1), a first drain electrode (DE1), and a first gate electrode (GE1).

[0162] The first semiconductor pattern (ACT1), the first source electrode (SE1), and the first drain electrode (DE1) can be located on the buffer layer (BFL).

[0163] The first semiconductor pattern (ACT1) may include a channel region, a first source region, and a first drain region of the first transistor (T1) as an area overlapping with the first gate electrode (GE1). The first source region is a part of the first semiconductor pattern (ACT1) and may be electrically and / or physically connected through contact holes of the first source electrode (SE1) and insulating layers (GI1, GI2, ILD). The first drain region is a part of the first semiconductor pattern (ACT1) and may be electrically and / or physically connected through contact holes of the first drain electrode (DE1) and insulating layers (GI1, GI2, ILD).

[0164] The first semiconductor pattern (ACT1) may be a semiconductor pattern composed of polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. For example, the first source region and the first drain region may be composed of an impurity-doped semiconductor layer, and the channel region may be composed of an impurity-undoped semiconductor layer. As for the impurity, for example, n-type impurities may be used, but the present invention is not limited thereto.

[0165] The first gate electrode (GE1) is located on the first gate insulating layer (GI1) and may be positioned to overlap with the first semiconductor pattern (ACT1). For example, the first gate electrode (GE1) may include a single layer structure made of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, either alone or in a mixture thereof.

[0166] The first gate insulating layer (GI1) may be located on the buffer layer (BFL) and the first semiconductor pattern (ACT1). The first gate insulating layer (GI1) may be an inorganic insulating layer including an inorganic material. For example, the first gate insulating layer (GI1) may be silicon nitride (SiNx) or silicon oxide (SiO2). x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (AlO x It may include at least one of metal oxides such as ). The present invention is not limited thereto, and according to an embodiment, the first gate insulating layer (GI1) may be an organic insulating layer including an organic material.

[0167] The first storage electrode (STE1) can be located on the first gate insulating layer (GI1).

[0168] The second gate insulating layer (GI2) may be located on the first gate insulating layer (GI1), the first gate electrode (GE1), and the first storage electrode (STE1). The second gate insulating layer (GI2) may be an inorganic insulating layer including an inorganic material. For example, the second gate insulating layer (GI2) may be silicon nitride (SiNx) or silicon oxide (SiO2). x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (AlO xIt may include at least one of metal oxides such as ). The present invention is not limited thereto, and according to an embodiment, the second gate insulating layer (GI2) may be an organic insulating layer including an organic material.

[0169] The second storage electrode (STE2) can be located on the second gate insulating layer (GI2) and can overlap with the first storage electrode (STE1) to form a storage capacitor (Cst) together with the first storage electrode (STE1).

[0170] The interlayer insulating layer (ILD) may be located on the second gate insulating layer (GI2) and the second storage electrode (STE2). The interlayer insulating layer (ILD) may be an inorganic insulating layer including an inorganic material. For example, the interlayer insulating layer (ILD) may be silicon nitride (SiNx) or silicon oxide (SiO2). x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (AlO x It may include at least one of metal oxides such as ). The present invention is not limited thereto, and according to an embodiment, the interlayer insulating layer (ILD) may be an organic insulating layer including an organic material.

[0171] The first source electrode (SE1) and the first drain electrode (DE1) may be located on the interlayer insulating layer (ILD). The first source electrode (SE1) may be electrically and / or physically connected to the source region of the first semiconductor pattern (ACT1) through a contact hole penetrating the interlayer insulating layer (ILD), the second gate insulating layer (GI2), and the first gate insulating layer (GI1), and the first drain electrode (DE1) may be electrically and / or physically connected to the drain region of the first semiconductor pattern (ACT1) through a contact hole penetrating the interlayer insulating layer (ILD), the second gate insulating layer (GI2), and the first gate insulating layer (GI1). The first drain electrode (DE1) may be electrically and / or physically connected to the first bridge electrode (BRD1) described later. For example, the first source electrode (SE1) and the first drain electrode (DE1) may comprise a single layer structure made of a single or a mixture of selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag) and alloys thereof, and may be a double layer or triple layer structure further comprising molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag).

[0172] A first via layer (VIA1) may be located on a first source electrode (SE1) and a first drain electrode (DE1). The first via layer (VIA1) may include at least one organic insulating layer. The first via layer (VIA1) may be composed of a single layer or multiple layers and may include an inorganic insulating material and an organic insulating material. For example, the first via layer (VIA1) may include at least one of an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0173] The first front insulating layer (FIN1) may be located on the first via layer (VIA1). The first front insulating layer (FIN1) may be an inorganic insulating layer including an inorganic material. For example, the first front insulating layer (FIN1) may be silicon nitride (SiNx) or silicon oxide (SiO2). x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (AlO x It may include at least one of metal oxides such as ). The present invention is not limited thereto, and according to an embodiment, the first front insulating layer (FIN1) may be an organic insulating layer including an organic material.

[0174] The first bridge electrode (BRD1) and the first data electrode (SD1) may be located on the first front insulating layer (FIN1). The first bridge electrode (BRD1) may be electrically and / or physically connected to the first drain electrode (DE1) through a contact hole formed on the first front insulating layer (FIN1) and the first via layer (VIA1). For example, the first data electrode (SD1) may correspond to a data line, a driving voltage line, a driving low voltage line, etc. The first bridge electrode (BRD1) and the first data electrode (SD1) may comprise a single layer structure composed of a single or a mixture thereof selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag) and alloys thereof, and may be a double layer or triple layer structure further comprising molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag).

[0175] A second via layer (VIA2) may be located on a first front insulating layer (FIN1), a first bridge electrode (BRD1), and a first data electrode (SD1). The second via layer (VIA2) may include at least one organic insulating layer. The second via layer (VIA2) may be composed of a single layer or multiple layers and may include an inorganic insulating material or an organic insulating material. For example, the second via layer (VIA2) may include at least one of an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0176] The second front insulating layer (FIN2) may be located on the second via layer (VIA2). The second front insulating layer (FIN2) may be an inorganic insulating layer including an inorganic material. For example, the second front insulating layer (FIN2) may be silicon nitride (SiNx) or silicon oxide (SiO2). x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (AlO x It may include at least one of metal oxides such as ). The present invention is not limited thereto, and according to an embodiment, the second front insulating layer (FIN2) may be an organic insulating layer including an organic material.

[0177] The second bridge electrode (BRD2) and the second data electrode (SD2) may be located on the second front insulating layer (FIN2). The second bridge electrode (BRD2) may be electrically and / or physically connected to the first bridge electrode (BRD1) through a contact hole formed on the second front insulating layer (FIN2) and the second via layer (VIA2). For example, the second data electrode (SD2) may correspond to a data line, a driving voltage line, a driving low voltage line, etc. The second bridge electrode (BRD2) and the second data electrode (SD2) may comprise a single layer structure composed of a single or a mixture thereof selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag) and alloys thereof, and may be a double layer or triple layer structure further comprising molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag).

[0178] A third via layer (VIA3) may be located on a second front insulating layer (FIN2), a second bridge electrode (BRD2), and a second data electrode (SD2). The third via layer (VIA3) may include at least one organic insulating layer. The third via layer (VIA3) may be composed of a single layer or multiple layers and may include an inorganic insulating material or an organic insulating material. For example, the third via layer (VIA3) may include at least one of an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0179] The third front insulating layer (FIN3) may be located on the third via layer (VIA3). The third front insulating layer (FIN3) may be an inorganic insulating layer including an inorganic material. For example, the third front insulating layer (FIN3) may be silicon nitride (SiNx) or silicon oxide (SiO2). x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (AlO x It may include at least one of metal oxides such as ). The present invention is not limited thereto, and according to an embodiment, the third front insulating layer (FIN3) may be an organic insulating layer including an organic material.

[0180] The first pixel electrode (PDE1) is located on the third front insulating layer (FIN3) and can come into contact with the upper surface of the second bridge electrode (BRD2) exposed by the third front insulating layer (FIN3) and the third via layer (VIA3). Accordingly, the first pixel electrode (PDE1) can be electrically and / or physically connected to the second bridge electrode (BRD2) and can be electrically connected to the first drain electrode (DE1) through the second bridge electrode (BRD2) and the first bridge electrode (BRD1). The first pixel electrode (PDE1) can be electrically connected to the first electrode (EL1, see FIG. 15) of the light-emitting element (LD) through a bump (not shown).

[0181] The second pixel electrode (PDE2) may be located on the third front insulating layer (FIN3). The second pixel electrode (PDE2) and the first pixel electrode (PDE1) may comprise a single-layer structure composed of a single or a mixture thereof selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, and may be a double-layer or triple-layer structure further comprising molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag). The second pixel electrode (PDE2) may be electrically connected to the second electrode (EL2, see FIG. 15) of the light-emitting element (LD) through a bump (not shown).

[0182] A first contact electrode (CNE1) may be positioned on the first pixel electrode (PDE1) to cover the first pixel electrode (PDE1). A second contact electrode (CNE2) may be positioned on the second pixel electrode (PDE2) to cover the second pixel electrode (PDE2). The first contact electrode (CNE1) and the second contact electrode (CNE2) may include a transparent conductive oxide. For example, the first contact electrode (CNE1) and the second contact electrode (CNE2) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc.

[0183] The fourth via layer (VIA4) may be located on a portion of the third front insulating layer (FIN3). The fourth via layer (VIA4) may expose the upper surface of the first contact electrode (CNE1) and the upper surface of the second contact electrode (CNE2). The fourth via layer (VIA4) may be composed of a single layer or multiple layers and may include an inorganic insulating material or an organic insulating material. For example, the fourth via layer (VIA4) may include at least one of an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0184] The fourth front insulating layer (FIN4) may be positioned on the fourth via layer (VIA4), the first contact electrode (CNE1), and the second contact electrode (CNE2). The fourth front insulating layer (FIN4) may be positioned to expose a portion of the upper surface of the first contact electrode (CNE1) and a portion of the upper surface of the second contact electrode (CNE2). The exposed portion of the upper surface of the first contact electrode (CNE1) may be electrically connected to the first electrode (EL1) of the light-emitting element (LD) by a bump, and the exposed portion of the upper surface of the second contact electrode (CNE2) may be electrically connected to the second electrode (EL2) of the light-emitting element (LD) by a bump.

[0185] The back wiring layer (RLL) may include a back wiring (RL) located on the second surface (SF2) of the base layer (BSL), a back pad electrode (RPD), a first insulating layer (INS1), a second insulating layer (INS2), and a back via layer (RVIA). According to an embodiment, a flattening layer (PLL) described with reference to FIG. 7 may be disposed between the base layer (BSL) and the first insulating layer (INS1).

[0186] The back wiring (RL), back pad electrode (RPD), and first insulating layer (INS1) constituting the back wiring layer (RLL) are identical to the configuration described with reference to FIG. 7, so the description below is omitted.

[0187] The back via layer (RVIA) is located on the first insulating layer (INS1) and may be positioned to cover the back wiring (RL) and the back pad electrode (RPD). The back via layer (RVIA) may be positioned to cover the back pad electrode (RPD) so as to expose at least a portion of the upper surface of the back pad electrode (RPD). The back via layer (RVIA) may be composed of a single layer or multiple layers and may include an inorganic insulating material and an organic insulating material. For example, the back via layer (RVIA) may include at least one of an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0188] The second insulating layer (INS2) may be positioned to cover the back via layer (RVIA) and to cover a portion of the back pad electrode (RPD). The second insulating layer (INS2) may cover the back pad electrode (RPD) so as to expose at least a portion of the upper surface of the back pad electrode (RPD).

[0189] Below, we will examine the structure of the display device with reference to FIGS. 17 and FIGS. 18.

[0190] FIG. 17 is a cross-sectional view schematically illustrating a part of the non-display area of ​​a display device according to one embodiment, and FIG. 18 is a cross-sectional view schematically illustrating the display area and the non-display area of ​​a display device according to one embodiment.

[0191] Referring to FIG. 17, a display device according to one embodiment may include a front wiring layer (FLL) and a back wiring layer (RLL) located on a base layer (BSL). Unlike the back wiring layer (RLL) shown in FIG. 16, the back wiring layer (RLL) shown in FIG. 17 is illustrated with a non-display area as the center, and may include a configuration identical or similar to the back wiring layer (RLL) of FIG. 16. Additionally, the description regarding the parts of the configuration shown in FIG. 17 that are identical to the configuration of FIG. 16 will be brief.

[0192] The front wiring layer (FLL) may include a buffer layer (BFL), a front wiring (FL), a front pad electrode (FPD), and a plurality of insulating layers (GI1, GI2, VIA1, VIA2, VIA3, FIN1, FIN2, FIN3, FIN4) located on the first surface (SF1) of the base layer (BSL).

[0193] The buffer layer (BFL) is located on the base layer (BSL) and may be an inorganic insulating layer containing an inorganic material.

[0194] The first gate insulating layer (GI1) is located on the buffer layer (BFL) and can cover at least a portion of the upper surface of the buffer layer (BFL). The first gate insulating layer (GI1) may be an inorganic insulating layer including an inorganic material.

[0195] The second gate insulating layer (GI2) is located on the first gate insulating layer (GI1) and can cover a portion of the upper surface of the buffer layer (BFL) together with the first gate insulating layer (GI1). The second gate insulating layer (GI2) may be an inorganic insulating layer containing an inorganic material.

[0196] The first via layer (VIA1) may be located on a portion of the second gate insulating layer (GI2) and may include at least one organic insulating layer.

[0197] The first front insulating layer (FIN1) may be positioned on the first via layer (VIA1) to cover the first via layer (VIA1). The first front insulating layer (FIN1) may be an inorganic insulating layer including an inorganic material.

[0198] The second via layer (VIA2) may be located on a portion of the first front insulating layer (FIN1) and may include at least one organic insulating layer.

[0199] The second front insulating layer (FIN2) may be located on the second via layer (VIA2) and the first front insulating layer (FIN1) so as to cover the second via layer (VIA2) and the first front insulating layer (FIN1). The second front insulating layer (FIN2) may be an inorganic insulating layer including an inorganic material.

[0200] The third via layer (VIA3) may be located on a portion of the second front insulating layer (FIN2) and may include at least one organic insulating layer.

[0201] The third front insulating layer (FIN3) may be located on the third via layer (VIA3) and the second front insulating layer (FIN2) to cover the third via layer (VIA3) and the second front insulating layer (FIN2). The third front insulating layer (FIN3) may be an inorganic insulating layer including an inorganic material.

[0202] The front wiring (FL) may be located on the second gate insulating layer (GI2) and / or the third front insulating layer (FIN3). The front wiring (FL) may correspond to data lines, gate lines, driving voltage lines, driving low voltage lines, pad wiring, etc. provided in the non-display area (NDA). The front wiring (FL) may comprise a single-layer structure consisting of a single or a mixture thereof selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, and may be a double-layer or triple-layer structure further comprising molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag).

[0203] The front pad electrode (FPD) may be positioned on the front wiring (FL) to cover the front wiring (FL). The front pad electrode (FPD) may include a transparent conductive oxide. For example, the front pad electrode (FPD) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc.

[0204] The fourth front insulating layer (FIN4) may be positioned on the front pad electrode (FPD), the third front insulating layer (FIN3), and the second gate insulating layer (GI2) to cover the front pad electrode (FPD), the third front insulating layer (FIN3), and the second gate insulating layer (GI2). The fourth front insulating layer (FIN4) may cover the front pad electrode (FPD) such that at least a portion of the upper surface of the front pad electrode (FPD) is exposed. The fourth front insulating layer (FIN4) may be an inorganic insulating layer comprising an inorganic material.

[0205] The back wiring layer (RLL) may include a first insulating layer (INS1), back wiring (RL), back pad electrode (RPD), back via layer (RVIA), and a second insulating layer (INS2) located on the second surface (SF2) of the base layer (BSL). According to an embodiment, a flattening layer (PLL) described with reference to FIG. 7 may be disposed between the base layer (BSL) and the first insulating layer (INS1).

[0206] The first insulating layer (INS1) can be located on a part of the base layer (BSL).

[0207] The back wiring (RL) may be positioned on a portion of the first insulating layer (INS1). The back pad electrode (RPD) may be positioned to cover the back wiring (RL), the first insulating layer (INS1), and the base layer (BSL), so as to cover at least a portion of the back wiring (RL), at least a portion of the first insulating layer (INS1), and a portion of the base layer (BSL).

[0208] The back via layer (RVIA) is located on the back wiring (RL) and can be positioned to cover at least a portion of the back wiring (RL) and the back pad electrode (RPD).

[0209] The second insulating layer (INS2) is located on the back via layer (RVIA) and can be positioned to cover a portion of the back via layer (RVIA) and the back pad electrode (RPD).

[0210] Referring to FIG. 18, a display device according to one embodiment may include wiring (SL) for electrically connecting wiring, pad electrodes, etc. located on a first surface (SF1) and a second surface (SF2) of a base layer (BSL), and may further include an overcoat layer (OC) for protecting wiring, pad electrodes, etc. in a non-display area (NDA). Here, a front wiring layer (FLL) and a back wiring layer (RLL) described with reference to FIG. 17 may be located in the non-display area (NDA), and a pixel circuit layer (PCL), etc. described with reference to FIG. 16 may be located in the display area (DA).

[0211] The wiring (SL) can be positioned to cover the first surface (SF1) and the second surface (SF2) of the base layer (BSL) and one side of the base layer (BSL). Accordingly, the wiring (SL) can electrically connect the front wiring, front pad electrode, etc. placed on the first surface (SF1) to the back wiring, back pad electrode, etc. placed on the second surface (SF2).

[0212] The overcoat layer (OC) may be positioned to cover the wiring (SL) and cover the first surface (SF1) and the second surface (SF2) of the base layer (BSL) and one side of the base layer (BSL). The overcoat layer (OC) may include organic materials such as polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimide resin, unsaturated polyesters resin, polyphenylene ethers resin, polyphenylene sulfides resin, and benzocyclobutene resin.

[0213] Hereinafter, with reference to FIG. 19, we will examine another structure of a display device according to one embodiment.

[0214] FIG. 19 is a cross-sectional view of a display device according to one embodiment.

[0215] Referring to FIG. 19, a display device according to one embodiment may include a base layer (BSL), a first insulating layer (INS1), a back wiring (RL), a back pad electrode (RPD), and a second insulating layer (INS2). Since the display device illustrated in FIG. 19 is similar to the display device illustrated in FIG. 7, the differences will be described below.

[0216] On the first surface (SF1) of the base layer (BSL), the aforementioned pixel circuit layer (PCL, see FIG. 16) and display element layer, etc., may be located.

[0217] A first insulating layer (INS1) may be located on the second surface (SF2) of the base layer (BSL). The first insulating layer (INS1) may cover the entire second surface (SF2) of the base layer (BSL).

[0218] The first insulating layer (INS1) may be an inorganic insulating layer comprising an inorganic material (or material). Additionally, the first insulating layer (INS1) may include a transparent inorganic insulating material to align wiring, etc.

[0219] Back wiring (RL) may be located on the first insulating layer (INS1).

[0220] A back pad electrode (RPD) may be located on the back wiring (RL). The back pad electrode (RPD) may be located on the back wiring (RL) and the first insulating layer (INS1) to cover the back wiring (RL).

[0221] A second insulating layer (INS2) may be positioned on the back pad electrode (RPD). The second insulating layer (INS2) may cover the back pad electrode (RPD) to expose at least a portion of the upper surface of the back pad electrode (RPD) and may cover the first insulating layer (INS1). A circuit board, etc., may be attached to the upper surface of the back pad electrode (RPD) exposed by the second insulating layer (INS2).

[0222] The second insulating layer (INS2) may be an inorganic insulating layer containing an inorganic material.

[0223] Hereinafter, with reference to FIGS. 20 to 22, we will examine the configuration of a display device, the structure of a pixel, and a driving method according to one embodiment.

[0224] FIG. 20 is a block diagram briefly illustrating the configuration of a display device according to one embodiment, FIG. 21 is a diagram briefly illustrating a pixel circuit of a display device according to one embodiment, and FIG. 22 is a circuit diagram illustrating a pixel circuit of a display device according to one embodiment.

[0225] Referring to FIG. 20, a display device according to one embodiment may include a display panel (DP) and a driving unit (DRV) for driving the display panel (DP).

[0226] The display panel (DP) may include a pixel circuit (PXC) and a light-emitting element (LD), and the pixel circuit (PXC) may be composed of elements of the pixel circuit layer (PCL) described with reference to FIG. 16.

[0227] The pixel circuit (PXC) can provide a driving current to the light-emitting element (LD). Specifically, the pixel circuit (PXC) can provide a driving current to the light-emitting element (LD) with a controlled magnitude and driving time based on a data voltage (e.g., VPAM_RGB, DATA_PWM), a driving voltage (e.g., VDD1, VDD2), and various control signals applied from the driver (DRV). Accordingly, the light-emitting element (LD) can express different brightness grayscale values ​​depending on the magnitude of the driving current or the pulse width of the driving current provided by the pixel circuit (PXC). That is, the pixel circuit (PXC) can control the brightness of the light emitted by the light-emitting element (LD) by driving the light-emitting element (LD) using Pulse Amplified Modulation (PAM) and / or Pulse Width Modulation (PWM). Here, the light-emitting element (LD) may correspond to the light-emitting element shown in FIGS. 12 and 13, and may also correspond to the light-emitting element shown in FIG. 15.

[0228] The pixel circuit (PXC) may include a first circuit (CIC1) for providing a constant current of a predetermined size to a light-emitting element (LD) based on a PAM voltage (VPAM_RGB), and a second circuit (CIC2) for providing the constant current provided by the first circuit (CIC1) to the light-emitting element (LD) for a time corresponding to an applied PWM voltage (DATA_PWM).

[0229] The driving unit (DRV) can apply a PWM voltage (DATA_PWM) corresponding to the grayscale value of each pixel to the second circuit (CIC2) of the display panel (DP). Accordingly, the driving time of the driving current (i.e., constant current) provided to the light-emitting element (LD) of each pixel through the second circuit (CIC2) can be controlled. Accordingly, various grayscale levels of the image of the display device can be implemented. In each display device (or display panel) constituting the plurality of display devices described with reference to FIG. 1, the same PAM voltage (VPAM_RGB) can be applied, and PAM voltages (VPAM_RGB) of different sizes can be applied.

[0230] Referring to FIG. 21, a pixel circuit (PXC) according to one embodiment may include a first circuit (CIC1), a second circuit (CIC2), a 15th transistor (T15) (or a first switching transistor), a 14th transistor (T14) (or a second switching transistor), and a light-emitting element (LD).

[0231] The first circuit (CIC1) can provide a constant current of a constant magnitude to the light-emitting element (LD). Additionally, the first circuit (CIC1) may include a compensation transistor to compensate for the threshold voltage of the driving transistor included in the first circuit (CIC1). Accordingly, the first circuit (CIC1) can provide a driving current of a magnitude corresponding to the PAM voltage (VPAM_RGB) to the light-emitting element (LD), regardless of the threshold voltage of the driving transistor.

[0232] The second circuit (CIC2) can control the turn-on and turn-off operation of the 15th transistor (T15) to control the time during which a constant current flows to the light-emitting element (LD). The second circuit (CIC2) may include a compensation transistor to compensate for the threshold voltage of the driving transistor included in the second circuit (CIC1). Additionally, the second circuit (CIC2) can change the gate voltage of the driving transistor according to the applied sweep voltage (SWEEP[n]). Accordingly, the second circuit (CIC2) can provide a driving current of a magnitude corresponding to the PWM voltage (DATA_PWM) to the light-emitting element (LD) regardless of the threshold voltage of the driving transistor. Additionally, the second circuit (CIC2) can control the turn-on and turn-off timing of the 15th transistor (T15) by changing the gate voltage of the 15th transistor (T15) described later.

[0233] The 15th transistor (T15) can be turned on and off according to a control signal of the driving unit (DRV). More specifically, the driving timing of the 15th transistor (T15) can be controlled by a driving current by the second circuit (CIC2). The turn-on and turn-off timing of the 15th transistor (T15) may be related to the implementation of a black gradation.

[0234] Referring to FIG. 22, a pixel circuit (PXC) according to one embodiment may include a first circuit (CIC1), a second circuit (CIC2), a 15th transistor (T15), a 14th transistor (T14), a 19th transistor (T19), and a light-emitting element (LD).

[0235] First, the second circuit (CIC2) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), and a first capacitor (C1).

[0236] The first transistor (T1) may include a first electrode connected to a first node (N1), a second electrode connected to a second node (N2), and a gate electrode connected to a third node (N3). The first transistor (T1) may be a driving transistor of the second circuit (CIC2).

[0237] The second transistor (T2) may include a first electrode connected to a PWM voltage (DATA_PWM), a second electrode connected to a first node (N1), and a gate electrode connected to a first gate line (GW[n]). As the second transistor (T2) is turned on, a PWM voltage (DATA_PWM) may be supplied to the first node (N1).

[0238] The third transistor (T3) may include two transistors (T3-1, T3-2) connected in series. The first electrode of the third-1 transistor (T3-1) may be connected to the third node (N3), and the second electrode of the third-2 transistor (T3-2) may be connected to the second node (N2). The second electrode of the third-1 transistor (T3-1) may be connected to the first electrode of the third-2 transistor (T3-2). The gate electrode of the third-1 transistor (T3-1) and the gate electrode of the third-2 transistor (T3-2) may be connected to the first gate line (GW[n]).

[0239] The fourth transistor (T4) may include two transistors (T4-1, T4-2) connected in series. The first electrode of the fourth-1 transistor (T4-1) may be connected to the third node (N3), and the second electrode of the fourth-2 transistor (T4-2) may be connected to the initialization voltage (Vint). The second electrode of the fourth-1 transistor (T4-1) may be connected to the first electrode of the fourth-2 transistor (T4-2). The gate electrode of the fourth-1 transistor (T4-1) and the gate electrode of the fourth-2 transistor (T4-2) may be connected to the second gate line (GI[n]).

[0240] The fifth transistor (T5) may include a first electrode connected to a second driving voltage (VDD2), a second electrode connected to a first node (N1), and a gate electrode connected to a light-emitting PWM line (EM_PWM[n]).

[0241] The sixth transistor (T6) may include a first electrode connected to the second node (N2), a second electrode connected to the fourth node (N4), and a gate electrode connected to the light-emitting PWM line (EM_PWM[n]).

[0242] The seventh transistor (T7) may include two transistors (T7-1, T7-2) connected in series. The first electrode of the seventh-1 transistor (T7-1) may be connected to the fourth node (N4), and the second electrode of the seventh-2 transistor (T7-2) may be connected to the initialization power supply (Vint). The second electrode of the seventh-1 transistor (T7-1) may be connected to the first electrode of the seventh-2 transistor (T7-2). The gate electrode of the seventh-1 transistor (T7-1) and the gate electrode of the seventh-2 transistor (T7-2) may be connected to the third gate line (GI2[n]).

[0243] The eighth transistor (T8) may include a first electrode connected to the fifth node (N5), a second electrode connected to a reference voltage (VGH), and a gate electrode connected to a sweep voltage (SWEEP[n]).

[0244] The first capacitor (C1) may include a first electrode connected to the fifth node (N5) and a second electrode connected to the third node (N3). The first capacitor (C1) may change the voltage of the third node (N3) according to a change in the sweep voltage (SWEEP[n]).

[0245] The first circuit (CIC1) may include a ninth transistor (T9), a tenth transistor (T10), an eleventh transistor (T11), a twelfth transistor (T12), a thirteenth transistor (T13), a sixteenth transistor (T16), a seventeenth transistor (T17), an eighteenth transistor (T18), a second capacitor (C2), and a third capacitor (C3).

[0246] The ninth transistor (T9) may include a first electrode connected to the sixth node (N6), a second electrode connected to the seventh node (N7), and a gate electrode connected to the eighth node (N8). The ninth transistor (T9) may be a driving transistor of the first circuit (CIC1).

[0247] The 10th transistor (T10) may include a first electrode connected to a PAM voltage (VPAM_RGB), a second electrode connected to a 6th node (N6), and a gate electrode connected to a 1st gate line (GW[n]). As the 10th transistor (T10) is turned on, a PAM voltage (VPAM_RGB) may be supplied to the 6th node (N6).

[0248] The eleventh transistor (T11) may include two transistors (T11-1, T11-2) connected in series. The first electrode of the eleventh-1 transistor (T11-1) may be connected to the eighth node (N8), and the second electrode of the eleventh-2 transistor (T11-2) may be connected to the seventh node (N7). The second electrode of the eleventh-1 transistor (T11-1) may be connected to the first electrode of the eleventh-2 transistor (T11-2). The gate electrode of the eleventh-1 transistor (T11-1) and the gate electrode of the eleventh-2 transistor (T11-2) may be connected to the first gate line (GW[n]).

[0249] The 12th transistor (T12) may include two transistors (T12-1, T12-2) connected in series. The first electrode of the 12-1 transistor (T12-1) may be connected to the 8th node (N8), and the second electrode of the 12-2 transistor (T12-2) may be connected to the 9th node (N9). The second electrode of the 12-1 transistor (T12-1) may be connected to the first electrode of the 12-2 transistor (T12-2). The gate electrode of the 12-1 transistor (T12-1) and the gate electrode of the 12-2 transistor (T12-2) may be connected to the second gate line (GI[n]).

[0250] The 13th transistor (T13) may include a first electrode connected to a first driving voltage (VDD1), a second electrode connected to a sixth node (N6), and a gate electrode connected to a light-emitting PWM line (EM_PWM[n]).

[0251] The 16th transistor (T16) may include a first electrode connected to the 10th node (N10), a second electrode connected to the first driving voltage (VDD1), and a gate electrode connected to the light-emitting PWM line (EM_PWM[n]).

[0252] The 17th transistor (T17) may include a first electrode connected to a second driving voltage (VDD2), a second electrode connected to a 10th node (N10), and a gate electrode connected to a third gate line (GI2[n]).

[0253] The 18th transistor (T18) may include a first electrode connected to the 9th node (N9), a second electrode connected to the 10th node (N10), and a gate electrode connected to the third gate line (GI2[n]).

[0254] The second capacitor (C2) may include a first electrode connected to the 10th node (N10) and a second electrode connected to the 8th node (N8).

[0255] The third capacitor (C3) may include a first electrode connected to the fourth node (N4) and a second electrode connected to the initialization voltage (Vint).

[0256] The 19th transistor (T19) may include a first electrode connected to the 11th node (N11), a second electrode connected to the driving low voltage (VSS), and a gate electrode connected to the test line (TEST). The 19th transistor (T19) is a transistor that is turned on according to the test voltage before the light-emitting element (LD) is electrically connected to the pixel circuit (PXC), so as to check for abnormalities in the pixel circuit (PXC).

[0257] A brief overview of the driving method of the pixel circuit (PXC) is as follows.

[0258] First, when a turn-on voltage (logic low level) is applied through the third gate line (GI2[n]), the seventh transistor (T7), the eighth transistor (T8), the seventh transistor (T17), and the eighth transistor (T18) can be turned on. Accordingly, an initialization voltage (Vint) can be applied to the fourth node (N4) and the ninth node (N9), a reference voltage (VGH) can be applied to the fifth node (N5), and a second driving voltage (VDD2) can be applied to the tenth node (N10). Here, the anode of the light-emitting element (LD) can be initialized with the initialization voltage (Vint).

[0259] After a turn-on voltage is applied to the third gate line (GI2[n]), when a turn-on voltage (logic low level) is applied through the first gate line (GW[n]), the second transistor (T2), the third transistor (T3), the tenth transistor (T10), and the eleventh transistor (T11) can be turned on. Accordingly, a PWM voltage (DATA_PWM) is applied to the first node (N1), and the voltage difference between the first node (N1) and the second node (N2) is set to be smaller than the threshold voltage of the first transistor (T1), so that the first transistor (T1) can be turned on. A PAM voltage (VPAM_RGB) is applied to the sixth node (N6), and the voltage difference between the eighth node (N8) and the seventh node (N7) is set to be smaller than the threshold voltage of the ninth transistor (T9), so that the ninth transistor (T9) can be turned on.

[0260] When a turn-on voltage (logic low level) is applied through the second gate line (GI[n]), the fourth transistor (T4) can be turned on, and an initialization voltage (Vint) can be supplied to the third node (N3). The time at which the turn-on voltage is applied to the second gate line (GI[n]) may be later than or the same as the time at which the turn-on voltage is applied to the first gate line (GW[n]).

[0261] Subsequently, when a turn-on voltage (logic low level) is applied to the light-emitting PWM line (EM_PWM[n]), the fifth transistor (T5), the sixth transistor (T6), the thirteenth transistor (T13), and the sixteenth transistor (T16) can be turned on. Accordingly, in the second circuit (CIC2), a current corresponding to the second driving voltage (VDD2) can be supplied to the fourth node (N4), and in the first circuit (CIC1), a current corresponding to the first driving voltage (VDD1) can be applied to the seventh node (N7).

[0262] When a turn-on voltage (logic low level) is applied to the light-emitting PAM line (EM_PAM[n]), the 14th transistor (T14) can be turned on. At this time, when the voltage difference between the 4th node (N4) and the 1st electrode of the 14th transistor (T14) is set lower than the threshold voltage of the 15th transistor (T15), the 15th transistor (T15) can be turned on. Accordingly, a driving current (or constant current) through the 1st circuit (CIC1) can flow to the light-emitting element (LD), and the light-emitting element (LD) can emit light corresponding to the magnitude of the driving current.

[0263] When a turn-on voltage is applied to the light-emitting PWM line (EM_PWM[n]), the sweep voltage (SWEEP[n]) can be reduced linearly for a predetermined period. Accordingly, the voltage of the third node (N3) can be reduced, and the voltage supplied to the fourth node (N4) can correspond to the PWM voltage (DATA_PWM). Depending on the magnitude of the PWM voltage (DATA_PWM), the voltage supplied to the fourth node (N4) can be changed, and if the PWM voltage (DATA_PWM) increases, the voltage of the fourth node (N4) can be increased, and the 15th transistor (T15) can be turned off by the voltage change of the fourth node (N4). That is, the second circuit (CIC2) can control the turn-on and turn-off of the 15th transistor (T15) by changing the gate voltage of the 15th transistor (T15). When the 15th transistor (T15) is turned off, no driving current flows through the light-emitting element (LD). Accordingly, since the light-emitting element (LD) does not emit light, the second circuit (CIC2) can control the light-emitting time of the light-emitting element (LD). That is, the pixel circuit (PXC) can control the light-emitting time of the light-emitting element (LD) by controlling the operating time of the 15th transistor (T15), and can improve the grayscale expression.

[0264] In one embodiment, the pixel circuit (PXC) is described as being driven by Pulse Amplified Modulation (PAM) and Pulse Width Modulation (PWM); however, depending on the embodiment, the pixel circuit (PXC) may be driven only by PAM or PWM.

[0265] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0266] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0267] BSL: Base layer PCL: Pixel circuit layer DPL: Display layer CVL: Cover layer RL: Back wiring RPD: Back pad electrode PLL: Flattening layer INS1: First insulating layer INS2: Second insulation layer LD: Light-emitting element

Claims

Claim 1 A display device comprising: a base layer including a first surface and a second surface opposite to the first surface; a pixel circuit layer located on the first surface; a display element layer located on the pixel circuit layer; a first insulating layer located on the second surface; a second insulating layer located on the first insulating layer; a flattening layer located between the second surface and the first insulating layer; a back wiring located between the first insulating layer and the second insulating layer; and a back pad electrode located between the back wiring and the second insulating layer, wherein the flattening layer comprises an organic material and the back pad electrode covers the side wall of the back wiring. Claim 2 delete Claim 3 In claim 1, the first insulating layer comprises a transparent inorganic insulating material in a display device. Claim 4 In claim 1, the base layer is a rigid substrate in the display device. Claim 5 In claim 1, the back wiring is a display device extending in a first direction on the second surface. Claim 6 In paragraph 5, the back pad electrode is a display device that covers the back wiring so as to overlap at least a portion with the back wiring. Claim 7 In claim 6, the back pad electrode is a display device comprising a transparent conductive oxide. Claim 8 delete Claim 9 In claim 1, the pixel circuit layer comprises a first transistor located on the first surface, in a display device. Claim 10 A display device according to claim 1, wherein the display element layer comprises a light-emitting element, and the light-emitting element comprises: a first semiconductor layer; a second semiconductor layer different from the first semiconductor layer; and an active layer located between the first semiconductor layer and the second semiconductor layer. Claim 11 A method for manufacturing a display device comprising: a step of preparing a base layer including a first surface and a second surface opposite to the first surface; a step of forming a pixel circuit layer and a display element layer on the first surface; a step of forming a planarization layer on the second surface; a step of forming a first insulating layer on the planarization layer; a step of forming a back wiring and a back pad electrode on the first insulating layer; and a step of forming a second insulating layer on the back wiring and the back pad electrode, wherein the planarization layer is formed with an organic material and the back pad electrode covers the side wall of the back wiring. Claim 12 delete Claim 13 In claim 11, a method for manufacturing a display device in which the first insulating layer is formed with a transparent inorganic insulating material. Claim 14 In claim 11, a method for manufacturing a display device that prepares the base layer, which is a rigid substrate. Claim 15 In claim 11, a method for manufacturing a display device by forming the back pad electrode with a transparent conductive oxide. Claim 16 delete Claim 17 In claim 11, a method for manufacturing a display device that forms the back wiring so as to extend in a first direction on the second surface. Claim 18 In claim 17, a method for manufacturing a display device, wherein the back pad electrode is formed to cover the back wiring by overlapping at least a portion with the back wiring. Claim 19 In claim 11, the step of forming the pixel circuit layer comprises the step of forming a first transistor on the first surface, in a method for manufacturing a display device. Claim 20 In claim 11, the step of forming the display element layer comprises the step of placing a light-emitting element on the pixel circuit layer, a method for manufacturing a display device.

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