Band pass filter circuit and sensor device including the same

Abstract

A bandpass filter circuit comprises: an amplifier circuit having first and second input terminals for receiving first and second analog signals, and first and second output terminals; and a plurality of capacitors and switches connected to the plurality of capacitors. When at least some of the plurality of capacitors are provided as a first group of capacitors connected between the first and second input terminals and the first and second output terminals by controlling the switches, the amplifier circuit and the first group of capacitors operate as a first bandpass filter. When at least some of the plurality of capacitors are provided as a second group of capacitors connected between the first input terminal and the first output terminal and a third group of capacitors connected between the second input terminal and the second output terminal by controlling the switches, the amplifier circuit, the second group of capacitors, and the third group of capacitors operate as second bandpass filters.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a band-pass filter circuit and a sensor device including the same. Background Technology

[0002] With the advancement of information technology, the importance of display devices, which serve as a medium connecting users and information, is being highlighted. In response to this, the use of display devices such as Liquid Crystal Displays (LCDs) and Organic Light Emitting Displays (OLEDs) is increasing.

[0003] The display device may include a display device for displaying images and a sensor device for detecting user input. The sensor device may include a band-pass filter for acquiring signals of a desired frequency band from the sensing signals.

[0004] The above description is intended solely to aid in understanding the background technology regarding the technical concepts of the present invention, and therefore, it should not be understood as prior art known to those skilled in the art of the present invention. The problem to be solved

[0005] The applicant recognized that touch input can be detected with enhanced reliability by using different types of bandpass filters depending on the type of object providing touch input in the sensor device.

[0006] A band-pass filter circuit according to an embodiment of the present invention and a sensor device including the same can provide different types of band-pass filters with a reduced area. For example, the band-pass filter circuit can support two types of band-pass filters, and the two types of band-pass filters may share one or more of the capacitors included in the band-pass filter circuit. Accordingly, the two types of band-pass filters can have a reduced area. means of solving the problem

[0007] A band-pass filter circuit according to an embodiment of the present invention comprises: an amplifier circuit having a first input terminal for receiving a first analog signal, a second input terminal for receiving a second analog signal, and first and second output terminals; and a plurality of capacitors and switches connected to the plurality of capacitors. When at least some of the plurality of capacitors are provided as a first group of capacitors connected between the first and second input terminals and the first and second output terminals by controlling the switches, the amplifier circuit and the first group of capacitors operate as a first band-pass filter that filters the first and second analog signals in a differential mode. When at least some of the plurality of capacitors are provided as a second group of capacitors connected between the first input terminal and the first output terminal and a third group of capacitors connected between the second input terminal and the second output terminal by controlling the switches, the amplifier circuit, the second group of capacitors, and the third group of capacitors operate as second bandpass filters that filter each of the first and second analog signals in a single-ended mode.

[0008] The second bandpass filters may share one or more of the plurality of capacitors with the first bandpass filter.

[0009] At least one of the capacitors in the second group and at least one of the capacitors in the third group may be included in the capacitors in the first group.

[0010] The amplifier circuit and the capacitors of the second group may be configured to be included in one of the second bandpass filters to filter the first analog signal, and the amplifier circuit and the capacitors of the third group may be configured to be included in another of the second bandpass filters to filter the second analog signal.

[0011] The amplifier circuit may include the first input terminal as an inverting input terminal, the second input terminal as a non-inverting input terminal, the first output terminal as a non-inverting output terminal, and the second output terminal as an inverting output terminal.

[0012] The plurality of capacitors may include a first gain capacitor connected between the first input terminal and the first output terminal; and a second gain capacitor connected between the second input terminal and the second output terminal.

[0013] It may further include first input capacitors connected in series to the first input terminal; and second input capacitors connected in series to the second input terminal, wherein the first analog signal may be transmitted to the first input terminal through the first input capacitors, and the second analog signal may be transmitted to the second input terminal through the second input capacitors.

[0014] In the second bandpass filter above, each of the first and second capacitors among the second group of capacitors may be configured to alternately perform integration over the first analog signal to output a first sampling signal. When performing integration over the first analog signal, the first capacitor may be configured to be connected to the second capacitor through a first connection node to perform integration over the charges of the second capacitor together with the first analog signal to output the first sampling signal.

[0015] In the second bandpass filter above, the second capacitor may be configured to output the first sampling signal by being connected to the first capacitor through the first connection node when performing integration with the first analog signal, thereby performing integration with the charges of the first capacitor together with the first analog signal.

[0016] In the second bandpass filter above, each of the third and fourth capacitors among the third group of capacitors may be configured to alternately perform integration over the second analog signal to output a second sampling signal. When performing integration over the second analog signal, the third capacitor may be configured to be connected to the fourth capacitor through a second connection node to perform integration over the charges of the fourth capacitor together with the second analog signal to output the second sampling signal.

[0017] In the second bandpass filter above, the fourth capacitor may be configured to output the second sampling signal by being connected to the third capacitor through the second connection node when performing integration on the second analog signal, thereby performing integration on the charges of the third capacitor together with the second analog signal.

[0018] In the first bandpass filter above, the first capacitor among the first group of capacitors may be configured to perform integration over the first analog signal and output a first sampling signal through the first output terminal. The second capacitor among the first group of capacitors may be configured to be connected to the first capacitor through a first connection node to store charges of the first capacitor.

[0019] In the first bandpass filter above, when the first capacitor performs integration with respect to the first analog signal, the second capacitor may be connected to the third capacitor among the first group of capacitors through a second connection node. The third capacitor may be configured to perform integration with respect to the charges of the second capacitor together with the second analog signal and output a second sampling signal through the second output terminal.

[0020] Another aspect of the present invention relates to a sensor device. A sensor device according to embodiments of the present invention comprises a sensor array; and a sensor driver comprising a band-pass filter circuit configured to filter first and second analog signals received from the sensor array. The band-pass filter circuit comprises an amplifier circuit having a first input terminal for receiving a first analog signal, a second input terminal for receiving a second analog signal, a first output terminal, and a second output terminal; and a plurality of capacitors and switches connected to the plurality of capacitors. When at least some of the plurality of capacitors are provided as a first group of capacitors connected between the first and second input terminals and the first and second output terminals by controlling the switches, the amplifier circuit and the first group of capacitors operate as a first band-pass filter that filters the first and second analog signals in a differential mode. When at least some of the plurality of capacitors are provided as a second group of capacitors connected between the first input terminal and the first output terminal and a third group of capacitors connected between the second input terminal and the second output terminal by controlling the switches, the amplifier circuit, the second group of capacitors, and the third group of capacitors operate as second bandpass filters that filter each of the first and second analog signals in a single-ended mode.

[0021] The sensor driver can control the switches to operate the band-pass filter circuit as the first band-pass filter to detect touch input of the body based on the first and second analog signals, and can control the switches to operate the band-pass filter circuit as the second band-pass filters to detect touch input of the pen based on the first and second analog signals.

[0022] The second bandpass filters may share one or more of the plurality of capacitors with the first bandpass filter.

[0023] At least one of the capacitors in the second group and at least one of the capacitors in the third group may be included in the capacitors in the first group.

[0024] The amplifier circuit and the second group of capacitors may be configured to be included in one of the second bandpass filters to filter the first analog signal. The amplifier circuit and the third group of capacitors may be configured to be included in the other of the second bandpass filters to filter the second analog signal. Effects of the invention

[0025] According to an embodiment of the present invention, a bandpass filter circuit providing different types of bandpass filters with a reduced area and a sensor device including the same may be provided.

[0026] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0027] FIG. 1 is a block diagram showing an embodiment of a sensor device according to the present invention. FIG. 2 is a block diagram showing an example of any one of the analog shears of FIG. 1. Figures 3 and 4 are diagrams illustrating the advantages of implementing a band-pass filter with high-pass filters. Figure 5 is a block diagram showing an example of the bandpass filter of Figure 2. FIG. 6a is a block diagram showing an example of a bandpass filter operating in a fully differential mode, switched from the bandpass filter of FIG. 5. FIG. 6b is a block diagram showing an example of a bandpass filter operating in a single-ended mode, switched from the bandpass filter of FIG. 5. Figure 7 is a circuit diagram showing an example of the band-pass filter of Figure 5. FIG. 8 is a circuit diagram showing the components forming a band-pass filter operating in full differential mode among the band-pass filter circuits of FIG. 7. FIG. 9 is a circuit diagram showing the components forming a single-ended mode bandpass filter among the bandpass filter circuits of FIG. 7. Figure 10 is a timing diagram showing the signals controlling the bandpass filter of Figure 8. FIGS. 11 and FIGS. 12 are circuit diagrams for explaining the current paths formed in the bandpass filter of FIG. 8 during the first period of FIG. 10. FIGS. 13 and FIGS. 14 are circuit diagrams for explaining the current paths formed in the bandpass filter of FIG. 8 during the second cycle of FIG. 10. Figure 15 is a timing diagram showing the signals controlling the bandpass filter of Figure 9. FIGS. 16 and FIGS. 17 are circuit diagrams for explaining the current paths formed in the bandpass filter of FIG. 9 during the first and fifth time periods of FIG. 15. FIGS. 18 and FIGS. 19 are circuit diagrams for explaining the current paths formed in the bandpass filter of FIG. 9 during the third and seventh time periods of FIG. 15. Specific details for implementing the invention

[0028] Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the present invention are described, and the description of other parts is omitted to avoid obscuring the gist of the present invention. Furthermore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided merely to explain in detail sufficient for a person skilled in the art to easily implement the technical concept of the present invention.

[0029] Throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected," but also cases where they are "indirectly connected" with other elements interposed between them. The terms used herein are intended to describe specific embodiments and are not intended to limit the invention. Throughout the specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes all combinations of one or more of such components.

[0030] Herein, terms such as first, second, etc. may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, the first component may refer to the second component without departing from what is disclosed herein.

[0031] Spatially relative terms, such as "below" and "above," may be used for descriptive purposes to explain the relationship between one element or feature and other element(s) or feature(s) as depicted in the drawings. Spatially relative terms are intended to include different directions during use, operation, and / or manufacturing, in addition to the directions depicted in the drawings. For example, if the device depicted in the drawings is inverted, elements described as being located "below" other elements or features are located in the direction "above" of other elements or features. Thus, in one embodiment, the term "below" may include both directions of up and down. Furthermore, the device may face other directions (e.g., rotated 90 degrees or in other directions), and accordingly, the spatially relative terms used herein are interpreted accordingly.

[0032] FIG. 1 is a block diagram showing an embodiment of a sensor device according to the present invention.

[0033] Referring to FIG. 1, the sensor device (100) may include a sensor array (110) and a sensor driver (120).

[0034] The sensor array (110) may include first sensors (TX1, TX2, TX3, TX4, TX5) and second sensors (RX1, RX2, RX3, RX4). The first sensors (TX1 to TX5) may extend in a first direction (DR1) and be arranged in a second direction (DR2) that intersects the first direction (DR1). The second sensors (RX1 to RX4) may extend in a second direction (DR2) and be arranged in the first direction (DR1). The second sensors (RX1 to RX4) may intersect the first sensors (TX1 to TX5). The first sensors (TX1 to TX5) and the second sensors (RX1 to RX4) may form mutual capacitance. For example, a capacitance (C11) may be formed between the first sensor (TX1) and the second sensor (RX1), and a capacitance (C12) may be formed between the first sensor (TX1) and the second sensor (RX2).

[0035] The sensor driver (120) can detect changes in such capacitances to detect touch input from a user. The sensor driver (120) may include a sensor transmitter (TDC) and a sensor receiver (TSC). The sensor transmitter (TDC) is connected to the first sensors (TX1 to TX5) and can supply driving signals to the first sensors (TX1 to TX5). The sensor transmitter (TDC) may be connected to the first sensors (TX1 to TX5) through the first sensor lines (TXL1, TXL2, TXL3, TXL4, TXL5).

[0036] The sensor receiver (TSC) is connected to the second sensors (RX1 to RX4) and can receive sensing signals from the second sensors (RX1 to RX4). The sensing signals may be analog signals. The sensor receiver (TSC) may be connected to the second sensors (RX1 to RX4) through the second sensor lines (RXL1, RXL2, RXL3, RXL4). The sensor receiver (TSC) may include an analog front-end group (AFEG) and a signal processor (DSP).

[0037] An analog front-end group (AFEG) may include a plurality of analog front-ends (AFE1, AFE2, AFE3, AFE4). Each of the analog front-ends (AFE1 to AFE4) may be connected to two adjacent second sensors (RX1 to RX4). For example, the first analog front-end (AFE1) may be connected to the second sensors (RX1, RX2). The second analog front-end (AFE2) may be connected to the second sensors (RX2, RX3). The third analog front-end (AFE3) may be connected to the second sensors (RX3, RX4). The fourth analog front-end (AFE4) may be connected to the second sensor (RX4) and the adjacent second sensor.

[0038] Each of the analog front-ends (AFE1 to AFE4) can operate in a fully differential mode. In a fully differential mode, each analog front-end can process the sensing signals of adjacent second sensors into differential signals to generate a digital signal from which the common signal and common noise of the sensing signals have been removed. In this case, the signal-to-noise ratio (SNR) can be improved. In the embodiments, to detect a touch input from a body (or person) adjacent to the sensor array (110), the analog front-ends (AFE1 to AFE4) can operate in a fully differential mode.

[0039] For example, in full differential mode, the first analog front-end (AFE1) can output to a signal processor (DSP) a digital signal corresponding to the value obtained by subtracting the level of the sensing signal of the second sensor (RX2) from the level of the sensing signal of the second sensor (RX1), and a digital signal corresponding to the value obtained by subtracting the level of the sensing signal of the second sensor (RX1) from the level of the sensing signal of the second sensor (RX2). The second analog front-end (AFE2) can output to a signal processor (DSP) a digital signal corresponding to the value obtained by subtracting the level of the sensing signal of the second sensor (RX2) from the level of the sensing signal of the second sensor (RX3), and a digital signal corresponding to the value obtained by subtracting the level of the sensing signal of the second sensor (RX3) from the level of the sensing signal of the second sensor (RX2). In this way, in full differential mode, each analog stage can output relative values ​​between neighboring sensing signals.

[0040] Each of the analog front-ends (AFE1 to AFE4) can operate in a single-ended mode. In a single-ended mode, each analog front-end can generate digital signals by processing each of the received sensing signals independently. In this case, the digital signals can reflect the magnitudes of the sensing signals. In embodiments, to detect touch input from a pen adjacent to the sensor array (110), the analog front-ends (AFE1 to AFE4) can operate in a single-ended mode.

[0041] For example, in single-ended mode, the first analog front end (AFE1) can output a digital signal corresponding to the level of the sensing signal of the second sensor (RX1) and a digital signal corresponding to the level of the sensing signal of the second sensor (RX2) to a signal processor (DSP). The second analog front end (AFE2) can output a digital signal corresponding to the level of the sensing signal of the second sensor (RX2) and a digital signal corresponding to the level of the sensing signal of the second sensor (RX3) to a signal processor (DSP). Each output digital signal can reflect the magnitude (or level) of the corresponding sensing signal.

[0042] The signal processor (DSP) can calculate sensing values ​​using digital signals provided by the analog front-end group (AFEG) and detect touch input based on the sensing values.

[0043] FIG. 2 is a block diagram showing an example of any one of the analog shears of FIG. 1.

[0044] Referring to FIG. 2, the first analog stage (AFE1) may include a charge amplifier (CAMP), a band-pass filter (BPF), a mixer (MXR), a low-pass filter (LPF), and an analog-to-digital converter (ADC). The other analog stages (AFE2 to AFE4) may be configured similarly to the first analog stage (AFE1), differing only in the second sensors connected thereto. Redundant descriptions are omitted below.

[0045] The charge amplifier (CAMP) may be configured to receive sensing signals from the second sensors (RX1, RX2) through the second sensor lines (RXL1, RXL2) and to transmit the received sensing signals to a bandpass filter (BPF). In embodiments, the charge amplifier (CAMP) may operate in a fully differential mode to output a signal corresponding to the difference between the level of the sensing signal of the second sensor (RX2) and the level of the sensing signal of the second sensor (RX1), and the inverted signal thereof. In embodiments, the charge amplifier (CAMP) may operate in a single-ended mode to output a signal corresponding to the level of the sensing signal of the second sensor (RX1) and a signal corresponding to the level of the sensing signal of the second sensor (RX2).

[0046] A charge amplifier (CAMP), a band-pass filter (BPF), a mixer (MXR), a low-pass filter (LPF), and an analog-to-digital converter (ADC) can form sequentially connected stages. In FIG. 2, the band-pass filter (BPF), mixer (MXR), low-pass filter (LPF), and analog-to-digital converter (ADC) are each shown as being connected to the previous stage via two internal signals. In a fully differential mode, each stage can receive and process an input signal and an inverted signal of the input signal via two internal signal lines. In this case, each stage has the advantage of being able to remove noise commonly contained in the input signal and the inverted signal. In a single-ended mode, each stage can receive and process an input signal corresponding to the sensing signal of the second sensor line (RXL1) and an input signal corresponding to the sensing signal of the second sensor line (RXL2) via two internal signal lines. In this case, each stage can process each input signal independently to provide an output signal that reflects the magnitude of the input signal.

[0047] A band-pass filter (BPF) can be connected to the output terminals of a charge amplifier (CAMP). The band-pass filter (BPF) can be configured to filter the output signals by sampling the output signals of the charge amplifier (CAMP) at a specific frequency. The band-pass filter (BPF) can filter the output signals to have a set frequency band. For example, the frequency band can be preset to include the frequency (or center frequency) of the sensing signals, and noise components can be located outside the frequency band. The center frequency of the sensing signals can be the same as the center frequency of the driving signals.

[0048] According to an embodiment of the present invention, the band pass filter (BPF) may include a dual-mode band pass filter that supports a fully differential mode and a single-ended mode.

[0049] A mixer (MXR) can be connected to the output terminals of a band-pass filter (BPF). The mixer (MXR) can mix the output signals of the band-pass filter (BPF) with the local clock signal (fLO). The mixer (MXR) can generate output signals that include frequency components corresponding to the difference and / or sum of the frequency of the output signal and the frequency of the local clock signal (fLO). For example, when the frequency of the output signal of the band-pass filter (BPF) and the frequency of the local clock signal (fLO) are the same, the output signal of the mixer (MXR) may include a frequency component having a center frequency of 0 Hz.

[0050] A low-pass filter (LPF) can filter the output signals of a mixer (MXR) to have a set frequency band. In this case, the set frequency band of the low-pass filter (LPF) may be lower than the set frequency band of a band-pass filter (BPF). For example, the low-pass filter (LPF) may allow only signals in the low-frequency band centered at 0 Hz to pass through among the output signals of the mixer (MXR). By doing so, the low-pass filter (LPF) can filter out frequency components corresponding to noise.

[0051] An analog-to-digital converter (ADC) can be connected to the output terminals of a low-pass filter (LPF). The analog-to-digital converter (ADC) can convert the output signals of the low-pass filter (LPF) into digital signals (OUT1, OUT2). In full differential mode, the digital signals (OUT1, OUT2) can be understood to correspond to a signal corresponding to the difference between the level of the sensing signal of the second sensor (RX2) and the level of the sensing signal of the second sensor (RX1), and the inverted signal thereof, respectively. In single-ended mode, the digital signals (OUT1, OUT2) can be understood to correspond to the sensing signal of the second sensor line (RXL1) and the sensing signal of the second sensor line (RXL2), respectively.

[0052] Since the analog-to-digital converter (ADC) receives a low-frequency band signal from a low-pass filter (LPF), it can operate at a small sampling rate and the frequency of the clock signal can also be low, which can have advantages in terms of power cost and configuration cost.

[0053] The signal processor (DSP) of FIG. 1 can detect touch input based on digital signals (OUT1, OUT2). Digital signals (OUT1, OUT2) received in full differential mode may be advantageous for detecting touch input from the body (e.g., fingers). Digital signals (OUT1, OUT2) received in single-ended mode may be advantageous for detecting touch input from a pen.

[0054] In the embodiments, the sensor receiver (TSC) may operate in bypass mode. In this case, the functions of the mixer (MXR) and the low-pass filter (LPF) may be performed digitally in a signal processor (DSP). In this case, the output signals of the band-pass filter (BPF) may be directly transmitted to an analog-to-digital converter (ADC).

[0055] Figures 3 and 4 are diagrams illustrating the advantages of implementing a band-pass filter with high-pass filters.

[0056] Referring to FIG. 3, the characteristics of a single SC (switched-capacitor) high-pass filter (SC_HPF) are illustrated. As is well known, the maximum value (0.5fs) of the Nyquist range of the SC high-pass filter (SC_HPF) corresponds to half of the sampling frequency (fs) of the SC high-pass filter (SC_HPF). In other words, the SC high-pass filter (SC_HPF) can have a passband with the maximum value (0.5fs) of the Nyquist range as the center frequency.

[0057] Referring to FIG. 4, in order to implement a bandpass filter having a passband of a center frequency (0.5fs) when considering the Nyquist range, two SC high-pass filters (SC_HPF1, SC_HPF2) connected in parallel may be provided.

[0058] When considering the sampling frequency (fs) of each SC high-pass filter (SC_HPF1, SC_HPF2), the frequency (2fs) of the input switch (INSH) and the frequency (2fs) of the output switch (OTSH) need to be twice the sampling frequency (fs). At this time, even if the sampling frequency (fs) of the clock signal provided to each SC high-pass filter (SC_HPF1, SC_HPF2) is the same, the phases will be different.

[0059] In this way, a band-pass filter can be implemented using two SC high-pass filters (SC_HPF1, SC_HPF2). An example of a band-pass filter implemented with high-pass filters is described below with reference to FIG. 5.

[0060] Figure 5 is a block diagram showing an example of the bandpass filter of Figure 2.

[0061] Referring to FIG. 5, the band-pass filter (BPF) may include first and second low-frequency attenuation sections (LFA1, LFA2), a first capacitor circuit (210), a second capacitor circuit (220), and an amplifier circuit (AMPC).

[0062] The first low frequency attenuation unit (LFA1) is configured to attenuate the low frequency components of the first input signal (IS1) and output them to the first line (L1). The second low frequency attenuation unit (LFA2) is configured to attenuate the low frequency components of the second input signal (IS2) and output them to the second line (L2). For example, environmental noise associated with the sensor device may cause low frequency components of the first and second input signals (IS1, IS2). The low frequency components of the first and second input signals (IS1, IS2) may be attenuated as they pass through the first and second low frequency attenuation units (LFA1, LFA2).

[0063] The amplifier circuit (AMPC) may have an inverting input terminal connected to a first line (L1) and a non-inverting input terminal connected to a second line (L2). A first sampling signal (SAM1) may be output through the non-inverting output terminal of the amplifier circuit (AMPC), and a second sampling signal (SAM2) may be output through the inverting output terminal of the amplifier circuit (AMPC).

[0064] The amplifier circuit (AMPC) can operate as a selected one of a fully differential amplifier and a single-ended amplifier in response to control signals.

[0065] The first capacitor circuit (210) may include first capacitors (CP1). The second capacitor circuit (220) may include second capacitors (CP2). The first and second capacitor circuits (210, 220) may be connected to first and second lines (L1, L2) through a channel (CH). The channel (CH) is connected between the first and second low-frequency attenuators (LFA1, LFA2) and the first and second lines (L1, L2). By transmitting control signals to switches included in the band-pass filter (BPF) and / or the first and second capacitor circuits (210, 220), the electrical connection relationship between the first capacitors (CP1), the second capacitors (CP2), and the amplifier circuit (AMPC) may be varied.

[0066] The first capacitor circuit (210) can be connected to the non-inverting output terminal of the amplifier circuit (AMPC). The second capacitor circuit (220) can be connected to the inverting output terminal of the amplifier circuit (AMPC). The current and / or voltage output through the first capacitor circuit (210) can be output as a first sampling signal (SAM1). The current and / or voltage output through the second capacitor circuit (220) can be output as a second sampling signal (SAM2).

[0067] FIG. 6a is a block diagram showing an example of a bandpass filter operating in a fully differential mode, switched from the bandpass filter of FIG. 5.

[0068] Referring to FIG. 6a, at least some of the first capacitors (CP1) can perform integration (or sampling) on ​​the first input signal (IS1) that has passed through the first low-frequency attenuation unit (LFA1). Additionally, at least some of the first capacitors (CP1) can be connected to at least some of the second capacitors (CP2) through the channel (CH) of FIG. 5 to transfer charges.

[0069] At least some of the second capacitors (CP2) receiving charges from the first capacitor circuit (210) can perform integration (or sampling) on ​​the second input signal (IS2) that has passed through the second low-frequency attenuation unit (LFA2). Accordingly, the second input signal (IS2) can be integrated together with the charges stored in at least some of the first capacitors (CP1) according to the first input signal (IS1), and accordingly, a second sampling signal (SAM2) can be output from the second capacitor circuit (220). In this way, at least some of the first capacitors (CP1), at least some of the second capacitors (CP2), and the amplifier circuit (AMPC) can function as a z-to-z transformed SC integrator or high-pass filter for the second input signal (IS2), using the first input signal (IS1) as a differential signal.

[0070] At least some of the second capacitors (CP2) can be connected to at least some of the first capacitors (CP1) through the channel (CH) of FIG. 5 to transfer charges. At least some of the first capacitors (CP1) receiving charges from the second capacitor circuit (220) can perform integration with respect to the first input signal (IS1). Accordingly, the first input signal (IS1) can be integrated with the charges stored in at least some of the second capacitors (CP2) according to the second input signal (IS2), and accordingly, a first sampling signal (SAM1) can be output from the first capacitor circuit (210). In this way, at least some of the first capacitors (CP1) and at least some of the second capacitors (CP2), the amplifier circuit (AMPC) can function as a z-to-z transformed SC integrator or high-pass filter for the first input signal (IS1), using the second input signal (IS2) as a differential signal.

[0071] Accordingly, the first and second low-frequency attenuation units (LFA1, LFA2), at least some of the first capacitors (CP1), at least some of the second capacitors (CP2), and the amplifier circuit (AMPC) can form a band-pass filter (BPF1) operating in a fully differential mode.

[0072] In the embodiments, when the band-pass filter (BPF) of FIG. 5 operates as a band-pass filter (BPF1) in full differential mode, the amplifier circuit (AMPC) can operate as a full differential mode amplifier.

[0073] FIG. 6b is a block diagram showing an example of a bandpass filter operating in a single-ended mode, switched from the bandpass filter of FIG. 5.

[0074] Referring to FIG. 6b, a band pass filter (BPF2) operating in single-ended mode may include two single-ended mode band pass filter circuits (BPF2_1, BPF2_2) that operate independently of each other. The band pass filter circuits (BPF2_1, BPF2_2) do not communicate with each other and may operate independently of each other.

[0075] At least some of the first capacitors (CP1) and the amplifier circuit (AMPC) can operate as at least two z-to-z transformed SC integrators or high-pass filters. For example, the third capacitors among the first capacitors (CP1) and the amplifier circuit (AMPC) can function as one z-to-z transformed SC integrator or high-pass filter to output a first sampling signal (SAM1). The fourth capacitors among the first capacitors (CP1) and the amplifier circuit (AMPC) can function as another z-to-z transformed SC integrator or high-pass filter to output a first sampling signal (SAM1). In this case, the third capacitors may be different from the fourth capacitors. Alternatively, at least some of the third capacitors may be included in the fourth capacitors. Accordingly, the first low-frequency attenuation unit (LFA1), at least some of the first capacitors (CP1), and the amplifier circuit (AMPC) can form a first band-pass filter circuit (BPF2_1) in single-ended mode that filters the first input signal (IS1) and outputs a first sampling signal (SAM1).

[0076] At least some of the second capacitors (CP2) and the amplifier circuit (AMPC) can function as at least two z-to-z transformed SC integrators or high-pass filters. For example, the fifth capacitor among the second capacitors (CP2) and the amplifier circuit (AMPC) can function as one z-to-z transformed SC integrator or high-pass filter to output a second sampling signal (SAM2). The sixth capacitor among the second capacitors (CP2) and the amplifier circuit (AMPC) can function as another z-to-z transformed SC integrator or high-pass filter to output a second sampling signal (SAM2). In this case, the fifth capacitors may be different from the sixth capacitors. Alternatively, at least some of the fifth capacitors may be included in the sixth capacitors. Accordingly, the second low-frequency attenuation unit (LFA2), at least some of the second capacitors (CP2), and the amplifier circuit (AMPC) can form a second band-pass filter circuit (BPF2_2) in single-ended mode that filters the second input signal (IS2) and outputs a second sampling signal (SAM2).

[0077] In embodiments, when the bandpass filter (BPF) of FIG. 5 operates as first and second bandpass filter circuits (BPF2_1, BPF2_2) in single-ended mode, the amplifier circuit (AMPC) may operate as first and second single-ended amplifiers that operate independently of each other. The first single-ended amplifier may have an inverting input terminal that receives a first input signal (IS1), a non-inverting input terminal that receives a reference voltage, and a single-ended output terminal that outputs a first sampling signal (SAM1). The second single-ended amplifier may have an inverting input terminal that receives a second input signal (IS2), a non-inverting input terminal that receives a reference voltage, and a single-ended output terminal that outputs a second sampling signal (SAM2).

[0078] In this way, the bandpass filter (BPF) of FIG. 5 can be converted into a bandpass filter in a fully differential mode that receives first and second input signals (IS1, IS2) as differential signals and performs sampling, and into a bandpass filter in a single-ended mode that samples each of the first and second input signals (IS1, IS2) independently. Accordingly, a bandpass filter (BPF, see FIG. 2) having a reduced area is provided compared to the case where the bandpass filter in a fully differential mode and the bandpass filter in a single-ended mode are each provided separately. Thus, a sensor device (100, see FIG. 1) having a reduced area can be provided.

[0079] FIG. 7 is a circuit diagram showing an example of the bandpass filter of FIG. 5. FIG. 8 is a circuit diagram showing the components forming a bandpass filter operating in full differential mode among the bandpass filter circuits of FIG. 7. FIG. 9 is a circuit diagram showing the components forming a bandpass filter in single-ended mode among the bandpass filter circuits of FIG. 7.

[0080] Referring to FIG. 7, the bandpass filter (200) may include an amplifier circuit (AMPC), input capacitors (CIN1, CIN2), first and second gain capacitors (CS1, CS2), first to ten capacitors (C1 to C10), and first to seventy-four switches (W1 to W74).

[0081] The amplifier circuit (AMPC) can be configured as a fully differential amplifier having two output terminals. The amplifier circuit (AMPC) may have an inverting input terminal connected to a first line (L1) and a non-inverting input terminal connected to a second line (L2).

[0082] Two first input capacitors (CIN1) connected in series may be connected between the first input node (IN1) and the first line (L1). Two second input capacitors (CIN2) connected in series may be connected between the second input node (IN2) and the second line (L2). The first input node (IN1) can receive the first input signal (IS1) of FIG. 5. The second input node (IN2) can receive the second input signal (IS2) of FIG. 5.

[0083] In the embodiments, each of the first input capacitors (CIN1) may have the same capacitance as each of the second input capacitors (CIN2).

[0084] The first switch (W1) may be connected between the first input node (IN1) and the first input capacitors (CIN1), and the second switch (W2) may be connected between the second input node (IN2) and the second input capacitors (CIN2). In FIG. 7, control signals for turning on and off each switch are indicated in the parentheses adjacent to the reference symbol of the corresponding switch.

[0085] The third switch (W3) is connected between the node between the first input capacitors (CIN1) and the reference voltage (or ground voltage), and the fourth switch (W4) is connected between the node between the second input capacitors (CIN2) and the reference voltage. The fifth switch (W5) is connected between one end of the seventh switch (W7) and the reference voltage, and the sixth switch (W6) is connected between one end of the eighth switch (W8) and the reference voltage.

[0086] The first input capacitors (CIN1) can function as the first low-frequency attenuation unit (LFA1) of FIGS. 5 and 6. When the first switch (W1) is turned on, the first input capacitors (CIN1) can perform low-frequency attenuation for the signal received through the first input node (IN1). When the third and fifth switches (W3, W5) are turned on, the first input capacitors (CIN1) can be initialized.

[0087] The second input capacitors (CIN2) can function as the second low-frequency attenuation unit (LFA2) of FIGS. 5 and 6. When the second switch (W2) is turned on, the second input capacitors (CIN2) can perform low-frequency attenuation for the signal received through the second input node (IN2). When the fourth and sixth switches (W4, W6) are turned on, the second input capacitors (CIN2) can be initialized.

[0088] The 7th switch (W7) has one end connected to the 1st input capacitors (CIN1) and the other end connected to the 1st line (L1). The 8th switch (W8) has one end connected to the 2nd input capacitors (CIN2) and the other end connected to the 2nd line (L2). In the circuit structure of FIG. 7, a channel (CH) is formed between the input capacitors (CIN1, CIN2) and the 1st and 2nd lines (L1, L2). The circuit structure of the 1st gain capacitor (CS1), the 1st to 5th capacitors (C1~C5), and the 9th to 39th switches (W9~W39), that is, the upper components of the amplifier circuit (AMPC), can be connected to the 1st and 2nd lines (L1, L2) through the channel (CH). The circuit structure of the second gain capacitor (CS2), the sixth to tenth capacitors (C6 to C10), and the forty to seventy switches (W40 to W70), that is, the lower components of the amplifier circuit (AMPC), can be connected to the first and second lines (L1, L2) through the channel (CH).

[0089] The first gain capacitor (CS1) is connected between one end of the seventh switch (W7) and the first output node (ON1). The second gain capacitor (CS2) is connected between one end of the eighth switch (W8) and the second output node (ON2).

[0090] The ninth switch (W9) is connected between the inverting input terminal of the amplifier circuit (AMPC) and the non-inverting output terminal of the amplifier circuit (AMPC), and the tenth switch (W10) is connected in parallel with the ninth switch (W9) between the inverting input terminal of the amplifier circuit (AMPC) and the non-inverting output terminal of the amplifier circuit (AMPC).

[0091] The first capacitor (C1) is connected between the inverting input terminal of the amplifier circuit (AMPC) and the non-inverting output terminal of the amplifier circuit (AMPC). The 13th switch (W13) is connected between one end of the first capacitor (C1) and the inverting input terminal of the amplifier circuit (AMPC). The 11th switch (W11) is connected between the other end of the first capacitor (C1) and the non-inverting output terminal of the amplifier circuit (AMPC), and the 12th switch (W12) is connected between the other end of the first capacitor (C1) and the reference voltage.

[0092] The second capacitor (C2) is connected between the inverting input terminal of the amplifier circuit (AMPC) and the non-inverting output terminal of the amplifier circuit (AMPC). The 15th switch (W15) is connected between one end of the second capacitor (C2) and the 13th switch (W13). The 16th switch (W16) is connected between the 15th switch (W15) and one end of the second capacitor (C2). The 17th switch (W17) is connected between one end of the second capacitor (C2) and the reference voltage. The 21st switch (W21) is connected between the other end of the second capacitor (C2) and the non-inverting output terminal of the amplifier circuit (AMPC), and the 22nd switch (W22) is connected between the 21st switch (21) and the non-inverting output terminal of the amplifier circuit (AMPC).

[0093] The 14th switch (W14) is connected between the node between the 15th and 16th switches (W15, W16) and the non-inverting input terminal of the amplifier circuit (AMPC). The 18th switch (W18) is connected between the 14th switch (W14) and one end of the 2nd capacitor (C2), the 19th switch (W19) is connected between the 14th switch (W14) and the other end of the 2nd capacitor (C2), and the 20th switch (W20) is connected between the other end of the 2nd capacitor (C2) and the 22nd switch (W22).

[0094] The third capacitor (C3) is connected between the inverting input terminal of the amplifier circuit (AMPC) and the non-inverting output terminal of the amplifier circuit (AMPC). The 24th switch (W24) is connected between one end of the third capacitor (C3) and the 23rd switch (W23). The 26th switch (W26) is connected between one end of the third capacitor (C3) and the reference voltage. The 29th switch (W29) is connected between the other end of the third capacitor (C3) and the reference voltage, and the 30th switch (W3) can be connected between the 29th switch (W29) and the reference voltage.

[0095] The 25th switch (W25) can be connected between one end of the 3rd capacitor (C3) and the 23rd switch (W23). The 27th switch (W27) is connected between the 23rd switch (W23) and the other end of the 3rd capacitor (C3), and the 28th switch (W28) is connected between the other end of the 3rd capacitor (C3) and the 30th switch (W30).

[0096] The 23rd switch (W23) is connected between the 24th switch (W24) and the other end of the 7th switch (W7).

[0097] The fourth capacitor (C4) is connected between the inverting input terminal of the amplifier circuit (AMPC) and the non-inverting output terminal of the amplifier circuit (AMPC). The 39th switch (W39) is connected between one end of the fourth capacitor (C4) and the reference voltage, and the 38th switch (W38) is connected between one end of the fourth capacitor (C4) and the 31st switch (W31). The 36th switch (W36) is connected between the 31st switch (W31) and the other end of the fourth capacitor (C4), and the 37th switch (W37) is connected between the other end of the fourth capacitor (C4) and the 30th switch (W30).

[0098] The fifth capacitor (C5) is connected between the inverting input terminal of the amplifier circuit (AMPC) and the non-inverting output terminal of the amplifier circuit (AMPC). The 35th switch (W35) is connected between one end of the fifth capacitor (C5) and the reference voltage, and the 34th switch (W34) is connected between one end of the fifth capacitor (C5) and the 31st switch (W31). The 32nd switch (W32) is connected between the 31st switch (W31) and the other end of the fifth capacitor (C5), and the 33rd switch (W33) is connected between the other end of the fifth capacitor (C5) and the 30th switch (W30).

[0099] The 31st switch (W31) is connected between the other end of the 7th switch (W7) and the 32nd switch (W32).

[0100] The circuit structure of the second gain capacitor (CS2), the 6th to 10th capacitors (C6 to C10), and the 40th to 70th switches (W40 to W70) can be formed symmetrically with respect to the circuit structure of the first gain capacitor (CS1), the 1st to 5th capacitors (C1 to C5), and the 9th to 39th switches (W9 to W39) centered on the amplifier circuit (AMPC).

[0101] The 40th switch (W40) is connected between the non-inverting input terminal of the amplifier circuit (AMPC) and the inverting output terminal of the amplifier circuit (AMPC), and the 41st switch (W41) is connected between the non-inverting input terminal of the amplifier circuit (AMPC) and the inverting output terminal of the amplifier circuit (AMPC).

[0102] The sixth capacitor (C6) is connected between the non-inverting input terminal of the amplifier circuit (AMPC) and the inverting output terminal of the amplifier circuit (AMPC). The sixth capacitor (C6) may have the same capacitance as the first capacitor (C1). The 42nd switch (W42) is connected between one end of the sixth capacitor (C6) and the non-inverting input terminal of the amplifier circuit (AMPC), and the 43rd switch (W43) is connected between one end of the sixth capacitor (C6) and the 45th switch (W45). The 44th switch (W44) is connected between the inverting input terminal of the amplifier circuit (AMPC) and the 43rd switch (W43).

[0103] The 51st switch (W51) is connected between the other end of the 6th capacitor (C6) and the reference voltage, and the 52nd switch (W52) is connected between the other end of the 6th capacitor (C6) and the 53rd switch (W53). The 53rd switch (W53) is connected between the 52nd switch (W52) and the other end of the 7th capacitor (C7).

[0104] The seventh capacitor (C7) is connected between the non-inverting input terminal of the amplifier circuit (AMPC) and the inverting output terminal of the amplifier circuit (AMPC). The seventh capacitor (C7) may have the same capacitance as the second capacitor (C2). The 45th switch (W45) is connected between the 43rd switch (W43) and one end of the seventh capacitor (C7). The 46th switch (W46) is connected between one end of the seventh capacitor (C7) and the 44th switch (W44). The 47th switch (W47) is connected between one end of the seventh capacitor (C7) and the reference voltage. The 48th switch (W48) is connected between the 46th switch (W46) and the other end of the seventh capacitor (C7), and the 49th switch (W49) is connected between the other end of the seventh capacitor (C7) and the 53rd switch (W53). The 50th switch (W50) is connected between the other end of the 7th capacitor (C7) and the 53rd switch (W53).

[0105] The eighth capacitor (C8) is connected between the non-inverting input terminal of the amplifier circuit (AMPC) and the inverting output terminal of the amplifier circuit (AMPC). The eighth capacitor (C8) may have the same capacitance as the third capacitor (C3). The 54th switch (W54) is connected between the other end of the eighth switch (W8) and one end of the eighth capacitor (C8). The 55th switch (W55) is connected between the 54th switch (W54) and one end of the eighth capacitor (C8), and the 57th switch (W57) is connected between the 54th switch (W54) and one end of the eighth capacitor (C8). The 56th switch (W56) is connected between one end of the eighth capacitor (C8) and a reference voltage.

[0106] The 58th switch (W58) is connected between the 54th switch (W54) and the other end of the 8th capacitor (C8). The 59th switch (W59) is connected between the other end of the 8th capacitor (C8) and the 61st switch (W61), and the 60th switch (W60) is connected between the other end of the 8th capacitor (C8) and the 61st switch (W61). The 61st switch (W61) is connected between the 60th switch (W60) and the reference voltage.

[0107] The ninth capacitor (C9) is connected between the non-inverting input terminal of the amplifier circuit (AMPC) and the inverting output terminal of the amplifier circuit (AMPC). The ninth capacitor (C9) may have the same capacitance as the fourth capacitor (C4). The 63rd switch (W63) is connected between one end of the ninth capacitor (C9) and the reference voltage, and the 64th switch (W64) is connected between one end of the ninth capacitor (C9) and the 62nd switch (W62). The 65th switch (W65) is connected between the 62nd switch (W62) and the other end of the ninth capacitor (C9), and the 66th switch (W66) is connected between the other end of the ninth capacitor (C9) and the 61st switch (W61).

[0108] The 62nd switch (W62) is connected between the other end of the 8th switch (W8) and the 65th switch (W65).

[0109] The 10th capacitor (C10) is connected between the non-inverting input terminal of the amplifier circuit (AMPC) and the inverting output terminal of the amplifier circuit (AMPC). The 10th capacitor (C10) may have the same capacitance as the 5th capacitor (C5). The 67th switch (W67) is connected between one end of the 10th capacitor (C10) and the reference voltage, and the 68th switch (W68) is connected between one end of the 10th capacitor (C10) and the 62nd switch (W62). The 69th switch (W69) is connected between the 62nd switch (W62) and the other end of the 10th capacitor (C10). The 70th switch (W70) is connected between the other end of the 10th capacitor (C10) and the 61st switch (W61).

[0110] The 71st switch (W71) may be connected between the non-inverting output terminal of the amplifier circuit (AMPC) and the first output node (ON1), and the 73rd switch (W73) may be connected between the inverting output terminal of the amplifier circuit (AMPC) and the second output node (ON2). The 72nd switch (W72) may be connected between the first output node (ON1) and the reference voltage, and the 74th switch (W74) may be connected between the second output node (ON2) and the reference voltage.

[0111] The first to fifth capacitors (C1 to C5) and the first gain capacitor (CS1) may be included in the first capacitors (CP1) of FIG. 5. The sixth to tenth capacitors (C6 to C10) and the second gain capacitor (CS2) may be included in the second capacitors (CP2) of FIG. 5.

[0112] Referring to FIG. 8, first input capacitors (CIN1), second input capacitors (CIN2), first to eighth switches (W1 to W8), first to third capacitors (C1 to C3), first gain capacitor (CS1), 10 to 16, 21, 22, 24, 29, and 30th switches (W10 to W16, W21, W22, W24, W29, W30), 6 to eighth capacitors (C6 to C8), second gain capacitor (CS2), 41 to 45, 49, 51 to 53, 55, 60, and 61st switches (W41 to W45, W49, W51 to 53, W55, W60, W61), 71 to 74 The switches (W71 to W74) can form a band-pass filter (200') operating in a fully differential mode. The band-pass filter (200') can operate as the band-pass filter (BPF1) of FIG. 6a.

[0113] In the embodiments, the 6th to 8th capacitors (C6~C8), the 2nd gain capacitor (CS2), the 41st to 45th, 49th, 51st to 53rd, 55th, 60th, and 61st switches (W41~W45, W49, W51~53, W55, W60, W61) may have a circuit structure symmetrical to the amplifier circuit (AMPC) and the 1st to 3rd capacitors (C1~C3), the 1st gain capacitor (CS1), the 10th to 16th, 21st, 22nd, 24th, 29th, and 30th switches (W10~W16, W21, W22, W24, W29, W30).

[0114] Referring to FIG. 9, first input capacitors (CIN1), second input capacitors (CIN2), first to eighth switches (W1~W8), second to fifth capacitors (C2~C5), ninth, tenth, seventeenth to twentyth, twenty-twoth, twenty-threeth, twenty-fiveth to twenty-eighth switches (W9, W10, W17~W20, W22, W23, W25~W28, W31~W39), seventh to tenth capacitors (C7~C10), forty-fourth, forty-fourth, forty-fourth to forty-eighth switches (W40, W41, W46~W48, W50, 40, W41, W46~W48, W42, W50, 40, W41, W46~W48, W46, W41, W41, W46, W48, W46, W41, W41, W46, W48, W46, W41, W41, W46, W48, W46, W41, W41, W41, W46, W48, W46, W41, W41, W41, W41, W41, W46, W48, W41 W53, W54, W56~W59, W62~W70), and the 71st to 74th switches (W71~W74) can form a band pass filter (200'') operating in a single-ended mode. The band pass filter (200'') can operate as the band pass filter (BPF2) of FIG. 6b.

[0115] At this time, the 7th to 10th capacitors (C7~C10), 40, 41, 46 to 48, 50, 53, 54, 56 to 59, and 62 to 70 switches (W40, W41, W46~W48, W50, W53, W54, W56~W59, W62~W70) may have a symmetrical circuit structure centered on the 2nd to 5th capacitors (C2~C5), 9th, 10th, 17th to 20th, 22th, 23rd, 25th to 28th, and 31st to 39 switches (W9, W10, W17~W20, W22, W23, W25~W28, W31~W39) and the amplifier circuit (AMPC).

[0116] In FIG. 8, the bandpass filter (200') includes second, third, seventh, and eighth capacitors (C2, C3, C7, C8). In FIG. 9, the bandpass filter (200'') includes second, third, seventh, and eighth capacitors (C2, C3, C7, C8). Thus, the bandpass filter (200') in full differential mode and the bandpass filter (200'') in single-ended mode may share the second, third, seventh, and eighth capacitors (C2, C3, C7, C8).

[0117] FIG. 10 is a timing diagram showing signals controlling the bandpass filter of FIG. 8. FIG. 11 and FIG. 12 are circuit diagrams for explaining the current paths formed in the bandpass filter of FIG. 8 during the first period of FIG. 10. FIG. 13 and FIG. 14 are circuit diagrams for explaining the current paths formed in the bandpass filter of FIG. 8 during the second period of FIG. 10.

[0118] Referring to FIG. 10, first and second cycles (CYC1, CYC2) may be provided. By repeating the first and second cycles (CYC1, CYC2), the bandpass filter of FIG. 8 may operate in a fully differential mode. The duration of each of the first and second cycles (CYC1, CYC2) may be 1 / fs. Thus, the switching frequency may be fs.

[0119] The control signals (DM, P1, P2, PD1~PD4, PDS1) of FIG. 10 may be provided from a controller included in the sensor driver (120) of FIG. 1. For example, the control signals (DM, P1, P2, PD1~PD4, PDS1) of FIG. 10 may be provided by a signal processor (DSP).

[0120] The first cycle (CYC1) may include a first time period (T1) and a second time period (T2). In the first time period (T1), the mode control signal (DM) and control signals (P2, PD2, PD3) have a high level. Switches receiving the high-level mode control signal (DM) and control signals (P2, PD2, PD3) may be turned on.

[0121] Accordingly, with reference to FIG. 11, a current path (a) flowing from the first input node (IN1) to the first output node (ON1) through the first input capacitors (CIN1) and the first capacitor (C1) can be formed. A current path (b) flowing from the first input node (IN1) to the first output node (ON1) through the first input capacitors (CIN1) and the first gain capacitor (CS1) can be formed. Thus, each of the first capacitor (C1) and the first gain capacitor (CS1) can perform integration (or sampling) of the first input signal received through the first input capacitors (CIN1).

[0122] Although not illustrated in FIG. 11 for clarity and concise explanation, the sixth capacitor (C6) and the second gain capacitor (CS2) can each perform integration on the first input signal received through the second input capacitors (CIN2). More specifically, a current path flowing from the second input node (IN2) to the second output node (ON2) through the second input capacitors (CIN2) and the sixth capacitor (C6) can be formed. A current path flowing from the second input node (IN2) to the second output node (ON2) through the second input capacitors (CIN2) and the second gain capacitor (CS2) can be formed.

[0123] A current path (c) flowing from the second capacitor (C2) through the sixth capacitor (C6) to the second output node (ON2) can be formed. Additionally, a current path (d) flowing from the second capacitor (C2) through the second gain capacitor (CS2) to the second output node (ON2) can be formed. Thus, the sixth capacitor (C6) and the second gain capacitor (CS2) can each integrate the charges of the second capacitor (C2) together with the second input signal, and accordingly, a second sampling signal can be output through the second output node (ON2). In this way, the second capacitor (C2), the sixth capacitor (C6), the second gain capacitor (CS2), and the amplifier circuit (AMPC) can function as a sign-inverted z to -z transformed SC integrator. For example, the second capacitor (C2), the sixth capacitor (C6), the second gain capacitor (CS2), and the amplifier circuit (AMPC) can use the first input signal as a differential signal and function as a high-pass filter for the second input signal.

[0124] For clarity and concise explanation, although not shown in FIG. 11, a current path flowing from the seventh capacitor (C7) through the first capacitor (C1) to the first output node (ON1) may be formed. Additionally, a current path flowing from the seventh capacitor (C7) through the first gain capacitor (CS1) to the first output node (ON1) may be formed. Thus, the first capacitor (C1) and the first gain capacitor (CS1) can each integrate the charges of the seventh capacitor (C7) together with the first input signal, and accordingly, a first sampling signal can be output through the first output node (ON1). In this way, the first capacitor (C1), the first gain capacitor (CS1), the seventh capacitor (C7), and the amplifier circuit (AMPC) can function as a sign-inverted z to -z transformed SC integrator. For example, the first capacitor (C1), the first gain capacitor (CS1), the seventh capacitor (C7), and the amplifier circuit (AMPC) can use the second input signal as a differential signal and function as a high-pass filter for the first input signal.

[0125] Referring again to FIG. 10, in the second time period (T2), the mode control signal (DM) and control signals (P1, PD1, PDS1, PD3) have a high level. Switches receiving the high-level mode control signal (DM) and control signals (P1, PD1, PDS1, PD3) can be turned on.

[0126] Accordingly, referring to FIG. 12, a current path (e) flowing from the first capacitor (C1) through the second capacitor (C2) to the non-inverting output terminal of the amplifier circuit (AMPC) can be formed. Accordingly, the charges of the first capacitor (C1) can be stored in the second capacitor (C2). Similarly, a current path (f) flowing from the sixth capacitor (C6) through the seventh capacitor (C7) to the inverting output terminal of the amplifier circuit (AMPC) can be formed. Accordingly, the charges of the sixth capacitor (C6) can be stored in the seventh capacitor (C7). In this way, during the second time period (T2) of the first cycle (CYC1) of FIG. 10, the charges of the first capacitor (C1) according to the first input signal are stored in the second capacitor (C2), so that the first input signal can be provided as a differential signal during the subsequent first time period (T1). In addition, the charges of the sixth capacitor (C6) according to the second input signal can be stored in the seventh capacitor (C7) so that the second input signal can be provided as a differential signal during the subsequent first time period (T1).

[0127] In the embodiments, a reset signal (RST) can be optionally enabled between each cycle and within each cycle.

[0128] Referring again to FIG. 10, the second cycle (CYC2) may include a third time period (T3) and a fourth time period (T4). In the third time period (T3), the mode control signal (DM) and control signals (P2, PD2, PD4) have a high level. Switches receiving the high-level mode control signal (DM) and control signals (P2, PD2, PD4) may be turned on.

[0129] Referring to FIG. 13, a current path (g) flowing from a first input node (IN1) to a first output node (ON1) through first input capacitors (CIN1) and a first capacitor (C1) can be formed. A current path (h) flowing from a first input node (IN1) to a first output node (ON1) through first input capacitors (CIN1) and a first gain capacitor (CS1) can be formed.

[0130] Although not illustrated in FIG. 13 for clarity and concise explanation, a current path flowing from the second input node (IN2) to the second output node (ON2) through the second input capacitors (CIN2) and the sixth capacitor (C6) may be formed. A current path flowing from the second input node (IN2) to the second output node (ON2) through the second input capacitors (CIN2) and the second gain capacitor (CS2) may be formed.

[0131] A current path (i) flowing from the third capacitor (C3) through the sixth capacitor (C6) to the second output node (ON2) can be formed. Additionally, a current path (j) flowing from the third capacitor (C3) through the second gain capacitor (CS2) to the second output node (ON2) can be formed. Thus, the sixth capacitor (C6) and the second gain capacitor (CS2) can each integrate the charges of the third capacitor (C3) together with the second input signal, and accordingly, a second sampling signal can be output through the second output node (ON2). In this way, the third capacitor (C3), the sixth capacitor (C6), the second gain capacitor (CS2), and the amplifier circuit (AMPC) can function as a sign-inverted z to -z transformed SC integrator. For example, the third capacitor (C3), the sixth capacitor (C6), the second gain capacitor (CS2), and the amplifier circuit (AMPC) can use the first input signal as a differential signal and function as a high-pass filter for the second input signal.

[0132] For clarity and concise explanation, although not shown in FIG. 13, a current path flowing from the eighth capacitor (C8) through the first capacitor (C1) to the first output node (ON1) may be formed. Additionally, a current path flowing from the eighth capacitor (C8) through the first gain capacitor (CS1) to the first output node (ON1) may be formed. Thus, the first capacitor (C1) and the first gain capacitor (CS1) can each integrate the charges of the eighth capacitor (C8) together with the first input signal, and accordingly, a first sampling signal can be output through the first output node (ON1). In this way, the first capacitor (C1), the first gain capacitor (CS1), the eighth capacitor (C8), and the amplifier circuit (AMPC) can function as a sign-inverted z to -z transformed SC integrator. For example, the first capacitor (C1), the first gain capacitor (CS1), the eighth capacitor (C8), and the amplifier circuit (AMPC) can use the second input signal as a differential signal and function as a high-pass filter for the first input signal.

[0133] Referring again to FIG. 10, in the fourth time period (T4), the mode control signal (DM) and control signals (P1, PD1, PDS1, PD4) have a high level. Switches receiving the high level mode control signal (DM) and control signals (P1, PD1, PDS1, PD4) can be turned on.

[0134] Accordingly, referring to FIG. 14, a current path (k) flowing from the first capacitor (C1) through the third capacitor (C3) to the non-inverting output terminal of the amplifier circuit (AMPC) can be formed. The charges of the first capacitor (C1) can be stored in the third capacitor (C3). Similarly, a current path (l) flowing from the sixth capacitor (C6) through the eighth capacitor (C8) to the inverting output terminal of the amplifier circuit (AMPC) can be formed. The charges of the sixth capacitor (C6) can be stored in the eighth capacitor (C8). In this way, in the fourth time period (T4) of the second cycle (CYC2) of FIG. 10, the charges of the first capacitor (C1) according to the first input signal can be stored in the third capacitor (C3) so that the first input signal can be provided as a differential signal in the subsequent third time period (T3). In addition, the charges of the 6th capacitor (C6) according to the 2nd input signal can be stored in the 8th capacitor (C8) so that the 2nd input signal can be provided as a differential signal in the subsequent 3rd time period (T3).

[0135] A band-pass filter in full differential mode can be implemented according to the high-pass filters provided in this way. In this case, the center frequency of the band-pass filter is fs / 4, and the gain value of the band-pass filter can be CIN / 4CS (CIN is the capacitance of one input capacitor, and CS is the capacitance of one gain capacitor). The Q factor of the band-pass filter can be adjusted according to the capacitances of the first to sixth capacitors (C1~C6) and the first and second gain capacitors (CS1, CS2).

[0136] FIG. 15 is a timing diagram showing signals controlling the bandpass filter of FIG. 9. FIG. 16 and FIG. 17 are circuit diagrams for explaining the current paths formed in the bandpass filter of FIG. 9 during the first and fifth time periods of FIG. 15. FIG. 18 and FIG. 19 are circuit diagrams for explaining the current paths formed in the bandpass filter of FIG. 9 during the third and seventh time periods of FIG. 15.

[0137] Referring to FIG. 15, first to fourth cycles (CYC1 to CYC4) may be provided. By repeating the first to fourth cycles (CYC1 to CYC4), the bandpass filter of FIG. 9 may operate as a single-ended mode bandpass filter circuit for each of the input signals. The duration of each of the first to fourth cycles (CYC1 to CYC4) may be 1 / fs. Thus, the switching frequency may be fs.

[0138] The first cycle (CYC1) may include a first time period (T1) and a second time period (T2). In the first time period (T1), control signals (PDS1, P2, PS3, PS5) have a high level. Switches receiving the high-level control signals (PDS1, P2, PS3, PS5) may be turned on.

[0139] The mode control signal (DM) is disabled. Switching elements receiving the mode control signal (DM) are turned off.

[0140] Referring to FIG. 16, a current path (m) can be formed from the first input node (IN1) through the first input capacitors (CIN1) to the third capacitor (C3). A current path (n) can be formed from the second capacitor (C2) through the third capacitor (C3) to the first output node (ON1). Thus, the third capacitor (C3) can integrate the charges of the second capacitor (C2) together with the first input signal. Additionally, a current path (o) is formed so that the first gain capacitor (CS1) can integrate the first input signal. Accordingly, the first sampling signal can be output through the first output node (ON1). In this way, the second and third capacitors (C2, C3), the first gain capacitor (CS1), and the amplifier circuit (AMPC) can function as a z-to-z transformed SC integrator for the first input signal, for example, as a high-pass filter.

[0141] Similarly, a current path (p) can be formed from the second input node (IN2) through the second input capacitors (CIN2) to the eighth capacitor (C8). A current path (q) can be formed from the seventh capacitor (C7) through the eighth capacitor (C8) to the second output node (ON2). Thus, the eighth capacitor (C8) can integrate the charges of the seventh capacitor (C7) together with the second input signal. Additionally, a current path (r) is formed so that the second gain capacitor (CS2) can integrate the second input signal. Accordingly, the second sampling signal can be output through the second output node (ON2). In this way, the seventh and eighth capacitors (C7, C8), the second gain capacitor (CS2), and the amplifier circuit (AMPC) can function as a z-to-z transformed SC integrator for the second input signal, for example, a high-pass filter.

[0142] Referring again to FIG. 15, in the second time period (T2), the control signals (P1, PS1) are enabled to a high level. The first and second input capacitors (CIN1, CIN2) and the first and second gain capacitors (CS1, CS2) can be initialized.

[0143] The second cycle (CYC2) may include a third time period (T3) and a fourth time period (T4). In the second cycle (CYC2), the control signal (PS4) is enabled to a high level. The third cycle (CYC3) may include a fifth time period (T5) and a sixth time period (T6). In the third cycle (CYC3), the control signal (PS3) is enabled to a high level, as in the first cycle (CYC1). Hereinafter, for convenience of explanation, the third cycle (CYC3) is described prior to the second cycle (CYC2).

[0144] In the fifth time period (T5), the control signals (PDS1, P2, PS3, PS7) have a high level. Switches receiving the high-level control signals (PDS1, P2, PS3, PS7) can be turned on.

[0145] Referring to FIG. 17, a current path(s) can be formed from the first input node (IN1) to the first output node (ON1) through the first input capacitors (CIN1) and the second capacitor (C2). A current path(t) can be formed from the third capacitor (C3) to the second capacitor (C2). Thus, the second capacitor (C2) can integrate the charges of the third capacitor (C3) together with the first input signal. In this way, the second and third capacitors (C2, C3) alternately perform integration with the first input signal during the first and fifth time periods (T1, T5), and each of the second and third capacitors (C2, C3) can perform integration with the first input signal together with the charges stored in the other capacitor when performing the integration. Additionally, a current path (u) is formed so that the first gain capacitor (CS1) can integrate the first input signal. In this way, the second and third capacitors (C2, C3), the first gain capacitor (CS1), and the amplifier circuit (AMPC) can function as a z-to-z transformed SC integrator for the first input signal, for example, a high-pass filter, to output a first sampling signal to the first output node (ON1).

[0146] Similarly, a current path (v) can be formed from the second input node (IN2) to the second output node (ON2) through the second input capacitors (CIN2) and the seventh capacitor (C7). A current path (w) can be formed from the eighth capacitor (C8) to the seventh capacitor (C7). Thus, the seventh capacitor (C7) can integrate the charges of the eighth capacitor (C8) together with the second input signal. In this way, the seventh and eighth capacitors (C7, C8) alternately perform integration with the second input signal during the first and fifth time periods (T1, T5), and each of the seventh and eighth capacitors (C7, C8) can perform integration with the second input signal together with the charges stored in the other capacitor when performing the integration. Additionally, a current path (x) is formed so that the second gain capacitor (CS2) can integrate the second input signal. In this way, the seventh and eighth capacitors (C7, C8), the second gain capacitor (CS2), and the amplifier circuit (AMPC) can function as a z-to-z transformed SC integrator for the second input signal, for example, a high-pass filter, to output a second sampling signal to the second output node (ON2).

[0147] Referring again to FIG. 15, in the sixth time period (T6), the control signals (P1, PS1) are enabled to a high level. The first and second input capacitors (CIN1, CIN2) and the first and second gain capacitors (CS1, CS2) can be initialized.

[0148] In the third time period (T3) of the second cycle (CYC2), the control signals (P2, PS4, PS6) have a high level. Switches receiving the high-level control signals (P2, PS4, PS6) can be turned on.

[0149] Referring to FIG. 18, a current path (y) can be formed from the first input node (IN1) to the fifth capacitor (C5). A current path (z) can be formed from the fourth capacitor (C4) through the fifth capacitor (C5) to the first output node (ON1). Thus, the fifth capacitor (C5) can integrate the charges of the fourth capacitor (C4) together with the first input signal. Additionally, a current path (aa) is formed so that the first gain capacitor (CS1) can integrate the first input signal. In this way, the fourth and fifth capacitors (C4, C5), the first gain capacitor (CS1), and the amplifier circuit (AMPC) can function as a z-to-z transformed SC integrator for the first input signal, for example, a high-pass filter, to output a first sampling signal through the first output node (ON1).

[0150] A current path (bb) can be formed from the second input node (IN2) to the tenth capacitor (C10). A current path (cc) can be formed from the ninth capacitor (C9) through the tenth capacitor (C10) to the second output node (ON2). Thus, the tenth capacitor (C10) can integrate the charges of the ninth capacitor (C9) together with the second input signal. Additionally, a current path (dd) is formed so that the second gain capacitor (CS2) can integrate the second input signal. In this way, the ninth and tenth capacitors (C9, C10), the second gain capacitor (CS2), and the amplifier circuit (AMPC) can function as a z-to-z transformed SC integrator for the second input signal, for example, a high-pass filter, to output a second sampling signal through the second output node (ON2).

[0151] Referring again to FIG. 15, in the fourth time period (T4), the control signals (P1, PS1) are enabled to a high level. The first and second input capacitors (CIN1, CIN2) and the first and second gain capacitors (CS1, CS2) can be initialized.

[0152] The fourth cycle (CYC4) may include the seventh time period (T7) and the eighth time period (T8). As in the second cycle (CYC2), the control signal (PS4) is enabled to a high level.

[0153] In the 7th time period (T7), the control signals (P2, PS4, PS8) have a high level. Switches receiving the high-level control signals (P2, PS4, PS8) can be turned on.

[0154] Referring to FIG. 19, a current path (ee) can be formed from the first input node (IN1) through the fourth capacitor (C4) to the first output node (ON1). A current path (ff) can be formed from the fifth capacitor (C5) to the fourth capacitor (C4). Thus, the fourth capacitor (C4) can integrate the charges of the fifth capacitor (C5) together with the first input signal. In this way, the fourth and fifth capacitors (C4, C5) alternately perform integration with respect to the first input signal during the third and seventh time periods (T3, T7), and each of the fourth and fifth capacitors (C4, C5) can perform integration with respect to the first input signal together with the charges stored in the other capacitor when performing the integration. Additionally, a current path (gg) is formed so that the first gain capacitor (CS1) can integrate the first input signal. In this way, the fourth and fifth capacitors (C4, C5), the first gain capacitor (CS1), and the amplifier circuit (AMPC) can function as a z-to-z transformed SC integrator for the first input signal, for example, a high-pass filter, to output the first sampling signal through the first output node (ON1).

[0155] A current path (hh) can be formed from the second input node (IN2) through the ninth capacitor (C9) to the second output node (ON2). A current path (ii) can be formed from the tenth capacitor (C10) to the ninth capacitor (C9). Thus, the ninth capacitor (C9) can integrate the charges of the tenth capacitor (C10) together with the second input signal. In this way, the ninth and tenth capacitors (C9, C10) alternately perform integration with respect to the second input signal during the third and seventh time periods (T3, T7), and each of the ninth and tenth capacitors (C9, C10) can perform integration with respect to the second input signal together with the charges stored in the other capacitor when performing the integration. Additionally, a current path (jj) is formed so that the second gain capacitor (CS2) can integrate the second input signal. In this way, the 9th and 10th capacitors (C9, C10), the second gain capacitor (CS2), and the amplifier circuit (AMPC) can function as a z-to-z transformed SC integrator for the second input signal, for example, a high-pass filter, to output a second sampling signal through the second output node (ON2).

[0156] Referring again to FIG. 15, in the eighth time period (T8), the control signals (P1, PS1) are enabled to a high level. The first and second input capacitors (CIN1, CIN2) and the first and second gain capacitors (CS1, CS2) can be initialized.

[0157] According to the high-pass filters provided in this manner, a single-ended mode band-pass filter circuit for filtering a first input signal and a single-ended mode band-pass filter circuit for filtering a second input signal can be implemented. The center frequency of each band-pass filter circuit is fs / 4, and the gain value of each band-pass filter circuit can be CIN / 4CS (CIN is the capacitance of one input capacitor, and CS is the capacitance of one gain capacitor). The Q factor of each band-pass filter circuit can be adjusted according to the capacitances of the second to fifth capacitors (C2~C5), the seventh to tenth capacitors (C7~C10), and the first and second gain capacitors (CS1, CS2).

[0158] Although specific embodiments and applications have been described herein, other embodiments and variations may be derived from the above description. Accordingly, the scope of the invention is not limited to these embodiments but extends to the claims set forth below, various obvious variations, and equivalents. Explanation of the symbols

[0159] 100: Sensor device 110: Sensor array 120: Sensor actuator TDC: Sensor transmitter TSC: Sensor receiver DSP: Signal Processor AFEG: Analog shear group BPF: Band Pass Filter

Claims

Claim 1 An amplifier circuit having a first input terminal for receiving a first analog signal, a second input terminal for receiving a second analog signal, and first and second output terminals; A bandpass filter circuit comprising a plurality of capacitors and switches connected to the plurality of capacitors, wherein when at least some of the plurality of capacitors are provided as a first group of capacitors connected between the first and second input terminals and the first and second output terminals by controlling the switches, the amplifier circuit and the first group of capacitors operate as a first bandpass filter that filters the first and second analog signals in a differential mode, and when at least some of the plurality of capacitors are provided as a second group of capacitors connected between the first input terminal and the first output terminal and a third group of capacitors connected between the second input terminal and the second output terminal by controlling the switches, the amplifier circuit, the second group of capacitors, and the third group of capacitors operate as second bandpass filters that filter each of the first and second analog signals in a single-ended mode. Claim 2 In claim 1, the second band-pass filters are a band-pass filter circuit that shares one or more of the plurality of capacitors with the first band-pass filter. Claim 3 In claim 1, at least one of the capacitors in the second group and at least one of the capacitors in the third group are band-pass filter circuits included in the capacitors in the first group. Claim 4 A band-pass filter circuit according to claim 1, wherein the amplifier circuit and the second group of capacitors are configured to be included in one of the second band-pass filters to filter the first analog signal, and the amplifier circuit and the third group of capacitors are configured to be included in the other of the second band-pass filters to filter the second analog signal. Claim 5 In claim 1, the amplifier circuit comprises a first input terminal as an inverting input terminal, a second input terminal as a non-inverting input terminal, a first output terminal as a non-inverting output terminal, and a second output terminal as an inverting output terminal, forming a band-pass filter circuit. Claim 6 A band-pass filter circuit according to claim 1, wherein the plurality of capacitors comprises: a first gain capacitor connected between the first input terminal and the first output terminal; and a second gain capacitor connected between the second input terminal and the second output terminal. Claim 7 A band-pass filter circuit according to claim 1, further comprising: first input capacitors connected in series to the first input terminal; and second input capacitors connected in series to the second input terminal, wherein the first analog signal is transmitted to the first input terminal through the first input capacitors and the second analog signal is transmitted to the second input terminal through the second input capacitors. Claim 8 A bandpass filter circuit according to claim 1, wherein in the second bandpass filter, each of the first and second capacitors among the second group of capacitors is configured to alternately perform integration over the first analog signal to output a first sampling signal, and wherein when the first capacitor performs integration over the first analog signal, it is connected to the second capacitor through a first connection node to perform integration over the charges of the second capacitor together with the first analog signal to output the first sampling signal. Claim 9 In claim 8, the second bandpass filter circuit is configured such that, when performing integration with the first analog signal, the second capacitor is connected to the first capacitor through the first connection node and performs integration with the charges of the first capacitor together with the first analog signal to output the first sampling signal. Claim 10 In claim 8, the second bandpass filter circuit is configured such that, in the second bandpass filter, each of the third and fourth capacitors among the third group of capacitors is configured to alternately perform integration over the second analog signal to output a second sampling signal, wherein when the third capacitor performs integration over the second analog signal, it is connected to the fourth capacitor through a second connection node to perform integration over the charges of the fourth capacitor together with the second analog signal to output the second sampling signal. Claim 11 In claim 10, the bandpass filter circuit is configured such that, in the second bandpass filter, the fourth capacitor is connected to the third capacitor through the second connection node when performing integration with the second analog signal, and performs integration with the charges of the third capacitor together with the second analog signal to output the second sampling signal. Claim 12 A bandpass filter circuit according to claim 1, wherein in the first bandpass filter, the first capacitor among the first group of capacitors is configured to perform integration with respect to the first analog signal and output a first sampling signal through the first output terminal, and the second capacitor among the first group of capacitors is configured to be connected to the first capacitor through a first connection node to store charges of the first capacitor. Claim 13 A bandpass filter circuit according to claim 12, wherein in the first bandpass filter, when the first capacitor performs integration with respect to the first analog signal, the second capacitor is connected to the third capacitor among the first group of capacitors through a second connection node, and the third capacitor performs integration with respect to the charges of the second capacitor together with the second analog signal, and is configured to output a second sampling signal through the second output terminal. Claim 14 A sensor driver comprising: a sensor array; and a band-pass filter circuit configured to filter first and second analog signals received from the sensor array, wherein the band-pass filter circuit comprises: an amplifier circuit having a first input terminal for receiving a first analog signal, a second input terminal for receiving a second analog signal, a first output terminal, and a second output terminal; A sensor device comprising a plurality of capacitors and switches connected to the plurality of capacitors, wherein when at least some of the plurality of capacitors are provided as a first group of capacitors connected between the first and second input terminals and the first and second output terminals by controlling the switches, the amplifier circuit and the first group of capacitors operate as a first bandpass filter that filters the first and second analog signals in a differential mode, and when at least some of the plurality of capacitors are provided as a second group of capacitors connected between the first input terminal and the first output terminal and a third group of capacitors connected between the second input terminal and the second output terminal by controlling the switches, the amplifier circuit, the second group of capacitors, and the third group of capacitors operate as second bandpass filters that filter each of the first and second analog signals in a single-ended mode. Claim 15 In claim 14, the sensor driver controls the switches to operate the band-pass filter circuit as the first band-pass filter to detect a touch input of a body based on the first and second analog signals, and controls the switches to operate the band-pass filter circuit as the second band-pass filters to detect a touch input of a pen based on the first and second analog signals. Claim 16 In claim 14, the sensor device wherein the second band-pass filters share one or more of the plurality of capacitors with the first band-pass filter. Claim 17 In claim 14, at least one of the capacitors in the second group and at least one of the capacitors in the third group are included in the capacitors in the first group, forming a sensor device. Claim 18 A sensor device according to claim 14, wherein the amplifier circuit and the second group of capacitors are configured to be included in one of the second bandpass filters to filter the first analog signal, and the amplifier circuit and the third group of capacitors are configured to be included in the other of the second bandpass filters to filter the second analog signal.

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