Substrate for packaging, semiconductor package, method for manufacturing a substrate for packaging and method for manufacturing a semiconductor package

Abstract

A packaging substrate is provided. The packaging substrate includes a first region that does not include a cavity and a second region that includes a cavity. The first region includes a first surface and a second surface facing each other, and the cavity structure of the second region includes a cavity space; a contact surface; and a side wall. The contact surface is positioned opposite to an opening of the cavity structure. The surface roughness value of the contact surface is about three times or less the surface roughness value of the first surface of the first region.

Description

Technology Field

[0001] [Cross-reference of related applications]

[0002] This application claims priority to U.S. provisional application No. 63 / 238,308 filed on August 30, 2021, the contents of said patent document are incorporated herein by reference.

[0003] The following content relates to a substrate for packaging, a semiconductor package, a method for manufacturing a substrate for packaging, and a method for manufacturing a semiconductor package, etc. Background Technology

[0004] In the manufacturing of electronic components, implementing circuits on a semiconductor wafer is called the Front-End (FE) process, and assembling the wafer into a state usable in an actual product is called the Back-End (BE) process. The packaging process is included in the back-end process.

[0005] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. While semiconductor technology is evolving into various forms, such as sub-micron and nano-scale linewidths, more than ten million cells, high-speed operation, and high heat dissipation, packaging technology has not been able to perfectly support this. Consequently, the electrical performance of packaged semiconductors is sometimes determined by packaging technology and the resulting electrical connections rather than by the performance of the semiconductor itself.

[0006] Ceramic or resin materials are used for packaging substrates. In the case of ceramic substrates, such as silicon substrates, it is difficult to mount high-performance, high-frequency semiconductor devices due to high resistance or dielectric constant. In the case of resin substrates, it is possible to mount relatively high-performance, high-frequency semiconductor devices. However, there are limitations in reducing the wiring pitch.

[0007] Recently, silicon or glass can be used as substrates for high-end packaging. By forming through-holes in silicon or glass substrates and applying conductive materials to these through-holes, the wiring length between the device and the motherboard can be shortened, and excellent electrical characteristics can be achieved.

[0008] In addition, semiconductor packages may generate heat during operation, and additional heat dissipation means may be included to release this heat. Relevant prior art includes Korean Published Patent Application No. 10-2019-0008103, Korean Published Patent Application No. 10-2016-0114710, and Korean Registered Patent Application No. 10-1468680. The problem to be solved delete means of solving the problem

[0009] [Problem to be Solved] The purpose of the embodiment is to provide a substrate for packaging, a semiconductor package, a method for manufacturing a substrate for packaging, and a method for manufacturing a semiconductor package, which have excellent integration density, simplified manufacturing processes, and are applicable to high-frequency high-performance packages. This summary is presented to introduce the detailed description of the invention described below in a simple conceptual manner. This summary is not intended to identify the main or essential features of the claimed claims, nor is it intended to aid in determining the scope of the claimed claims.

[0010] In one embodiment, a substrate for packaging includes a first region and a second region, wherein the first region is a region where a cavity structure is not disposed, and the second region is a region where a cavity structure is disposed, and the first region has a first surface and a second surface facing each other, and the cavity structure includes a cavity space, a contact surface and a side wall, the cavity space is a recessed space of the cavity structure, the cavity space includes an opening disposed on the upper or lower part of the cavity structure, the contact surface is a surface disposed opposite to the opening of the cavity space, the side wall is a wall surrounding the contact surface, and the surface roughness value of the contact surface is about three times or less of the surface roughness value of the first surface of the first region.

[0011] The first region and the second region may be arranged adjacent to each other.

[0012] The surface roughness of the above contact surface may be 20 nm or less.

[0013] The above side wall can connect the first surface of the first region and the contact surface, and can have an angle of 75 to 100 degrees based on a line parallel to the second surface of the first region.

[0014] The substrate of the first region may include a glass substrate, and the substrate of the second region includes a glass substrate, and the glass substrate of the first region and the glass substrate of the second region are connected to each other.

[0015] The second region may have a first surface and a second surface facing each other, and the first distance, which is the distance between the first surface of the second region and the second surface of the second region, is 0.3 to 0.7 times the second distance, which is the distance between the first surface of the first region and the second surface of the first region.

[0016] The above first distance may be 100 μm or more.

[0017] The second area above may include a frame, and the frame may divide the cavity space into two or more zones.

[0018] The second region may further include a cavity that penetrates the packaging substrate.

[0019] A semiconductor package may include a substrate for packaging; an upper redistribution layer disposed on the first surface of the first region; and a connection portion disposed under the second surface of the first region.

[0020] Passive components may be placed in the above cavity space.

[0021] Other features and aspects will become apparent from the detailed description, drawings, and claims set forth below. Effects of the invention

[65535] The packaging substrate and semiconductor package of the embodiment have excellent integration density and can be applied as high-frequency, high-performance packages. The manufacturing method of the packaging substrate and semiconductor package of the embodiment allows for the formation of vias with complex structures or large-area cavities to be manufactured in a relatively short time using a relatively simplified manufacturing process. Brief explanation of the drawing

[0022] FIG. 1 is a perspective view illustrating one example of a substrate for packaging according to one or more embodiments. FIG. 2 is a conceptual diagram illustrating the AA' cross-section of FIG. 1. FIG. 3 is another conceptual diagram illustrating the AA' section of FIG. 1. FIG. 4 is a perspective view illustrating one example of a substrate for packaging according to one or more embodiments. FIG. 5 is a conceptual diagram illustrating the BB' cross-section of FIG. 4. FIG. 6 is a perspective view illustrating one example of a substrate for packaging according to one or more embodiments. FIG. 7 is a conceptual diagram illustrating the XX' cross-section of FIG. 6. FIG. 8 is a diagonal downward view of a substrate for packaging manufactured according to one embodiment. FIG. 9 is the result of AFM analysis of the surface of a glass substrate manufactured as a packaging substrate according to one or more embodiments before primary etching. FIG. 10 is the result of AFM analysis of the surface of the glass substrate of FIG. 9 after the first etching, according to one or more embodiments. FIG. 11 is a photograph showing the surface of a glass substrate etched after irradiating it with a laser according to one or more embodiments. Throughout the drawings and detailed description, the same reference numerals indicate the same or similar configurations. Drawings may not be presented to scale, and for clarity, descriptiveness, and convenience, the relative sizes, proportions, and depictions of elements within the drawings may be exaggerated. Specific details for implementing the invention

[0023] To facilitate a comprehensive understanding of the methods, apparatuses, and / or systems described herein, the following detailed description is provided. However, various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described herein will become apparent after understanding the contents presented in this application. For example, the order of operations described herein is merely illustrative and is not limited to the operations described herein; the order of operations may be changed according to an understanding of the contents presented in this application, except for steps that must proceed in a specific order. Furthermore, descriptions of already known features may be omitted to enhance clarity and conciseness after understanding the disclosure of this application; however, such omission of features and descriptions is not intended to be accepted as general knowledge.

[0024] The features described herein may be implemented in different forms and are not to be interpreted as being limited to the examples described herein. Rather, the embodiments described herein are provided to illustrate some of the many possible methods, devices, and / or systems described herein that will become apparent after understanding the disclosure of this application.

[0025] In this specification, terms such as “first,” “second,” “third,” etc., may be used to describe various members, components, regions, layers, or sections, but are not to limit these members, components, regions, layers, or sections to these words. Instead, these terms are used for the purpose of distinguishing one member, component, region, layer, or section from another member, component, region, layer, or section. Accordingly, a first member, component, region, layer, or section mentioned in the embodiments described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the embodiments.

[0026] Throughout the specification, where an element, such as a layer, region, or substrate, is described as being "on," "connected to," or "bonded to" another element, it may be described as being directly "on," "connected to," or "bonded" to the other element, or one or more other elements may be interposed between them. In contrast, when an element is described as being "directly on," "directly connected to," or "directly bonded," no other elements may intervene between them. Likewise, expressions such as, for example, "between" and "directly between," and "contacting" and "directly contacting," may be interpreted as described above.

[0027] The terms used in this specification are for describing specific examples only and are not intended to limit the disclosure. The singular forms used in this specification are intended to include the plural forms unless the context clearly indicates otherwise. The term “and / or” used in this specification includes any one or more combinations of the related listed items. The terms “comprising,” “composing,” and “holding” used in this specification specify the presence of the specified features, numbers, actions, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, actions, elements, components, and / or combinations thereof. The use of the term “may” in relation to an example or embodiment (e.g., what an example or embodiment may include or implement) means that there is at least one example or embodiment in which such features are included or implemented, but not all examples are limited thereto.

[0028] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as generally understood by any of the ordinary art in the field to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with that in the context of the prior art and embodiments, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0029] In the above examples, the “~” system may mean that the compound contains a compound corresponding to “~” or a derivative of “~”.

[0030] In the above examples, the meaning that B is located on A means that B is located in direct contact with A or that B is located on A with another layer in between, and is not interpreted as being limited to B being located in contact with the surface of A.

[0031] In the above examples, the statement that B is connected to A means that A and B are directly connected or connected through other components between A and B, and unless otherwise specified, it is not interpreted as being limited to a direct connection between A and B.

[0032] In the above examples, the singular form is contextually interpreted to include not only the singular form but also the plural form, unless otherwise specifically noted.

[0033] In the above examples, the length, thickness, angle, ratio, etc. of the drawings may be expressed in an exaggerated manner, and the above examples cannot be interpreted as having rights restricted due to such exaggeration.

[0034] The above examples can be integrated into a simplified manufacturing process and applied to high frequency, high-performance packages.

[0035] One or more examples provide a substrate for packaging, a semiconductor package, a method for manufacturing a substrate for packaging, and a method for manufacturing a semiconductor package, which can be excellently integrated by a simplified manufacturing process and can be applied to high frequency, high performance packages.

[0036] The packaging substrate and semiconductor package of the embodiment can be excellently integrated and can be applied to high frequency and high performance packages.

[0037] The method for manufacturing a substrate for packaging and the method for manufacturing a semiconductor package can manufacture vias formed with complex structures or cavities formed with large areas within a significantly reduced time by executing a relatively simplified manufacturing process.

[0038] The following will be described in more detail regarding the embodiments.

[0039] Substrate for packaging

[0040] FIG. 1 is a perspective view illustrating an example of a substrate for packaging, FIG. 2 is a conceptual diagram illustrating a cross-section AA' of FIG. 1, and FIG. 3 is another conceptual diagram illustrating a cross-section AA' of FIG. 1. Hereinafter, a substrate for packaging will be described in detail with reference to FIG. 1 to 3.

[0041] A packaging substrate (200) according to one or more examples includes a G region and a C region that are distinct from each other. The C region is a region where a cavity structure is arranged, and the G region is a region where a cavity structure is not arranged. The G region and the C region may be arranged adjacent to each other. The packaging substrate (200) may include one C region and may include two or more C regions.

[0042] The G region has a first-1 surface (211) and a first-2 surface (212), and the first-1 surface (211) and the first-2 surface (212) face each other. In the G region, the first-1 surface (211) and the first-2 surface (212) are arranged flatly side by side, and, for example, the first-1 surface (211) and the first-2 surface (212) may be substantially parallel. In a non-limiting example, the G region may include a glass substrate.

[0043] Region G may include one or more through vias (23). The through vias (23) may be formed by penetrating from the first-1 surface (211) to the first-2 surface (212), and the opening (not shown) may be generally circular. However, the through vias are not limited to having a circular opening, but may be circular, elliptical, square, etc.

[0044] For example, region C may include a cavity structure.

[0045] The above cavity structure refers to a structure that includes a recess in a part of the packaging substrate (200) so as to substantially allow a component to be placed inside the packaging substrate (200). The space formed by the recess is called a cavity space.

[0046] The cavity structure includes a cavity space (25); a contact surface (255); and a side wall (253).

[0047] The cavity space (25) is a space formed by a sinkhole and has an opening at the top or bottom.

[0048] The contact surface (255) comes into direct contact with the element or through another layer when the element is placed in the cavity. The contact surface (255) is positioned opposite the opening.

[0049] The side wall (253) is a wall surrounding the contact surface (255). If the contact surface (255) has a rectangular shape, the side wall (253) may include four faces. If the contact surface (255) is circular, the side wall (253) may, for example, generally have a cylindrical, truncated conical, or hourglass shape.

[0050] The side wall (253) connects the first-1 surface (211) and the contact surface (255).

[0051] As a non-limiting example, one or more cavity structures may be placed within area C. If two or more cavity structures are placed within area C, the cavity space may be separated by one or more frames (257).

[0052] That is, a frame (257) may be further disposed in the above C area, and the frame (257) may divide the cavity space (25) into two or more cavities.

[0053] The side wall (253) can connect adjacent contact surfaces (255) and the frame (257).

[0054] Referring to FIG. 3, region C has a second-1 surface (251) and a second-2 surface (252) facing each other. In region C, which includes a plurality of cavity structures, each cavity structure includes a contact surface (255), and this contact surface (255) becomes the second-1 surface (251) or the second-2 surface (252).

[0055] The frame (257) may include glass. For example, bar-shaped glass may be applied as the frame.

[0056] The upper surface of the frame can be positioned substantially identically to the first-1 surface. The upper surface of the frame can be positioned substantially identically to the first-2 surface. In this example, it is easier to form a redistribution layer on the upper surface of the frame.

[0057] The cavity space may be positioned above the center of the packaging substrate (see FIG. 2). The cavity space may be positioned below the center of the packaging substrate (not shown). The cavity space may be positioned both above and below the center of the packaging substrate (see FIG. 3).

[0058] Among the substrates for packaging, if the upper surface is the 2-1 surface (251) and the lower surface is the 2-2 surface (252), the contact surface is the 2-1 surface (251) when the cavity space is located at the top, and the 2-2 surface (252) when the cavity space is located at the bottom.

[0059] The above-mentioned second-1 surface (251) and the above-mentioned second-2 surface (252) may face each other. The above-mentioned second-1 surface (251) and the above-mentioned second-2 surface (252) may be arranged flatly side by side with each other, and, for example, substantially parallel. Region C may include a glass substrate.

[0060] In regions G and C, the substrate for packaging may be provided with a glass substrate (21) of substantially the same material. As a non-limiting example, regions G and C may be formed integrally.

[0061] The above glass may be any glass applied to a substrate for packaging, and may include borosilicate glass, alkali-free glass, etc., but is not limited thereto.

[0062] A packaging substrate (200) can be applied by processing a glass substrate into the shape described above. A packaging substrate having through-vias, cavity structures, etc., can be obtained by processing a single sheet of glass, such as by masking or forming defects, and then etching it. A specific processing method will be described later.

[0063] CRa is the surface roughness Ra (arithmetic mean roughness value) at the contact surface (255), and GRa is the surface roughness Ra at the first-1 surface (211). The packaging substrate (200) has the characteristic that CRa is about 3 times or less of GRa.

[0064] The first-1 surface (211) and the contact surface (255) are allowed to come into contact with the device directly or through another layer. The device must be connected to an electrically conductive layer called a redistribution line so that it can receive or transmit signals. In cases where the device and the surface come into direct contact, as well as in cases where the device comes into contact through another layer, the surface roughness can affect the physical properties of the surface that comes into direct contact with the device. It has been confirmed that as the width and spacing of the redistribution line become finer, the aforementioned surface roughness can affect the formation of the redistribution line. Therefore, the surface roughness of the surfaces on which the redistribution line is placed needs to be controlled.

[0065] In the above examples, CRa may be about 2.5 times or less than GRa, and about 2 times or less. CRa may be about 1.8 times or less than GRa, and about 1.7 times or less. CRa may be about 0.1 times or more than GRa, and about 0.3 times or more. When surface roughness is controlled within this range, it becomes more advantageous for forming fine redistribution lines, and it becomes possible to manufacture thinner semiconductor packages.

[0066] CRa may be a value smaller than GRa. In one or more examples, the device placed in the cavity space may be thinner than the device typically mounted on the packaging substrate, or may be a device with both thickness and size smaller. Accordingly, the surface roughness of the contact surface (255) is preferably controlled to a significantly small level, for example, CRa may be about 20 nm or less, about 10 nm or less, or about 5 nm or less. CRa may be about 0.1 nm or more.

[0067] CRq is the surface roughness Rq (Root mean squared roughness) at the contact surface (255), and GRq is the surface roughness Rq at the first-1 surface (211). The substrate for packaging (200) has the characteristic that CRq is about twice or less than GRq.

[0068] In one or more examples, CRq may be about 1.8 times or less than GRq, or about 1.7 times or less. CRq may be about 0.1 times or more than GRq, or about 0.3 times or more. When surface roughness is controlled within this range, it becomes more advantageous for forming fine redistribution lines, and it may be possible to manufacture thinner semiconductor packages.

[0069] In the case of a substrate for packaging in which a pre-leg is applied as an interposer, it is practically difficult to lower the surface roughness due to the inherent properties of the glass fiber and the polymer itself. Furthermore, it is rare to indent the pre-leg itself to form a cavity structure. Although a cavity structure can be formed by applying punching, etc., rather than forming a cavity structure like the embodiment, a cavity structure that penetrates from top to bottom can be formed.

[0070] In the case of a glass substrate, a three-dimensional structure such as vias is formed by utilizing the characteristic that the defective part is etched faster than the defect-free part. For example, a defect is partially formed in the glass by irradiating it with a laser, and vias are formed in the defective area by etching.

[0071] Even when forming a cavity in a glass substrate, multiple defects can be formed in the glass by densely irradiating the portion that will become the cavity depression at regular intervals with a laser. During the etching process, the defects are connected to each other to form the cavity depression.

[0072] Since laser irradiation typically proceeds in the form of points or lines, defects are formed as points or lines rather than as surfaces, and due to the difference in the degree of etching between the defective area and its surroundings, the etched surface (the bottom or top surface of the cavity) has a significantly rough surface. Typically, it may have a surface roughness Ra of about 10 μm or more (see Fig. 11, where the surface roughness Ra at the bottom of the cavity is about 16 μm).

[0073] In an embodiment, the surface excluding the location to form the cavity space (25) among the G region and the C region may be masked, and after first forming the recessed portion of the cavity by a method such as etching (first etching), laser irradiation for forming vias, etc. may be performed. Afterward, additional etching (second etching) methods may be applied. Specific methods will be described later.

[0074] When a cavity space is formed without the formation of separate point- or line-shaped defects in this way, the surface shape of the etching surface (bottom or top surface of the cavity) can be controlled relatively easily, and it is possible to provide an etching surface that does not differ significantly from the surface roughness of the G region (refer to FIGS. 8 to 10; surface roughness before processing in FIG. 9 Rq: 1.041 nm, Ra: 0.796 nm, surface roughness before processing in FIG. 10 Rq: 1.730 nm, Ra: 1.306 nm).

[0075] The controlled surface roughness of the bottom or top surface of the cavity provides a basis for forming a sophisticated electrically conductive layer in the cavity space, which helps to facilitate device placement in the cavity space.

[0076] When the surface roughness is high on the bottom or top surface of the cavity, a method of flattening the surface through an insulating layer can be considered, but this may unnecessarily thicken the substrate for packaging, complicate the process, and make it substantially difficult to form through-vias (cavity vias, 255a) on the bottom or top surface of the cavity.

[0077] The side wall (253) can connect the first-1 surface (211) and the contact surface (255), and, for example, may have an angle of about 75 degrees to about 100 degrees with respect to a line parallel to the first-2 surface (212). For example, the angle may be about 80 degrees to about 95 degrees, and may be about 85 degrees to about 92 degrees. A side wall having such an angle can reduce the possibility of void formation between the device placed in the cavity space and the side wall during the semiconductor packaging manufacturing process.

[0078] Dg is the thickness of the substrate for packaging in the region where the cavity structure is not formed, and Dc is the thickness of the substrate for packaging in the cavity space. That is, Dg is the distance between the first-1 surface (211) and the first-2 surface (212), and Dc is the distance between the second-1 surface (251) and the second-2 surface (252).

[0079] As an example, the length Dc may be 0.3 to 0.7 times the length Dg.

[0080] As an example, the length Dc may be 0.3 to 0.55 times the length Dg.

[0081] With this thickness ratio, it is possible to provide a durable packaging substrate while sufficiently performing the support performance of the packaging substrate.

[0082] For example, the length Dc may be about 100 μm, about 150 μm, about 200 μm, or about 300 μm. Such a Dc value can enable the device to have support performance, durability, etc., even in a cavity region having a relatively thin substrate thickness.

[0083] The above length Dg may be about 300 μm or more, about 400 μm or more, or about 500 μm or more. The above length Dg may be about 3000 μm or less, about 2500 μm or less, about 2000 μm or less, or about 1000 μm or less.

[0084] The substrate for packaging may be a glass substrate. Regions G and C are each glass substrates and can be connected to form a single unit. The frame may be made of glass material, and the glass substrate of region C and the frame made of glass material can be connected to form a single unit.

[0085] The framework of the packaging substrate may be a glass substrate. The framework of the packaging substrate refers to a substrate prepared before forming an electrically conductive layer or an insulating layer.

[0086] The packaging frame may have a G region and a C region derived from one glass substrate. The packaging frame may have a cavity structure and a frame derived from one glass substrate.

[0087] FIG. 4 is a perspective view illustrating another example of a substrate for packaging, and FIG. 5 is a conceptual diagram illustrating the BB' cross section of FIG. 4. FIG. 6 is a perspective view illustrating an example of a substrate for packaging, and FIG. 7 is a conceptual diagram illustrating the XX' cross section of FIG. 6. A substrate for packaging according to one or more embodiments will be described in detail with reference to FIG. 4 to 7.

[0088] A packaging substrate according to one or more embodiments is a packaging substrate including a G region and a C region, and all the descriptions above regarding each region, cavity structure, contact surface, roughness, etc. apply to this embodiment as well.

[0089] As an example, region C may include a through-via.

[0090] For example, a through-via penetrating the contact surface may be placed in region C. This through-via is referred to as a cavity via (255a) to distinguish it from the through-via in region G. The cavity via (255a) penetrates the cavity substrate from the second-1 surface (251) to the second-2 surface (252).

[0091] An electrically conductive layer may be disposed within the via of the cavity space (255a). The electrically conductive layer may connect the device disposed in the cavity space (25) with another device disposed on the packaging substrate or a motherboard (not shown) disposed under the packaging substrate.

[0092] The cavity allows a short distance connection between the cavity space and one side of the packaging substrate by penetrating the packaging substrate. The term "connection" refers to a connection that enables electrical signal transmission through an electrically conductive layer such as copper. For example, the connection may be a connection by a redistribution line.

[0093] For example, a through-via that penetrates the frame may be placed in area C. To distinguish this through-via from the through-via in area G, it is called a frame via (257a).

[0094] Referring to FIG. 4, the frame via (257a) penetrates one side of the frame.

[0095] If the C region includes a cavity space located at the bottom of the substrate, the frame via (257a) can penetrate the cavity substrate from one side of the frame to the second-1 side (251).

[0096] If the C region includes a cavity space positioned on the upper surface of the substrate, the frame via (257a) can penetrate the cavity substrate from one side of the frame to the second-second side (252).

[0097] If region C includes a cavity space vertically, the frame via (257a) can penetrate the packaging substrate from one side of the upper frame to one side of the lower frame.

[0098] The frame via (257a) penetrates the packaging substrate and allows the C region to connect the upper and lower surfaces over a short distance. At this time, the term "connection" refers to a connection that enables electrical signal transmission through an electrically conductive layer such as copper. For example, the connection may be a connection by a redistribution line.

[0099] A semiconductor package can be configured such that a device (cavity device) is positioned within a cavity space and the semiconductor device is mounted on one side of a packaging substrate. In this case, a frame via allows one side of the packaging substrate to be connected to the other side by a short distance.

[0100] A semiconductor package may place a computational element (or memory element) on a first surface, place a motherboard, etc. on a second surface, and place a power transfer element in a cavity space. The cavity via (255a) allows the computational element (or memory element) and the motherboard, etc. to be connected over a short distance. The cavity via (255a) allows the power transfer element and the computational element (or memory element), and the power transfer element and the motherboard, etc. to be connected over a short distance.

[0101] Such short-distance connections allow for rapid signal transmission and are particularly advantageous for packaging high-frequency, high-performance devices.

[0102] The cavity via (255a) and frame via (257a) may include an opening (not shown) that is generally circular. However, the opening is not limited to being circular, and various shapes such as circular, elliptical, and square may be applied, as described above for the through via.

[0103] In addition, the description of the material or framework of the substrate for packaging is as above. The framework of the substrate for packaging may have through-vias and cavity vias originating from a single glass substrate. The framework of the substrate for packaging may have through-vias and frame vias originating from a single glass substrate. The framework of the substrate for packaging may have through-vias, cavity vias, and frame vias originating from a single glass substrate.

[0104] semiconductor package

[0105] A semiconductor package according to one or more embodiments comprises a packaging substrate described above, an upper redistribution layer disposed on the first-1 surface (211); and a connection portion disposed under the first-2 surface (212).

[0106] The semiconductor package stably supports a computing element or memory element mounted on the upper redistribution layer by means of a packaging substrate, and enables the upper redistribution layer to have an electrically conductive layer with fine wires, and is useful for packaging high-frequency high-performance semiconductor devices.

[0107] Passive components may be placed in the above cavity space, and, for example, power transfer elements such as capacitors may be placed therein.

[0108] Method for manufacturing a substrate for packaging

[0109] A method for manufacturing a substrate for packaging according to one or more embodiments comprises: a step of providing a target substrate including a masking region to which a masking treatment of etch resistance characteristics is applied and a non-masking region to which the masking treatment is not applied; a step of providing a first etched substrate by first etching the target substrate; a step of providing a pretreated substrate by preparing the first etched substrate and forming a defect at a predetermined location on the first etched substrate; and a step of providing a substrate for packaging by second etching the pretreated substrate.

[0110] The above-mentioned packaging substrate is the packaging substrate described above.

[0111] The masking region of the above target substrate includes a region corresponding to the G region of the above packaging substrate.

[0112] The masking area of ​​the above target substrate includes an area corresponding to the frame in the C area of ​​the above packaging substrate.

[0113] The non-masking area of ​​the above target substrate includes an area corresponding to the cavity space of the C region of the above packaging substrate.

[0114] The substrate for packaging may further include through-vias. The through-vias are positioned in the G region and have the same characteristics as described above, such as being vias that penetrate the substrate.

[0115] The through-via can substantially be formed through the second etching above.

[0116] The substrate for packaging may further include a cavity. The cavity is positioned in the C region and has the same characteristics as described above, such as a via penetrating the substrate.

[0117] The cavity can substantially be formed through the second etching mentioned above.

[0118] The substrate for packaging may further include frame vias. The frame vias are placed in the frame and have the same characteristics as described above, such as being vias that penetrate the substrate.

[0119] The frame via can substantially be formed through the above second etching.

[0120] Through vias and cavity spaces can be formed practically simultaneously.

[0121] The cavity space and the frame via can be formed practically simultaneously.

[0122] The cavity space and the frame via can be formed practically simultaneously.

[0123] This increases process efficiency, facilitates control of surface roughness of the bottom or top surface of the cavity space, and enables the efficient and high-precision formation of vias or through-vias at various locations on the substrate for packaging.

[0124] Method for manufacturing a semiconductor package

[0125] A method for manufacturing a semiconductor package according to one or more embodiments comprises: a step of providing a substrate for packaging; a step of providing a core substrate by forming an electrically conductive layer and an insulating layer at predetermined locations on vias and surfaces of the substrate for packaging and arranging a device in the cavity space; a step of providing a substrate including a redistribution line by forming an upper distribution layer on one surface of the core substrate; and a step of mounting a semiconductor device on the substrate including the redistribution line.

[0126] The above-described packaging substrate may have the characteristics described above.

[0127] The above-described packaging substrate may be manufactured using the method described above.

[0128] The component placed in the above cavity space may be a passive component.

[0129] The above redistribution line includes fine lines in at least a part thereof.

[0130] The above fine wire may be an electrically conductive layer with a width of 5 μm or less, or an electrically conductive layer with a width of 4 μm or less. The above fine wire may be an electrically conductive layer with a width of more than 1 μm.

[0131] The electrically conductive layer may have a smooth surface. For example, the electrically conductive layer may have a surface roughness Ry of about 200 nm or less, greater than about 0 nm and less than or equal to 180 nm, about 2 nm to about 150 nm, and about 5 nm to about 100 nm.

[0132] The above semiconductor package enables the implementation of fine lines by utilizing a packaging substrate and allows for the realization of a high-performance semiconductor package in a small size. Furthermore, by applying a glass substrate as the packaging substrate, it can possess process and performance advantages that distinguish it from conventional silicon (e.g., implementation of fine lines, suppression of parasitic device generation at high frequencies, etc.), and enables the simplification of the process for forming cavity space.

[0133] Although this disclosure includes specific examples, it will be clear to those skilled in the art that, after understanding the disclosure of this application, various forms and details in these examples may be modified without departing from the meaning and scope of the claims and their equivalents. The examples described herein should be considered for illustrative purposes only and not for limiting purposes. Descriptions of features or aspects of each example are considered applicable to similar features or aspects of other examples. Suitable results may be achieved if the described techniques are performed in a different order, and / or if the components of the described system, structure, device, or circuit are combined in a different way, and / or replaced or supplemented by other components or equivalents thereof.

[0134] Therefore, the scope of disclosure is defined by the claims and their equivalents, not by the detailed description, and all variations belonging to the claims and their equivalents should be interpreted as being included in the disclosure. Explanation of the symbols 200: Substrate for packaging C: Area C 21: Glass substrate 211: 1-1 surface 212: 1-2 surface 23: Through-via G: Area G 25: Cavity space 251: 2-1 surface 252: 2-2 surface 253: Sidewall 255: Contact surface 255a: Cavity via 257: Frame 257a: Frame via

Claims

Claim 1 A substrate for packaging comprising a first region and a second region, wherein the first region is a region in which a cavity structure is not disposed, and the second region is a region in which a cavity structure is disposed, and the first region has a first surface and a second surface facing each other, and the cavity structure comprises a cavity space; a contact surface; A substrate for packaging comprising: a cavity space, a recessed space of the cavity structure, and an opening disposed at the upper or lower part of the cavity structure; a contact surface, a surface disposed opposite to the opening of the cavity space; a side wall, a wall surrounding the contact surface; a surface roughness value of the contact surface is 3 times or less than the surface roughness value of the first surface of the first region; a surface roughness of the contact surface is 20 nm or less; a substrate of the first region comprises a glass substrate; a substrate of the second region comprises a glass substrate; the glass substrate of the first region and the glass substrate of the second region are connected to each other; and the second region comprises a frame that divides the cavity space into two or more zones. Claim 2 A substrate for packaging according to claim 1, wherein the first region and the second region are arranged adjacent to each other. Claim 3 delete Claim 4 A substrate for packaging according to claim 1, wherein the sidewall connects the first surface of the first region and the contact surface, and the sidewall has an angle of 75 to 100 degrees with respect to a line parallel to the second surface of the first region. Claim 5 delete Claim 6 A substrate for packaging according to claim 1, wherein the second region has a first surface and a second surface facing each other, and the first distance, which is the distance between the first surface and the second surface of the second region, is 0.3 to 0.7 times the second distance, which is the distance between the first surface and the second surface of the first region. Claim 7 A substrate for packaging according to claim 6, wherein the first distance is 100 μm or more. Claim 8 delete Claim 9 A packaging substrate according to claim 1, wherein the second region further comprises a cavity that penetrates the packaging substrate. Claim 10 A semiconductor package comprising: a substrate for packaging according to claim 1; an upper redistribution layer disposed on the first surface of the first region; and a connection portion disposed under the second surface of the first region. Claim 11 A semiconductor package according to claim 10, wherein a passive component is disposed in the cavity space.

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