Integrated circuit device and an automotive sensor network

Abstract

Safety serial bus communication methods and devices suitable for automotive applications. An exemplary sensor IC comprises: a sensor controller that operates a converter to acquire measurement data formattable as data packets; a scrambler that masks each data packet with a scramble operation before the data block is transmitted over the serial bus to a bus controller device—the scramble operation having a secret configuration and / or a secret initial state—; and an integrated circuit component that operates on a seed value to derive the secret configuration and / or a secret initial state.

Description

Technology Field

[0001] This application relates to the implementation of a serial bus protocol suitable for an automotive environment, and more specifically, to protecting such implementation against cyber attacks. Background Technology

[0002] Current and future vehicles are integrating an increasing number of onboard sensors and systems to enable or assist critical vehicle functions, including Adaptive Cruise Control (ACC), Parking Assist, Forward Collision Warning (FCW), Forward Collision with Active Braking, Blind Spot Warning (BSW), and Lane Keeping System (LKS). These technologies provide direct driver assistance in normal driving and critical scenarios, and some can even enhance driver control or provide autonomous control to prevent or mitigate collisions or other adverse outcomes.

[0003] To accommodate the many sensors, actuators, and control systems used for such features, manufacturers are implementing increasingly sophisticated data communication networks in each vehicle. The third-generation DSI (DSI3) standard published by the Distributed System Interface (DSI) Consortium (dsiconsortium.org) provides one example of such a communication network intended for automotive applications, but other examples are the DS2, PSI5, LIN, and CAN standards.

[0004] DSI3 and these other communication standards must compete with a unique set of situations that challenge their performance. Networks are portable, battery-powered (i.e., low voltage), and have wire runs long enough to cause (and be susceptible to) electromagnetic interference (EMI). Networks must be resistant to vibration effects while still being inexpensive and easy to repair. Shared features of these standards include serial communication over one or two data transmission conductors, limited bandwidths, and the use of signaling schemes intended to cope with the aforementioned situations.

[0005] As the complexity and capabilities of advanced driver assistance systems continue to increase, concerns regarding their vulnerability to cyberattacks and data breaches are growing. In addition to potentially compromising the systems themselves, such incidents pose a risk of harm to passengers and pedestrians. However, attempts to safeguard these systems against such attacks must ideally avoid compromising their performance or excessively increasing their complexity and costs.

[0006] Accordingly, safety serial bus communication methods and devices suitable for automotive applications are disclosed herein. An exemplary sensor IC comprises: a sensor controller that operates a converter to acquire measurement data formattable as data packets; a scrambler that masks each data packet with a scrambler operation before the data block is transmitted over the serial bus to a bus controller device—the scrambler operation having a secret configuration and / or a secret initial state—; and an integrated circuit component that operates on a seed value to derive the secret configuration and / or a secret initial state.

[0007] An exemplary communication method includes the steps of: receiving a seed value from a bus controller device via an automotive serial bus; operating on the seed value with an integrated circuit component to derive a secret configuration and / or a secret initial state for a scrambler; masking data packets using a scrambler; and transmitting the masked data packets to the bus controller device via the automotive serial bus.

[0008] An exemplary automotive sensor network comprises a plurality of sensor devices—each of which has a free-run scrambler for masking data packets from the sensor device—; and a bus master device coupled to the plurality of sensor devices by a serial bus to receive masked data packets from each of the plurality of sensor devices—the bus master device is configured to track the descrambler status for each of the plurality of sensor devices.

[0009] Each of the above-described embodiments may be used individually or in combination and may optionally include one or more of the following features in any suitable combination: 1. The seed value is one of a unique identifier for the integrated circuit device and a value supplied by the bus controller device. 2. The scrambler is a multiplication scrambler. 3. The scrambler is a non-linear scrambler. 4. The scrambler is an alternating step generator having mutually prime register lengths of at least 100 cells. 5. A descrambler that unmasks command messages from the bus controller device. 6. The scrambling operation has a secret initial state. 7. The sensor controller resets the scrambler to the secret initial state after detecting a retransmission request. 8. The sensor controller disables further communication if a number of retransmission requests exceed a predetermined limit. 9. The integrated circuit component includes an embedded self-test (BIST) circuit that provides a secret configuration and / or a secret initial state as a test result. 10. The integrated circuit component includes a filter that operates on a seed value to generate truncation bits derived therefrom the secret configuration and / or secret initial state. 11. A scrambler is used to mask multiple data packets without being reset between data packets. 12. Detecting a retransmission request for a given data packet; resetting the scrambler to a secret initial state; masking the given data packet using the scrambler; and transmitting the masked given data packet to a bus controller device via an automotive serial bus. 13. Disabling further communication if the seed value is not received within a predetermined window. 14. A free-execution scrambler for masking command messages to each of the multiple sensor devices, and a bus master device is configured to track the individual scrambler state for each of the multiple sensor devices. Brief explanation of the drawing

[0010] Figure 1 is a block diagram of an exemplary data communication network. FIG. 2a is a block diagram of an exemplary slave device for a DSI3 bus. FIG. 2b is a block diagram of an exemplary master device for a DSI3 bus. Figure 3 is a graph of an exemplary TDMA frame syntax. Figure 4 is a signal flow diagram of an exemplary adder scrambler / scrambler. Figure 5a is a signal flow diagram of an exemplary multiplication scrambler. Figure 5b is a signal flow diagram of an exemplary multiplication descrambler. Figure 6 is a signal flow diagram of an exemplary additive nonlinear scrambler / scrambler. Figure 7a is a signal flow diagram of an exemplary multiplication nonlinear scrambler. Figure 7b is a signal flow diagram of an exemplary multiplication nonlinear descrambler. Figure 8 is a flowchart of an exemplary detection method. Specific details for implementing the invention

[0011] It should be understood that while the attached drawings and the following description present specific embodiments and details for the purpose of explanation, the drawings and the corresponding detailed description do not limit the present disclosure. On the contrary, they provide the basis for disclosing and enabling all modifications, equivalents, and alternatives that fall within the scope of the appended claims, as understood by those skilled in the art.

[0012] FIG. 1 illustrates an electronic control unit (ECU) (102) coupled to a first set of ultrasonic sensors (104) via a first bus master device (103) and to a second set of ultrasonic sensors (106) via a second bus master device (105). The ECU (102) obtains measurement results from the ultrasonic sensors and optionally from other sensors (e.g., radar, lidar, imaging) to determine spatial relationships to any obstacles of the vehicle, its surroundings, and within it. To provide automated parking, assisted parking, lane-change assist, obstacle and blind spot detection, autonomous driving, and other desirable features, the ECU (102) may be additionally connected to a set of actuators such as a rotary-signal actuator (108), a steering actuator (110), a braking actuator (112), and a throttle actuator (114). The ECU (102) can be additionally coupled to a user-interactive interface (116) to accept user input and provide a display of various measurement results and system status.

[0013] Various standards exist to support communication between the ECU (102) and various sensors and actuators. Of particular interest to the present disclosure is the third-generation Distributed System Interface (DSI3) bus standard, which provides half-duplex single-ended signal communication between a bus master device and one or more slave devices (e.g., sensors and actuators). Because the DSI3 bus requires only one signal conductor, it may sometimes be referred to as a "1-wire" bus. Other suitable standards include DS2, PSI5, LIN, and CAN standards. For communication between the ECU (102) and nearby integrated circuit devices (e.g., bus masters (103, 105)), inter-chip standards such as SPI, I2C, and MDIO may be preferred. Because I2C and MDIO standards typically provide separate data and clock conductors, they are sometimes referred to as "2-wire" buses. SPI and other inter-chip communication standards typically provide additional conductors for control signals and / or unidirectional data signals. Although the following discussion focuses on DSI3, the disclosed principles for securely protecting data communications can be applied to data signals for any of these serial bus standards.

[0014] The DSI3 standard supports parallel connection of multiple slave devices (104) to a bus master (103) and also supports serial connection of multiple slave devices (106) to a bus master (105). Point-to-point connections are also supported.

[0015] FIG. 2a is a block diagram of an exemplary sensor device (200) suitable for connection as a slave device to a standard DSI3 bus having parallel or point-to-point connection of slave devices to a master device. While maintaining physical compatibility with the DSI3 standard, the exemplary device (200) includes certain features to improve communication performance, at least some of which extend the standard in a way that may require firmware adjustments at the bus master device as further discussed below. Other features may be utilized to improve performance without deviating from full compatibility with the existing standard. In addition to such features disclosed in the jointly owned U.S. Patent No. 10,756,925 (“Slave device for enhancing the data rate of a DSI3 bus”) and U.S. Patent No. 10,771,281 (“Semi-differential signaling for enhancing a DSI3 bus”), and the co-pending U.S. Application No. 17 / 585,531 (“DSI3 bus with enhanced robustness”), certain features for protecting bus communication from interception by unauthorized devices and by interaction with them are disclosed herein. These features may be used individually or in various combinations.

[0016] The sensor device (200) includes a controller (202) that buffers relevant messages in memory (204) to collect measurement results and communicate measurement data to a bus master device. The message length may vary, but in at least one embodiment considered, each message is 16 bytes and may begin with a preamble of one or two nibbles in length, or the preamble may precede each message. A scrambler (206) protects the messages from interception and modification by masking each message using a linear or non-linear feedback shift register and a bitwise exclusive OR (XOR) operation. Where present, the preamble is not masked to preserve the preamble pattern in the output bitstream of the scrambler.

[0017] A channel encoder (208) encodes a bitstream from a scrambler (206) by mapping each nibble to a triplet of corresponding channel symbols. Each triplet contains three ternary channel symbols. A channel symbol is also referred to herein as a “chip” and is transmitted as one of three unipolar non-zero return levels of 0, 1, or 2, and each symbol has a fixed symbol duration which may be about 3 or 4 microseconds. As provided in the standard, “0” is I Q It can correspond to the idle channel signal current of. "1" is I Q +I RESP It can correspond to the response channel signal current, and "2" is I Q +2I RESP It can correspond to the response channel signal current. In at least some embodiments, I Q is limited to 2 mA or less, and I RESPis approximately 12 mA. Some embodiments under consideration may switch from 3-level signaling to 2-level signaling to improve noise immunity. In such embodiments, the channel encoder (208) maps an 8-bit byte to an 8-bit codeword, in this case I Q and I Q +2I RESP Only the current level is used.

[0018] A pulse-shaping filter (210) may operate on a channel symbol stream from an encoder (208) to provide a transfer function that converts a rectangular pulse (e.g., an NRZ chip) into a smoother pulse shape, providing a channel signal with more desirable spectral characteristics. A digital-to-analog converter (212) may operate on the filtered channel signal to convert it from a digital form to an analog form, which may be referred to herein as the uplink channel signal. An optional transmit correction filter (214) may operate on the uplink channel signal to further shape the channel signal spectrum. A channel driver (216) converts the uplink channel signal into current at the input / output pin of the slave device (200). A low-pass RC filter (capacitor (C3), resistor (R3)) couples the input / output pin to the signal conductor of the DSI3 bus.

[0019] Current biasing of the input / output pin is provided by a current sink (218) and a receive buffer (220). The controller (202) adjusts the current sink (218) as needed for biasing during the forward (downlink) and reverse (uplink) communication phases of the half-duplex DSI3 communication protocol. During the downlink communication phase, the input / output pin receives a downlink channel signal in the form of a voltage signal. The receive buffer (220) provides a high input impedance to the input / output pin to buffer the downlink channel signal to the analog-to-digital converter (224).

[0020] The downlink receive filter (225) may limit the digital receive signal bandwidth and / or improve the signal-to-noise ratio of the downlink signal. In at least some embodiments, the filter (225) operates to suppress noise exceeding 300 kHz. In system embodiments where the master device uses a transmit correction filter (similar to the filter (214) above), the downlink receive filter (225) may include a compensation function that boosts the downlink signal frequency to about 150 kHz before rolling off to suppress noise at signal frequencies exceeding about 250 or 300 kHz.

[0021] A symbol detector (226) operates on a filtered received signal to detect channel symbols of a masked command message (when the device is operating in command-response mode) or to detect a broadcast read command (BRC) pulse (when the device is operating in periodic data acquisition mode). A descrambler (228) operates on a masked command message using a linear or non-linear feedback shift register and a bitwise exclusive OR (XOR) operation to unmask the command type and associated payload, placing the information that the controller (202) will use when making a response into a receive buffer. In periodic data acquisition mode, the detector (226) signals the sensor controller (202) to make a data packet for transmission in an appropriate TDMA slot.

[0022] FIG. 2a illustrates both the pulse-shaping filter (210) and the transmit correction filter (214). Either or both of these filters may be omitted. The order of the filters may also be reversed, and digital-to-analog conversion may occur before, between, or after the filtering operations. As described in the incorporating U.S. Application No. 17 / 585,531 (“DSI3 Bus with Enhanced Robustness”), the detector (226) may be configured to detect retransmission requests, whether signaled using different BRC pulse widths or by slow changes in the input / output line voltage while other slave devices are modulating the bus current.

[0023] FIG. 2b is a block diagram of an exemplary bus master device (240) suitable for use on a standard DSI3 bus. As with the slave device (200), the master device (240) maintains physical compatibility with the DSI3 standard, but may include certain features to improve uplink communication performance when used with a compatible slave device.

[0024] The master device (240) includes a controller (242) that creates downlink messages in memory (244) for communication with one or more slave devices. When the bus is configured for command-response mode, the downlink messages are typically commands directed to a specific slave device to obtain a response. When the bus is configured for periodic data acquisition mode, the controller may directly initiate the transmission of a pulse representing a broadcast read command (BRC) that provides a timing reference for a TDMA frame—during which sensor devices transmit packets in their assigned slots. As described in the included U.S. Application No. 17 / 585,531 (“DSI3 Bus with Enhanced Robustness”), the controller (242) may be further configured to generate retransmission requests by potentially using different BRC pulse widths or by causing slow changes in the input / output lines.

[0025] A scrambler (245) protects messages from interception and modification by masking each command message using a linear or non-linear feedback shift register and a bitwise exclusive OR (XOR) operation. (The scrambler operation may be bypassed for BRC pulses and any synchronization preamble for command messages.) A channel encoder (246) encodes the masked downlink messages by mapping bit 0 and bit 1 to up and down channel voltage transitions, such as those provided by Manchester-1 encoding, for example. A digital-to-analog converter (248) converts the encoded signal into an analog downlink signal. An driver (249) supplies the analog downlink signal as a voltage signal to the input / output pins of the master device (240). The DSI3 standard provides a 2-volt swing between the "high" symbol voltage and the "low" symbol voltage, but some embodiments under consideration use a 4-volt swing to improve noise immunity. A low-pass RC filter (capacitor (C1), resistor (R1)) connects the input / output pins to the signal conductors of the DSI3 bus.

[0026] A high-impedance receive buffer (250) combines an uplink signal from an input / output pin to an optional receive correction filter (251). The optional receive correction filter (251), for example, can boost the high-frequency content of the uplink signal to compensate for the operation of the transmit correction filter (214). An analog-to-digital converter (252) digitizes the uplink signal, and an uplink receive filter (253) operates on the digital signal to limit the signal bandwidth and / or improve the signal-to-noise ratio. The filter (253) may be a matched filter having a filter response at least partially based on the pulse shape provided by the pulse shaping filter (210). The filters (251 and 253) may be reordered, merged into a single filter, and each implemented in digital or analog form.

[0027] A chip detector (254) operates on a filtered uplink signal to detect channel symbol levels. A threshold capture unit (255) may capture and / or adapt comparator threshold levels for the chip detector (254) based at least partially on message preambles as discussed in the aforementioned jointly owned patents. A decoder (256) operates on a channel symbol sequence from the chip detector (254) to reverse the operation of the encoder (208) and map chip triplets to binary nibbles. A descrambler (257) operates on a masked bitstream from the decoder (256) to reverse the operation of the scrambler (206) and extract message data transmitted by the slave device. The message data may be stored in memory (244) for analysis and use by the controller (242).

[0028] The exemplary slave device illustrated in FIG. 2a utilizes a receive buffer (220) and a channel driver (216) operating in relation to ground. Here, it is known that the ground node can drift with respect to the ground used by the master device in a symmetrical manner, having the drift typically experienced by the voltage supply nodes of the master and slave devices. (The symmetry is a result of the power supply conductor impedances on the DSI3 bus.) Consequently, a higher degree of noise immunity can be achieved if the slave and master devices use a half-voltage reference as described in the aforementioned jointly owned patents, rather than using the ground node as a reference for signal transmission and reception. Accordingly, at least some considered embodiments of the slave and master devices use a half-voltage node as a reference voltage for transmitting and receiving signals on the DSI3 bus.

[0029] According to the standard, DSI3 master devices communicate with slave devices in a half-duplex manner. The bus can operate in Command and Response (CRM) mode, or in Periodic Data Acquisition (PDCM) mode if higher data throughput is required. In CRM, the bus master transmits a multi-byte command word addressing a command to individual slave devices and receives a response from those devices. In PDCM, the bus master transmits a Broadcast Read Command (BRC) pulse initiating a Time Division Multiple Access (TDMA) frame having an allocated time slot for each active sensor. Each active sensor responds by transmitting a data packet to the master during its allocated time slot.

[0030] The bus is initially in the CRM, where the master device transmits commands to the sensor devices. The first action of the master device is preferably to provide an initial configuration for its scrambler (206) and descrambler (228) to each sensor device, as described in more detail below. The initial configurations for each sensor device may differ, or alternatively, they may all share the same initial configuration. To allow the scramblers to run freely (meaning the scramblers are not reset for each communication), the master device preferably maintains a separate session for each sensor device to save the states of the scrambler (245) and descrambler (257) after receiving a message from a given sensor device and to restore those states before the next communication with that device. In at least some of the embodiments considered, the sensor devices will refuse to communicate until their scramblers (206) are initialized. If communication is attempted more than a predetermined number of times, the sensor devices may shut down until power is cycled next.

[0031] When initiating a measurement cycle, the master device may transmit command messages specifying which of the sensors will be active and the type of measurement they will perform. Exemplary measurements include transmit and receive; and receive only ("listen"). Measurement parameters may additionally include frequency channels to enable multi-channel operation, e.g., upper sideband, lower sideband, and broadband. The command may further specify the allocation of TDMA slots for various slave devices, but it is expected that the slave devices may rely on their bus identifiers to determine their allocation, e.g., to transmit in numerical order.

[0032] FIG. 3 is a graph of an exemplary TDMA frame syntax that can be used once the master device transitions the bus to PDCM. The master device communicates with slave devices via the forward or "downlink" channel by modulating the voltage on the input / output signal line, and the slave devices communicate with the master device via the reverse or "uplink" channel by modulating the current on the input / output signal line. A BRC pulse (31) initiates each TDMA frame. After a programmable interval (32)—Figure 3 is shown as being measured from the falling edge of the BRC pulse, but alternatively it can be measured from the rising edge—active slave devices begin to alternately transmit packets containing their measurement data. In at least some systems, each sensor needs to transmit multiple data packets, which will require multiple TDMA frames because each sensor can only transmit one fixed-length data packet per frame. Each TDMA slot (33A-33N) contains one data packet from the corresponding sensor. The master device can delay the start of the next frame by the programmable interval (35).

[0033] In at least some of the embodiments considered, each data packet includes a parity check, a checksum, or other form of redundancy to enable error detection. Even in embodiments without such redundancy, the master device may monitor for an equalization error of excessive noise or other indicators to detect when the packet has not been reliably received. When an error is detected in a data packet or the presence of excessive noise is detected during its reception, the master device requests the retransmission of the data packet. As described in the included U.S. Application No. 17 / 585,531 (“DSI3 Bus with Enhanced Robustness”), the master device may request the retransmission of the data packet using a modified BRC pulse or a slow voltage change. Upon detection of the retransmission request, the associated sensor device may restore its scrambler and descrambler to the configurations initially set by the master device.

[0034] FIG. 4 illustrates an additive linear scrambler comprising a shift register (402) that accepts a feedback signal. Values ​​from selected cells of the shift register (402) are combined by one or more exclusive OR (XOR) gates (404) to generate a feedback signal. The selected cells are typically chosen to ensure that the feedback signal is a maximum length pseudo-random binary sequence (PRBS), at least as long as the shift register is initialized to a non-zero value. A masking XOR gate (406) combines the feedback signal with a data stream (IN) to provide a masked data stream (OUT). The shift register preferably contains 60 or more cells, and much more preferably about 128 cells, making it more difficult for unauthorized persons to derive a masking pattern from the masked data stream.

[0035] At the receiving end, the same PRBS is generated by a shift register (402) that is configured and initialized in the same way. An XOR gate (406) combines the masked data stream (IN) with the PRBS to restore the original unmasked data stream (OUT). If an error occurs during initialization (e.g., due to a communication error when the initial value or the seed generated from it is transmitted), the PRBS of the descrambler is not aligned and the entire message is corrupted. An alternative is to use a predetermined value, but this can create a vulnerability to reverse engineering.

[0036] FIG. 5a illustrates a multiplicative linear scrambler that may be preferred due to its ability to limit error propagation. Rather than receiving a direct feedback signal, a shift register (402) receives a masked data stream (OUT) from a masking XOR gate (406). Subsequently, one or more XOR gates (404) derive a feedback signal from the masked data stream itself. At the receiving end, the scrambler is configured as shown in FIG. 5b to supply the masked data stream (IN) to the shift register (402) and reconstruct the original data stream (OUT) by using one or more XOR gates (404) to derive a feedback signal to mask the XOR gate (406). The impact of any communication errors is limited to the immediate neighbor of the communication error.

[0037] While the linear scramblers of FIGS. 4 and 5a may be satisfactorily safe for sufficiently long shift registers, stronger protection can be achieved with non-linear scramblers such as those illustrated in FIGS. 6 and 7a. The illustrated non-linear scramblers are "alternating step generators," wherein the first linear shift feedback register (LSFR) (602) generates a PRBS as previously described in relation to FIG. 4. A clock signal (CLK) is supplied to the first LSFR (602) to shift the register contents and generate the next PRBS bit with each clock cycle. The PRBS is then used to gate the clock signal (CLK) for two additional LSFRs (604, 606). When the PRBS is asserted (logic "1"), a logic gate (612) transmits the clock signal (CLK) to the LSFR (604). When the PRBS signal is deselected (logic "0"), the logic gate (614) instead delivers the clock signal (CLK) to the LSFR (606). A combination XOR gate (608) derives a mask signal by combining the PRBSs from the LSFRs (604, 606) and supplies it to the masking XOR gate (406). The registers for the LSFRs (602, 604, 606) preferably have comparable register lengths that are pairwise coprime (i.e., have 1 as their greatest common divisor), each having more than 100 cells.

[0038] The multiplication counterpart of the scrambler in FIG. 6 is illustrated in FIG. 7a. That is, rather than operating on their individual feedback signals, the LSFRs (602, 604, 606) each operate on a masked data stream. At the receiving end, the masked data stream is supplied to each of the LSFRs (602, 604, 606) as illustrated in FIG. 7b, so that they can derive appropriate sequences that form the correct masking signal, and then the masking XOR gate (406) can remove it to restore the original data stream. The effect of any communication errors is limited to a window around the communication error.

[0039] Other non-linear scrambling approaches exist and can be used. One suitable example is the A5 / 1 stream cipher disclosed in the GSM cellular phone standard. Reduced generators and self-reducing generators can also be used, but they may require buffering and / or higher clock rates to overcome their variable generation rates.

[0040] To maximize protection, scrambler / scrambler configurations are established in a secure manner. Configurations can be modified by selecting different combinations of cells to derive PRBS from shift register(s), by selecting different combinations of cells to derive a gating signal for the clock (CLK), by changing shift register length(s), and / or by changing the initial contents of the register(s). These parameters can optionally be established during initial system assembly, for example, by securely storing parameters for dynamic selection or multiple sets of parameters in the built-in non-volatile memory of both the master device and the sensor device. (Scrambler configurations are essentially identical to scrambler configurations, allowing the scrambler to be easily configured once the scrambler configuration parameter(s) are known.) However, this secure storage approach entails added complexity and cost to ensure that the stored parameters are protected from reverse engineering attacks.

[0041] The preferred approach utilizes the exclusive handling of the seed value, which can be stored in a clear or provided by the master device at startup. One implementation under consideration uses Die Level Traceability (DLT) code as the seed value to ensure that the seed value of each sensor device is unique. The master device is programmed with DLT information for each sensor device when the system is assembled. Alternatively, the master device dynamically generates seed values ​​and provides one to each sensor device.

[0042] Proprietary processing derives one or more scrambler configuration parameters from a seed value using a certain aspect of the sensor device structure. For example, integrated circuit devices typically include an embedded self-test (BIST) circuit with registers for supplying test patterns to circuit components and capturing test results. A seed value can be supplied to the existing BIST circuit to enable the relevant components of the sensor device to operate on the seed value—as if it were a test pattern—and generate test results that can be taken as one or more scrambler configuration parameters. The master device is designed to also include the relevant sensor device components, allowing the master device to independently derive scrambler configuration parameters. Since there are far fewer master devices than sensor devices, integrating additional circuits into the master device does not excessively increase system costs.

[0043] Functional components other than the BIST circuitry may be utilized in a similar manner. For example, ultrasonic sensor devices include digital correlation filters. These filters calculate the sum of products, which are derived from the multiplication of signal samples and filter coefficients. The binary representation of each product is much longer than the representations of the coefficients and samples. For example, if the signal sample is 22 bits wide and the coefficient is 22 bits wide, the representation of their product is 44 bits wide. The useful dynamic range may be limited to approximately 16 bits, which means that 28 least significant bits may be truncated before or after the summation operation. The truncated bits may nevertheless be retained for other purposes, for example, to provide scrambler configuration parameters. The sensor device may take a seed value from the master device, pass the seed value through the correlation filter, and accumulate the truncated bits to be used as one or more scrambler configuration parameters. In order to enable the master device to independently derive one or more scrambler configuration parameters from a seed value, the master device will be designed to include a correlation filter having the same coefficient values.

[0044] Multiple such functions can be used in series. For example, seed values ​​can be passed through a digital correlation filter, and truncation bits can be accumulated as test patterns from which the BIST circuit derives scrambler configuration parameters. The use of existing sensor device components utilizes existing proven device designs and avoids excessively increasing their cost and complexity.

[0045] FIG. 8 is a flowchart of an exemplary method that can be implemented by a master device. In block (802), a CRM is used to initialize the scrambler / scrambler configuration of each sensor device. For example, the master device may transmit a first CRM command message to convey a seed value for proprietary processing as described above to configure the scrambler and scrambler of the sensor device. The scrambler configuration of the sensor device does not need to be identical to the scrambler configuration of the sensor device. The master device stores the corresponding scrambler and scrambler configurations for future communication with the sensor device, including the contents of their shift registers. Each sensor device is configured in this manner.

[0046] In block (804), using appropriate scrambler settings for each sensor device selected to be active, the master device transmits a masked CRM message to each sensor device specifying the measurement parameters to be used and optionally specifying the PDCM time slot(s) to be used by each sensor device to transmit measurement information to the master device. Once each sensor device is configured, the master device initiates PDCM in block (806) and transmits a block read command (BRC) pulse to define the time slots within the PDCM frame.

[0047] As active sensor devices transmit masked data packets in response to a BRC pulse, the master device receives and unmasks each data packet in block (808). In block (810), the master device determines whether each data packet was received correctly (e.g., using checksum bits), and if so, sets the error count for that sensor device to 0 in block (812). In block (814), the master device determines whether more data packets are expected for the PDCM frame, and if so, returns to block (808). When the frame is complete, the master device checks in block (816) to determine whether the current measurement cycle is complete. If not, control returns to block (806). Otherwise, data from the current measurement cycle is processed in block (818) and provided to support whichever driver assistance service initiated the measurement. Control returns to block (804) to initiate the next measurement cycle.

[0048] If a data packet is not received correctly in block (810), the master device increments the error counter for the sensor in block (820) and tests whether the counter exceeds a predetermined limit. If not, the master device sends a retransmission request in block (822) to reset the scrambler configuration for the sensor to its initial value. (A sensor device that detects a retransmission request will also reset its scrambler configuration to its initial value. Note that the sensor device may impose a limit on the maximum number of retransmission requests and disable itself if the limit is exceeded.) The master device returns to block (808). If the counter exceeds the limit in block (820), the master device designates the sensor as faulty in block (824) and stops the measurement cycle. The master device may exclude the faulty sensor device from future measurements.

[0049] One exemplary embodiment of the present disclosure stores initial scrambler settings in the non-volatile memory (NVM) of the ECU and sensor devices. For example, the ECU software may be stored in flash memory. In this embodiment, the initial scrambler settings are stored in flash memory via software and paired with the corresponding initial scrambler settings within the sensor NVM. This exemplary embodiment pairs the ECU software with peripheral nodes for increased security.

[0050] Although exemplary embodiments have been described in relation to ultrasonic sensors and engine control units, the embodiments of this disclosure may also be used in other applications of controllers and peripheral devices. Although specific examples have been made for the DSI3 bus protocol, implementations of the described embodiments may use other communication protocols. Although exemplary cryptographic methods such as hashing, CRC encryption, and signature verification have been presented, other cryptographic methods may be implemented. The exemplary embodiments of this disclosure can provide efficient and robust security for data processing systems.

[0051] The present technology has been described above in relation to several exemplary embodiments. However, changes and modifications may be made to the exemplary embodiments without departing from the scope of the present technology. For example, while the exemplary embodiments may describe an ECU and an accompanying ultrasonic sensor implementing various security methods for communication protocols, those skilled in the art will understand that the described methods may be used in other applications. Additionally, while exemplary specifications such as polynomial sizes and command frames have been described, those skilled in the art will understand that the present technology is not limited to such specifications. Such and other changes or modifications are intended to be included within the scope of the present technology.

[0052] Once the foregoing disclosure is fully recognized, many modifications, equivalents, and alternatives will be apparent to those skilled in the art. The following claims are intended to be interpreted to encompass all such modifications, equivalents, and alternatives where applicable.

Claims

Claim 1 An integrated circuit comprising: a scrambler configured to process data packets into masked data packets using a configuration or initial state derived by the exclusive processing of a seed value stored in a clear or received through a bus; and a digital-to-analog converter configured to transmit said masked data packets through said bus. Claim 2 In claim 1, the scrambler is an integrated circuit that processes data packets without being reset between transmits. Claim 3 An integrated circuit according to claim 1 or 2, further comprising an integrated circuit component configured to derive the configuration or initial state using an embedded self-test (BIST) circuit, wherein the BIST circuit is configured to provide the configuration or initial state as a test result. Claim 4 An integrated circuit according to claim 1 or 2, further comprising an integrated circuit component configured to derive the configuration or initial state using a digital filter, wherein the digital filter is configured to generate truncation bits while operating on the seed value, and the configuration or initial state is derived using the truncation bits. Claim 5 A bus controller comprising: an integrated circuit component configured to perform exclusive processing of a plurality of seed values, wherein each of the plurality of seed values ​​is associated with a respective slave device, and the exclusive processing generates a scrambler configuration or an initial scrambler state for each of the slave devices; and a descrambler configured to unmask masked data packets received from each of the slave devices using the scrambler configuration or the initial scrambler state for each of the slave devices. Claim 6 A bus controller according to claim 5, further comprising: a memory configured to preserve the current scrambler state for each slave device between the reception of masked data packets from each slave device; a scrambler configured to process message packets into masked message packets for each slave device using the scrambler configuration or initial scrambler state for each slave device; and a digital-to-analog converter configured to transmit the masked message packets through the bus.

Images