Method and Apparatus for Generating Algorithmic Pattern Based on Auxiliary Instructions in High-Speed Memory Test Device

Abstract

A method for generating an auxiliary instruction-based algorithm pattern in a high-speed memory test device and an apparatus for the same are disclosed. An algorithm pattern generation device according to an embodiment of the present invention may include: a pre-synthesis instruction storage unit that receives and stores a compiled instruction including at least one of a general instruction and an auxiliary instruction; an auxiliary instruction decoder that retrieves the auxiliary instruction when the compiled instruction includes the auxiliary instruction and decodes the auxiliary instruction to generate high-speed synthesis auxiliary information; an instruction synthesizer that synthesizes instructions for a loop based on the information retrieved from the general instruction or the high-speed synthesis auxiliary information; a plurality of pattern generators that generate a test pattern based on the synthesized instruction; and a serializer that transmits a final test pattern, serialized from a plurality of test patterns, to a test target device.

Description

Technology Field

[0001] The present invention relates to a method for generating an algorithm pattern using auxiliary instructions in a high-speed memory test device and an apparatus for the same. Background Technology

[0002] The content described in this section merely provides background information regarding embodiments of the present invention and does not constitute prior art.

[0003] The slow operating speed of memory relative to the processing power (e.g., CPU) of computing systems acted as a bottleneck, and high-speed memory rapidly evolved to overcome this. Consequently, test devices also had to advance to test high-speed memory with complex functions.

[0004] These advancements in memory have posed a challenge to the field of memory testing, as the operating speed of the test device had to increase in line with the operating speed of the memory. To perform functional tests among the various tests performed on memory, the Algorithmic Pattern Generator (ALPG) inside the test device generates various instructions (address to access, control signal, input data, or expected data) to be input into the memory, called test patterns.

[0005] The aforementioned ALPG performs a variety of functions, and due to the complexity of its hardware, its operating speed is structurally slower than that of memory. In other words, the ALPG acts as a bottleneck for memory testing. To address this, a parallel ALPG was proposed that arranges N pattern generators in parallel internally. Since the pattern generators within the parallel ALPG are independent hardware components that generate patterns simultaneously, test patterns are generated in parallel every clock cycle from the perspective of the parallel ALPG. A serializer receives these as inputs and serializes each test pattern, thereby generating test patterns that are N times faster than the existing ones.

[0006] Conventional parallel ALPG structures, which enable high-speed test pattern generation, require not only multiple pattern generators but also the conversion of instructions that each generator must execute as a cost. In the case of an ALPG with a single pattern generator, the pattern intended by the user can be generated simply by the generator executing the user-inputted instructions; however, in a parallel ALPG structure, the result of N pattern generators interleaving with each other must be serialized to become the user's intended pattern. Instruction synthesis for this purpose can be performed by the user inputting a test algorithm that takes into account the parallel pattern generator structure.

[0007] However, this structure requires an instruction synthesizer to synthesize instructions in order to maintain the context of the test pattern as intended by the user after serialization; at the same time, generating high-speed test patterns consumes a significant amount of the instruction synthesis clock, which increases the total test time and consequently raises test costs. The problem to be solved

[0008] The main objective of the present invention is to provide a method for generating an auxiliary instruction-based algorithm pattern in a high-speed memory test device, which decodes auxiliary instructions to generate high-speed synthesis auxiliary information, synthesizes instructions based on the high-speed synthesis auxiliary information, and transmits them to a plurality of pattern generators to generate a test pattern, and an apparatus for the same. means of solving the problem

[0009] According to one aspect of the present invention, in a device for generating an auxiliary instruction-based algorithm pattern in a high-speed memory test device for achieving the above objective, the algorithm pattern generating device may include: a pre-synthesis instruction storage unit that receives and stores a compiled instruction including at least one of a general instruction and an auxiliary instruction; an auxiliary instruction decoder that retrieves the auxiliary instruction when the compiled instruction includes the auxiliary instruction and decodes the auxiliary instruction to generate high-speed synthesis auxiliary information; an instruction synthesizer that synthesizes instructions for a loop based on the information retrieved from the general instruction or the high-speed synthesis auxiliary information; a plurality of pattern generators that generate a test pattern based on the synthesized instruction; and a serializer that transmits a final test pattern, serialized from a plurality of test patterns, to a test target device.

[0010] In addition, according to another aspect of the present invention, a method for generating an auxiliary instruction-based algorithm pattern in an algorithm pattern generation device included in a high-speed memory test device for achieving the above objective, wherein the algorithm pattern generation method may include: a pre-synthesis instruction storage step of receiving and storing a compiled instruction including at least one of a general instruction and an auxiliary instruction; an auxiliary instruction decoding step of retrieving the auxiliary instruction when the compiled instruction includes the auxiliary instruction and decoding the auxiliary instruction to generate high-speed synthesis auxiliary information; an instruction synthesis step of synthesizing instructions for a loop based on the information retrieved from the general instruction or the high-speed synthesis auxiliary information; a plurality of pattern generation steps of generating a test pattern based on the synthesized instruction; and a serialization processing step of transmitting a final test pattern, obtained by serializing a plurality of test patterns, to a test target device. Effects of the invention

[0011] As explained above, when using auxiliary instructions and an algorithm pattern generation device that supports them, the present invention facilitates the processing of various factors that make instruction synthesis difficult, thereby enabling high-speed processing. Consequently, the instruction synthesis clock is reduced, which in turn has the effect of reducing test costs.

[0012] In addition, the algorithm pattern generation device for fetching and synthesizing a single instruction per clock in the present invention has a simple structure, which requires relatively low hardware overhead and has the effect of being advantageous for high-speed operation. Brief explanation of the drawing

[0013] Figure 1 is a diagram illustrating the operation of generating a test pattern in a general algorithm pattern generation device. FIG. 2 is a block diagram schematically showing an auxiliary instruction-based algorithm pattern generation device according to an embodiment of the present invention. FIG. 3 is a flowchart illustrating an auxiliary instruction-based algorithm pattern generation method according to an embodiment of the present invention. FIG. 4 shows examples of two possible instruction synthesis processes when using instruction synthesizer hardware according to an embodiment of the present invention. FIG. 5 is a diagram showing the execution of a command including a repetition command according to an embodiment of the present invention. FIG. 6 is a diagram showing auxiliary instructions that support high-speed synthesis for instructions constituting a loop according to an embodiment of the present invention. FIG. 7 is a diagram illustrating a command synthesis operation according to an embodiment of the present invention. FIG. 8 is a diagram showing an example in which a plurality of instructions stored in a pre-synthesis instruction storage according to an embodiment of the present invention form a repeating loop and auxiliary instructions are arranged. FIG. 9 is a diagram showing the result after the instruction loop of FIG. 8 according to an embodiment of the present invention is synthesized for four pattern generators. Specific details for implementing the invention

[0014] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, detailed descriptions of related known configurations or functions are omitted if it is determined that such detailed descriptions may obscure the essence of the present invention. Furthermore, while preferred embodiments of the present invention will be described below, the technical concept of the present invention is not limited or restricted thereto and can be modified and implemented in various ways by those skilled in the art. Hereinafter, with reference to the drawings, the method for generating an auxiliary instruction-based algorithm pattern in a high-speed memory test device and the apparatus for such method proposed in the present invention will be described in detail.

[0015] The present invention relates to a technology for an N-way parallel algorithm pattern generation device (ALPG) used in a high-speed memory test device. By accelerating the instruction synthesis process required to operate the N-way parallel algorithm pattern generation device by using auxiliary instructions, a memory test device capable of generating high-speed test patterns can be designed, and the total test time can be reduced.

[0016] Figure 1 is a diagram illustrating the operation of generating a test pattern in a general algorithm pattern generation device.

[0017] To implement recently popular new technologies such as artificial intelligence and big data, users wanted computing systems to be able to process vast amounts of data, and in response to this demand, the latest memory with significantly improved operating speeds became a factor that increased the difficulty of testing. Memory testing is performed by automated test equipment (ATE), and to determine whether the manufactured memory is functionally normal, a test pattern consisting of an address, data, and control signal must be input, which is generated by an algorithm pattern generation device (ALPG) inside the ATE.

[0018] Implementing an algorithm pattern generator compatible with the latest memory presents two major challenges. First, the algorithm pattern generator must generate test patterns at a speed that matches the memory's operating speed. However, algorithm pattern generators, which operate based on instructions similar to processors, generally run slower than hard-wired hardware. Therefore, to compensate for this, ALPGs feature a parallel ALPG structure that incorporates multiple internal pattern generators (PGs) in parallel to generate test patterns; however, such parallel algorithm pattern generators require significant additional costs. Second, as memory evolves and becomes functionally and structurally more complex, testing memory with a high failure detection rate requires algorithm pattern generators to produce test patterns that are more complex than before. This contributes to the additional costs mentioned in the first reason. The need to generate complex test patterns increases hardware overhead, making the configuration of parallel algorithm pattern generators more difficult.

[0019] Before explaining the additional costs required for operating a parallel algorithm pattern generator, Figure 1 (A) illustrates an example of the execution process of instructions received by an ALPG equipped with a single pattern generator. The algorithm pattern generator operates by decoding the received instructions and controlling the program counter (PC). In the sequential operation of the example, NOP means to execute the instruction at the PC+1 address after executing the corresponding instruction, and IDXIn means to repeat the instruction at the PC address as many times as specified in the index register #n. Accordingly, as shown in the bottom part of Figure 1 (A), a sequence is executed in which the operation of assigning 0 to the XC value and then incrementing it by 1 is repeated 200 times. The method of operating four pattern generators in parallel involves serializing each test pattern generated by the four pattern generators, which can generate test patterns four times faster than a conventional single pattern generator. However, for this to work, the test patterns generated by each pattern generator must be test patterns that take into account the interleaving operation of the four pattern generators.

[0020] It can be seen that in order to generate the test pattern of (A) in Fig. 1 in a structure of four parallel pattern generators, each pattern generator must execute different commands as shown in (B) of Fig. 1.

[0021] It is extremely difficult for ATE users to input different instructions for each pattern generator, taking into account factors such as the number of pattern generators that differ for each ATE and whether pattern generators can be operated in parallel depending on memory operation speed. For this reason, parallel algorithm pattern generators assume a single pattern generator structure and incorporate an instruction synthesizer that combines input instructions into the instructions to be executed by each parallel pattern generator. In addition to its own greater hardware overhead, this instruction synthesizer requires two additional costs.

[0022] First, since the instruction synthesizer reads one instruction per clock cycle to synthesize it, the parallel algorithm pattern generator requires instruction synthesis time in addition to the actual test pattern generation time. This implies an increase in the total test time. Hiding synthesis time by generating the actual test pattern immediately after instruction synthesis through a pipeline configuration is difficult to implement in the case of a parallel ALPG equipped with N pattern generators, as it must execute N instructions per clock cycle during actual test pattern generation. Second, because immediate test pattern generation via pipelines is impossible, an additional post-synthesis instruction memory (IM) must be provided to store the synthesized instructions.

[0023] FIG. 2 is a block diagram schematically showing an auxiliary instruction-based algorithm pattern generation device according to an embodiment of the present invention.

[0024] The algorithm pattern generation device (200) according to the present embodiment is connected to a compiler (100) and a DUT (Device Under Test, 300). The components shown in FIG. 1 are part of the components of a high-speed memory test device, and descriptions of the CPU, interface, etc., provided in a general high-speed memory test device are omitted.

[0025] The compiler (100) performs the operation of translating a test algorithm entered by a user into instructions. Here, the compiler (100) may be configured to operate within the CPU of a high-speed memory test device, but is not necessarily limited thereto.

[0026] The user's requirements for memory testing input to the compiler (100) can be input in a complex structure such as instructions for jumps and memory addresses, similar to code using a for loop.

[0027] The compiler (100) generates compiled instructions through compilation, and the compiled instructions can be classified into general instructions and auxiliary instructions. The data fields of the general instructions are basically the same as the existing ones, but identification information distinguishing between general instructions and auxiliary instructions is added to the first field.

[0028] The algorithm pattern generation device (200) according to the present embodiment includes a pre-synthesis instruction storage unit (210), an instruction synthesizer (220), an auxiliary instruction decoder (230), a plurality of pattern generators (240), and a serializer (250). The algorithm pattern generation device (200) of FIG. 2 is according to one embodiment, and not all blocks shown in FIG. 2 are essential components, and some blocks included in the algorithm pattern generation device (200) in other embodiments may be added, changed, or deleted.

[0029] The pattern generation operation of the algorithm pattern generation device (200) is as follows.

[0030] The pattern generation operation of the present invention begins with a series of test algorithms input by a user being translated into instructions by a compiler. During the process of reading the test algorithms for instruction translation, the compiler appropriately generates auxiliary instructions of the present invention according to the context.

[0031] Commands entered by the user are translated into instructions by the test device's internal compiler and input into the pre-synthesis instruction store. During this process, the compiler reads the instructions and, if necessary, generates auxiliary instructions to store alongside them in the pre-synthesis instruction store. Once all instructions have been entered, instruction synthesis proceeds rather than generating test patterns immediately. Test pattern generation begins only after the synthesis of all entered instructions has been completed.

[0032] Instruction synthesis involves the instruction synthesizer retrieving general instructions stored in the pre-synthesis instruction repository one by one, synthesizing instructions to be input into the pattern generator based on the information of previously retrieved instructions, and transmitting these instructions to the post-synthesis instruction repository within the pattern generator. In other words, instruction synthesis is a process that sequentially retrieves instructions stored in the pre-synthesis instruction repository, considers the relationships between multiple previously retrieved instructions and the currently retrieved instruction, and converts them into new instructions to be executed by each independently operating pattern generator.

[0033] Meanwhile, when the instruction to be fetched is an auxiliary instruction rather than a general instruction, the auxiliary instruction decoder fetches it instead.

[0034] The auxiliary instruction decoder decodes auxiliary instructions and transmits the information necessary for high-speed instruction synthesis to the instruction synthesizer, and the instruction synthesizer utilizes this to perform instruction synthesis faster than before.

[0035] The information generated through the decoding process assists in accelerating the instruction synthesis process; it is then transmitted to the instruction synthesizer, enabling instruction synthesis to be performed in fewer clock cycles compared to conventional methods. Since auxiliary instructions are used and discarded only during the instruction synthesis stage, they do not affect the test pattern generation stage of the pattern generator.

[0036] Although the information contained in auxiliary instructions can be generated by equipping hardware within the algorithm pattern generator, this requires relatively complex calculations, resulting in significant hardware overhead and potentially slowing down the overall system clock. Therefore, the information is generated in advance using the compiler's computational capabilities and delivered to the algorithm pattern generator in the form of auxiliary instructions. High-speed instruction synthesis using auxiliary instructions can be applied to various factors that make instruction synthesis difficult, such as instruction loop processing, branch instruction processing, and boundary condition processing.

[0037] The present invention relates to high-speed instruction synthesis using an auxiliary instruction to compensate for the disadvantage of separating the instruction synthesis step and the test pattern generation step for high-speed test pattern generation in an algorithm pattern generation device (200) that performs instruction synthesis through an instruction synthesizer.

[0038] Hereinafter, each component of the algorithm pattern generation device (200) according to the present embodiment will be described.

[0039] The pre-synthesis command storage unit (210) receives and stores a compiled command including at least one of a general command and an auxiliary command.

[0040] The pre-synthesis command storage unit (210) stores the compiled command including a plurality of fields. The compiled command includes an identification field in which identification information distinguishing between a general command or an auxiliary command is recorded.

[0041] Additionally, the compiled instruction includes a classification field in which classification information regarding the type of auxiliary instruction is recorded, a sequence field in which loop sequence information of the auxiliary instruction is recorded, and a loop field in which loop start information regarding the program counter where the auxiliary instruction loop starts is recorded.

[0042] Additionally, the compiled instruction includes a pattern field in which pattern start information for a pattern generator where the loop of the auxiliary instruction starts is recorded, a loop loop field in which loop loop information for the synthesis of the auxiliary instruction is recorded, a synthesis loop field in which synthesized instruction loop information of the pattern generator after synthesis is recorded, and an additional instruction execution field in which additional instruction execution information after synthesis is recorded.

[0043] The instruction synthesizer (220) performs the operation of synthesizing instructions for a loop based on information retrieved from a general instruction or high-speed synthesis auxiliary information.

[0044] The command synthesizer (220) sequentially retrieves general commands when the identification information of the identification field is a second identification value (e.g., 0), synthesizes commands to be input to each pattern generator one by one based on the information of the previously retrieved commands, and transmits them to the pattern generator.

[0045] When the instruction synthesizer (220) receives the high-speed synthesis auxiliary information from the auxiliary instruction decoder, it performs instruction synthesis with a minimum number of clocks by utilizing the high-speed synthesis auxiliary information.

[0046] The instruction synthesizer (220) deletes the high-speed synthesis auxiliary information based on auxiliary instructions without transmitting it to the pattern generator. As a result, no delay occurs in the pattern generation operation of the pattern generator (240).

[0047] The auxiliary instruction decoder (230) retrieves the auxiliary instruction when the compiled instruction includes the auxiliary instruction, and decodes the auxiliary instruction to generate high-speed synthetic auxiliary information.

[0048] The auxiliary command decoder (230) retrieves and decodes the auxiliary command when the identification information of the identification field is a first identification value (e.g., 1).

[0049] The auxiliary instruction decoder (230) decodes auxiliary instructions for at least one of instruction loop processing, branch instruction processing, and boundary condition processing to generate high-speed synthesis auxiliary information so that instruction synthesis is performed in the instruction synthesizer with a minimum number of clocks.

[0050] A plurality of pattern generators (240) generate test patterns based on synthesized commands. Each of the plurality of pattern generators (240) may include a post-synthesis command storage (not shown).

[0051] The pattern generator (240) is a part that generates a pattern for memory testing, and is basically composed of a sequence controller that determines the order of the pattern, an address generator that generates an address, a data generator that generates data to be written to the address, and a control signal generator that generates a signal to be entered into memory.

[0052] The serializer (250) serializes a plurality of the above test patterns and transmits the final test pattern to the test target device.

[0053] The DUT (300) is a device to be tested and may be a volatile memory device such as SRAM, DRAM, SDRAM, etc., or a non-volatile memory device such as ROM, PROM, EPROM, EEPROM, flash memory, PRAM, MRAM, RRAM, FRAM, etc., and a memory component including these. In addition, the DUT is not limited to a memory device or a memory package, and may be, for example, a memory module, memory card, or memory stick formed by combining memory components. Furthermore, the DUT may include various chips containing memory devices.

[0054] FIG. 3 is a flowchart illustrating an auxiliary instruction-based algorithm pattern generation method according to an embodiment of the present invention.

[0055] The test algorithm entered by the user is translated into instructions through a compiler (S310).

[0056] The algorithm pattern generation device (200) stores the translated command in the pre-synthesis command storage (S320).

[0057] The algorithm pattern generation device (200) performs instruction synthesis when all instructions to be executed are stored (S330).

[0058] The algorithm pattern generation device (200) checks whether the stored instruction is a general instruction (S340).

[0059] If the stored instruction is a general instruction, the algorithm pattern generation device (200) retrieves the stored general instruction from the instruction synthesizer (S350) and synthesizes the instruction to be input to each of the multiple pattern generators based on the information of the previously retrieved instructions (S360).

[0060] Meanwhile, if the stored instruction is an auxiliary instruction, the algorithm pattern generation device (200) retrieves the stored auxiliary instruction through the auxiliary instruction decoder (S342).

[0061] The algorithm pattern generation device (200) decodes auxiliary commands and transmits information required for high-speed command synthesis to the command synthesizer (S344), and synthesizes commands to be input to each of the multiple pattern generators based on information of previously retrieved commands (S360).

[0062] The algorithm pattern generation device (200) generates a test pattern by transmitting the synthesized command to each pattern generator (S370).

[0063] Afterwards, the algorithm pattern generation device (200) transmits the final test pattern, in which the stored command serializes a plurality of test patterns, to the DUT so that a memory test is performed (S380).

[0064] Although FIG. 3 describes each step as being executed sequentially, it is not necessarily limited to this. In other words, FIG. 3 is not limited to a chronological order, as it may be applicable to execute the steps described in FIG. 3 by modifying them or to execute one or more steps in parallel.

[0065] The algorithm pattern generation method according to the present embodiment described in FIG. 3 may be implemented as an application (or program) and recorded on a recording medium readable by a terminal device (or computer). The recording medium on which the application (or program) for implementing the algorithm pattern generation method according to the present embodiment is recorded and which is readable by a terminal device (or computer) includes all types of recording devices or media in which data that can be read by a computing system is stored.

[0066] FIG. 4 shows examples of two possible instruction synthesis processes when using instruction synthesizer hardware according to an embodiment of the present invention.

[0067] When an instruction synthesizer synthesizes instructions, instruction synthesis can proceed in two main ways, as shown in Fig. 4.

[0068] Referring to Figure 4(a), when using the first method, instruction synthesis and test pattern generation proceed in real-time, and since the pattern is generated immediately upon instruction synthesis, there is an advantage in that all clocks required for instruction synthesis are hidden. However, in this case, a parallel ALPG equipped with N pattern generators must complete a series of processes to fetch N existing instructions and perform instruction synthesis within one clock cycle, so the clock used cannot be faster than a certain level due to the complexity of the aforementioned process.

[0069] This means that the pattern generator clock, which is synchronized with the instruction synthesizer clock, cannot be sped up either, consequently implying that high-speed test pattern generation is impossible.

[0070] Therefore, for high-speed test pattern generation, it is desirable to separate the instruction synthesis process and the test pattern generation process, and to use the second method in which the instruction synthesizer fetches and synthesizes existing instructions one by one per clock cycle.

[0071] Referring to Figure 4(b), when using the second method, the instruction synthesis process is significantly simplified compared to the first method, so the clock required for instruction synthesis can be faster, and also, since the test pattern generation does not operate synchronously with the instruction synthesis, there is no need for the two modules to use the same clock.

[0072] However, the second method, which is suitable for generating high-speed test patterns, has the disadvantage that it requires many clocks for instruction synthesis.

[0073] In the case of a parallel ALPG equipped with N pattern generators, it produces the same effect as executing N existing instructions prior to synthesis (hereinafter referred to as pre-synthesis instructions) per clock cycle; therefore, if there are M pre-synthesis instructions to be executed, M / N clock cycles are used for test pattern generation.

[0074] However, if the instruction synthesizer fetches and synthesizes only one instruction per clock cycle, M clock cycles are fully utilized for instruction synthesis; therefore, the clock cycles required for instruction synthesis cannot be fully hidden through the synthesis-generation pipeline.

[0075] Consequently, M clocks are required for the final processing of M pre-synthesized instructions.

[0076] The present invention proposes a technique for high-speed instruction synthesis using auxiliary instructions to compensate for the disadvantage of using many instruction synthesis clocks when separating the instruction synthesis step and the test pattern generation step for high-speed test pattern generation in an ALPG that performs instruction synthesis through an instruction synthesizer.

[0077] FIG. 5 is a diagram showing the execution of a command including a repetition command according to an embodiment of the present invention.

[0078] Figure 5 is an example of a test program containing a repeating instruction that is repeated many times. Here, JNI ST0 is a repeating instruction that means to return to the PC tagged with ST0 after executing this instruction and repeat a certain sequence of instructions. Similarly, JNI repeats the instruction as many times as the value of the specified index register. In this example, it is repeated 192 times.

[0079] Therefore, the example in Fig. 5 shows that through JNI, addition is performed 192 times, with the XC register increasing sequentially from 1 to 6. The bottom part of Fig. 5 shows the instructions required for each pattern generator to execute the upper pattern program by the parallel ALPG. As can be seen in Fig. 5, when synthesizing an instruction sequence including a repetition instruction, it can be seen that the synthesized instruction also has a repeating part, and by utilizing this point, synthesis information for the repetition instruction synthesis proposed in the present invention is generated.

[0080] FIG. 6 is a diagram showing auxiliary instructions that support high-speed synthesis for instructions constituting a loop according to an embodiment of the present invention.

[0081] The pre-synthesis command storage unit (210) stores the compiled command including a plurality of fields. The compiled command includes an identification field (610) in which identification information distinguishing between a general command or an auxiliary command is recorded. Here, the identification field (610) may correspond to SYN.

[0082] Additionally, the compiled instruction includes a classification field (612) in which classification information regarding the type of auxiliary instruction is recorded, a sequence field (614) in which loop sequence information of the auxiliary instruction is recorded, and a loop field (616) in which loop start information regarding the program counter where the loop of the auxiliary instruction starts is recorded. Here, the classification field (612) may correspond to OPC, the sequence field (614) may correspond to NUM, and the loop field (616) may correspond to NXT.

[0083] Additionally, the compiled instruction includes a pattern field (618) in which pattern start information for a pattern generator where the loop of the auxiliary instruction starts is recorded, a loop repetition field (620) in which loop repetition information for the synthesis of the auxiliary instruction is recorded, a synthesis repetition field (622) in which synthesized instruction repetition information of the pattern generator after synthesis is recorded, and an additional instruction execution field (624) in which additional instruction execution information after synthesis is recorded. Here, the pattern field (618) may correspond to POS, and the loop repetition field (620) may correspond to CYC. Additionally, the synthesis repetition field (622) may correspond to ITER, and the additional instruction execution field (624) may correspond to MOD.

[0084] For example, in the case of an auxiliary command for command loop processing, an auxiliary command such as that shown in Fig. 6 can be configured as an example.

[0085] In the example of Figure 6, SYN has 1 bit added as a bit to distinguish whether the instruction is a general instruction or an auxiliary instruction containing synthesis information.

[0086] OPC indicates the purpose of the synthesis information and indicates which auxiliary instruction it is among the auxiliary instructions. In this example, when it is 00, it is an auxiliary instruction for instruction loop processing (repetitive instruction synthesis).

[0087] NUM indicates which loop in the instruction sequence the auxiliary instruction of the corresponding synthesis information is for.

[0088] NXT indicates from which PC (Program Counter) the loop will start following the address of the auxiliary instruction's PC. In other words, NXT indicates how many instructions after the main instruction the loop instruction specified by NUM begins. POS indicates from which of the parallel pattern generators the loop starts. NXT and POS are necessary information due to dependencies between registers.

[0089] CYC indicates how many times a loop must be repeated to synthesize a specified loop. CYC has a significant impact on greatly accelerating loop synthesis through this synthesis information. ITER indicates the total number of times each PG must repeat the synthesized iterative instruction after synthesis, while MOD specifies how many additional instructions must be executed after synthesis to match the number of iterations before synthesis. CYC, ITER, and MOD are key pieces of information that can drastically reduce the clock cycles required for instruction synthesis. The core of the method to accelerate instruction loop synthesis by utilizing the aforementioned information lies in the fact that the instruction loop remains an instruction loop even after being synthesized into instructions for N pattern generators. When instruction synthesis is performed without utilizing this point, the instruction synthesizer continues to fetch the instructions before synthesis until the number of iterations of the instruction loop is exhausted.

[0090] Given the significant recent improvement in memory density, the proportion of instruction loops within the overall instruction sequence has increased substantially; consequently, conventional methods consume an enormous amount of time for instruction synthesis. However, by leveraging the fact that the instruction loop prior to synthesis becomes the instruction loop following synthesis, the clock time required for instruction loop synthesis can be drastically reduced, ultimately leading to a substantial decrease in the total clock time required for instruction loop synthesis.

[0091] Examples of using the auxiliary command of Fig. 6 are described in Figs. 8 and 9.

[0092] FIG. 7 is a diagram illustrating a command synthesis operation according to an embodiment of the present invention.

[0093] The reason the aforementioned information is required for fast loop instruction synthesis can be confirmed through Fig. 7. The test sequence in Fig. 7 is that of Fig. 5. A to D on the right side of the operation column represent the method of synthesizing the operations that PG-A to D must perform, respectively. The parts marked in bold represent the operations that the corresponding pattern generator must perform in sequence, and the parts enclosed in squares including the parts marked in bold represent the bundle of operations that each pattern generator must actually perform cumulatively for this purpose.

[0094] The reason why NXT and POS are needed for synthesis information is shown in sequences #1 through 4.

[0095] Sequence #1 is an instruction that is not included in the loop instruction, but it is an instruction that provides a write-after-read dependency with the loop instruction described later. For this reason, the operation of Sequence #1 cannot be ignored during loop instruction synthesis and affects instruction synthesis for the following three sequences. Since actual loop instruction synthesis starts from Sequence #2, PG-B, and instructions over four sequences are synthesized to perform one clock operation of each pattern generator, the four sequences starting from Sequence #2 are grouped into a single cycle, and this first cycle becomes the cycle affected by XC < 0. This is indicated in blue in Fig. 7. Generalizing this, if there are instructions providing a write-after-read dependency among the three instructions prior to the start of the loop, the first cycle of the loop produces a synthesis result different from subsequent cycles due to the influence of the previous instructions. This is also indicated at the bottom of Fig. 5. While this process can be easily understood by listing the entire test sequence as in Fig. 7, it is difficult to judge when reading instructions one by one; therefore, NXT and POS are used as references for instruction synthesis.

[0096] FIG. 8 is a diagram showing an example in which a plurality of instructions stored in a pre-synthesis instruction storage according to an embodiment of the present invention form a repeating loop and auxiliary instructions are arranged.

[0097] Figure 8 shows that the second instruction is marked as ST0, and JNI ST0 of the seventh instruction means to return to the instruction marked as ST0, so the second instruction to the seventh instruction are combined into a single instruction loop. The number of iterations of the instruction loop refers to the value of a specific internal ALPG register, and in this example, it is assumed to be 192 times. In this case, if instructions are synthesized using the conventional method, 1 + 7 * 192 clocks are required.

[0098] Specifically, FIG. 8 shows that synthesis information has been added to the instruction sequence of FIG. 5. It indicates that instruction synthesis should start with XC < 0, positioned one instruction ahead of XC < 0.

[0099] In addition, it indicates that the loop will start from XC < XC+1, after NXT (1) instructions. Also, since it can be seen that the pattern generator will repeat the three cycles shown in green after the cycle shown in Fig. 7, it suggests that if instructions are synthesized for a clock cycle equal to the product of the number of pattern generators (N) and a certain number of cycles (CYC), the subsequent instructions can be processed as repeat instructions. Through this process, the time required for synthesis can be significantly reduced compared to the conventional method of simply reading instructions one by one to synthesize instructions.

[0100] FIG. 9 is a diagram showing the result after the instruction loop of FIG. 8 according to an embodiment of the present invention is synthesized for four pattern generators.

[0101] However, looking at Fig. 9, which is the result of synthesizing the pre-synthesis instruction of Fig. 8, since the post-synthesis instruction also forms a loop, it can be confirmed that instruction synthesis only needs to be performed during one iteration in which the instruction constituting the loop for each pattern generator is derived. In this process, the information required is the aforementioned CYC, ITER, and MOD, so if there are N pattern generators, the instruction synthesizer only needs to fetch the pre-synthesis instruction for N*(CYC+1) clock cycles to perform synthesis.

[0102] The number of iterations of the completed post-synthesis instruction loop is ITER, and MOD represents the number of remaining instructions that were not included in the post-synthesis instruction loop during the process of converting the pre-synthesis instruction loop into the post-synthesis instruction loop. It is information that adds several instructions following the post-synthesis instruction loop to some pattern generators in combination with POS information. In conclusion, in this example, when synthesizing the instruction loop using auxiliary instructions, only 1+4*(3+1) clocks are required for the synthesis of the entire instruction sequence.

[0103] Specifically, since the repetition instruction after synthesis has a different number of repetitions than before synthesis, it can be seen that the value of the index register has changed to 97.

[0104] In addition, in the case of PG-B and C, XC < XC+14 and XC < XC+18 are performed once more even after the repetition instruction, which is to match the 192 repetitions of the repetition instruction in Fig. 5.

[0105] Synthesis can be performed by referring to ITER to determine how many times the repeat instruction needs to be repeated after synthesis, and by referring to MOD to determine how many additional instructions the parallel pattern generators need to synthesize after synthesis.

[0106] Each of the CYC, ITER, and MOD written in the auxiliary command is derived by mathematical formulas 1 to 3.

[0107]

[0108]

[0109]

[0110] N is the number of pattern generators in the parallel ALPG, O_ITER is the number of iterations of the iteration instruction prior to synthesis, and LEN is the number of instructions constituting the loop. Since this is computationally complex and difficult to implement in hardware, it can be handled by having the compiler calculate it and write it into the synthesis information.

[0111] The foregoing description is merely an illustrative explanation of the technical concept of the embodiments of the present invention, and those skilled in the art to which the embodiments of the present invention pertain will be able to make various modifications and variations within the scope that does not deviate from the essential characteristics of the embodiments of the present invention. Accordingly, the embodiments of the present invention are intended to explain, not limit, the technical concept of the embodiments of the present invention, and the scope of the technical concept of the embodiments of the present invention is not limited by these embodiments. The scope of protection of the embodiments of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the embodiments of the present invention. Explanation of the symbols

[0112] 100: Compiler 200: Algorithm Pattern Generator 210: Pre-synthesis command storage 220: Command synthesizer 230: Auxiliary instruction decoder 240: Multiple pattern generators 250: Serial weapon 300: DUT

Claims

Claim 1 An algorithm pattern generation device for generating an auxiliary instruction-based algorithm pattern in a high-speed memory test device, comprising: a pre-synthesis instruction storage unit that receives and stores a compiled instruction including at least one of a general instruction and an auxiliary instruction; an auxiliary instruction decoder that retrieves the auxiliary instruction when the compiled instruction includes the auxiliary instruction and decodes the auxiliary instruction to generate high-speed synthesis auxiliary information; an instruction synthesizer that synthesizes instructions for a loop based on the information retrieved from the general instruction or the high-speed synthesis auxiliary information; a plurality of pattern generators that generate a test pattern based on the synthesized instruction; and a serializer that transmits a final test pattern serialized from a plurality of test patterns to a test target device, wherein the pre-synthesis instruction storage unit stores the compiled instruction including a plurality of fields, and the compiled instruction includes an identification field in which identification information distinguishing the general instruction or the auxiliary instruction is recorded; and the instruction synthesizer is characterized by performing instruction synthesis with a minimum clock speed by utilizing the high-speed synthesis auxiliary information when the high-speed synthesis auxiliary information is received from the auxiliary instruction decoder. Claim 2 delete Claim 3 An algorithm pattern generation device according to claim 1, wherein the compiled instruction comprises a classification field in which classification information regarding the type of the auxiliary instruction is recorded, a sequence field in which loop sequence information regarding the auxiliary instruction is recorded, and a loop field in which loop start information regarding the program counter where the loop of the auxiliary instruction starts is recorded. Claim 4 An algorithm pattern generation device according to paragraph 3, wherein the compiled instruction comprises a pattern field in which pattern start information for a pattern generator in which a loop of the auxiliary instruction starts is recorded, a loop repetition field in which loop repetition information for the synthesis of the auxiliary instruction is recorded, a synthesis repetition field in which the synthesized instruction repetition information of the pattern generator after synthesis is recorded, and an additional instruction execution field in which additional instruction execution information after synthesis is recorded. Claim 5 An algorithm pattern generation device according to claim 1, wherein the auxiliary command decoder retrieves and decodes the auxiliary command when the identification information of the identification field is a first identification value. Claim 6 An algorithm pattern generation device according to claim 5, wherein the auxiliary instruction decoder generates high-speed synthesis auxiliary information by decoding an auxiliary instruction for at least one of instruction loop processing, branch instruction processing, and boundary condition processing to perform instruction synthesis with a minimum clock speed in the instruction synthesizer. Claim 7 An algorithm pattern generation device according to claim 1, wherein the command synthesizer sequentially retrieves general commands when the identification information of the identification field is a second identification value, synthesizes commands to be input to each of the pattern generators one by one based on the information of the previously retrieved commands, and transmits them to the pattern generators. Claim 8 delete Claim 9 An algorithm pattern generation device according to claim 1, wherein the instruction synthesizer deletes the high-speed synthesis auxiliary information based on the auxiliary instruction without transmitting it to the pattern generator. Claim 10 A method for generating an algorithm pattern based on auxiliary instructions in an algorithm pattern generation device included in a high-speed memory test device, comprising: a pre-synthesis instruction storage step for receiving and storing a compiled instruction including at least one of a general instruction and an auxiliary instruction; an auxiliary instruction decoding step for retrieving the auxiliary instruction when the compiled instruction includes the auxiliary instruction and decoding the auxiliary instruction to generate high-speed synthesis auxiliary information; an instruction synthesis step for synthesizing instructions for a loop based on the information retrieved from the general instruction or the high-speed synthesis auxiliary information; a plurality of pattern generation steps for generating a test pattern based on the synthesized instruction; and a serialization processing step for transmitting a final test pattern, serialized from a plurality of test patterns, to a test target device, wherein the pre-synthesis instruction storage step stores the compiled instruction including a plurality of fields, wherein the compiled instruction includes an identification field in which identification information distinguishing the general instruction or the auxiliary instruction is recorded; and the instruction synthesis step is characterized by performing instruction synthesis with a minimum clock speed by utilizing the high-speed synthesis auxiliary information when the high-speed synthesis auxiliary information is received from the auxiliary instruction decoding step.

Images