Hybrid Analog-to-Digital Converter Circuit for performing Self-Successive Doubling Operation and Successive Approximation Register Operation

Abstract

A hybrid ADC circuit is disclosed that digitally converts the upper bits of 2N digital code bits through an SSD operation and digitally converts the remaining lower bits through a SAR operation. The difference between the pixel voltage supplied by the CIS and the negative reference voltage is amplified by a factor of 2, and then an SSD operation is performed based on this. The difference between the previous state's self-comparison voltage and the negative reference voltage is amplified by a factor of 2 and compared with the reset voltage to form a digital code. Additionally, if the self-comparison voltage is greater than or equal to the reset voltage, a reset operation of the self-comparison voltage is performed.

Description

Technology Field

[0001] The present invention relates to an ADC circuit that converts an analog signal into a digital code, and more specifically, to an ADC (Analog to Digital Converter) circuit that performs SSD (Self-Successive Doubling) operation and SAR (Successive Approximation Register) operation. This patent is a result derived as part of the “Seoul Regional Innovation Center University Support System (RISE),” which was conducted with funding from the Ministry of Education and the Seoul Metropolitan Government and supported by the Seoul RISE Center in 2025. (2025-RISE-01-007-04) Background Technology

[0002] Light incident on the CMOS image sensor is converted into an electrical signal, and the converted electrical signal is transmitted to the ADC. The ADC transmits the converted digital code externally to form an image signal. The CIS (CMOS Image Sensor) constituting the pixel sequentially [uses] the reset voltage V RST and signal voltage V SIG Prints V RST is the voltage when the pixel is reset, corresponding to a high reference value. Also, the signal voltage V SIG represents the voltage of the CIS reduced by the incident light, and V RST and V SIG The CDS (Correlated Doubling Sampling) technique is a method that removes pixel noise by deriving the difference.

[0003] The aforementioned CDS technique or circuit is implemented by a SAR (Successive Approximation Register) ADC. This is referred to as successive approximation operation, a method that derives a digital approximation by continuously comparing the input analog voltage with a reference voltage. To achieve this, it consists of sampling, comparison operations, and bit-unit approximation iteration. A sample-and-hold circuit, a register, and a comparator are required for this purpose.

[0004] Figure 1 is a schematic diagram illustrating the operation of a CDS through a SAR ADC according to the prior art.

[0005] Referring to FIG. 1, the SAR ADC has an input voltage generating unit (10), a comparison voltage generating unit (20), a comparator (30), and a logic unit (40).

[0006] In the input voltage generating unit (10), V RST and V SIG V, the difference value of IN This is formed. The comparison voltage generating unit (20) receives a switching control signal SW formed by the logic unit (40) according to the output of the comparator (30). The reference voltage V of the comparison voltage generating unit (20) is formed by the switching control signal SW. CDAC is determined. The input voltage V corresponding to the analog voltage in the comparator (30) is determined. IN and reference voltage V CDAC It is compared and formed into a digital output.

[0007] Meanwhile, the reference voltage V CDAC It changes according to the formed digital code, so the digital code is V IN It operates to approximate.

[0008] For example, the difference value V IN The maximum voltage range of this branch is called Vpp, and this is the maximum value V REFH (=V RST ) and minimum value V REFL It is the difference of, and V IN It is set within the above range. MSB is V INIt is obtained by comparing with Vpp / 2, and the next most significant bit is a new reference value V set by the bit obtained in the previous step. CDAC and V IN It is determined through a comparison. A new reference value V is determined based on the code from the previous step. CDAC Vpp / 2 ± Vpp / 4 is determined by comparison. Vpp / 8 is subtracted or added to subsequent low bits.

[0009] V in the above operation IN For the formation of , the signal voltage V SIG It is necessary to sample and store, and this is reset voltage V RST A subtraction operation is required. That is, a separate amplifier, capacitor, and switch are required for the sample & hold operation.

[0010] Furthermore, to achieve high resolution, the number of comparisons must increase, and the number of bits in the output digital code must also increase. To this end, the reference voltage V for the comparison operation is required. CDAC The number of times it is formed also increases. Typically, the reference voltage V CDAC The formation is achieved by the switching control signal SW supplied from the SAR logic circuit. When the resolution is N bits, the switching control signal is used to switch the reference voltage supplied to one end of N capacitors connected in parallel.

[0011] FIG. 2 shows the reference voltage V of FIG. 1 according to the prior art. CDAC This is a circuit diagram to explain the formation of.

[0012] Referring to FIG. 2, a digital code, which is the output of a comparator, is input to the logic unit. The logic unit receives and stores the digital code and forms a switching control signal SW. The switching control signal SW is applied to a comparison voltage generation unit.

[0013] The above comparison voltage generation unit requires N+1 capacitors if the digital code to be generated is N bits. However, in the actual semiconductor manufacturing process, the unit capacitance of a capacitor is defined as Cu, and the maximum capacitance is 2 N-1 If we speak of Cu, the maximum capacitance is 2 N-1 It is impossible to form Cu into a single capacitor. Typically, unit capacitance Cu is 2 N-1 The desired maximum capacitance is achieved by connecting them in parallel. Therefore, although it is depicted as a simple parallel connection of capacitors in the equivalent circuit, in reality, it is 2 0 Cu, 2 0 Cu, 2 1 Cu, ..., 2 N-1 To implement Cu capacitors, the unit capacitor Cu is 2 N They must be connected in parallel. This occupies an excessive amount of chip area in the semiconductor process and remains a burden for the designer.

[0014] In other words, if an ADC operation is performed on a portion of the upper bits during CDS operation, and a normal SAR ADC operation is performed on the remaining lower bits, the number of capacitors used will be drastically reduced. The problem to be solved

[0015] The technical problem that the present invention aims to solve is to provide a hybrid ADC capable of performing SSD operation and SAR operation in a single circuit. means of solving the problem

[0016] The present invention, for achieving the aforementioned technical problem, relates to a hybrid ADC that forms a 2N-bit digital code, wherein the upper bits are formed through an SSD operation in which a self-comparison voltage, in which the difference between the signal voltage of a CIS and a negative reference voltage is amplified by a factor of 2, is compared with a reset voltage of a pixel voltage to form a digital code, and the remaining lower bits are formed through a SAR operation in which a determination voltage finally derived by the SSD operation is compared with an approximation voltage that approximates the determination voltage, wherein the hybrid ADC

[0017] A hybrid ADC circuit is provided comprising: a self-comparison voltage generation unit that forms a new current self-comparison voltage by amplifying the difference between the previous self-comparison voltage formed in the previous step and the negative reference voltage by a factor of two; a continuous approximation voltage generation unit that supplies the reset voltage; a comparison unit that receives the reset voltage from the continuous approximation voltage generation unit and receives the current self-comparison voltage from the self-comparison voltage generation unit to form a digital code through a comparison operation; and an SSD logic unit that forms a self-control signal according to the digital code of the previous step in the SSD operation and induces the generation of the current self-comparison voltage of the self-comparison voltage generation unit through a switching operation of the self-comparison voltage generation unit. Effects of the invention

[0018] According to the present invention described above, for a 2N-bit digital conversion operation, digital conversion is first performed on the upper bits through an SSD operation. Once the digital conversion through the SSD is completed, a SAR operation is performed on the remaining lower bits. Through this, the operation speed for digital conversion is improved, and the number of required unit capacitors can be drastically reduced. Brief explanation of the drawing

[0019] Figure 1 is a schematic diagram illustrating the operation of a CDS through a SAR ADC according to the prior art. FIG. 2 shows the reference voltage V of FIG. 1 according to the prior art. CDAC This is a circuit diagram to explain the formation of. FIG. 3 is a circuit diagram illustrating a hybrid ADC circuit according to a preferred embodiment of the present invention. FIG. 4 is a timing diagram for explaining the SSD operation of the hybrid ADC of FIG. 3 according to a preferred embodiment of the present invention. FIG. 5 is an equivalent circuit for explaining the initialization operation of FIG. 4 according to a preferred embodiment of the present invention. FIG. 6 is an equivalent circuit for explaining the first SSD operation of FIG. 4 according to a preferred embodiment of the present invention. FIG. 7 shows the self-comparison voltage V derived from FIG. 6 according to a preferred embodiment of the present invention. IP1 This is an equivalent circuit and timing diagram illustrating the reset operation of. FIG. 8 is an equivalent circuit for explaining the SSD operation for the upper second bit of FIG. 4 following FIG. 7, according to a preferred embodiment of the present invention. Figure 9 is a circuit diagram and timing diagram illustrating a continuous approximation voltage generation unit capable of performing SAR operation. Specific details for implementing the invention

[0020] The present invention is susceptible to various modifications and may take various forms; therefore, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the invention to the specific disclosed forms, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. Similar reference numerals have been used for similar components in the description of each drawing.

[0021] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0022] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings.

[0024] Examples

[0025] FIG. 3 is a circuit diagram illustrating a hybrid ADC circuit according to a preferred embodiment of the present invention.

[0026] Referring to FIG. 3, the hybrid ADC circuit has a self-comparison voltage generation unit (100), a successive approximation voltage generation unit (200), a comparison unit (300), an SSD logic unit (400), and a SAR logic unit (500).

[0027] Pixel voltage V supplied from the CIS PIX is the signal voltage V SIG and reset voltage V RST It consists of signal voltage V. SIG and reset voltage V RST is pixel voltage V PIX It forms one cycle of. That is, the signal voltage V SIG After is applied, reset voltage V RST A is applied. When light is incident on the CIS that was reset in the previous cycle, the signal voltage V SIG A is formed, and the signal voltage V is formed. SIG is the reset voltage V RST It has a lower level compared to. Signal voltage V SIG After is supplied to the hybrid ADC circuit, the reset voltage V RSTPixel voltage V is applied PIX A reset is performed.

[0028] In addition, the hybrid ADC of Fig. 3 above has an SSD operation mode and a SAR operation mode in a time series.

[0029] In SSD operation mode, the self-comparison voltage V formed in the self-comparison voltage generating unit (100) IP and reset voltage V RST is compared. Through this, the upper N bits of the 2N-bit digital code are formed. Subsequently, the SAR operation mode is performed, and the approximation voltage V supplied from the continuous approximation voltage generation unit (200) is compared. IN and the determination voltage V of the self-comparison voltage generation unit IP * It is compared with the above determination voltage V. IP * This corresponds to the voltage set by the final operation of the self-comparison voltage generation unit described later.

[0030] The continuous approximation voltage generation unit (200) for the above SAR operation has a conventional SAR operation mode known in the art. However, as the SSD operation mode precedes it, in the SSD operation mode, a digital conversion operation is performed on the upper N bits of a 2N-bit digital code, and finally, the self-comparison voltage generation unit (100) determines the voltage V IP * Generates. Determination voltage V IP * In the SAR operation mode that follows for , a digital conversion operation for the lower N bits is performed.

[0031] In the following description of the present invention, it is explained that the digital code to be formed has 2N bits, and that digital conversion is performed on the upper N bits through an SSD operation, and digital conversion is performed on the lower N bits through a SAR operation. However, if the digital code to be converted has 2N bits, it does not deviate from the spirit of the present invention if some of the upper bits are digitally converted through an SSD operation and the remaining lower bits are SAR operated.

[0032] The SSD logic unit (400) receives a digital code generated by the comparator (300) and, based on the digital code generated in the SSD operation mode, sends a self-control signal Φ to the self-comparison voltage generation unit (100). n Supplies the self-control signal Φ above. n The switching operation of the self-comparison voltage generation unit (100) is performed by means of, and the self-comparison voltage V IP is generated.

[0033] The SAR logic unit (500) receives a digital code of the lower N bits generated during the SAR operation and forms a switching control signal SW. Based on the switching control signal SW, the continuous approximation voltage generation unit (200) forms an approximation voltage, and the approximation voltage is the negative input terminal V of the comparison unit (00). IN It is entered into.

[0034] The above self-comparison voltage generation unit (100) performs SSD operation. That is, the circuit itself generates the self-comparison voltage V from the previous stage. IP and negative reference pressure V REFL It performs an operation that doubles the difference. The self-comparison voltage generating unit (100) generates the self-comparison voltage V IP Generate and input this into the comparison unit (300).

[0035] While SSD operation is being performed in the self-comparison voltage generation unit (100) above, the continuous approximation voltage generation unit (200) stops operation, and a reset voltage V is applied to the negative input terminal of the comparison unit (300). RST It supplies. That is, the input V of the comparison unit (300) in FIG. 3 above. IN is V RST It becomes.

[0036] For the above-described operation, the self-comparison voltage generating unit (100) has a first capacitor unit (110), a first switching unit (120), a second switching unit (130), and an amplifier unit (140).

[0037] The first capacitor section (110) is composed of a plurality of capacitors connected in parallel to the negative input terminal of the amplifier section (140). Each of the first capacitor sections (110) is 2 N-1 Cu, 2 N-2 Cu, ..., 2 1 Cu, 2 0 Cu and 2 0 It consists of N+1 capacitors, each having a capacitance of Cu. That is, the first capacitor section consists of a unit capacitor Cu acting as a buffer capacitor and N capacitors that increase geometrically with respect to the unit capacitor Cu. In addition, 2 having the largest capacitance N-1 Cu is defined as the top-level capacitor, and the lower-level capacitors are defined based on this.

[0038] One end of the capacitors is commonly connected to the negative input terminal of the amplifier (140), and the other end is connected to the first switching unit (120). In particular, the two at the outermost end 0 Cu acts as a buffer capacitor, and the total capacitance of the first capacitor section (110) is 2 N Make it Cu.

[0039] The first switching unit (120) has N+1 switches, each assigned to a respective capacitor. One end of the parallel-connected switches is connected to the first capacitor unit (110), and the other end is connected to the pixel voltage V PIXAlternatively, it is connected to the second switching unit (130). Through the operation of the first switching unit (120), the initial total charge amount in the first capacitor unit (110) can be set, and through the second switching unit (130), the self-comparison voltage V IP A can be generated. Additionally, the switch at the end of the first switching unit (120) is connected to the other end of the buffer capacitor, and the other end of the end switch is connected to the pixel voltage V. PIX or self-comparison voltage V IP It connects to.

[0040] The first switching unit (120) above has a set control signal Φ SET Pixel voltage V by PIX Or it is connected to the second switching unit (130). Set control signal Φ SET When this is activated or becomes a high level, the first switching unit (120) switches the capacitors of the first capacitor unit (110) to the pixel voltage V PIX Connect to. Pixel voltage V PIX When connected to, the first capacitor unit (110) is initialized, and the total amount of charge stored in the entire first capacitor unit (110) is determined.

[0041] Set control signal Φ SET When this is a low level or inactive state, the first capacitor unit (110) is connected to the second switching unit (130). The switching operation of the second switching unit (130) is a self-control signal Φ n It is determined by, and through this, SSD operation is performed.

[0042] One end of the second switching unit (130) is connected to the first switching unit (120), and the other end of the second switching unit (130) is connected to the pixel voltage V PIX , negative reference voltage V REFL or self-comparison voltage V IP It is connected to. The second switching unit (130) has N switches connected in parallel, and the other end of the first switch is connected to the pixel voltage V. PIX or negative reference voltage V REFLIt is connected to, and the other ends of the remaining N-1 switches are connected to the pixel voltage V PIX , negative reference voltage V REFL or self-comparison voltage V IP It is connected to. That is, the second switching unit (130) does not separately provide a switch connected to the buffer capacitor.

[0043] The amplifier (140) performs selective negative feedback operation. To this end, a negative feedback switch is provided between the negative input terminal and the output terminal, and the negative feedback switch is a set control signal Φ SET It is turned on by. The amplifier (140) has an amplifier, and the amplifier may be a normal OP-AMP or an amplifier with a predetermined gain.

[0044] The negative input terminal of the amplifier (140) is to which the voltage of one end of the first capacitor (110) is applied, and the positive input terminal is to which the negative reference voltage V is applied. REFL It is connected to. Since a virtual short circuit exists at the input terminal of the amplifier (140), the negative input terminal is also connected to the negative reference voltage V. REFL It is set to.

[0045] In particular, the set control signal Φ SET When activated, the negative feedback path is completed, and the self-comparison voltage V IP is the negative reference voltage V REFL It is set to. That is, the initialization operation is the set control signal Φ SET It is performed by the activation of, and the self-comparison voltage V by the initialization operation IP is the negative reference voltage V REFL It is set to.

[0046] Set control signal Φ SET When the activation of is stopped, the amplifier has an open-circuit gain, and the self-comparison voltage V IP Creates.

[0047] The hybrid ADC of the present invention sequentially performs SSD mode operation and SAR mode operation. Through SSD mode operation, the pixel voltage V PIXThe signal voltage V included in SIG and negative reference voltage V REFL The difference value of increases by a factor of 2, and this is the reset voltage V RST It is compared with. Through this, the signal voltage V to be converted into a 2N-bit digital code SIG The upper N bits of can be obtained through SSD mode operation.

[0048] In addition, in the present invention, the set control signal Φ SET , SAR control signal Φ SAR It can be supplied through a separate controller, and can also be supplied from a processor, etc.

[0049] First, a description of the SSD operation mode is disclosed.

[0050] FIG. 4 is a timing diagram for explaining the SSD operation of the hybrid ADC of FIG. 3 according to a preferred embodiment of the present invention.

[0051] Referring to Fig. 4, for convenience of explanation, the upper N bits of the digital code converted through the SSD operation mode are set to 6 bits.

[0052] First, an initialization operation is performed immediately before the SSD operation mode. The initialization operation is the SAR control signal Φ SAR Through, the negative input terminal V of the comparison section IN Pixel voltage V PIX Connect and set control signal Φ SET Through this, all switches of the first switching unit pixel voltage V PIX It is connected to. In addition, the negative feedback switch is turned on, and the amplifier performs negative feedback operation.

[0053] FIG. 5 is an equivalent circuit for explaining the initialization operation of FIG. 4 according to a preferred embodiment of the present invention.

[0054] Referring to FIG. 5, the other end of the first capacitor part (110) is the pixel voltage V PIX It is connected to, and pixel voltage V PIX is the signal voltage VSIG It has the size of. Also, due to the virtual short circuit, the negative input terminal of the amplifier (140) has a negative reference voltage V. REFL It has. Therefore, the total charge stored in the first capacitor part (110) follows the following formula 1.

[0055] [Formula 1]

[0056]

[0057] In Equation 1 above, the voltage difference ΔV across the capacitor section SIG is V SIG -V REFL Defined as. ΔV SIG is the voltage difference across the first capacitor section (110), and the signal voltage V SIG and negative reference voltage V REFL It refers to the difference value. Typically, the negative reference voltage V REFL This represents the lowest level that signals can have during the operation of semiconductor devices including CIS, and this can be understood as ground.

[0058] Referring again to FIG. 4, the SSD operation mode is executed. Set control signal Φ SET It is deactivated, and the negative feedback switch is turned off. Additionally, the first switching unit connects the first capacitor unit to the second switching unit. Furthermore, in SSD operation mode, the pixel voltage V PIX is the reset voltage V RST It is set to.

[0059] Top capacitor 2 in section 1 5 The first switch connected to Cu has a negative reference voltage V REFL It is connected to, and the remaining switches are connected to the self-comparison voltage V IPIt is connected to. Through this, the first SSD operation is performed. The operation for the first switch is such that the capacitance connected thereto is the largest, which corresponds to the most significant bit among the 6 bits to be converted. That is, in the present invention, the SSD operation applies a negative reference voltage V to a capacitor to which a weighted capacitance is assigned so as to correspond from the most significant bit to the least significant bit to be converted. REFL It is an action that connects.

[0060] Below, the upper order of N bits of the switch operated through the second switching unit is determined according to the capacitance of the capacitor connected thereto.

[0061] FIG. 6 is an equivalent circuit for explaining the first SSD operation of FIG. 4 according to a preferred embodiment of the present invention.

[0062] 2 5 The negative reference voltage V on Cu REFL This is applied, and due to the virtual short circuit of the amplifier (140), 2 5 The amount of charge stored in Cu is 0. Also, at the other end of the remaining capacitors, the self-comparison voltage V, which is the output of the amplifier (140), is IP is connected. The self-comparison voltage generated by the operation of the switch is V IP1 Defined as such, and applying the law of conservation of charge, the following Equation 2 is obtained.

[0063] [Equation 2]

[0064]

[0065]

[0067] Derived self-comparison voltage V IP1 and negative reference voltage V REFL The difference is the signal voltage V SIG and negative reference voltage V REFL The difference ΔV SIG It has been doubled. The above self-comparison voltage V IP1 The pixel voltage V is applied to the positive input terminal of the comparator (300).PIX In reset voltage V RST It is compared to.

[0068] Comparison result: Reset voltage V RST Self-comparison voltage V compared to IP1 If this is low, the comparator (300) outputs digital code 0, and the self-comparison voltage V IP1 This reset voltage V RST If it is greater than or equal to, output digital code 1.

[0069] When digital code 0 is output from the comparator (300), the SSD logic unit (400) outputs a self-control signal Φ to perform the next stage of SSD operation. n Prints.

[0070] In particular, when digital code 1 is output, the generated self-comparison voltage V IP1 Since it has a high level, the reset voltage V in subsequent SSD operation RST A contradiction arises in which it always has a higher value. Therefore, when digital code 1 is output, the SSD logic section (400) has a self-control signal Φ n Self-comparison voltage V through the control of IP1 Performs the reset operation of. Self-comparison voltage V IP1 The reset self-comparison voltage V newly generated by the reset of IP1 For ', no digital code output is produced through comparison operation, and this applies equally to the reset self-comparison voltages described below.

[0071] The reset operation V on the other end of the switch of the second switching unit that is the target of the SSD operation. IP from V PIX It is an operation to switch to. Through this, the reset voltage V on the other end of the first switch. RST is authorized.

[0072] FIG. 7 shows the self-comparison voltage V derived from FIG. 6 according to a preferred embodiment of the present invention. IP1This is an equivalent circuit and timing diagram illustrating the reset operation of.

[0073] Referring to FIG. 7, the self-comparison voltage V IP1 This V RST If higher, the pixel voltage V in the capacitor assigned to the corresponding bit PIX is connected. Therefore, V IP is reset and follows Formula 3 below. V being reset IP ul V IP1 If we assume this, the formula is as follows.

[0074] [Equation 3]

[0075]

[0076]

[0078] In other words, the self-comparison voltage V during the first SSD operation IP1 This reset voltage V RST If it is smaller, digital code 0 is generated, and the generated self-comparison voltage V IP1 It is used for the next stage of SSD operation. However, the self-comparison voltage V IP1 This reset voltage V RST If abnormal, a reset operation is performed, and the reset self-comparison voltage V IP ' is used for the next stage of SSD operation. The above reset is calculated by subtracting the difference between the reset voltage and the negative reference voltage from the existing value doubled by the SSD, which is V RST A level exceeding the negative reference voltage V REFL It corresponds to lowering the standard.

[0079] In the SSD operation in the second section, the capacitor that was switched in the previous stage maintains the state of the previous stage, and a negative reference voltage V is applied to the capacitor corresponding to the bit currently to be switched. REFL Connects. For example, 2 5 Cu maintains the previous SSD operating state, and 2 4 For Cu, the negative reference voltage V REFLConnect it. Also, for the remaining capacitors, apply the self-comparison voltage V exactly as in the previous state. IP It is an action that connects.

[0080] FIG. 8 is an equivalent circuit for explaining the SSD operation for the upper second bit of FIG. 4 following FIG. 7, according to a preferred embodiment of the present invention.

[0081] Referring to Fig. 8, an SSD operation is performed on the second-highest bit among the N bits to be converted in the second interval.

[0082] Figure (a) shows the self-comparison voltage V in the previous step. IP Illuminates the case where the reset operation of was not performed. In the previous step, 2 5 The negative reference voltage V on Cu REFL Since this is in a connected state, it remains as is, and 2 4 A new negative reference voltage V is applied to Cu REFL This is connected. Also, due to the virtual short circuit of the amplifier (140), 2 5 Cu and 2 4 The amount of charge stored in Cu is 0, and the amount of charge stored in the remaining capacitors follows the law of conservation of charge.

[0083] This follows Formula 4 below.

[0084] [Equation 4]

[0085]

[0086]

[0087] That is, the self-comparison voltage V from the previous step IP and negative reference voltage V REFL The difference value ΔV1 is amplified by a factor of 2.

[0088] If, in the previous step, the self-comparison voltage V IP1 A reset operation is performed on the reset self-comparison voltage V. IP1If ' is set, the SSD operation at the current stage is configured as shown in diagram (b). That is, 2 corresponding to the most significant bit 5 In Cu, V is the same as the previous state RST is connected, and the 2 corresponding to the corresponding bit 4 The negative reference voltage V on Cu REFL This is connected, and the remaining capacitors are connected to the self-comparison voltage V IP It is connected. Applying the law of conservation of electric charge, it is as shown in Equation 5 below.

[0089] [Formula 5]

[0090]

[0091]

[0093] In other words, the self-comparison voltage V formed through SSD operation IP2 and negative reference voltage V REFL The difference is that the voltage difference ΔV1' reset in the previous step has been doubled.

[0094] Self-comparison voltage V formed through (a) and (b) above IP2 Reset voltage V RST If it is smaller than, the comparator (300) outputs digital code 0, and reset voltage V RST If it is more than that, the comparison unit (300) outputs digital code 1.

[0095] If the output of the comparator (300) is digital code 1, a reset operation for the self-comparison voltage is performed.

[0096] Figures (c) and (d) are equivalent circuit diagrams illustrating the reset operation of the second-highest bit, Figure (c) is the equivalent circuit during the reset operation of the self-comparison voltage when digital code 1 is output in Figure (a), and Figure (d) is the equivalent circuit diagram during the reset operation of the self-comparison voltage when digital code 1 is output in Figure (b).

[0097] Referring to diagram (c), the 2 corresponding to the upper second bit 4 Cu is the reset voltage V RST It is connected to, and the remaining capacitors maintain the state of diagram (a). Applying the law of conservation of charge to the above configuration yields the following Equation 6.

[0098] [Equation 6]

[0099]

[0100]

[0102] That is, the self-comparison voltage V reset in the above Equation 4 IP2 and negative reference voltage V REFL The difference is the value obtained by subtracting Vpp from ΔV2. Through this, V IP2 ' is V RST Maintains a value less than or equal to 1.

[0103] Figure (d) shows the self-comparison voltage V in Figure (b) above. IP2 Reset voltage V RST This is an equivalent circuit diagram explaining the reset operation of the self-comparison voltage when it exceeds .

[0104] The equivalent circuit is the 2 corresponding to the state in Figure (b) above. 4 Reset voltage V on Cu capacitor RST It is an operation to apply. Applying the law of conservation of charge to the above connection configuration yields Equation 7 below.

[0105] [Equation 7]

[0106]

[0107]

[0109] That is, the reset self-comparison voltage V IP2 and negative reference voltage V REFL The difference value ΔV2' is the value obtained by subtracting Vpp from the difference value ΔV2 amplified by 2 times before reset.

[0110] The above-described operation corresponds to 2 of the least significant bit excluding the buffer capacitor. 0 The process proceeds up to Cu. Through the aforementioned process, the SSD operation for the upper N bits is completed.

[0111] The least significant bit among the N bits is 2 excluding the buffer capacitor 0 This is achieved by connecting Cu to a negative reference voltage and maintaining the other capacitors in their previous state. The self-comparison voltage V generated by this is IP is the determining voltage V IP * forms.

[0112] As shown in Fig. 4, a 6-bit digital code is formed, and the unit capacitor Cu is 2 5 +2 4 +...2 1 +2 0 +2 0 A dog is required, and this is 2 6 A number is required. If you want to obtain N bits through SSD operation, the unit capacitor Cu is 2 N Dogs are required.

[0113] Once the SSD operation for the upper bits is completed, digital conversion for the lower N bits is performed. The digital conversion operation for the lower N bits is implemented through the SAR operation known in the industry.

[0114] SAR operation can be implemented in various ways, and the present specification discloses the following circuits and operations as examples.

[0115] Figure 9 is a circuit diagram and timing diagram illustrating a continuous approximation voltage generation unit capable of performing SAR operation.

[0116] Referring to FIG. 9, circuit diagram (a) illustrates an example of a successive approximation voltage generation unit, assuming that the lower N bits to be digitally converted are 6 bits. Therefore, 6 types of capacitors 2 5 Cu, 2 4 Cu, ..., 21 Cu and 2 0 Cu is placed, and additionally, buffer capacitor 2 0 Cu is arranged in parallel.

[0117] Each capacitor is responsible for each of the 6-bit digital codes. The most significant bit is 2 5 It is Cu, and the least significant bit is 2 0 It is Cu.

[0118] First, the total charge of all capacitors is set to zero through a switching operation. To achieve this, switch Ks is connected to apply an equal approximate voltage V across the capacitors. IN Ensure that this is authorized. Also, in SAR operation mode, switch K SAR Set to open state so that pixel voltage V PIX It blocks input to the comparison section.

[0119] Next, turn off switch Ks, and capacitor 2 corresponding to the most significant bit 5 Reset voltage V for Cu RST Connect to, and the remaining capacitors to the negative reference voltage V REFL Connect to. Therefore, capacitor 2 5 The amount of charge stored in Cu is 2 5 Cu(V RST -V IN ) and the amount of charge stored in the remaining capacitors is 2 5 Cu(V REFL -V IN ) and, approximate voltage V IN is Vpp / 2+V REFL This becomes.

[0120] In addition, in SAR operation mode, the positive input terminal of the comparator receives the determination voltage V derived in SSD operation mode. IP * is applied. If, the determining voltage V IP * Ga V RST If it exceeds, the reset determination voltage V as previously explained IP *is used.

[0121] V generated through the operation of the comparison unit IN This V IP If it is smaller, the comparison unit outputs the digital code 1 of the most significant bit among the lower N bits.

[0122] In addition, the SAR logic unit that receives digital code 1 increases the approximate voltage VIN through the switching control signal SW, and the amount of increase is 1 / 2 2 It is Vpp. To do this, 2 5 Cu remains the same as the previous state V RST Maintain the connection to, and new capacitor 2 4 Reset voltage V for Cu RST Connect to, and the remaining capacitors are connected to the negative reference voltage V, identical to the previous state. REFL Connect to. Therefore, reset voltage V RST The amount of charge stored in the two capacitors connected to is (2 5 +2 4 )Cu(V RST -V IN ) and the amount of charge stored in the remaining capacitors is 2 4 Cu(V REFL -V IN It is. Since the total charge is preserved as 0, applying this gives the approximate voltage V IN 3 / 4 (V RST -V REFL )+V REFL =3 / 4Vpp+V REFL is. The generated approximate voltage V IN The determined voltage V in the comparator IP * It is compared with the generated approximate voltage V. IN If the digital code of the previous stage is 1, then the approximate voltage V of the previous state IN It becomes the value obtained by adding 1 / 4Vpp.

[0123] If, the generated V IN This V IP *If it is greater, the comparator outputs digital code 0. Upon receiving the digital code, the SAR logic unit uses the switching control signal SW to divide the existing approximate voltage VIN by half. 3 The value obtained by reducing Vpp is output as a new approximate voltage. That is, 2 of the switches 5 Cu and 2 3 Cu V RST Connect to, and the remaining capacitors to the negative reference voltage V REFL Connect to. The amount of charge stored in the two capacitors is (2 5 +2 3 )Cu(V RST -V IN ) and the amount of charge stored in the remaining capacitors is (2 4 +2 3 )Cu(V REFL -V IN ) is. Therefore, the approximate voltage V IN 5 / 8(V RST -V REFL )+V REFL It is set to.

[0124] The SAR operation is completed through the process described above. However, the continuous approximation voltage generation unit illustrated in FIG. 9 is an example of SAR mode operation, and various SAR operation modes or circuits may be applied in the present invention.

[0125] However, capacitors required for the implementation of the SAR operation mode need to be considered.

[0126] For example, in Fig. 9 above, the capacitors for the lower 6 bits are unit capacitors Cu 2 5 +2 4 +...+2 0 +2 0 A number of units are required, and 64 unit capacitors are needed. As mentioned above, 64 unit capacitors are also required for SSD operation.

[0127] Therefore, in the present invention, 2 for forming a 12-bit digital code 7Unit capacitors are required.

[0128] However, if only SAR operation is used for 12-bit digital conversion, up to 2 11 Cu capacitance is required, and the unit capacitor used is 2 12 A number of capacitors is required. In other words, a very large number of capacitors are needed, which can act as a design burden.

[0129] In the present invention described above, for a 2N-bit digital conversion operation, digital conversion is first performed on N bits through an SSD operation. Once the digital conversion through SSD is completed, a SAR operation is performed on the lower N bits. Through this, the operation speed for digital conversion is improved, and the number of required unit capacitors can be drastically reduced. Explanation of the symbols

[0130] 100 : Self-comparison voltage generator 200 : Continuous approximation voltage generator 300: Comparison section 400: SSD logic section 500 : SAR Logic Section

Claims

Claim 1 A hybrid ADC that forms a 2N-bit digital code, wherein the upper bits are formed through an SSD operation in which the difference between the signal voltage and the negative reference voltage is amplified by two times at a pixel voltage supplied from a CIS and composed of a signal voltage and a reset voltage, and the remaining lower bits are formed through a SAR operation in which the difference between the signal voltage and the negative reference voltage is amplified by two times, thereby forming a digital code, and the remaining lower bits are formed through a SAR operation in which a determination voltage finally derived by the SSD operation is compared with an approximation voltage approximating the determination voltage, wherein the hybrid ADC comprises: a self-comparison voltage generation unit that forms a new current self-comparison voltage by amplifying the difference between the previous self-comparison voltage formed in the previous step and the negative reference voltage by two times; a continuous approximation voltage generation unit that selects and supplies the reset voltage of the pixel voltage in the SSD operation; and a comparison unit that receives the reset voltage from the continuous approximation voltage generation unit and receives the current self-comparison voltage from the self-comparison voltage generation unit in the SSD operation, and forms a digital code through a comparison operation. A hybrid ADC circuit comprising an SSD logic unit that forms a self-control signal according to the digital code of the preceding step in the SSD operation and induces the generation of the current self-comparison voltage of the self-comparison voltage generation unit through the switching operation of the self-comparison voltage generation unit. Claim 2 A hybrid ADC circuit according to claim 1, wherein the self-comparison voltage generating unit comprises: a first capacitor unit in which a unit capacitor and capacitors increasing in a geometric sequence relative to the unit capacitor are connected in parallel; a first switching unit connected to the first capacitor unit and selectively connected to the pixel voltage by a set control signal; a second switching unit selectively connected to the first switching unit by the set control signal and connected to the pixel voltage, the negative reference voltage, or the current self-comparison voltage; and an amplifier unit that receives one end of the first capacitor unit and the negative reference voltage and generates the current self-comparison voltage, wherein when the pixel voltage is connected to the first switching unit, the second switching unit is not connected to the first switching unit. Claim 3 In paragraph 2, the self-comparison voltage generating unit gives the first capacitor part ΔV, which is the difference between the signal voltage and the negative reference voltage. SIG Initialization operation storing and the above ΔV SIG A hybrid ADC circuit characterized by performing the SSD operation of amplifying by a factor of 2 to form the self-comparison voltage, and setting the self-comparison voltage to the previous self-comparison voltage to form the current self-voltage. Claim 4 A hybrid ADC circuit according to claim 3, wherein in the initialization operation, the first switching unit is connected to the signal voltage of the pixel voltage, the amplifier has a negative feedback structure, and the self-comparison voltage is set to the negative reference voltage. Claim 5 In paragraph 3, the SSD operation is initiated after the initialization operation, the first capacitor unit is connected to the second switching unit through the first switching unit, the uppermost capacitor of the first capacitor unit is connected to the negative reference voltage, the remaining capacitors are connected to the first self-comparison voltage of the amplifier unit, and ΔV1, which is the difference between the first self-comparison voltage and the negative reference voltage, is the ΔV SIG A hybrid ADC circuit characterized by being twice that of Claim 6 A hybrid ADC circuit according to claim 5, characterized in that if the first self-comparison voltage is less than the reset voltage, the comparator outputs digital code 0, and if the first self-comparison voltage is greater than or equal to the reset voltage, the comparator outputs digital code 1. Claim 7 A hybrid ADC circuit according to claim 6, characterized in that when the digital code 1 is output, the self-comparison voltage generating unit subtracts Vpp, which is the difference between the reset voltage and the negative reference voltage, from ΔV1 to form a first reset self-comparison voltage. Claim 8 A hybrid ADC circuit according to claim 7, characterized in that the difference between the first reset self-comparison voltage and the negative reference voltage, ΔV1', has a value obtained by subtracting Vpp from the first self-comparison voltage. Claim 9 A hybrid ADC circuit according to claim 5, characterized in that if the first self-comparison voltage is greater than or equal to the reset voltage, the top capacitor is connected to the reset voltage and the remaining capacitors maintain a connected state. Claim 10 A hybrid ADC circuit according to claim 5, wherein if the first self-comparison voltage is less than the reset voltage, the self-comparison voltage generating unit forms a second self-comparison voltage, and ΔV2, which is the difference between the second self-comparison voltage and the negative reference voltage, is twice ΔV1.

Images