Trimming circuit and method for driving trimming circuit

Abstract

The present invention provides a highly reliable trimming circuit, a rewritable trimming circuit, a method for driving a highly reliable trimming circuit, and a method for driving a rewritable trimming circuit. A trimming circuit is configured with a memory node connected to the source or drain electrode of a transistor having a very small off-leakage current, and a transistor having its gate electrode connected to the memory node. Additionally, the trimming state of a device or circuit connected in parallel to the source and drain electrodes of the transistor having its gate electrode connected to the memory node is controlled using the transistor having a very small off-leakage current.

Description

Technology Field

[0001] The present invention relates to a trimming circuit. It also relates to a method for driving a trimming circuit. Background Technology

[0002] In the manufacturing process of integrated circuits (e.g., AD converters or DA converters) that require high precision voltage and current values, there is a need for a method to correct deviations in characteristics that cannot be suppressed even by adjusting manufacturing conditions.

[0003] In addition, in the manufacturing process of integrated circuits requiring high yield (e.g., large-capacity memory devices), a method for switching connections to the embedded storage circuit is required.

[0004] A circuit called a trimming circuit is used for this purpose. A trimming circuit is a circuit that selects whether to make an element or circuit connected in parallel to the trimming circuit available or unavailable (trimming state). Conventional trimming circuits use, for example, fuses or Zener zap diodes.

[0005] In addition, a transistor using an oxide semiconductor in the channel forming region is known (see Patent Document 1). Since the oxide semiconductor layer can be fabricated relatively easily using methods such as sputtering, a transistor using an oxide semiconductor in the channel forming region has the characteristic of being easy to fabricate. Prior art literature

[0006] Japanese Publication No. 2007-123861 The problem to be solved

[0007] However, there may be reliability issues with fuses or Zener Zap diodes. For example, with the laser cutting method used to cut fuses by firing them with a laser, residue may remain at the cut site, preventing the circuit from being properly cut.

[0008] In addition, conventional trimming circuits that use irreversible components such as fuses or Zener Zap diodes have the problem that they cannot be restored to their original state once cut, so trimming or rewriting cannot be done again.

[0009] One embodiment of the present invention has been made under this technical background. One embodiment of the present invention has as its objective to provide a highly reliable trimming circuit. Or, as its objective to provide a rewritable trimming circuit. Or, as its objective to provide a method for driving a highly reliable trimming circuit. Or, as its objective to provide a method for driving a rewritable trimming circuit. means of solving the problem

[0010] To achieve the above objective, one embodiment of the present invention focuses on a configuration that maintains a switch in a designed state for a long period without physically cutting the circuit. Furthermore, a configuration was devised comprising a memory node connected to the source or drain electrode of a transistor having a very small off-leakage current, and a transistor having its gate electrode connected to said memory node. Additionally, by using said transistor having a very small off-leakage current, a method was devised to control the trimming state of a device or circuit connected in parallel to the source and drain electrodes of the transistor having its gate electrode connected to said memory node, thereby solving the above problem.

[0011] That is, one embodiment of the present invention has a capacitive element in which one electrode is electrically connected to a memory node and the other electrode is electrically connected to a ground potential line, respectively; a first transistor in which the gate electrode is electrically connected to a recording terminal, and one of the source electrode or drain electrode is electrically connected to a memory node and the other is electrically connected to a power potential line, respectively; a second transistor in which the gate electrode is electrically connected to an erase terminal, and one of the source electrode or drain electrode is electrically connected to a memory node and the other is electrically connected to a ground potential line, respectively; and a third transistor in which the gate electrode is electrically connected to a memory node. Furthermore, the first transistor and the second transistor are trimming circuits in which a semiconductor material having a bandgap of 2.5 eV or more is provided in a channel forming region, and the source electrode and drain electrode of the third transistor are connected in parallel to a resistor element.

[0012] A trimming circuit, which is one embodiment of the present invention, comprises a first transistor and a second transistor, each having a semiconductor material having a bandgap of 2.5 eV or more provided in a channel forming region; a memory node connected to one of the source electrode or drain electrode of each transistor, the gate electrode of a third transistor, and one electrode of a capacitive element. The transistor having a semiconductor material having a bandgap of 2.5 eV or more provided in a channel forming region has a small off-leakage current, and the memory node with this configuration has excellent charge retention capability, and can stably maintain the operating state of the third transistor connected to the memory node. Therefore, the operating state of the third transistor can be maintained for a long period without changing the structure of the components (e.g., without destroying the device or wiring). By doing so, a highly reliable trimming circuit can be provided.

[0013] In addition, the trimming circuit, which is one embodiment of the present invention, can change the operating state of the third transistor without irreversibly changing the structure of its components. Therefore, the operating state of the third transistor can be changed multiple times. By doing so, a rewritable trimming circuit can be provided.

[0014] In addition, one embodiment of the present invention comprises a capacitive element in which one electrode is electrically connected to a memory node and the other electrode is electrically connected to a ground potential line, respectively; a first transistor in which the gate electrode is electrically connected to a recording terminal, and one of the source electrode or drain electrode is electrically connected to a memory node and the other is electrically connected to a power potential line, respectively; a second transistor in which the gate electrode is electrically connected to an erase terminal, and one of the source electrode or drain electrode is electrically connected to a memory node and the other is electrically connected to a ground potential line, respectively; and a third transistor in which the gate electrode is electrically connected to a memory node. Furthermore, the off-leakage current of the first transistor and the second transistor is 1×10 per 1 μm channel width. -17 It is a trimming circuit in which the source electrode and drain electrode of the third transistor are connected in parallel with a resistor element, and the amount is less than or equal to A.

[0015] A trimming circuit, which is one embodiment of the present invention, comprises a first transistor and a second transistor having very small off-leakage currents. Specifically, the transistor has an oxide semiconductor layer in a channel forming region, and the magnitude of the off-leakage current is 1 × 10⁻⁶ per 1 μm channel width. -17A is less than or equal to A. A memory node is provided, to which one of the source electrodes or drain electrodes of each transistor, the gate electrode of a third transistor, and one electrode of a capacitive element are connected. A memory node with this configuration has excellent charge retention capabilities and can stably maintain the operating state of the third transistor to which the gate electrode is connected to the memory node. Therefore, the operating state of the third transistor can be maintained for a long period of time without changing the structure of the components (e.g., without destroying the elements or wiring). By doing so, a highly reliable trimming circuit can be provided.

[0016] In addition, the trimming circuit, which is one embodiment of the present invention, can change the operating state of the third transistor without irreversibly changing the structure of its components. Therefore, the operating state of the third transistor can be changed multiple times. By doing so, a rewritable trimming circuit can be provided.

[0017] In addition, one embodiment of the present invention is the trimming circuit in which both the first transistor and the second transistor have an oxide semiconductor layer in the channel forming region.

[0018] A trimming circuit, which is one embodiment of the present invention, comprises a first transistor and a second transistor having very small off-leakage currents. Specifically, the transistor has an oxide semiconductor layer in a channel forming region and has a memory node connected to one of the source electrodes or drain electrodes of each transistor, the gate electrode of a third transistor, and one electrode of a capacitive element. Transistors using oxide semiconductor layers have very small off-leakage currents. In addition, the oxide semiconductor layer can be easily formed by methods such as sputtering. Therefore, a highly reliable trimming circuit can be easily provided. Furthermore, the trimming circuit can be formed by stacking it on another semiconductor device (e.g., a semiconductor device using a silicon single crystal). By doing so, a semiconductor device with high added value can be provided.

[0019] In addition, one embodiment of the present invention comprises a capacitive element in which one electrode is electrically connected to a memory node and the other electrode is electrically connected to a ground potential line, respectively; a first transistor in which the gate electrode is electrically connected to a recording terminal, and one of the source electrode or drain electrode is electrically connected to a memory node and the other is electrically connected to a power potential line, respectively; a second transistor in which the gate electrode is electrically connected to an erase terminal, and one of the source electrode or drain electrode is electrically connected to a memory node and the other is electrically connected to a ground potential line, respectively; and a third transistor in which the gate electrode is electrically connected to the memory node. In addition, the off-leakage current of the first transistor and the second transistor is 1×10 per 1 μm channel width. -17A is a method for driving a trimming circuit of a resistor element, wherein the source electrode and drain electrode of a third transistor are connected in parallel to the resistor element. The method comprises a first step of inputting a signal to turn on the first transistor to a recording terminal and a signal to turn off the second transistor to an erasure terminal, respectively, thereby setting the potential of the memory node to a potential where the third transistor turns on, and a second step of inputting a signal to turn off the first transistor to a recording terminal and a signal to turn off the second transistor to an erasure terminal, respectively, thereby driving a trimming circuit of a resistor element into a trimmed state.

[0020] A driving method for a trimming circuit, which is one embodiment of the present invention, comprises the steps of setting the potential of a memory node to a potential such that the third transistor is turned on, and turning off the first transistor and the second transistor, to which the source electrode or drain electrode is connected to the memory node. By doing so, the operating state of the third transistor can be reversibly changed without changing the structure of all elements constituting the trimming circuit. Therefore, a driving method for a trimming circuit with high reliability can be provided.

[0021] In addition, one embodiment of the present invention comprises a capacitive element in which one electrode is electrically connected to a memory node and the other electrode is electrically connected to a ground potential line, respectively; a first transistor in which the gate electrode is electrically connected to a recording terminal, and one of the source electrode or drain electrode is electrically connected to a memory node and the other is electrically connected to a power potential line, respectively; a second transistor in which the gate electrode is electrically connected to an erase terminal, and one of the source electrode or drain electrode is electrically connected to a memory node and the other is electrically connected to a ground potential line, respectively; and a third transistor in which the gate electrode is electrically connected to a memory node. In addition, the off-leakage current of the first transistor and the second transistor is 1×10 per 1 μm channel width. -17A is a method for driving a trimming circuit of a resistor element, wherein the source electrode and drain electrode of a third transistor are connected in parallel to the resistor element. The method comprises a first step of inputting a signal to turn off the first transistor to a recording terminal and a signal to turn on the second transistor to an erasure terminal, respectively, thereby setting the potential of the memory node to a potential at which the third transistor turns off, and a second step of inputting a signal to turn off the first transistor to a recording terminal and a signal to turn off the second transistor to an erasure terminal, respectively, thereby making the resistor element usable.

[0022] A driving method for a trimming circuit, which is one embodiment of the present invention, comprises the steps of setting the potential of a memory node to a potential at which the third transistor is turned off, and turning off the first transistor and the second transistor, to which the source electrode or drain electrode is connected to the memory node. By doing so, the operating state of the third transistor can be reversibly changed without changing the structure of all elements constituting the trimming circuit. Therefore, a driving method for a trimming circuit with high reliability can be provided.

[0023] In addition, one embodiment of the present invention is a method for driving a trimming circuit that changes the trimming state of a resistor element, comprising: a third step in which, following the second step described above, a signal that turns on the first transistor at the recording terminal and a signal that turns off the second transistor at the erasure terminal are each input to make the potential of the memory node a potential that turns on the third transistor, or a signal that turns off the first transistor at the recording terminal and a signal that turns on the second transistor at the erasure terminal are each input to make the potential of the memory node a potential that turns off the third transistor, thereby making the potential of the memory node a potential different from that of the second step; and a fourth step in which a signal that turns off the first transistor at the recording terminal and a signal that turns off the second transistor at the erasure terminal are each input to make the potential of the memory node a potential that turns off the third transistor.

[0024] A driving method for a trimming circuit, which is one embodiment of the present invention, comprises the steps of setting the potential of a memory node to a potential different from that before driving, and turning off a first transistor and a second transistor, to which a source electrode or a drain electrode is connected to the memory node. By doing so, the operating state of the third transistor can be reversibly changed without changing the structure of all elements constituting the trimming circuit. Therefore, a driving method for a rewritable trimming circuit can be provided. Effects of the invention

[0025] According to one embodiment of the present invention, a highly reliable trimming circuit can be provided. Alternatively, a rewritable trimming circuit can be provided. Alternatively, a method for driving a highly reliable trimming circuit can be provided. Alternatively, a method for driving a rewritable trimming circuit can be provided. Brief explanation of the drawing

[0026] FIG. 1 is a drawing for explaining the configuration of a trimming circuit according to an embodiment. FIGS. 2a to 2c are drawings for explaining the operation of a trimming circuit according to an embodiment. FIGS. 3a to 3c are drawings for explaining the configuration of a trimming circuit according to an embodiment. FIGS. 4a to 4d are drawings for explaining a method of manufacturing a trimming circuit according to an embodiment. FIGS. 5a to 5d are drawings for explaining a method of manufacturing a trimming circuit according to an embodiment. FIGS. 6a to 6e are drawings for explaining the structure of an oxide material according to an embodiment. FIGS. 7a to 7c are drawings for explaining the structure of an oxide material according to an embodiment. FIGS. 8a to 8c are drawings for explaining the structure of an oxide material according to an embodiment. FIGS. 9A and 9B are drawings for explaining the structure of an oxide material according to an embodiment. Specific details for implementing the invention

[0027] The embodiments are described in detail using the drawings. However, those skilled in the art will readily understand that the present invention is not limited to the descriptions provided below, and that various changes to its form and details can be made without departing from the spirit and scope of the invention. Accordingly, the present invention is not to be interpreted as being limited to the descriptions of the embodiments provided below. Furthermore, regarding the configuration of the invention described below, the same reference numerals are commonly used in different drawings for identical parts or parts having the same function, and their repeated description is omitted.

[0028] (Embodiment 1)

[0029] In this embodiment, the configuration of a trimming circuit having a memory node connected to the source electrode or drain electrode of a transistor having a very small off-leakage current, and a transistor having a gate electrode connected to the memory node, will be explained with reference to FIG. 1.

[0030] The configuration of a trimming circuit, which is an embodiment of the present invention, is illustrated in FIG. 1. The trimming circuit (100) exemplified in FIG. 1 has a capacitance element (140), a first transistor (110), a second transistor (120), and a third transistor (130). In addition, the first transistor (110) and the second transistor (120) are transistors in which a semiconductor material having a bandgap of 2.5 eV or more is provided in the channel forming region and the off-leakage current is very small. By making the off-leakage current very small, the charge recorded in the memory node (150) can be maintained for a long period of time. For example, an oxide semiconductor layer having a bandgap of 3.15 eV is provided in the channel forming region, and the magnitude of the off-leakage current is 1 × 10⁻⁶ per 1 μm channel width. -17 A transistor with an A or lower value can be used.

[0031] A transistor suitable for use in the first transistor (110) and the second transistor (120) is a transistor in which a semiconductor material having a band gap greater than 1.12 eV of silicon semiconductor is provided in the channel forming region. For example, a transistor in which a semiconductor material having a band gap of 2.5 eV or more, preferably 3.0 eV or more, is provided in the channel forming region may be used, specifically, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a carbide semiconductor, a diamond thin film exhibiting semiconductor characteristics, etc., is provided in the channel forming region. A transistor in which a semiconductor material having a band gap of 2.5 eV or more is provided in the channel forming region can have a smaller off-leakage current than a transistor in which a silicon semiconductor having a band gap of 1.12 eV is provided in the channel forming region.

[0032] In addition, various configurations of transistors may be used to reduce the off-leakage current of the first transistor and the second transistor. For example, a multi-gate type transistor including semiconductor layers having two or more channel-forming regions connected in series may be used. In addition, a transistor having a gap (also called an offset) formed between the source electrode or drain electrode and the channel-forming region may be used.

[0033] One electrode of the capacitance element (140) is electrically connected to the memory node (150) and the other electrode is electrically connected to the ground potential line.

[0034] A memory node (150) is connected to a first transistor (110), a second transistor (120), and a capacitance element (140) in which off-leakage current is reduced, and the semiconductor material having a bandgap of 2.5 eV or more is provided in the channel forming region. Forming the capacitance element (140) is desirable because it can suppress the occurrence of a phenomenon in which the potential of the memory node (150) becomes unstable due to surge current, etc., thereby improving reliability.

[0035] The first transistor (110) is electrically connected such that its gate electrode is connected to the recording terminal (115), one of its source electrode or drain electrode is connected to the memory node (150), and the other is connected to the power potential line. Additionally, a power potential Vdd higher than the ground potential is supplied to the power potential line.

[0036] The second transistor (120) is electrically connected such that its gate electrode is to the erase terminal (125), one of its source electrode or drain electrode is to the memory node (150), and the other is to the power potential line.

[0037] The third transistor (130) has its gate electrode electrically connected to the memory node (150), and its source electrode and drain electrode are connected in parallel to the resistor element (105).

[0038] A memory node (150) is connected to one electrode of a capacitive element (140), is electrically isolated from the power potential line by a first transistor (110) with very small off-leakage current, and is electrically isolated from the ground potential line by a second transistor (120) with very small off-leakage current. A memory node (150) configured in this way can stably maintain the recorded charge for a long period of time.

[0039] By a configuration in which the gate electrode of a third transistor (130) is connected to a memory node (150) capable of maintaining a recorded charge for a long period of time, the operating state of the third transistor (130) (specifically, either an on state or an off state) can be maintained for a long period of time through the gate electrode.

[0040] In addition, according to this configuration, the operating state of the third transistor (130) can be maintained for a long period of time without irreversibly changing the structure of all components, so reliability is particularly high. In addition, the operating state of the third transistor (130) can be changed several times by rewriting the potential of the memory node (150) without irreversibly changing the structure.

[0041] According to one embodiment of the present invention, a highly reliable trimming circuit can be provided. Alternatively, a rewritable trimming circuit can be provided.

[0042] In addition, this embodiment can be appropriately combined with other embodiments presented in this specification.

[0043] (Embodiment 2)

[0044] In this embodiment, a driving method for a trimming circuit comprising a memory node connected to the source electrode or drain electrode of a transistor having a very small off-leakage current, and a transistor having a gate electrode connected to said memory node, will be explained with reference to FIGS. 2a to 2c. Specifically, a driving method for the trimming circuit (100) exemplified in Embodiment 1 will be explained.

[0045] <Operation Method Example 1>

[0046] First, we will explain the method of making an element or circuit connected in parallel to the trimming circuit unusable (trimming state) using FIG. 2a and FIG. 2c.

[0047] A signal that turns on the first transistor (110) is input to the recording terminal (115), and a signal that turns off the second transistor (120) is input to the erasure terminal (125). As a result, the memory node (150) is connected to the power supply potential line through the first transistor (110), and charge is accumulated in the memory node (150) connected to the capacitance element (140). In addition, the third transistor, to which the gate electrode is connected to the memory node (150), turns on, and current flows through the third transistor through its source electrode and drain electrode. Furthermore, the steps up to this point are referred to as the first step of the driving method example 1 (see FIG. 2a).

[0048] Next, a signal to turn off the first transistor (110) is input to the recording terminal (115), and a signal to turn off the second transistor (120) is input to the erasure terminal (125). As a result, the memory node (150) is electrically isolated from both the power potential line and the ground potential line, and the charge recorded in the memory node (150) is maintained. Additionally, the steps up to this point are referred to as the second step of driving method example 1 (see FIG. 2c).

[0049] A driving method for a trimming circuit (100), which is one embodiment of the present invention, comprises a first step of setting the potential of a memory node (150) to a potential such that the third transistor (130) is turned on, and a second step of turning off the first transistor (110) and the second transistor (120), to which the source electrode or drain electrode is connected to the memory node (150). By doing so, more current can be flowed to the third transistor (130) without changing the structure of all elements constituting the trimming circuit (100). By doing so, a driving method for a trimming circuit with high reliability can be provided.

[0050] <Operation Method Example 2>

[0051] Next, a method for making an element or circuit connected in parallel to a trimming circuit available for use will be explained using FIGS. 2b and 2c.

[0052] A signal that turns the first transistor (110) off is input to the recording terminal (115), and a signal that turns the second transistor (120) on is input to the erasure terminal (125). As a result, the memory node (150) is connected to the ground potential line through the second transistor (120), and the memory node (150) becomes at the same potential as the ground potential. In addition, the third transistor, to which the gate electrode is connected to the memory node (150), turns off, and current flows through the resistor element (105) connected in parallel to its source electrode and drain electrode. In addition, the steps up to this point are referred to as the first step of driving method example 2 (see FIG. 2b).

[0053] Next, a signal to turn off the first transistor (110) is input to the recording terminal (115), and a signal to turn off the second transistor (120) is input to the erasure terminal (125). As a result, the memory node (150) is electrically isolated from both the power potential line and the ground potential line, and the charge recorded in the memory node (150) is maintained. Additionally, the steps up to this point are referred to as the second step of driving method example 2 (see FIG. 2c).

[0054] A driving method for a trimming circuit (100), which is one embodiment of the present invention, comprises a first step of setting the potential of a memory node (150) to a potential such that the third transistor (130) is turned off, and a second step of turning off the first transistor (110) and the second transistor (120), to which the source electrode or drain electrode is connected to the memory node (150). By doing so, more current can be flowed through a resistor element (105) connected in parallel to the source electrode and drain electrode of the third transistor (130) without changing the structure of all elements constituting the trimming circuit (100). By doing so, a driving method for a trimming circuit (100) with high reliability can be provided.

[0055] <Operation Method Example 3>

[0056] Next, a method for changing the settings of a trimming circuit (100) in which a trimming state is set using the method described in Driving Method Example 1 or Driving Method Example 2 will be explained.

[0057] A signal that turns on the first transistor (110) is input to the recording terminal (115) and a signal that turns off the second transistor (120) is input to the erasure terminal (125), respectively, to set the potential of the memory node (150) to a potential where the third transistor (130) turns on (see FIG. 2a), or a signal that turns off the first transistor (110) is input to the recording terminal (115) and a signal that turns on the second transistor (120) is input to the erasure terminal (125), respectively, to set the potential of the memory node (150) to a potential where the third transistor (130) turns off (see FIG. 2b), and then the potential of the memory node (150) with the trimming state set is re-recorded using the method described in Driving Method Example 1 or Driving Method Example 2. In addition, since the steps up to this point are carried out following the first and second steps of either driving method Example 1 or driving method Example 2, it will be called the third step of driving method Example 3.

[0058] Next, a signal to turn off the first transistor (110) is input to the recording terminal (115), and a signal to turn off the second transistor (120) is input to the erasure terminal (125). As a result, the memory node (150) is electrically isolated from both the power potential line and the ground potential line, and the charge recorded in the memory node (150) is maintained. Additionally, the steps up to this point are referred to as the fourth step of driving method example 3 (see FIG. 2c).

[0059] A driving method for a trimming circuit (100), which is one embodiment of the present invention, comprises a third step of setting the potential of a memory node (150) to a different potential than before driving the trimming circuit (100) using driving method 3, and a fourth step of turning off a first transistor (110) and a second transistor (120) to which a source electrode or a drain electrode is connected to the memory node (150). By doing so, the operating state of the third transistor (130) can be changed without changing the structure of all elements constituting the trimming circuit. By doing so, a driving method for a rewritable trimming circuit (100) can be provided.

[0060] <Variation Example>

[0061] Although driving method example 3 describes a method for changing the operating state of the third transistor (130), a driving method of recording data by re-inputting signals to the recording terminal (115) and the erase terminal (125) without changing the operating state of the third transistor (130) can also be considered a form of the present invention.

[0062] A trimming circuit, which is one embodiment of the present invention, is equipped with transistors having very small off-leakage current in the first transistor (110) and the second transistor (120), and can maintain the charge recorded in the memory node (150) for a long period of time. Here, reliability can be further improved by inputting signals to the recording terminal (115) and the erasure terminal (125) so that the memory node (150) maintains a state such as the state of maintaining the charge.

[0063] In addition, this embodiment can be appropriately combined with other embodiments presented in this specification.

[0064] (Embodiment 3)

[0065] In this embodiment, the configuration of a trimming circuit, which is one form of the present invention, will be described with reference to FIGS. 3a to 3c. Specifically, the configuration of a trimming circuit including a transistor using a semiconductor other than an oxide semiconductor and a transistor having an oxide semiconductor layer in a channel forming region will be described.

[0066] The configuration of a trimming circuit, which is one embodiment of the present invention, is illustrated in FIGS. 3a to 3c. FIG. 3a is a top view of the trimming circuit (300), FIG. 3b is a cross-sectional view of the section of the cutting line C1-C2 shown in FIG. 3a, and FIG. 3c is a cross-sectional view of the section of the cutting line D1-D2 shown in FIG. 3a.

[0067] The trimming circuit (300) illustrated in FIGS. 3a to 3c has a first transistor (310), a second transistor (320), and a capacitance element (340) formed by interposing an insulating layer (304) on a substrate (301) on which a third transistor (330) and a resistor element (305) are formed.

[0068] <Composition of the 3rd Transistor and Resistor Elements>

[0069] In this embodiment, a case in which a semiconductor material other than an oxide semiconductor is applied to the channel forming region of the third transistor (330) is described. Specifically, a configuration in which a silicon single-crystal substrate is used on the substrate (301) and the third transistor (330) is formed on its surface is described (see FIG. 3b).

[0070] In addition, as semiconductor materials other than oxide semiconductors, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide may be used. Furthermore, organic semiconductor materials may also be used.

[0071] In addition, any of the above semiconductor materials may include an amorphous state or a crystalline state, but using a single-crystal semiconductor substrate is preferable because it allows for the fabrication of transistors capable of high-speed operation.

[0072] In addition, SOI substrates, etc., may be applied. Generally speaking, an "SOI substrate" refers to a substrate having a configuration in which a silicon semiconductor film is formed on an insulating surface; however, the present specification and others also include substrates having a configuration in which a semiconductor film made of a material other than silicon is formed on an insulating surface. That is, the semiconductor film of the "SOI substrate" is not limited to a silicon semiconductor film. Furthermore, SOI substrates also include substrates having a configuration in which a semiconductor film is formed by interposing an insulating layer on an insulating substrate, such as a glass substrate.

[0073] A device isolation insulating layer (302) is formed to surround the third transistor (330). The gate electrode (331) of the third transistor (330) is electrically connected to the wiring (332) through an opening formed in the insulating layer (303).

[0074] A curved portion of a wiring (335) formed with the same conductive layer as the wiring (332) functions as a resistor element (305). The resistor element (305) is connected in parallel to the source electrode and drain electrode of the third transistor (330) (see FIG. 3a).

[0075] <Configuration of Capacitive Element, First Transistor, and Second Transistor>

[0076] A capacitive element (340) is provided by inserting an insulating layer between the wiring (341) and the wiring (352) and is formed on the insulating layer (304). Additionally, the wiring (352) is connected to the wiring (332) through an opening formed in the insulating layer (304) (see FIG. 3b).

[0077] The first transistor (310) has an oxide semiconductor layer (313) formed on an insulating layer (304) and a gate insulating layer (312) between the wiring (311) which functions as a gate electrode. Additionally, the wiring (311) has an insulating layer formed on its sidewall and is insulated from the wiring (351) and wiring (352) which function as a source electrode or drain electrode (see FIG. 3c).

[0078] The second transistor (320) has an oxide semiconductor layer (323) formed on an insulating layer (304) and a gate insulating layer (322) between the wiring (321) that functions as a gate electrode. Additionally, the wiring (321) has an insulating layer formed on its sidewall and is insulated from the wiring (352) and wiring (353) that function as a source electrode or drain electrode (see FIG. 3c).

[0079] The trimming circuit exemplified in this embodiment comprises a first transistor (310) and a second transistor (320) having very small off-leakage currents. Specifically, the transistors are provided with an oxide semiconductor layer in a channel forming region, and the magnitude of the off-leakage current is 1 × 10⁻⁶ per 1 μm channel width. -17 It is less than A. The off-leakage current is very small (e.g., 1 × 10⁻⁶ per 1 µm channel width). -17 By doing A or less, the charge recorded in the memory node can be maintained for a long period of time.

[0080] In addition, the trimming circuit exemplified in the present embodiment has a transistor having an oxide semiconductor layer, and the transistor having the oxide semiconductor layer is formed on a substrate on which a transistor using a semiconductor other than an oxide semiconductor is formed. By making such a configuration, for example, a transistor using a semiconductor other than an oxide semiconductor that operates at high speed and a transistor using an oxide semiconductor with reduced off-leakage current can be combined and utilized. Thus, a trimming circuit that utilizes the advantages of a semiconductor other than an oxide semiconductor and an oxide semiconductor with reduced off-leakage current, and a semiconductor device equipped with said trimming circuit can be provided.

[0081] In addition, the trimming circuit exemplified in this embodiment has a stacked configuration. Specifically, a transistor equipped with an oxide semiconductor layer and a resistor element are formed by overlapping. This allows the area occupied by the trimming circuit to be reduced. Furthermore, by applying the trimming circuit, the semiconductor device can be miniaturized.

[0082] In addition, this embodiment can be appropriately combined with other embodiments presented in this specification.

[0083] (Embodiment 4)

[0084] In this embodiment, the configuration of a transistor that can be used in a trimming circuit, which is one form of the present invention, is described. Specifically, the configuration of a transistor in which a semiconductor material having a bandgap of 2.5 eV or more is provided in a channel forming region is described. In addition, the method of manufacturing the transistor exemplified in this embodiment is to be described in Embodiment 5.

[0085] The configuration of the transistor exemplified in this embodiment will be explained using FIG. 4d. FIG. 4d shows a cross-section of the transistor.

[0086] The transistor (710) exemplified in this embodiment has an insulating layer (704) that forms an insulating layer on a substrate (701), an oxide semiconductor layer (713), a gate insulating layer (712), a gate electrode (711), an electrode (751) and an electrode (752) that function as a source electrode or a drain electrode, and an insulating layer (705) that protects the transistor.

[0087] <Composition of the insulating layer serving as the base>

[0088] The insulating layer (704) that serves as the lower layer has an insulating surface and serves as the lower layer of the oxide semiconductor layer (713) where the channel is formed.

[0089] The insulating layer (704) that serves as the base layer may be a single-layer structure containing one or more materials selected from, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, hafnium oxide, gallium oxide, etc., or may be a structure in which two or more layers are stacked.

[0090] <Oxide Semiconductor Layer>

[0091] The oxide semiconductor layer (713) in which the channel is formed overlaps with the gate electrode (711) through the gate insulating layer (712), and the electrode (751) and electrode (752) formed by sandwiching the gate electrode (711) are electrically connected. Additionally, the electrode (751) and electrode (752) function as source electrodes or drain electrodes.

[0092] The thickness of the oxide semiconductor layer (713) in which the channel is formed is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less.

[0093] In addition, the oxide semiconductor layer (713) does not need to be processed into an island shape.

[0094] The oxide semiconductor layer (713) can be in a single crystal, polycrystalline (also called polycrystalline), or amorphous state.

[0095] Preferably, the oxide semiconductor layer is a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) layer.

[0096] An example of a crystalline oxide semiconductor layer is an oxide semiconductor layer having c-axis aligned crystals (CAAC). In addition, details of the oxide semiconductor layer having c-axis aligned crystals are described in Example 7.

[0097] The oxide semiconductor layer (713) is preferably composed of an excess of oxygen compared to its stoichiometric ratio. By containing an excess of oxygen, the generation of carriers caused by oxygen deficiency in the metal oxide layer can be suppressed.

[0098] The oxide semiconductor layer (713) preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains In and Zn.

[0099] In addition, as a stabilizer for reducing deviations in the electrical characteristics of a transistor using the oxide semiconductor layer, it is preferable to have gallium (Ga) in addition to these. In addition, it is preferable to have tin (Sn) as a stabilizer. In addition, it is preferable to have hafnium (Hf) as a stabilizer. In addition, it is preferable to have aluminum (Al) as a stabilizer.

[0100] In addition, as another stabilizer, any one or more types of lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) may be used.

[0101] For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide, oxides of binary metals such as In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, oxides of ternary metals such as In-Ga-Zn oxide (also denoted as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, and oxides of quaternary metals such as In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, and In-Hf-Al-Zn oxide can be used.

[0102] Here, for example, an In-Ga-Zn-O system material refers to an oxide containing indium (In), gallium (Ga), and zinc (Zn), and the composition ratio is not particularly specific. In addition, metal elements other than In, Ga, and Zn may be contained. For example, SiO2 may be contained.

[0103] In addition, as an oxide semiconductor, InMO3(ZnO) m Materials denoted as (m > 0, and m is not an integer) may also be used. Additionally, M represents one or more metal elements selected from Ga, Fe, Mn, and Co. Additionally, as an oxide semiconductor, In2SnO5(ZnO) nYou may use materials denoted as (n > 0, and n is an integer).

[0104] However, the composition is not limited to the aforementioned composition, and it is preferable to use one having an appropriate composition depending on the required semiconductor properties (mobility, critical value, deviation, etc.). Furthermore, to obtain the required semiconductor properties, it is desirable to appropriately adjust the carrier concentration, impurity concentration, defect density, the ratio of the number of metal elements to oxygen atoms, the interatomic bond distance, density, etc.

[0105] Gate insulation layer

[0106] The gate insulating layer (712) can be made of silicon oxide, silicon nitride, silicon nitride, silicon nitride, gallium oxide, aluminum oxide, aluminum nitride, tantalum oxide, etc.

[0107] The gate insulating layer (712) may use a high-k dielectric material. Examples of high-k dielectric materials include hafnium oxide, yttrium oxide, lanthanum oxide, and hafnium silicate (HfSi₂). x O y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0)), nitrogen-doped hafnium aluminate (HfAl x O y N z Examples include (x>0, y>0, z>0).

[0108] The gate insulating layer (712) may be either a single-layer structure or a stacked structure. For example, it may be a stacked structure containing a layer containing a high-k material and a layer containing a material selected from silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, etc.

[0109] If the gate insulating layer (712) is made thinner or the above-described high-k material is used for the material, the transistor can be miniaturized while maintaining operating characteristics.

[0110] For example, when using silicon oxide, the size can be 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less.

[0111] On the other hand, when using high-k materials, transistors can be miniaturized without reducing their thickness to the point where gate leakage caused by tunnel effects occurs.

[0112] Additionally, an insulating material containing a group 13 element and oxygen can be applied to the gate insulating layer (712). Additionally, an insulating material containing a group 13 element means that the insulating material contains one or more group 13 elements.

[0113] For example, gallium oxide, aluminum oxide, aluminum gallium oxide, and gallium aluminum oxide can be cited as examples of insulating materials containing Group 13 elements and oxygen. Here, aluminum gallium oxide means that the aluminum content (atomic%) is greater than the gallium content (atomic%), and gallium aluminum oxide means that the gallium content (atomic%) is greater than or equal to the aluminum content (atomic%).

[0114] Many oxide semiconductor materials contain Group 13 elements, and insulating materials containing Group 13 elements and oxide semiconductor materials have good compatibility. Therefore, by using an insulating material containing Group 13 elements and oxygen in the insulating layer in contact with the oxide semiconductor layer, the interface between the oxide semiconductor layer and the insulating layer can be maintained in good condition.

[0115] For example, when forming a gate insulating layer in contact with a gallium-containing oxide semiconductor layer, using a gallium-containing material in the gate insulating layer allows the interface characteristics between the oxide semiconductor layer and the gate insulating layer to be maintained well.

[0116] In addition, by forming an oxide semiconductor layer and an insulating layer containing gallium oxide in contact, hydrogen pile-up at the interface between the oxide semiconductor layer and the insulating layer can be reduced.

[0117] For example, it is also effective to form an insulating layer using a material containing aluminum oxide. Furthermore, since aluminum oxide has the characteristic of being impermeable to water, using the said material is also desirable to prevent water from penetrating the oxide semiconductor layer.

[0118] In this way, the same effect can be obtained when an element belonging to the same group as the constituent elements of the oxide semiconductor is used in the insulating layer.

[0119] Gate Electrode

[0120] The gate electrode (711) overlaps with the oxide semiconductor layer (713) via the gate insulating layer (712) and functions as the gate electrode of the transistor (710).

[0121] The gate electrode (711) may be a single-layer structure containing a conductive material, or a stacked structure of two or more layers.

[0122] The conductive material may be a material capable of withstanding a heat treatment process, and for example, one metal selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc., or an alloy containing one metal selected from these may be used.

[0123] In addition, a semiconductor layer represented by a polycrystalline silicon layer doped with impurities such as phosphorus, or a silicide layer such as nickel silicide may be used.

[0124] Insulating layer and sidewall on the gate electrode

[0125] The insulating layer (714a) on the gate electrode overlaps with the gate electrode (711) and has insulating properties.

[0126] The side wall (714b) is in contact with the side of the stack of the gate insulating layer (712), the gate electrode (711), and the insulating layer (714a) on the gate electrode, and has an insulating layer.

[0127] Source electrode and drain electrode

[0128] Both electrodes (751) and (752) are electrically connected to the oxide semiconductor layer (713) and function as the source electrode and drain electrode of the transistor.

[0129] The electrode functioning as a source electrode or drain electrode may have a single-layer structure containing a conductive material, or a stacked structure of two or more layers.

[0130] The conductive material may be a material capable of withstanding a heat treatment process, and for example, one metal selected from aluminum, chromium, copper, titanium, tantalum, molybdenum, and tungsten, or an alloy containing one metal selected from these may be used. In addition, one metal selected from manganese, magnesium, zirconium, beryllium, neodymium, and scandium, or an alloy containing one metal selected from these may also be used.

[0131] In addition, metal nitrides can be used as conductive materials. Specifically, titanium nitride, molybdenum nitride, and tungsten nitride can be cited as examples.

[0132] In addition, conductive metal oxides can be used as conductive materials. Specifically, indium oxide, tin oxide, indium-tin oxide (also known as ITO), indium-zinc oxide, zinc oxide, zinc oxide with added gallium or aluminum, or metal oxide materials containing silicon oxide can be used.

[0133] In addition, graphene and the like can be used as conductive materials.

[0134] For example, a single-layer structure made of titanium or titanium nitride, a single-layer structure of aluminum containing silicon, a two-layer structure in which a titanium layer is stacked on top of an aluminum layer, a two-layer structure in which a titanium layer is stacked on top of a titanium nitride layer, and a three-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked can be cited.

[0135] In addition, the channel length (L) of the transistor is determined by the gap between the end of the source electrode in contact with the oxide semiconductor layer and the end of the drain electrode in contact with the oxide semiconductor layer.

[0136] Insulating layer protecting the transistor

[0137] The insulating layer (705) that protects the transistor is a layer that protects the transistor by preventing impurities such as moisture from entering from the outside.

[0138] The thickness of the insulating layer (705) is at least 1 nm.

[0139] The insulating layer (705) may be a single-layer structure including an insulator having barrier properties, or a structure in which two or more layers are stacked.

[0140] In particular, a composition containing aluminum oxide is preferred, and a laminated structure containing an aluminum oxide layer and other inorganic insulating materials may also be used. This is because aluminum oxide is difficult to permeate moisture, oxygen, and other impurities.

[0141] Additionally, the insulating layer (705) may be a laminate of an oxide insulating layer having an oxygen excess region and an aluminum oxide layer, and may be configured to form an oxide insulating layer having an oxygen excess region on the side of the oxide semiconductor layer.

[0142] An oxide insulating layer having an oxygen-excess region can be, for example, a silicon oxide film, a silicon nitride film, etc.

[0143] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments.

[0144] (Embodiment 5)

[0145] In this embodiment, a method for fabricating a transistor (710) having a semiconductor material having a band gap of 2.5 eV or more as described in Embodiment 4 is explained using FIGS. 4a to 4d.

[0146] <Formation of an insulating layer that becomes the lower layer>

[0147] First, an insulating layer (704) that serves as the lower layer of the oxide semiconductor layer where the channel is formed is formed. The insulating layer (704) that serves as the lower layer is formed on a substrate (701) using a plasma CVD method or a sputtering method.

[0148] The substrate (701) should have sufficient heat resistance to withstand processing in the process after the process of forming the insulating layer that serves as the base, and there is no limitation on its size.

[0149] Other semiconductor elements may be formed on the substrate (701) in advance.

[0150] As a substrate (701), for example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc., may be used. In addition, a single-crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc., may also be applied.

[0151] A flexible substrate may be used as the substrate (701). A transistor may be fabricated directly on the flexible substrate, or a transistor may be fabricated on another fabrication substrate, peeled off, and transferred to the flexible substrate. Additionally, when peeling off from the fabrication substrate and transferring to the flexible substrate, it is preferable to form a peeling layer between the fabrication substrate and the transistor including the oxide semiconductor layer.

[0152] <Formation of Oxide Semiconductor Layer>

[0153] Next, an oxide semiconductor layer (713) in which a channel is formed is formed on the insulating layer (704) that serves as the substrate.

[0154] The oxide semiconductor layer can be formed by sputtering, molecular beam epitaxy, atomic layer deposition, or pulsed laser deposition.

[0155] For example, when using an In-Ga-Zn-O based material as an oxide semiconductor, it can be fabricated using a target. Various materials and composition ratios of the target can be used, for example, an oxide target containing In2O3, Ga2O3, and ZnO in a ratio of 1:1:1 [mol ratio] (=In2O3:Ga2O3:ZnO). In addition, for example, an oxide target containing In2O3, Ga2O3, and ZnO in a ratio of 1:1:2 [mol ratio] (=In2O3:Ga2O3:ZnO) can also be used.

[0156] In addition, when using an In-Zn-O based material as an oxide semiconductor, the atomic number ratio of the metal elements of the target used is set to In:Zn = 50:1 to 1:2 (converted to a molar ratio, In2O3:ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (converted to a molar ratio, In2O3:ZnO = 10:1 to 1:2), and more preferably In:Zn = 15:1 to 1.5:1 (converted to a molar ratio, In2O3:ZnO = 15:2 to 3:4). For example, the target used for forming the In-Zn-O based oxide semiconductor is set to Z > 1.5X + Y when the atomic number ratio is In:Zn:O = X:Y:Z.

[0157] In addition, for example, when using an In-Sn-Zn-O-based material as an oxide semiconductor, it can be fabricated using a target. The composition ratio of the target can be set in various ways, for example, an oxide target containing In, Sn, and Zn in an atomic ratio of 1:2:2 (=In:Sn:Zn) can be used. In addition, for example, an oxide target containing In, Sn, and Zn in an atomic ratio of 2:1:3 (=In:Sn:Zn) can be used. In addition, for example, an oxide target containing In, Sn, and Zn in an atomic ratio of 1:1:1 (=In:Sn:Zn) can be used. In addition, for example, an oxide target containing In, Sn, and Zn in an atomic ratio of 20:45:35 (=In:Sn:Zn) can be used.

[0158] In addition, the relative density of the target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a target with a high relative density, the formed oxide semiconductor layer can be made into a dense film.

[0159] In addition, the oxide semiconductor layer can be substantially made into Type I by reducing the carrier density. Details of this method are explained in Example 6.

[0160] Next, a resist mask is formed by a photolithography process, and an oxide semiconductor layer is selectively etched using the resist mask to form an island shape (see FIG. 4a).

[0161] In addition, by etching while retracting the resist mask, the oxide semiconductor layer can be formed into a tapered shape. By forming the island-shaped oxide semiconductor layer into a tapered shape, the discontinuity of the layer formed after this process can be prevented, thereby improving coverage.

[0162] <Gate insulating layer, gate electrode, and formation of insulating layer on gate electrode>

[0163] Next, a stack of a gate insulating layer (712), a gate electrode (711), and an insulating layer (714a) on the gate electrode is formed on an oxide semiconductor layer (713).

[0164] The insulating layer serving as the gate insulating layer and the insulating layer serving as the insulating layer on the gate electrode are formed using methods such as plasma CVD or sputtering.

[0165] The conductive layer serving as the gate electrode is formed using methods such as sputtering.

[0166] Next, a resist mask is formed by a photolithography process, and by using the resist mask to etch an insulating layer that becomes a gate insulating layer, a conductive layer that becomes a gate electrode, and an insulating layer that becomes an insulating layer on the gate electrode, a laminate including a gate insulating layer (712), a gate electrode (711), and an insulating layer (714a) on the gate electrode is formed.

[0167] <Formation of Sidewalls>

[0168] Next, a sidewall (714b) is formed to contact the side of the stack of the gate insulating layer (712), the gate electrode (711), and the insulating layer (714a) on the gate electrode.

[0169] The insulating layer serving as the sidewall can be formed using methods such as plasma CVD or sputtering.

[0170] Next, anisotropic etching is performed to form sidewalls by leaving an insulating layer in contact with the side of the laminate (see FIG. 4b).

[0171] <Formation of an electrode functioning as a source electrode or drain electrode>

[0172] Next, electrodes (751) and (752) that function as source electrodes or drain electrodes are formed.

[0173] A layer containing a conductive material that serves as a source electrode or drain electrode is formed using a sputtering method or the like.

[0174] Next, a resist mask is formed by a photolithography process, and electrodes (751) and (752) are formed by selectively etching a layer containing a conductive material using the resist mask (see FIG. 4c). Additionally, wiring, etc. (not shown) made of a layer containing the same conductive material is also formed by the same process.

[0175] In addition, when forming a transistor with a channel length (L) of 10 nm or more and 1000 nm (1 µm) or less, particularly less than 25 nm, it is desirable to form a mask using short extreme ultraviolet rays with a wavelength of several nm to tens of nm. This is because using extreme ultraviolet rays results in high resolution and a large depth of focus.

[0176] In addition, it is preferable to form the electrode functioning as a source electrode or drain electrode in a tapered shape. If the electrode functioning as a source electrode or drain electrode is formed in a tapered shape, the coverage can be improved by preventing the discontinuity of the layer (e.g., gate insulating layer) formed after this process. In addition, it is preferable to set the taper angle to, for example, 30° or more and 60° or less.

[0177] In addition, when the layer containing the conductive material is formed as a single layer structure of a titanium layer or a titanium nitride layer, it is easy to process into a source electrode and a drain electrode having a tapered shape.

[0178] Formation of an insulating layer protecting the transistor

[0179] Next, an insulating layer (705) is formed to protect the transistor.

[0180] The insulating layer protecting the transistor can be formed using methods such as plasma CVD or sputtering.

[0181] By the above-described process, a transistor (710) using an oxide semiconductor material in the region where the channel is formed can be fabricated.

[0182] In addition, the resist mask used in the present embodiment is not limited to being formed by a photolithography process. It can be formed by appropriately utilizing methods other than photolithography, such as inkjet printing or printing. If the resist mask is formed without using a photomask, the manufacturing cost of the semiconductor device can be reduced.

[0183] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments.

[0184] (Embodiment 6)

[0185] In this embodiment, a trimming circuit that can be used as one form of the present invention has a very small off-leakage current (e.g., 1 × 10⁻⁶ per 1 μm channel width). -17 A) A method for forming an oxide semiconductor layer applicable to a transistor is described. Specifically, a method for fabricating an oxide semiconductor layer that is substantially Type I with reduced carrier density is described using FIGS. 5a to 5d.

[0186] <Composition of the insulating layer serving as the substrate and method of manufacturing the same>

[0187] It is preferable that the region of the insulating layer (504) that is the lower part of the oxide semiconductor layer where the channel is formed, which is in contact with the oxide semiconductor layer, be configured to include an insulating layer from which oxygen is removed by heat treatment. This is because if the insulating layer (504) has an oxygen-excess region, the phenomenon of oxygen moving from the oxide semiconductor layer to the insulating layer (504) can be prevented, and oxygen can be supplied from the insulating layer (504) to the oxide semiconductor layer by performing the heat treatment described later.

[0188] In the case where the insulating layer serving as the substrate has a stacked structure, it is more preferable to have an oxide insulating layer having an oxygen-excess region on the side of the oxide semiconductor layer.

[0189] For example, the composition of the insulating layer that serves as the base is preferably a structure in which a silicon oxide layer having an oxygen-excess region from the oxide semiconductor layer side and an aluminum oxide layer are laminated.

[0190] In addition, regarding the statement in this specification, etc. that 'oxygen is released by heat treatment,' in TDS (Thermal Desorption Spectroscopy) analysis, the amount of oxygen released (or emitted) converted into oxygen atoms is 1.0 × 10⁻⁶ 18 cm -3 Ideally, 3.0×10 20 cm -3 It means that it is above. In addition, 'oxygen is not released by heat treatment' means that the amount of oxygen released (or emitted), converted into oxygen atoms in TDS analysis, is 1.0 × 10⁻⁶ 18 cm -3 It means less than

[0191] Methods for forming an insulating layer from which oxygen is removed by heat treatment include forming a film under an oxygen atmosphere, or injecting oxygen (containing at least any one of oxygen radicals, oxygen atoms, or oxygen ions) after forming the film.

[0192] As oxygen injection methods, ion implantation, ion doping, plasma infiltration ion implantation, plasma treatment, etc., can be used.

[0193] <Method for Forming an Oxide Semiconductor Layer with Reduced Impurity Concentration 1: Film Formation Method>

[0194] An oxide semiconductor layer (413a) is formed on an insulating layer (504) that serves as the substrate (see FIG. 5a). Since the oxide semiconductor layer (413a) becomes an oxide semiconductor layer where a channel is subsequently formed, it is formed in such a way that impurities containing hydrogen atoms are excluded as much as possible. This is because impurities containing hydrogen atoms are prone to forming donor levels in the oxide semiconductor layer.

[0195] As a method for fabricating an oxide semiconductor layer with reduced impurities containing hydrogen atoms, it is preferable to form it using a sputtering method. In particular, it is preferable to form an oxide semiconductor layer continuously on an insulating layer that is not exposed to the atmosphere.

[0196] For example, hydrogen-containing impurities attached to the surface of a substrate may be removed by heat treatment or plasma treatment, and then an insulating layer that serves as a substrate may be formed without being exposed to the atmosphere, and subsequently an oxide semiconductor layer may be formed without being exposed to the atmosphere. By doing so, hydrogen-containing impurities attached to the surface of the insulating layer that serves as a substrate can be reduced, and the phenomenon of atmospheric components adhering to the interface between the substrate and the insulating layer that serves as a substrate, and the interface between the insulating layer that serves as a substrate and the oxide semiconductor layer, can be suppressed.

[0197] In addition, it is desirable to perform reverse sputtering, which involves introducing argon gas into a processing chamber to generate plasma, before forming an oxide semiconductor layer using the sputtering method, in order to remove powdery materials (also called particles or dust) attached to the surface of the insulating layer serving as the substrate.

[0198] Reverse sputtering is a method of modifying a surface by generating plasma near a substrate by applying voltage to the substrate side using an RF power source under an argon atmosphere without applying voltage to the target side. In addition, nitrogen, helium, oxygen, etc., may be used instead of an argon atmosphere.

[0199] In addition, a method of forming an oxide semiconductor layer using a processing chamber with a low leakage rate is preferred. Specifically, the leakage rate of the processing chamber of the sputtering device is 1×10 -10 Pa·m 3 By keeping it below 1 second, the incorporation of impurities such as alkali metals and hydrides into the oxide semiconductor layer during film formation can be reduced.

[0200] In addition, a method of forming an oxide semiconductor layer in the processing chamber of a sputtering device evacuated using an adsorption type vacuum pump (e.g., a cryopump) is preferred. This can reduce the backflow of impurities such as alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, or hydrides from the exhaust system.

[0201] In addition, a method of forming an oxide semiconductor layer by supplying a high-purity atmosphere gas into the processing chamber of a sputtering device is preferred. Specifically, a high-purity noble gas from which impurities such as water, compounds containing hydroxyl groups, or hydrides have been removed (typically argon), oxygen, or a mixture of noble gas and oxygen is appropriately used.

[0202] For example, the purity of argon is set to 9N (99.9999999%) or higher (H2O is 0.1 ppb, H2 is 0.5 ppb) and the dew point is set to -121°C. In addition, the purity of oxygen is set to 8N (99.999999%) or higher (H2O is 1 ppb, H2 is 1 ppb) and the dew point is set to -112°C.

[0203] In addition, when using a mixture of noble gas and oxygen, it is desirable to increase the oxygen flow rate ratio.

[0204] An Example of Conditions for Forming an Oxide Semiconductor Layer

[0205] As an example of the conditions for forming an oxide semiconductor layer, conditions are applied such that the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the DC power supply is 0.5 kW, and the atmosphere is oxygen (oxygen flow rate 100%). In addition, using a pulsed DC power supply is desirable because it can reduce dust generated when forming the film and ensure a uniform film thickness distribution.

[0206] <Method for Forming an Oxide Semiconductor Layer with Reduced Impurity Concentration 2: First Heat Treatment>

[0207] An oxide semiconductor layer (413b) is formed in which impurities containing hydrogen atoms are excluded as much as possible (see FIG. 5b).

[0208] As a method for fabricating an oxide semiconductor layer with reduced impurities containing hydrogen atoms, it is preferable to perform a first heat treatment on the oxide semiconductor layer to reduce impurities such as moisture or hydrogen within the oxide semiconductor layer (also called dehydration or dehydrogenation).

[0209] When performing the first heat treatment, it is preferable to use an insulating layer in contact with the oxide semiconductor layer from which oxygen is released during the heat treatment. This is because, when the first heat treatment is performed, oxygen is released from the oxide semiconductor layer along with impurities containing hydrogen atoms. There is a concern that some of the oxygen vacancies generated in the oxide semiconductor layer from which oxygen has been released may become donors, causing carriers to be generated in the oxide semiconductor layer and affecting the characteristics of the transistor.

[0210] The temperature of the first heat treatment is, for example, 150°C or higher and below the deformation point of the substrate, preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower.

[0211] The first heat treatment time is 3 minutes to 24 hours. Heat treatment exceeding 24 hours is undesirable as it leads to a decrease in productivity.

[0212] The first heat treatment is performed under an oxidizing atmosphere or an inert atmosphere. Here, an oxidizing atmosphere refers to an atmosphere containing 10 ppm or more of an oxidizing gas, such as oxygen, ozone, or nitrous oxide. In addition, an inert atmosphere refers to an atmosphere in which the above-mentioned oxidizing gas is less than 10 ppm and the remainder is filled with nitrogen or a noble gas.

[0213] For example, it is to be under a reduced pressure atmosphere, under an inert gas atmosphere such as nitrogen or noble gas, under an oxygen gas atmosphere, or under an ultra-dry air atmosphere (air in which the moisture content measured using a CRDS (cavity ring down laser spectroscopy) type dew point meter is 20 ppm (converted to -55°C in dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less).

[0214] In addition, it is desirable that water, hydrogen, etc., are not included in nitrogen, or noble gases such as helium, neon, or argon. Alternatively, it is desirable to have a purity of nitrogen, or noble gases such as helium, neon, or argon introduced into a heat treatment device of 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably 0.1 ppm or less).

[0215] The heating device used for the first heat treatment is not particularly limited. The heating device may be equipped with a device that heats the workpiece by heat conduction or heat radiation generated from a heating element such as a resistance heating element.

[0216] For example, RTA (Rapid Thermal Annealing) devices such as electric furnaces, LRTA (Lamp Rapid Thermal Annealing) devices, and GRTA (Gas Rapid Thermal Annealing) devices can be used. An LRTA device is a device that heats a workpiece by radiation of light (electromagnetic waves) generated from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0217] By performing the first heat treatment described above, hydrogen (water, a compound containing hydroxyl groups) can be released from the oxide semiconductor layer. In addition, impurities are reduced by the first heat treatment, so that an oxide semiconductor layer that is Type I (intrinsic) or substantially Type I can be formed.

[0218] By the first heat treatment, hydrogen, an unstable carrier source, can be removed from the oxide semiconductor layer, thereby suppressing the phenomenon where the threshold voltage of the transistor fluctuates in the negative direction. In addition, the reliability of the transistor can be improved.

[0219] <Variation Example>

[0220] After the first heat treatment, oxygen (including at least any of oxygen radicals, oxygen atoms, or oxygen ions) may be injected into the oxide semiconductor layer.

[0221] As oxygen injection methods, ion implantation, ion doping, plasma infiltration ion implantation, plasma treatment, etc., can be used.

[0222] <Composition of Gate Insulation Layer and Method of Fabrication>

[0223] It is preferable that the region of the gate insulating layer (512) covering the oxide semiconductor layer (513) where the channel is formed, which is in contact with at least the oxide semiconductor layer, be configured to include an insulating layer from which oxygen is removed by heat treatment. This is because if the gate insulating layer (512) has an oxygen excess region, the phenomenon of oxygen moving from the oxide semiconductor layer (513) to the gate insulating layer (512) can be prevented, and oxygen can be supplied from the gate insulating layer (512) to the oxide semiconductor layer (513) by performing the second heat treatment described later.

[0224] In the case where the insulating layer covering the oxide semiconductor layer where the channel is formed has a stacked structure, it is more preferable to have an oxide insulating layer having an oxygen-excess region on the side of the oxide semiconductor layer.

[0225] For example, the insulating layer covering the oxide semiconductor layer where the channel is formed preferably has a structure in which a silicon oxide layer having an oxygen-excess region on the side of the oxide semiconductor layer and an aluminum oxide layer are stacked.

[0226] This is because the aluminum oxide layer has a high blocking effect, in other words, that it does not allow both impurities such as hydrogen and moisture and oxygen to pass through, and if a second heat treatment is performed after forming the aluminum oxide layer, it is possible to prevent oxygen from being released from the oxide semiconductor layer.

[0227] <Gate insulating layer, gate electrode, and formation of insulating layer on gate electrode>

[0228] Next, a stack of a gate insulating layer (512), a gate electrode (511), and an insulating layer (514a) on the gate electrode is formed on an oxide semiconductor layer (513).

[0229] The insulating layer serving as the gate insulating layer and the insulating layer serving as the insulating layer on the gate electrode are formed using methods such as plasma CVD or sputtering.

[0230] The conductive layer serving as the gate electrode is formed using methods such as sputtering.

[0231] Next, a resist mask is formed by a photolithography process, and by using the resist mask to etch an insulating layer that becomes a gate insulating layer, a conductive layer that becomes a gate electrode, and an insulating layer that becomes an insulating layer on the gate electrode, a laminate including a gate insulating layer (512), a gate electrode (511), and an insulating layer (514a) on the gate electrode is formed.

[0232] <Formation of Sidewalls>

[0233] Next, an insulating layer (514b) is formed to contact the side wall of a laminate including a gate insulating layer (512), a gate electrode (511), and an insulating layer (514a) on the gate electrode.

[0234] The insulating layer serving as the sidewall can be formed using methods such as plasma CVD or sputtering.

[0235] Next, anisotropic etching is performed to form a sidewall by leaving an insulating layer in contact with the side of the laminate.

[0236] <Method for Fabricating Oxygen-Supplyed Oxide Semiconductor Layer 1: Second Heat Treatment>

[0237] The oxide semiconductor layer (513) in which the channel is formed is preferably an oxide semiconductor layer supplied with oxygen. In particular, an oxide semiconductor layer in which oxygen vacancies are preserved is preferred. This is because there is a concern that some of the oxygen vacancies may become donors, causing carriers to be generated in the oxide semiconductor layer and affecting the characteristics of the transistor.

[0238] As a method for fabricating an oxide semiconductor layer supplied with oxygen, a second heat treatment can be performed while the insulating layer from which oxygen is released by heat treatment and the oxide semiconductor layer in which a channel is formed are in contact. Specifically, it is preferable to form an insulating layer covering the region where the insulating layer and / or the region where a channel is formed using the insulating layer from which oxygen is released by heat treatment, and to supply oxygen to the oxide semiconductor layer by performing a second heat treatment (see FIG. 5c).

[0239] In addition, the second heat treatment is effective regardless of which process is performed, provided that the insulating layer, including the insulating layer from which oxygen is removed by the heat treatment, is formed in contact with the region where the channel is formed within the oxide semiconductor layer.

[0240] A method is particularly preferred in which a silicon oxide layer having an oxygen excess region from the side of the oxide semiconductor layer and an aluminum oxide layer having a high blocking effect (blocking effect) are stacked in a structure, and a second heat treatment is performed with the aluminum oxide layer formed.

[0241] The second heat treatment may be performed under an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or noble gas (argon, helium, etc.), but it is preferable that the atmosphere of nitrogen, oxygen, ultra-dry air, or noble gas does not contain water, hydrogen, etc. In addition, it is preferable to make the purity of the nitrogen, oxygen, or noble gas introduced into the heat treatment device 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably 0.1 ppm or less).

[0242] ≪Method for Measuring Oxygen Loss Converted to Oxygen Atoms≫

[0243] The method for quantifying the amount of oxygen released by converting it into oxygen atoms in TDS analysis will be explained below.

[0244] When measured by TDS analysis, the amount of gas escape is proportional to the integral of the spectrum. Therefore, the amount of gas escape can be calculated by the ratio of the integral of the insulating layer's spectrum to the reference value of the standard sample. The reference value of the standard sample is the ratio of the atomic density to the integral of the spectrum of a sample containing a specific atom.

[0245] For example, from the TDS analysis results of a standard sample silicon wafer containing hydrogen of a predetermined density and the TDS analysis results of an insulating layer, the amount of oxygen molecules released from the insulating layer (N O2 ) can be calculated using Equation 1. Here, it is assumed that all spectra detected with a mass number of 32 obtained by TDS analysis originate from oxygen molecules. Although CH3OH has a mass number of 32, it is not considered here as it is unlikely to exist. Additionally, oxygen molecules containing oxygen atoms with a mass number of 17 or 18, which are isotopes of the oxygen atom, are not considered because their proportion in nature is very small.

[0246] N O2 = N H2 / S H2 ×S O2 ×α (Mathematical Formula 1)

[0247] N H2 is the value converted into density of hydrogen molecules detached from the standard sample. S H2 is the integral value of the spectrum when the standard sample is measured by TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 It shall be done as. S O2 ε is the integral value of the spectrum when the insulating layer is measured by TDS analysis. α is a coefficient that affects the spectral intensity in TDS analysis. For a detailed explanation of Equation 1, refer to Japanese Patent Publication No. 6-275697. Furthermore, the value of the oxygen escape amount described above was obtained using the EMD-WA1000S / W temperature escape analysis device (manufactured by ESCO, Ltd.), and 1×10⁻⁶ as a standard sample. 16 cm -3 This is a value measured using a silicon wafer containing hydrogen atoms.

[0248] In addition, in TDS analysis, some of the oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Also, since the aforementioned α includes the ionization rate of oxygen molecules, the amount of oxygen atoms lost can be estimated by evaluating the amount of oxygen molecules lost.

[0249] In addition, NO2 is the amount of oxygen molecules lost. In the insulating layer, the amount of oxygen lost when converted to oxygen atoms is twice the amount of oxygen molecules lost.

[0250] As an example of a layer from which oxygen is removed by heat treatment, silicon oxide (SiO₂) containing an excess of oxygen x There is (x>2)). Silicon oxide (SiO₂) containing an excess of oxygen. x(x>2)) means containing more than twice the number of oxygen atoms per unit volume. The number of silicon atoms and oxygen atoms per unit volume are values ​​measured by Rutherford backscattering spectrometry.

[0251] <Formation of an electrode functioning as a source electrode or drain electrode>

[0252] Next, electrodes (551) and (552) that function as source electrodes or drain electrodes are formed.

[0253] A layer containing a conductive material that serves as a source electrode or drain electrode is formed using a sputtering method or the like.

[0254] Next, a resist mask is formed by a photolithography process, and a layer containing a conductive material is selectively etched using the resist mask to form electrodes (551) and (552). Additionally, wiring (not shown) made of a layer containing the same conductive material is also formed by the same process.

[0255] In addition, when forming a transistor with a channel length (L) of 10 nm or more and 1000 nm (1 µm) or less, particularly less than 25 nm, it is desirable to form a mask using short extreme ultraviolet rays with a wavelength of several nm to tens of nm. This is because using extreme ultraviolet rays results in high resolution and a large depth of focus.

[0256] In addition, it is preferable to process the electrode functioning as a source electrode or drain electrode into a tapered shape. By making the electrode functioning as a source electrode or drain electrode into a tapered shape, the coverage can be improved by preventing the discontinuity of the layer (e.g., gate insulating layer) formed after this process. Furthermore, it is preferable to make the taper angle, for example, 30° or more and 60° or less.

[0257] In addition, when the layer containing the conductive material is formed as a single layer structure of a titanium layer or a titanium nitride layer, it is easy to process into a source electrode and a drain electrode having a tapered shape.

[0258] Formation of an insulating layer protecting the transistor

[0259] Next, an insulating layer (505) is formed to protect the transistor.

[0260] An insulating layer protecting the transistor is formed using a plasma CVD method or a sputtering method (see FIG. 5d).

[0261] As described above, since the generation of carriers within the oxide semiconductor layer where the channel is formed can be prevented, variations in the characteristics of the transistor can be suppressed.

[0262] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments.

[0263] (Embodiment 7)

[0264] In this embodiment, a trimming circuit that can be used as one form of the present invention has a very small off-leakage current (e.g., 1 × 10⁻⁶ per 1 μm channel width). -17 A) We will now describe an oxide semiconductor layer applicable to a transistor. Specifically, we will describe an oxide semiconductor layer having crystals oriented along the c-axis.

[0265] In this embodiment, an oxide comprising a crystal (also called a C Axis Aligned Crystal) that is oriented along the c-axis and has a triangular or hexagonal atomic arrangement when viewed from the direction of the ab plane, surface, or interface, in which metal atoms are arranged in layers along the c-axis or metal atoms and oxygen atoms are arranged in layers, and in which the direction of the a-axis or b-axis is different from that of the a-axis (rotated around the c-axis) in the ab plane.

[0266] The CAAC-OS film is neither a perfect single crystal nor a perfect amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed-phase structure having crystalline and amorphous parts in the amorphous phase. Furthermore, the crystalline part is often sized to fit within a cube with a side length of less than 100 nm. Additionally, the boundary between the amorphous and crystalline parts contained in the CAAC-OS film is not clear when observed using a transmission electron microscope (TEM). Moreover, grain boundaries (also called grain boundaries) cannot be identified in the CAAC-OS film by TEM. Therefore, the reduction in electron mobility caused by grain boundaries is suppressed in the CAAC-OS film.

[0267] The crystal portions included in the CAAC-OS film have a c-axis aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface of the CAAC-OS film, and also have a triangular or hexagonal atomic arrangement when viewed from a direction perpendicular to the ab plane, and metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers when viewed from a direction perpendicular to the c-axis. In addition, the directions of the a-axis and b-axis may differ between different crystal portions. In cases where it is simply stated as "perpendicular" in this specification, a range of 85° or more and 95° or less is included. In addition, in cases where it is simply stated as "parallel," a range of -5° or more and 5° or less is included.

[0268] Furthermore, the distribution of crystalline regions in the CAAC-OS film does not need to be uniform. For example, when crystal growth is performed from the surface side of the oxide semiconductor film during the formation process of the CAAC-OS film, the proportion of crystalline regions near the surface may be higher than near the surface to be formed. Additionally, by adding impurities to the CAAC-OS film, the crystalline regions may become amorphous in the impurity-added regions.

[0269] Since the c-axis of the crystal portion included in the CAAC-OS film is aligned parallel to the normal vector of the surface to be formed or the normal vector of the surface of the CAAC-OS film, it may point in different directions depending on the shape of the CAAC-OS film (cross-sectional shape of the surface to be formed or cross-sectional shape of the surface). Furthermore, the direction of the c-axis of the crystal portion becomes parallel to the normal vector of the surface to be formed or the normal vector of the surface when the CAAC-OS film is formed. The crystal portion is formed by forming the film, or by performing a crystallization treatment such as heat treatment after forming the film.

[0270] Transistors using a CAAC-OS film can reduce variations in electrical characteristics caused by irradiation with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0271] In a broad sense, an oxide containing CAAC refers to a single crystal that has an atomic arrangement of triangles, hexagons, equilateral triangles, or regular hexagons when viewed from a direction perpendicular to the ab plane, and contains a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers when viewed from a direction perpendicular to the c-axis.

[0272] CAAC is not a single crystal, but it is not formed solely of amorphous material either. Furthermore, while CAAC contains crystallized portions (crystalline regions), there are cases where the boundary between one crystalline region and another cannot be clearly distinguished.

[0273] If oxygen is included in the CAAC, a portion of the oxygen may be replaced with nitrogen. Additionally, the c-axis of each crystal part constituting the CAAC may be aligned in a specific direction (e.g., a direction perpendicular to the substrate surface on which the CAAC is formed, the surface of the CAAC, etc.). Alternatively, the normal of the ab plane of each crystal part constituting the CAAC may be oriented in a specific direction (e.g., a direction perpendicular to the substrate surface on which the CAAC is formed, the surface of the CAAC, etc.).

[0274] CAAC can be in a conductor, semiconductor, or insulator state depending on its composition, etc. Additionally, depending on its composition, it can be transparent or opaque to visible light.

[0275] As an example of such a CAAC, a crystal may be cited that is formed in a film shape, and when observed from a direction perpendicular to the film surface or the supporting substrate surface, a triangular or hexagonal atomic arrangement is observed, and when the cross-section of the film is observed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed.

[0276] An example of a crystal structure included in CAAC will be explained in detail using FIGS. 6a to 8c. Additionally, unless otherwise specified, FIGS. 6a to 8c define the upper direction as the c-axis direction, and the plane orthogonal to the c-axis direction as the ab plane. Furthermore, when simply referred to as the upper half and lower half, they mean the upper half and lower half when the ab plane serves as the boundary. Also, in FIGS. 6a to 6c, an O atom enclosed in a circle represents a tetracoordinate O atom, and an O atom enclosed in a double circle represents a tricoordinate O atom.

[0277] Figure 6a illustrates a structure having one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereinafter referred to as tetracoordinate O atoms) adjacent to the In atom. Here, a structure in which only the oxygen atoms adjacent to a single metal atom are depicted is called a subgroup. Although the structure depicted in Figure 6a has an octahedral structure, it is depicted as a planar structure for simplification. Additionally, there are three tetracoordinate O atoms in each of the upper and lower halves of Figure 6a. The subgroup depicted in Figure 6a has a charge of zero.

[0278] Figure 6b illustrates a structure having one penta-coordinated Ga atom, three tri-coordinated oxygen atoms (hereinafter referred to as tri-coordinated O atoms) adjacent to the Ga atom, and two tetra-coordinated O atoms adjacent to the Ga atom. All tri-coordinated O atoms exist in the ab plane. There is one tetra-coordinated O atom in each of the upper and lower halves of Figure 6b. Additionally, since the In atom also has a penta-coordinated structure, it can have the structure illustrated in Figure 6b. The subgroup illustrated in Figure 6b has a charge of zero.

[0279] A structure having one tetracoordinate Zn atom and four tetracoordinate O atoms adjacent to the Zn atom is illustrated in FIG. 6c. In FIG. 6c, there is one tetracoordinate O atom in the upper half and three tetracoordinate O atoms in the lower half. Alternatively, there may be three tetracoordinate O atoms in the upper half and one tetracoordinate O atom in the lower half. The subgroup illustrated in FIG. 6c has a charge of 0.

[0280] A structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom is illustrated in Fig. 6d. In the upper half of Fig. 6d, there are three tetracoordinate O atoms, and in the lower half, there are three tetracoordinate O atoms. The subgroup illustrated in Fig. 6d has a charge of +1.

[0281] A subgroup containing two Zn atoms is shown in Fig. 6e. In the upper half of Fig. 6e, there is one tetracoordinate O atom, and in the lower half, there is one tetracoordinate O atom. The subgroup shown in Fig. 6e has a charge of -1.

[0282] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a large group (also called a unit cell).

[0283] Here, the rules governing the bonding of these subgroups are explained. In the hexacoordinate In atom shown in Fig. 6a, the three O atoms located in the upper half each have three adjacent In atoms in the downward direction, and the three O atoms located in the lower half each have three adjacent In atoms in the upward direction. In the quincoordinate Ga atom shown in Fig. 6b, the one O atom located in the upper half has one adjacent Ga atom in the downward direction, and the one O atom located in the lower half has one adjacent Ga atom in the upward direction. In the tetracoordinate Zn atom shown in Fig. 6c, the one O atom located in the upper half has one adjacent Zn atom in the downward direction, and the three O atoms located in the lower half each have three adjacent Zn atoms in the upward direction. In this way, the number of tetracoordinate O atoms located above the metal atom and the number of adjacent metal atoms located below that O atom are the same, and likewise, the number of tetracoordinate O atoms located below the metal atom and the number of adjacent metal atoms located above that O atom are the same. Since the O atom is tetracoordinate, the sum of the number of adjacent metal atoms located below and the number of adjacent metal atoms located above is 4. Therefore, when the sum of the number of tetracoordinate O atoms located above the metal atom and the number of tetracoordinate O atoms located below another metal atom is 4, two types of subgroups containing metal atoms can bond. For example, in the case where a hexacoordinate metal atom (In or Sn) is bonded through a tetracoordinate O atom in the lower half, since there are 3 tetracoordinate O atoms, it is bonded with either a pentocordial metal atom (Ga or In) or a tetracoordinate metal atom (Zn).

[0284] Metal atoms with coordination numbers 4, 5, and 6 are bonded in the c-axis direction through a 4-coordinate O atom. In addition, multiple subgroups are combined to form a middle group so that the total charge of the layered structure becomes zero.

[0285] Figure 7a shows a model of the middle group constituting the In-Sn-Zn-O layered structure. Figure 7b shows a large group consisting of three middle groups. Additionally, Figure 7c shows the atomic arrangement when the layered structure of Figure 7b is observed from the c-axis direction.

[0286] In FIG. 7a, for simplification, triporvical O atoms are omitted, and only the number of tetracoordinate O atoms is shown; for example, three tetracoordinate O atoms are shown in the upper and lower halfs of the Sn atom, respectively, as circle 3. Similarly, in FIG. 7a, one tetracoordinate O atom is shown in the upper and lower halfs of the In atom, respectively, as circle 1. Additionally, FIG. 7a shows a Zn atom with one tetracoordinate O atom in the lower half and three tetracoordinate O atoms in the upper half, and a Zn atom with one tetracoordinate O atom in the upper half and three tetracoordinate O atoms in the lower half.

[0287] In FIG. 7a, the middle group constituting the In-Sn-Zn-O layered structure is configured such that, sequentially from the top, Sn atoms with three tetracoordinate O atoms each in the upper and lower half are bonded to In atoms with one tetracoordinate O atom each in the upper and lower half, the In atoms are bonded to Zn atoms with three tetracoordinate O atoms each in the upper half, through one tetracoordinate O atom in the lower half below the Zn atoms, the In atoms are bonded to a subgroup consisting of two Zn atoms with one tetracoordinate O atom each in the upper half, and Sn atoms with three tetracoordinate O atoms each in the upper and lower half are bonded through one tetracoordinate O atom in the lower half of the subgroup. A plurality of the above middle groups combine to form a large group.

[0288] Here, for the tripartite and tetraartite O atoms, the charge per bond can be considered to be -0.667 and -0.5, respectively. For example, the charges of In (6-coordinate or 5-coordinate) atoms, Zn (4-coordinate) atoms, and Sn (5-coordinate or 6-coordinate) atoms are +3, +2, and +4, respectively. Therefore, a subgroup containing Sn atoms has a charge of +1. Consequently, to form a layered structure containing Sn atoms, a charge of -1 is required to offset the charge of +1. As a structure with a charge of -1, a subgroup containing two Zn atoms can be cited, as shown in Fig. 6e. For example, if there is one subgroup containing two Zn atoms for every one subgroup containing Sn atoms, the charges are offset, so the total charge of the layered structure can be made zero.

[0289] Specifically, an In-Sn-Zn-O system crystal (In2SnZn3O8) is obtained by forming the major group shown in FIG. 7b. Furthermore, the obtained In-Sn-Zn-O system layered structure has the compositional formula In2SnZn2O7(ZnO) m It can be represented as (m is 0 or a natural number).

[0290] In addition, there are also oxides of quaternary metals such as In-Sn-Ga-Zn-O oxides, or oxides of ternary metals such as In-Ga-Zn-O oxides (also denoted as IGZO), In-Al-Zn-O oxides, Sn-Ga-Zn-O oxides, Al-Ga-Zn-O oxides, Sn-Al-Zn-O oxides, In-Hf-Zn-O oxides, In-La-Zn-O oxides, In-Ce-Zn-O oxides, In-Pr-Zn-O oxides, In-Nd-Zn-O oxides, In-Sm-Zn-O oxides, In-Eu-Zn-O oxides, In-Gd-Zn-O oxides, In-Tb-Zn-O oxides, In-Dy-Zn-O oxides, In-Ho-Zn-O oxides, and In-Er-Zn-O oxides, The same applies when using In-Tm-Zn-O oxides, In-Yb-Zn-O oxides, In-Lu-Zn-O oxides, or binary metal oxides such as In-Zn-O oxides, Sn-Zn-O oxides, Al-Zn-O oxides, Zn-Mg-O oxides, Sn-Mg-O oxides, In-Mg-O oxides, or In-Ga-O oxides.

[0291] For example, Figure 8a shows a model diagram of a middle group constituting an In-Ga-Zn-O layered structure.

[0292] In FIG. 8a, the middle group constituting the In-Ga-Zn-O layered structure is configured such that, sequentially from the top, three tetracoordinate O atoms each are bonded to In atoms in the upper and lower halfs, one tetracoordinate O atom is bonded to a Zn atom in the upper half, one tetracoordinate O atom is bonded to a Ga atom in the upper and lower halfs through three tetracoordinate O atoms in the lower half below the Zn atom, and three tetracoordinate O atoms each are bonded to In atoms in the upper and lower halfs through one tetracoordinate O atom in the lower half below the Ga atom. A plurality of the above middle groups combine to form a large group.

[0293] Figure 8b illustrates a large group consisting of three medium groups. Additionally, Figure 8c illustrates the atomic arrangement when the layer structure of Figure 8b is observed from the c-axis direction.

[0294] Here, since the charges of the In (6-coordinate or 5-coordinate) atom, Zn (4-coordinate) atom, and Ga (5-coordinate) atom are +3, +2, and +3, respectively, the charge of any subgroup containing an In atom, Zn atom, or Ga atom is 0. Therefore, if these subgroups are combined, the total charge of the middle group is always 0.

[0295] In addition, the middle group constituting the In-Ga-Zn-O layered structure is not limited to the middle group shown in FIG. 8a, and may also constitute a large group composed of a middle group in which the arrangement of In atoms, Ga atoms, and Zn atoms differs from that in FIG. 8a.

[0296] Specifically, by forming the major group shown in FIG. 8b, an In-Ga-Zn-O system crystal is obtained. Furthermore, the obtained In-Ga-Zn-O system layered structure is composed of the formula InGaO3(ZnO). n It can be expressed as (n is a natural number).

[0297] In the case of n=1 (InGaZnO4), for example, the crystal structure shown in Fig. 9a can be taken. In addition, in the crystal structure shown in Fig. 9a, as explained using Fig. 6b, since the Ga atoms and In atoms are pentagonal, a structure in which the Ga atoms are substituted with In atoms can also be taken.

[0298] In addition, in the case of n=2 (InGaZn2O5), for example, the crystal structure shown in Fig. 9b can be taken. Also, in the crystal structure shown in Fig. 9b, since the Ga atoms and In atoms are pentagonal as explained using Fig. 6b, a structure in which the Ga atoms are substituted with In atoms can also be taken.

[0299] It is desirable to configure the transistor used in one embodiment of the present invention with an oxide semiconductor layer including CAAC applied to the channel forming region, as this is expected to provide high reliability.

[0300] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. Explanation of the symbols

[0301] 100: Trimming circuit 105: Resistor element 110: Transistor 115: Terminal 120: Transistor 125: Erase terminal 130: Transistor 140: Capacitive element 150: Memory Node 300: Trimming Circuit 301: Substrate 302: Device isolation insulating layer 303: Insulating layer 304: Insulating layer 305: Resistor Element 310: Transistor 311: Wiring 312: Gate insulation layer 313: Oxide semiconductor layer 320: Transistor 321: Wiring 322: Gate insulation layer 323: Oxide semiconductor layer 330: Transistor 331: Gate electrode 332: Wiring 335: Wiring 340: Capacitive element 341: Wiring 351: Wiring 352: Wiring 353: Wiring 413a: Oxide semiconductor layer 413b: Oxide semiconductor layer 504: Insulating layer 505: Insulating layer 511: Gate electrode 512: Gate insulating layer 513: Oxide semiconductor layer 514a: Insulating layer 514b: Insulating layer 551: Electrode 552: Electrode 701: Substrate 704: Insulating layer 705: Insulating layer 710: Transistor 711: Gate electrode 712: Gate insulating layer 713: Oxide semiconductor layer 714a: Insulation layer 714b: Sidewall 751: Electrode 752: Electrode

Claims

Claim 1 A first conductive layer; a first insulating layer having a region disposed above the first conductive layer; a first oxide semiconductor layer having a region disposed above the first insulating layer and also having a channel forming region of a first transistor; a second oxide semiconductor layer having a region disposed above the first insulating layer and also having a channel forming region of a second transistor; a second conductive layer having a region disposed above the first oxide semiconductor layer; a third conductive layer having a region disposed above the first oxide semiconductor layer and also having a region disposed above the second oxide semiconductor layer; a fourth conductive layer having a region disposed above the second oxide semiconductor layer; a fifth conductive layer having a region disposed above the first oxide semiconductor layer and also functioning as a gate of the first transistor; and a sixth conductive layer having a region disposed above the second oxide semiconductor layer and also functioning as a gate of the second transistor, wherein the first transistor is identical to the second transistor A semiconductor device having a conductivity type, wherein the second conductive layer functions as one side of the source or drain of the first transistor, the third conductive layer functions as the other side of the source or drain of the first transistor, and also functions as one side of the source or drain of the second transistor, and the fourth conductive layer functions as the other side of the source or drain of the second transistor, wherein a first power supply potential is supplied to the second conductive layer and a second power supply potential is supplied to the fourth conductive layer, and the operating state of the device is controlled according to the potential of the third conductive layer, and the first transistor is off and also has a period in which the second transistor is off. Claim 2 A first conductive layer; a first insulating layer having a region disposed above the first conductive layer; a first oxide semiconductor layer having a region disposed above the first insulating layer and also having a channel forming region of a first transistor; a second oxide semiconductor layer having a region disposed above the first insulating layer and also having a channel forming region of a second transistor; a second conductive layer having a region disposed above the first oxide semiconductor layer; a third conductive layer having a region disposed above the first oxide semiconductor layer and also having a region disposed above the second oxide semiconductor layer; a fourth conductive layer having a region disposed above the second oxide semiconductor layer; a fifth conductive layer having a region disposed above the first oxide semiconductor layer and also functioning as a gate of the first transistor; and a sixth conductive layer having a region disposed above the second oxide semiconductor layer and also functioning as a gate of the second transistor, wherein the first transistor is identical to the second transistor A semiconductor device having a conductivity type, wherein the second conductive layer functions as one side of the source or drain of the first transistor, the third conductive layer functions as the other side of the source or drain of the first transistor, and also functions as one side of the source or drain of the second transistor, and the fourth conductive layer functions as the other side of the source or drain of the second transistor, wherein a first power supply potential is supplied to the second conductive layer, a second power supply potential is supplied to the fourth conductive layer, a first signal is input to the fifth conductive layer, a second signal is input to the sixth conductive layer, and the operating state of the device is controlled according to the potential of the third conductive layer, and the first transistor is off and also has a period in which the second transistor is off. Claim 3 A first conductive layer; a first insulating layer having a region disposed above the first conductive layer; a first oxide semiconductor layer having a region disposed above the first insulating layer and also having a channel forming region of a first transistor; a second oxide semiconductor layer having a region disposed above the first insulating layer and also having a channel forming region of a second transistor; a second conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer; a third conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer and also having a region in contact with the upper surface of the second oxide semiconductor layer; a fourth conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer; a fifth conductive layer having a region disposed above the first oxide semiconductor layer and also functioning as a gate of the first transistor; and a sixth conductive layer having a region disposed above the second oxide semiconductor layer and also functioning as a gate of the second transistor, wherein the first transistor is identical to the second transistor A semiconductor device having a conductivity type, wherein the second conductive layer functions as one side of the source or drain of the first transistor, the third conductive layer functions as the other side of the source or drain of the first transistor, and also functions as one side of the source or drain of the second transistor, and the fourth conductive layer functions as the other side of the source or drain of the second transistor, wherein a first power supply potential is supplied to the second conductive layer and a second power supply potential is supplied to the fourth conductive layer, and the operating state of the device is controlled according to the potential of the third conductive layer, and the first transistor is off and also has a period in which the second transistor is off. Claim 4 A first conductive layer; a first insulating layer having a region disposed above the first conductive layer; a first oxide semiconductor layer having a region disposed above the first insulating layer and also having a channel forming region of a first transistor; a second oxide semiconductor layer having a region disposed above the first insulating layer and also having a channel forming region of a second transistor; a second conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer; a third conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer and also having a region in contact with the upper surface of the second oxide semiconductor layer; a fourth conductive layer having a region in contact with the upper surface of the second oxide semiconductor layer; a fifth conductive layer having a region disposed above the first oxide semiconductor layer and also functioning as a gate of the first transistor; and a sixth conductive layer having a region disposed above the second oxide semiconductor layer and also functioning as a gate of the second transistor, wherein the first transistor is identical to the second transistor A semiconductor device having a conductivity type, wherein the second conductive layer functions as one side of the source or drain of the first transistor, the third conductive layer functions as the other side of the source or drain of the first transistor, and also functions as one side of the source or drain of the second transistor, and the fourth conductive layer functions as the other side of the source or drain of the second transistor, wherein a first power supply potential is supplied to the second conductive layer, a second power supply potential is supplied to the fourth conductive layer, a first signal is input to the fifth conductive layer, a second signal is input to the sixth conductive layer, and the operating state of the device is controlled according to the potential of the third conductive layer, and the first transistor is off and also has a period in which the second transistor is off. Claim 5 A semiconductor device according to any one of claims 1 to 4, wherein the third conductive layer functions as an electrode of a capacitive element.

Images