Memory chip with integrated data mover

Abstract

A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device through a first wiring. A memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device through a second wiring separate from the first wiring. A memory chip also having a data mover configured to facilitate access to the second microchip or device through the second set of pins to read data from the second microchip or device and write data to the second microchip or device. Additionally, a system having a memory chip, a first microchip or device, and a second microchip or device.

Description

Technology Field

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 573,780, titled “Memory chip having an integrated data carrier,” filed on September 17, 2019, the entire contents of which are incorporated herein by reference.

[0003] Technology field

[0004] At least some embodiments disclosed herein relate to a memory chip having an integrated data carrier. Also, at least some embodiments disclosed herein relate to using such a memory chip in the flexible provisioning of a string of memory chips to form a memory. Background Technology

[0005] The memory of a computing system can be hierarchical. Often referred to as memory hierarchy in computer architecture, a memory hierarchy can divide computer memory into layers based on specific factors such as response time, complexity, capacity, persistence, and memory bandwidth. These factors can be interrelated and often constitute tradeoffs that further highlight the utility of the memory hierarchy.

[0006] In general, memory hierarchy affects the performance of a computer system. To prioritize memory bandwidth and speed over other factors, limitations of the memory hierarchy, such as response time, complexity, capacity, and persistence, may need to be considered. To manage these priorities, various types of memory chips can be combined to balance faster chips with more stable or cost-effective ones. Each of these various chips can be viewed as part of the memory hierarchy. For example, to reduce the latency of a faster chip, another chip in the memory chip combination can respond by filling a buffer and then sending a signal to enable data transfer between the chips.

[0007] A memory hierarchy can consist of chips with different types of memory units. For example, a memory unit can be a Dynamic Random Access Memory (DRAM) unit. DRAM is a type of random access semiconductor memory that stores each bit of data in a memory cell, and it typically includes a capacitor and a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The capacitor can be charged or discharged to represent two values, "0" and "1". In DRAM, charge leaks from the capacitor, so an external memory refresh circuit is required to periodically rewrite data to the capacitor by restoring the original charge per capacitor. In contrast, Static Random Access Memory (SRAM) units do not require a refresh function. Additionally, DRAM is considered volatile memory because data is rapidly lost when the power is cut off. This differs from other types of non-volatile memory, such as flash memory and Non-Volatile Random Access Memory (NVRAM), where data storage is more permanent.

[0008] One type of NVRAM is 3D XPoint memory. With 3D XPoint memory, memory units store bits based on changes in bulk resistance along with a stackable cross-gridded data access array. 3D XPoint memory can be more cost-effective than DRAM but less cost-effective than flash memory.

[0009] Flash memory is another type of non-volatile memory. The advantage of flash memory is that it can be electrically erased and reprogrammed. Flash memory is considered to have two main types: NAND flash memory and NOR flash memory, named after the NAND and NOR logic gates that implement the memory units of flash memory. Flash memory units or cells exhibit internal characteristics similar to their corresponding gates. NAND flash memory contains NAND gates. NOR flash memory contains NOR gates. NAND flash memory can be written to and read in blocks, which can be smaller than the entire device. NOR flash allows a single byte to be written to an erased location or read independently. Due to the advantages of NAND flash memory, this type of memory has been frequently utilized in memory cards, USB flash drives, and solid-state drives. However, a major disadvantage of using flash memory in general is that only a relatively small number of write cycles are possible per specific block compared to other types of memory, such as DRAM and NVRAM. Brief explanation of the drawing

[0010] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. FIG. 1 illustrates an exemplary memory system configured to provide flexible provisioning of multi-layer memory according to some embodiments of the present disclosure. FIG. 2 illustrates an exemplary memory system and a processor chip configured to provide flexible provisioning of multi-layer memory according to some embodiments of the present disclosure. FIG. 3 illustrates an exemplary memory system and a memory controller chip configured to provide flexible provisioning of a multi-layer memory according to some embodiments of the present disclosure. FIG. 4 illustrates an exemplary memory system configured to provide flexible provisioning of a multi-layer memory having layers, each comprising multiple memory chips, according to some embodiments of the present disclosure. FIG. 5 illustrates an exemplary portion of an exemplary computing device according to some embodiments of the present disclosure. FIG. 6 illustrates an exemplary system comprising a memory chip having an integrated data mover according to some embodiments of the present disclosure. FIG. 7 illustrates an exemplary system comprising a memory chip illustrated in FIG. 6 according to some embodiments of the present disclosure, as well as a microchip or device having a logical-to-physical mapping for receiving data transmitted from a data carrier and mapping the received data. FIG. 8 illustrates an exemplary system comprising a memory chip illustrated in FIG. 6, which is shown having encryption and authentication circuits according to some embodiments of the present disclosure. Specific details for implementing the invention

[0011] At least some embodiments disclosed herein relate to a memory chip having an integrated data mover (see, for example, FIG. 6 to 8 and the corresponding text herein). Also, at least some embodiments disclosed herein relate to using such a memory chip in the flexible provisioning of a string of memory chips to form a memory (see, for example, FIG. 1 to 8 and the corresponding text herein). For example, one or more instances of the memory chip shown in FIG. 6 to 8 may be used as one or more memory chips in the flexible provisioning of the string of memory chips (102) shown in FIG. 1 to 3 as well as the string of memory chips (402) shown in FIG. 4.

[0012] For the purposes of the present disclosure, a data mover is a circuit of a memory chip or device that manages the transfer of data to another memory chip or device. Such a data mover may be used in a group of memory chips or devices of a memory layer. Thus, the data mover can facilitate the transfer of data from one memory chip or device to another memory chip or device in a memory layer.

[0013] A memory chip (e.g., see memory chip (602)) comprising an integrated data mover (e.g., see data mover (608)) may have two separate sets of pins (e.g., see sets of pins (604 and 606) shown in FIGS. 6 through 8) for respective individual connections to a first microchip or device (e.g., see first microchip or device (624) shown in FIGS. 6 through 8) and a second microchip or device (e.g., see second microchip or device (626) shown in FIGS. 6 through 8). The first microchip or device may be a processor, such as a system-on-chip (SoC) or another memory chip. The second microchip or device may be a memory device, such as another memory chip or a mass storage device.

[0014] In some embodiments, the memory chip may include an encryption engine (e.g., see encryption engine (802) illustrated in FIG. 8) in addition to a data mover to protect data to be moved to a second microchip or device. Additionally, in these and other embodiments, the memory chip may include a gatekeeper device (e.g., see gatekeeper (804) illustrated in FIG. 8) capable of performing authentication for access to data stored in the second microchip or device.

[0015] The data transfer device can combine data stored in a memory chip directed toward a second microchip or device (e.g., see portion of memory (610) having data accessible by the first microchip or device (624) as illustrated in FIGS. 6 to 8) using various strategies. This can improve the recording performance and durability of the second microchip or device.

[0016] Generally, the memory chip may include a first pin set, a second pin set, and an integrated data mover. The first pin set may be configured to allow the memory chip to be coupled to a first microchip or device through a first wiring. The second pin set may be configured to allow the memory chip to be coupled to a second microchip or device through a second wiring separate from the first wiring. The data mover may be configured to facilitate access to the second microchip or device through the second pin set in order to read data from the second microchip or device or to write data to the second microchip or device.

[0017] The memory chip may be a non-volatile random access memory (NVRAM) chip in that the memory chip includes a plurality of NVRAM cells. In some embodiments, the plurality of NVRAM cells may include a plurality of 3D XPoint memory cells. Additionally, the memory chip may be a dynamic random access memory (DRAM) chip in that the memory chip includes a plurality of DRAM cells. Additionally, the memory chip may be a flash memory chip in that the memory chip includes a plurality of flash memory cells. The plurality of flash memory cells may include a plurality of NAND-type flash memory cells.

[0018] The first microchip or device may be another memory chip or memory device or a processor chip or processor device. In some embodiments, for example, the first microchip or device is an SoC. In some embodiments, for example, the first microchip or device is a DRAM chip. In some embodiments, for example, the first microchip or device is an NVRAM chip. Data stored in a portion of the memory chip may be accessible by or through the first microchip or device via a first set of pins. Additionally, if data stored in a portion of the memory chip is accessible through the first microchip or device, it is accessed by another memory chip or device or a processor chip or device. Furthermore, the first microchip or device may not only write data to the memory chip but also read data from the memory chip.

[0019] The second microchip or device may be another memory chip or memory device. In some embodiments, for example, the second microchip or device is a DRAM chip. In some embodiments, for example, the second microchip or device is an NVRAM chip. In some embodiments, for example, the second microchip or device is a flash memory chip (e.g., a NAND flash memory chip). Data stored in a portion of the second microchip or device may be accessible by or through the memory chip via a second set of pins. Additionally, if data stored in a portion of the second microchip or device is accessible through the memory chip, it is accessed by another memory chip or device or a processor chip or device (such as the first microchip or device). Furthermore, the memory chip may not only read data from the second microchip or device but also write data to the second microchip or device.

[0020] A data mover can be configured to combine data stored in a portion of a memory chip by moving data to a second microchip or device in blocks. For example, a data mover can be configured to combine data stored in a portion of a memory chip accessible by or through a first set of pins to a first microchip or device by moving data to a second microchip or device in blocks. By moving data in blocks, the data mover can improve the write performance and durability of the second microchip or device, and sequential or block access to the memory chip is tens of times faster than random access to the memory chip.

[0021] In some embodiments, the block is at a coarser granularity than the data initially stored in a portion of the memory chip. For example, the block is at a coarser granularity than the data initially stored in a portion of the memory chip accessible by or through the first set of pins to the first microchip or device. A block at a coarser granularity than pre-blocked data in the memory chip, such as data accessed by the first microchip or device, can reduce the frequency of data writing to the second microchip or device.

[0022] The data mover may also be configured to buffer the movement of changes to data stored in a portion of the memory chip, such as data stored in a portion of the memory chip accessible to the first microchip or device. And, in such an embodiment, the data mover may also be configured to transmit a write request to the second microchip or device in an appropriate size due to buffering by the data mover. When the second microchip or device is the second microchip or device and the write to the second microchip or device is in an appropriate size due to buffering by the data mover, the second microchip or device can erase blocks according to the write and program blocks of the second microchip or device without additional processing or minimal processing in the second microchip or device. This is one exemplary method by which a data mover integrated into the memory chip can improve the write performance and durability of the second microchip or device. Additionally, when there is buffering by a data mover and frequent and / or random changes to data in a portion of the memory chip (such as data in a portion of the chip accessible by the first microchip or device), the second microchip or device does not need to be frequently erased and reprogrammed in a manner corresponding to the changes occurring in the portion of the memory chip.

[0023] Buffering by a data mover is significantly more advantageous when the second microchip or device is a flash memory chip, as buffering can eliminate or at least limit the effects of write amplification occurring in the flash memory. Write amplification can be reduced or even eliminated by buffering because using buffering allows write requests transmitted by the memory chip to be modified to the appropriate size or granularity expected at the receiving flash memory chip. Consequently, the flash memory chip can erase and program blocks according to write requests without the possibility of write duplication, thereby avoiding additional processing at the second microchip or device.

[0024] The data mover may also be configured to bundle changed addresses in changes to the data stored in a portion of the memory chip (e.g., data in a portion of the memory chip accessible to the first microchip or device). In such an embodiment, the data mover may also be configured to write the changed addresses bundled in another portion of the memory chip to be moved to the second microchip or device via a write request to the second microchip or device. This function of the data mover can improve buffering by the data mover and the transmission of write requests following buffering, because the bundling of the changed addresses can be controlled by the data mover to correspond to the appropriate size or granularity expected by the receiving second microchip or device.

[0025] In some embodiments, the memory chip may also include a logical-to-physical mapping to the second microchip or device (see, for example, the logical-to-physical mapping (612) shown in FIG. 6). And, the logical-to-physical mapping to the second microchip or device may be configured to use bundled modified addresses as inputs. In some other embodiments, the second microchip or device may itself include a logical-to-physical mapping configured to use bundled modified addresses as inputs when bundled modified addresses are transmitted as a write request to the second microchip or device (see, for example, the logical-to-physical mapping (712) shown in FIG. 7).

[0026] Some embodiments described herein may include a system comprising an intermediate memory chip (e.g., see memory chip (602)), a first memory chip (e.g., see first microchip or device (624)), and a second memory chip (e.g., see second microchip or device (626)). In such embodiments, the intermediate memory chip may be an NVRAM chip (e.g., a 3D XPoint memory chip), the second memory chip may be a flash memory chip (e.g., a NAND flash memory chip), and the first memory chip may be a DRAM chip. Some other embodiments described herein may include a system comprising an intermediate memory chip (e.g., see memory chip (602)), a second memory chip (e.g., see second microchip or device (626)), and a processor chip such as an SoC (e.g., see first microchip or device (624)). In such an embodiment, the intermediate memory chip may be an NVRAM chip (e.g., a 3D XPoint memory chip) or a DRAM chip, and the second memory chip may be a flash memory chip (e.g., a NAND flash memory chip) or an NVRAM chip.

[0027] Additionally, at least some aspects of the present disclosure relate to the flexible provisioning of strings of memory chips to form memory for a processor chip or a system-on-chip (SoC), with reference, for example, to FIGS. 1 through 5 and the corresponding text of the present invention. In view of a processor chip or SoC wired to memory, a string of memory chips in memory appears no different from a single memory chip implementation; however, by using flexible provisioning, the advantages of using strings of memory chips are achieved. For example, through flexible provisioning, the advantages of using strings of memory chips with a memory hierarchy can be obtained.

[0028] A processor chip or SoC may be wired directly to a first memory chip of a string and may interact with the first memory chip without recognizing a memory chip downstream of the string of the first memory chip. In memory, the first memory chip may be wired directly to a second memory chip and may interact with the second memory chip, so that the processor chip or SoC may take advantage of a string of the first and second memory chips without recognizing the second memory chip. Also, the second memory chip may be wired directly to a third memory chip so that the processor chip or SoC takes advantage of a string of multiple memory chips without recognizing and interacting with multiple memory chips downstream of the first memory chip. Additionally, in some embodiments, each chip of the string recognizes and interacts with the immediate upstream and downstream chips of the string without recognizing a chip further upstream or downstream of the string.

[0029] In some embodiments, the first memory chip of the string may be a DRAM chip. The second memory chip of the string immediately downstream of the first chip may be an NVRAM chip (e.g., a 3D XPoint memory chip). The third memory chip of the string immediately downstream of the second chip may be a flash memory chip (e.g., a NAND flash memory chip). Additionally, for example, the string may be DRAM-DRAM-NVRAM, or DRAM-NVRAM-NVRAM, or DRAM-flash memory-flash memory; however, DRAM-NVRAM-flash memory may provide a more effective solution for a string of memory chips that are flexibly provisioned as multi-tier memory. Furthermore, to understand the flexible provisioning of the string of memory chips disclosed herein, examples will often refer to a three-chip string of memory chips; however, it should be understood that a string of memory chips may include three or more memory chips.

[0030] Additionally, for the purposes of this disclosure, it should be understood that DRAM, NVRAM, 3D XPoint memory, and flash memory are technologies for individual memory units, and that a memory chip for any one of the memory chips described herein may include logic circuits for command and address decoding as well as an array of memory units of DRAM, NVRAM, 3D XPoint memory, or flash memory. For example, a DRAM chip described herein includes logic circuits for command and address decoding and an array of memory units of DRAM. Also, for example, an NVRAM chip described herein includes logic circuits for command and address decoding and an array of memory units of NVRAM. And, for example, a flash memory chip described herein includes logic circuits for command and address decoding and an array of memory units of flash memory.

[0031] Additionally, a memory chip for any one of the memory chips described herein may include a cache or buffer memory for incoming and / or outgoing data. In some embodiments, a memory unit implementing the cache or buffer memory may be different from a unit on the chip hosting the cache or buffer memory. For example, a memory unit implementing the cache or buffer memory may be a memory unit of SRAM.

[0032] Each of the chips in a string of memory chips may be connected directly to a downstream and / or upstream chip via wiring, for example, Peripheral Component Interconnect Express (PCIe) or Serial Advanced Technology Attachment (SATA). Each of the connections between the chips in the string of memory chips may be connected sequentially by wiring, and the connections may be separated from each other. Each chip in the string of memory chips may include one or more sets of pins for connecting to the upstream chip and / or downstream chip of the string. In some embodiments, each chip in the string of memory chips may include a single integrated circuit (IC) enclosed within an IC package. In these embodiments, the IC package may include a set of pins at the boundary of the package.

[0033] A first memory chip (e.g., a DRAM chip) of a string of memory chips for a processor chip or SoC may include a portion that can be configured as a cache for a second memory chip (e.g., an NVRAM chip) of the string of memory chips by, for example, the processor chip or SoC. A portion of the memory units in the first memory chip may be used as cache memory for the second memory chip.

[0034] A second memory chip within a string of memory chips for a processor chip or SoC may include a portion that can be configured as a buffer for accessing a third memory chip (e.g., a flash memory chip) within the string of memory chips, directly by the first memory chip and indirectly by the processor chip or SoC. A portion of the memory units of the second memory chip may be used as a buffer for accessing the third memory chip. Additionally, the second memory chip may include a portion that can be configured as a table for logical-physical address mapping (a logical-physical table) or generally a logical-physical address mapping, directly by the first memory chip and indirectly by the processor chip or SoC. A portion of the memory units of the second memory chip may be used for logical-physical address mapping.

[0035] A third memory chip within a string of memory chips for a processor chip or SoC may include a controller capable of using the logical-physical address mapping of the second memory chip to manage the translation layer of the third memory chip (e.g., a flash translation layer function). The translation layer of the third memory chip may include a logical-physical address mapping such as a copy or derivative of the logical-physical address mapping of the second memory chip.

[0036] Additionally, in some embodiments, a processor chip or SoC connected to the memory may configure cache policy parameters of the first chip (e.g., write through vs. write back), logical-physical address mapping and buffers of the second memory chip, and the location and size of the cache of the first memory chip by writing data to the first memory chip. Furthermore, the configuration and settings described above by the processor chip or SoC may be delegated to a second data processing chip so that these operations are removed from the processor chip or SoC. For example, a memory having a string of memory chips may have a dedicated controller separate from the SoC or processor chip configured to provide and control the configuration and settings described above for the memory.

[0037] Generally, the flexibility to allocate a portion of memory units to specific memory chips in a string of chips as a cache or buffer, as described herein to provide flexible provisioning of multi-tier memory, is a method of configuring memory chips (e.g., DRAM, NVRAM, and flash memory chips) to make the connection operable and flexible. Cache and buffer operations allow downstream memory devices of different sizes and / or different types to be connected to upstream devices, and vice versa. In a sense, some functions of the memory controller are implemented in the memory chip to enable the operation of the memory chip's cache and buffer.

[0038] FIG. 1 illustrates an exemplary memory system (100) configured to provide flexible provisioning of a multi-layer memory according to some embodiments of the present disclosure. The memory system (100) includes a first memory chip (104) of a string (102) of memory chips. The memory system (100) also includes a second memory chip (106) of the string (102) of memory chips and a third memory chip (108) of the string of memory chips.

[0039] In FIG. 1, the first memory chip (104) is wired directly to the second memory chip (106) (e.g., see wiring (124)) and configured to interact directly with the second memory chip. Additionally, the second memory chip (106) is wired directly to the third memory chip (108) (e.g., see wiring (126)) and configured to interact directly with the third memory chip.

[0040] Additionally, each chip of the string of memory chips (102) may include one or more sets of pins for connecting to the upstream chip and / or downstream chip of the string (see, for example, sets of pins (132, 134, 136 and 138)). In some embodiments, each chip of the string of memory chips (see, for example, the string of memory chips (102) or the string of groups of memory chips (402) shown in FIG. 4) may include a single IC enclosed within an IC package. For example, set of pins (132) is part of the first memory chip (104) and connects the first memory chip (104) to the second memory chip (106) through wiring (124) and set of pins (134) which is part of the second memory chip (106). Wiring (124) connects the two sets of pins (132, 134). Additionally, for example, a pin set (136) is part of the second memory chip (106) and connects the second memory chip (106) to the third memory chip (108) through wiring (126) and a pin set (138) which is part of the third memory chip (108). Wiring (126) connects the two pin sets (136, 138).

[0041] Additionally, as illustrated, the first memory chip (104) includes a cache (114) for the second memory chip (106). And, the second memory chip (106) includes a buffer (116) for the third memory chip (108) as well as a logical-physical mapping (118) for the third memory chip (108).

[0042] The cache (114) for the second memory chip (106) may be configured by a processor chip or a memory controller chip (e.g., see processor chip (202) shown in FIG. 2 and memory controller chip (302) shown in FIG. 3). The location and size of the cache (114) within the first memory chip (104) may be configured by the processor chip or the memory controller chip by having corresponding data written to the first memory chip by the processor or the memory controller chip. Additionally, the cache policy parameters of the cache (114) of the first memory chip (104) may be configured by the processor or the memory controller chip by having corresponding data written to the first memory chip by the processor or the memory controller chip.

[0043] The buffer (116) for the third memory chip (108) may be configured by a processor chip or a memory controller chip (see, for example, the processor chip (202) shown in FIG. 2 and the memory controller chip (302) shown in FIG. 3). The location and size of the buffer (116) of the second memory chip (106) may be configured by the processor chip or the memory controller chip by writing corresponding data to the second memory chip, for example, indirectly through the first memory chip (104). Additionally, the buffer policy parameter of the buffer (116) of the second memory chip (106) may be configured by the processor chip or the memory controller chip by writing corresponding data to the second memory chip, for example, indirectly through the first memory chip (104).

[0044] The logical-physical mapping (118) for the third memory chip (108) can be configured by a processor chip or a memory controller chip (see, for example, the processor chip (202) shown in FIG. 2 and the memory controller chip (302) shown in FIG. 3). The location and size of the logical-physical mapping (118) of the second memory chip (106) can be configured by the processor chip or the memory controller chip by writing corresponding data to the second memory chip, for example, indirectly through the first memory chip (104). Additionally, the buffer policy parameters of the logical-physical mapping (118) of the second memory chip (106) can be configured by the processor chip or the memory controller chip by writing corresponding data to the second memory chip, for example, indirectly through the first memory chip (104).

[0045] In some embodiments, the third memory chip (108) may have the lowest memory bandwidth among the chips in the string. In some embodiments, the first memory chip (104) may have the highest memory bandwidth among the chips in the string. In such embodiments, the second memory chip (106) may have the next highest memory bandwidth among the chips in the string, so that the first memory chip (104) has the highest memory bandwidth among the chips in the string and the third memory chip (108) has the lowest memory bandwidth among the chips in the string.

[0046] In some embodiments, the first memory chip (104) is a DRAM chip or includes the same. In some embodiments, the first memory chip (104) is an NVRAM chip or includes the same. In some embodiments, the second memory chip (106) is a DRAM chip or includes the same. In some embodiments, the second memory chip (106) is an NVRAM chip or includes the same. In some embodiments, the third memory chip (108) is a DRAM chip or includes the same. In some embodiments, the third memory chip (108) is an NVRAM chip or includes the same. And, in some embodiments, the third memory chip (108) is a flash memory chip or includes the same.

[0047] In an embodiment having one or more DRAM chips, the DRAM chip may include logic circuits for command and address decoding as well as an array of memory units of the DRAM. Additionally, the DRAM chip described herein may include a cache or buffer memory for incoming and / or outgoing data. In some embodiments, the memory unit implementing the cache or buffer memory may be different from the DRAM unit on the chip hosting the cache or buffer memory. For example, the memory unit implementing the cache or buffer memory on the DRAM chip may be a memory unit of SRAM.

[0048] In an embodiment having one or more NVRAM chips, the NVRAM chip may include an array of memory units of the NVRAM, such as units of 3D XPoint memory, as well as logic circuits for command and address decoding. Additionally, the NVRAM chip described herein may include a cache or buffer memory for incoming and / or outgoing data. In some embodiments, the memory unit implementing the cache or buffer memory may be different from the NVRAM unit on the chip hosting the cache or buffer memory. For example, the memory unit implementing the cache or buffer memory on the NVRAM chip may be a memory unit of SRAM.

[0049] In some embodiments, the NVRAM chip may include a cross-section array of non-volatile memory cells. The cross-section array of non-volatile memory can perform bit storage based on changes in bulk resistance together with a stackable cross-grid data access array. Also, unlike many flash-based memories, the cross-section non-volatile memory can perform write-in-place operations, wherein the non-volatile memory cells can be programmed without the non-volatile memory cells being erased in advance.

[0050] As described herein, the NVRAM chip may be or include a crossover storage and memory device (e.g., 3D XPoint memory). The crossover memory device uses transistor-less memory elements, each having a memory cell and a selector stacked together as a column. The memory element columns are connected through two vertical lays of wiring, where one lay is above the memory element columns and the other lay is below the memory element columns. Each memory element can be individually selected at the intersection of a wiring on each of the two layers. The crossover memory device is fast, non-volatile, and can be used as an integrated memory pool for processing and storage.

[0051] In an embodiment having one or more flash memory chips, the flash memory chip may include logic circuits for command and address decoding as well as an array of memory units of flash memory, such as units of NAND flash memory. Additionally, the flash memory chip described herein may include a cache or buffer memory for incoming and / or outgoing data. In some embodiments, the memory unit implementing the cache or buffer memory may be different from the flash memory unit on the chip hosting the cache or buffer memory. For example, the memory unit implementing the cache or buffer memory on the flash memory chip may be a memory unit of SRAM.

[0052] Additionally, for example, an embodiment of a string of memory chips may include DRAM-DRAM-NVRAM or DRAM-NVRAM-NVRAM, or DRAM-flash memory-flash memory; however, DRAM-NVRAM-flash memory may provide a more effective solution for a string of memory chips that is flexibly provisioned as a multi-layer memory.

[0053] Additionally, for the purposes of this disclosure, it is understood that DRAM, NVRAM, 3D XPoint memory, and flash memory are technologies for individual memory units, and that a memory chip for any one of the memory chips described herein may include logic circuits for command and address decoding as well as an array of memory units of DRAM, NVRAM, 3D XPoint memory, or flash memory. For example, a DRAM chip described herein includes logic circuits for command and address decoding and an array of memory units of DRAM. For example, an NVRAM chip described herein includes logic circuits for command and address decoding as well as an array of memory units of NVRAM. For example, a flash memory chip described herein includes logic circuits for command and address decoding as well as an array of memory units of flash memory.

[0054] Additionally, a memory chip for any one of the memory chips described herein may include a cache or buffer memory for incoming and / or outgoing data. In some embodiments, a memory unit implementing the cache or buffer memory may be different from a unit on the chip hosting the cache or buffer memory. For example, a memory unit implementing the cache or buffer memory may be a memory unit of SRAM.

[0055] FIG. 2 illustrates an exemplary memory system (100) and a processor chip (202) configured to provide flexible provisioning of multi-layer memory according to some embodiments of the present disclosure. In FIG. 2, the processor chip (202) is wired directly to a first memory chip (104) (see, for example, wiring (204)) and configured to interact directly with the first memory chip.

[0056] In some embodiments, the processor chip (202) is an SoC or includes the same. The SoC described herein may be an integrated circuit or chip that integrates any two or more components of a computing device or may include the same. The two or more components may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), memory, an input / output port, and an auxiliary storage device. For example, the SoC described herein may also include a CPU, a GPU, a graphics and memory interface, a hard disk, a USB connection, random access memory, read-only memory, auxiliary storage, or a combination thereof on a single circuit die. Additionally, if the processor chip (202) is an SoC, the SoC includes at least a CPU and / or a GPU.

[0057] In the case of the SoC described herein, two or more components may be embedded on a single substrate or microchip (chip). Generally, the SoC differs from conventional motherboard-based architectures in that it integrates all its components into a single integrated circuit; the motherboard accommodates and connects separate or replaceable components. Because two or more components are integrated on a single substrate or chip, the SoC consumes less power and occupies a much smaller area than a multi-chip design with the same functionality. Accordingly, in some embodiments, the memory system described herein may be connected to or part of the SoC in mobile computing devices (such as smartphones), embedded systems, and Internet of Things devices.

[0058] The processor chip (202) may be configured to configure a cache (114) for the second memory chip (106). The processor chip (202) may also be configured to configure the location and size of the cache (114) by writing corresponding data to the first memory chip (104). The processor chip (202) may also be configured to configure cache policy parameters by writing corresponding data to the first memory chip (104).

[0059] Additionally, the processor chip (202) may be configured to configure a buffer (116) for the third memory chip (108) and / or a logical-physical mapping (118) for the third memory chip. The processor chip (202) may also be configured to configure the location and size of the buffer (116) by writing corresponding data to the first memory chip (104). The processor chip (202) may also be configured to configure the location and size of the logical-physical mapping (118) by writing corresponding data to the first memory chip (104).

[0060] FIG. 3 illustrates an exemplary memory system (100) and a memory controller chip (302) configured to provide flexible provisioning of a multi-layer memory according to some embodiments of the present disclosure. In FIG. 3, the memory controller chip (302) is wired directly to a first memory chip (104) (see, for example, wiring (304)) and configured to interact directly with the first memory chip.

[0061] In some embodiments, the memory controller chip (302) is an SoC or includes the same. Such an SoC may be an integrated circuit or chip that integrates any two or more components of a computing device or includes the same. The two or more components may include at least one of separate memory, input / output ports, and separate auxiliary storage. For example, the SoC may include a memory interface, a hard disk, a USB connection, random access memory, read-only memory, auxiliary storage, or a combination thereof on a single circuit die. Additionally, if the memory controller chip (302) is an SoC, the SoC includes at least a data processing unit.

[0062] The memory controller chip (302) may be configured to configure a cache (114) for the second memory chip (106). The memory controller chip (302) may also be configured to configure the location and size of the cache (114) by writing corresponding data to the first memory chip (104). The memory controller chip (302) may also be configured to configure cache policy parameters by writing corresponding data to the first memory chip (104).

[0063] Additionally, the memory controller chip (302) may be configured to configure a buffer (116) for the third memory chip (108) and / or a logical-physical mapping (118) for the third memory chip. The memory controller chip (302) may also be configured to configure the location and size of the buffer (116) by writing corresponding data to the first memory chip (104). The memory controller chip (302) may also be configured to configure the location and size of the logical-physical mapping (118) by writing corresponding data to the first memory chip (104).

[0064] FIG. 4 illustrates an exemplary memory system (400) configured to provide flexible provisioning of multi-layer memory in layers, each comprising multiple memory chips, according to some embodiment of the present disclosure. The memory system (400) comprises a string (402) of groups of memory chips. The string (402) of groups of memory chips comprises a first group of memory chips comprising a first type of memory chips (e.g., see memory chips (404a and 404b) which are chips of the same type). The string (402) of groups of memory chips comprises a second group of memory chips comprising the first type of memory chips or a second type of memory chips (e.g., see memory chips (406a and 406b) which are chips of the same type). A string (402) of groups of memory chips also includes memory chips of a first type, memory chips of a second type, or a third group of memory chips including memory chips of a third type (e.g., see memory chips (408a and 408b) which are chips of the same type). A memory chip of the first type may be a DRAM chip or may include one. A memory chip of the second type may be an NVRAM chip or may include one. A memory chip of the third type may be a flash memory chip or may include one.

[0065] Additionally, as illustrated in FIG. 4, the chips of the first group of memory chips are directly wired to the chips of the second group of memory chips through wiring (424) and are configured to directly interact with one or more chips of the second group of memory chips. Additionally, as illustrated in FIG. 4, the chips of the second group of memory chips are directly wired to the chips of the third group of memory chips through wiring (426) and are configured to directly interact with one or more chips of the third group of memory chips.

[0066] Additionally, as illustrated in FIG. 4, each chip of the first group of memory chips includes a cache for the second group of memory chips (e.g., see cache (414)). And each chip of the second group of memory chips includes a buffer (416) for the third group of memory chips as well as a logical-physical mapping (418) for the third group of memory chips.

[0067] In some embodiments, each chip of the third group of memory chips (e.g., see memory chips (408a and 408b)) may have the lowest memory bandwidth compared to other chips in the string (402) of memory chips. In some embodiments, each chip of the first group of memory chips (e.g., see memory chips (404a and 404b)) may have the highest memory bandwidth compared to other chips in the string (402) of memory chips. In these embodiments, each chip of the second group of memory chips (e.g., see memory chips (406a, 406b)) may have the next highest memory bandwidth compared to other chips in the string (402) of memory chips, and thus each chip of the first group of memory chips has the highest memory bandwidth and each chip of the third group of memory chips has the lowest memory bandwidth.

[0068] In some embodiments, the first group of memory chips (e.g., see memory chips (404a and 404b)) may include DRAM chips or NVRAM chips. In some embodiments, the second group of memory chips (e.g., see memory chips (406a and 406b)) may include DRAM chips or NVRAM chips. In some embodiments, the third group of memory chips (e.g., see memory chips (408a and 408b)) may include DRAM chips, NVRAM chips, or flash memory chips.

[0069] As illustrated in FIGS. 1 through 4, the present disclosure relates to the flexible provisioning of a string of memory chips (see, for example, the string of memory chips (102) illustrated in FIGS. 1 through 3 or the string of groups of memory chips (402) illustrated in FIG. 4). And, the flexible provisioning of the string of memory chips forms a memory (see, for example, the memory system (100) illustrated in FIG. 2 or the memory system (400) illustrated in FIG. 4).

[0070] The memory system disclosed herein, such as the memory system (100 or 400), may be a device itself or be within its own packaging.

[0071] In some embodiments, the memory system disclosed herein, such as the memory system (100 or 400), may be combined with a processor chip or SoC (e.g., see FIG. 2). When combined with a processor chip or SoC, the memory system and the processor chip or SoC may be part of a single device and / or may be combined into a single package.

[0072] Additionally, in some embodiments, the memory system disclosed herein, such as the memory system (100 or 400), may be combined with a memory controller chip (see, for example, FIG. 3). When combined with the memory controller chip, the memory system and the memory controller chip may be part of a single device and / or combined into a single package. Alternatively, each chip of the string of chips, or at least the first memory chip and the second memory chip, may include a respective memory controller that provides a function similar to the memory controller chip shown in FIG. 3.

[0073] In terms of a processor chip or SoC wired to memory (e.g., see processor chip (202) shown in FIG. 2) or memory controller chip (e.g., see memory controller chip (302) shown in FIG. 3), a string of memory chips in memory is no different from a single memory chip implementation; however, using flexible provisioning achieves the advantage of using a string of memory chips. In this embodiment, the processor chip or SoC—or memory controller chip—can be wired directly to the first memory chip (e.g., see the first memory chip (104)) of the string of memory chips (102) (e.g., see the wiring (204) shown in FIG. 2 or the wiring (304) shown in FIG. 3) and can interact with the first memory chip without recognizing the memory chips in the string downstream of the first memory chip (e.g., see the second memory chip (106) and the third memory chip (108) downstream of the first memory chip (104)).

[0074] In memory (e.g., see memory system (100 or 400)), a first memory chip (e.g., see one of the first memory chip (104) or memory chips (404a or 404b)) can be wired directly to a second memory chip (e.g., see one of the second memory chip (106) or memory chips (406a or 406b)) and interact with the second memory chip so that a processor chip, SoC, or memory controller chip (e.g., see processor chip (202) and memory controller chip (302)) can take advantage of the string of the first and second memory chips without the processor chip (202) and memory controller chip (302)) recognizing the second memory chip. And, the second memory chip (e.g., refer to one of the first memory chip (104) or memory chips (404a or 404b)) is wired directly to the third memory chip (e.g., refer to one of the third memory chip (108) or memory chips (408a or 408b)) so that the processor chip, SoC, or memory controller chip can obtain the benefits of a string of multiple memory chips (e.g., refer to a string of memory chips (102) or a string of groups of memory chips (402)) without the processor chip, SoC, or memory controller chip recognizing and interacting with the multiple memory chips downstream of the first memory chip. Additionally, in some embodiments, each chip of the string recognizes and interacts with the immediate upstream and downstream chips of the string without recognizing the chips higher upstream or downstream of the string.

[0075] As mentioned, with flexible provisioning, the advantage of using a string of memory chips with a memory hierarchy can be achieved. Thus, for example, in some embodiments, the first memory chip of the string (e.g., see first memory chip (104)) may be the chip having the highest memory bandwidth in the memory. The second memory chip of the string immediately downstream of the first chip (e.g., see second memory chip (106)) may be the chip having the next highest memory bandwidth in the memory (which may have other advantages such as being cheaper to manufacture than the first chip or being more stable or persistent than the first chip when storing data). The third memory chip of the string immediately downstream of the second chip (e.g., see third memory chip (108)) (or the final downstream chip of the string if there are three or more memory chips in the string) may have the lowest memory bandwidth. In these examples, the third memory chip (or the final downstream chip in other examples with three or more memory chips) may be the most cost-effective chip or the most stable or persistent chip for storing data.

[0076] In some embodiments, the first memory chip of the string may be a DRAM chip. In these embodiments, the second memory chip of the string immediately downstream of the first chip may be an NVRAM chip (e.g., a 3D XPoint memory chip). And, in such embodiments, the third memory chip of the string immediately downstream of the second chip may be a flash memory chip (e.g., a NAND flash memory chip).

[0077] As mentioned, to understand the flexible provisioning of a string of memory chips disclosed herein, examples often refer to a string of three memory chips (see, for example, the string of memory chips (102) shown in FIG. 1 to 3 and the string of groups of memory chips (402) shown in FIG. 4); however, a string of memory chips may include three or more memory chips or groups of three or more chips, each of which is a hierarchy of chips.

[0078] As mentioned, some embodiments of a string of memory chips may include a DRAM memory chip as the first chip of the string, an NVRAM chip as the second chip of the string, and a flash memory chip (e.g., a NAND flash memory chip) as the third chip of the string that can be used as a bulk memory chip in the string. In these embodiments and other embodiments having different arrangements of memory chip types, each of the chips in the string of memory chips is connected directly to a downstream and / or upstream chip via wiring (e.g., PCIe or SATA). Each of the connections between the chips in the string of memory chips may be connected sequentially via wiring, and the connections may be separated from each other (e.g., see wiring (124 and 126) and wiring (424 and 426). Additionally, each chip of the string of memory chips may include one or more sets of pins for connecting to the upstream chip and / or downstream chip of the string (e.g., see sets of pins (132, 134, 136, and 138) illustrated in FIG. 1). In some embodiments, each chip of the string of memory chips (e.g., see string of memory chips (102) or string of groups of memory chips (402)) may include a single IC enclosed within an IC package. In such embodiments, the IC package may include sets of pins (such as sets of pins (132, 134, 136, and 138)) at the boundaries of the package.

[0079] A first memory chip (e.g., a DRAM chip) of a string of memory chips for a processor chip or SoC may include a portion that can be configured by the processor chip or SoC, for example, as a cache for a second memory chip (e.g., an NVRAM chip) of the string (e.g., see cache for the second memory chip (114)). A portion of the memory units of the first memory chip may be used as cache memory for the second memory chip.

[0080] A second memory chip of a string of memory chips for a processor chip or SoC may include a portion that can be configured as a buffer (e.g., for a third memory chip (116)) for accessing a third memory chip of the string (e.g., a flash memory chip) directly by the first memory chip and indirectly by the processor chip or SoC. A portion of the memory units of the second memory chip may be used as a buffer for accessing the third memory chip. Additionally, the second memory chip may include a portion that can be configured as a table for logical-physical address mapping (a logical-physical table) or generally for logical-physical address mapping (e.g., for a logical-physical mapping (118)), directly by the first memory chip and indirectly by the processor chip or SoC. A portion of the memory units of the second memory chip may be used for logical-physical address mapping.

[0081] A third memory chip of a string of memory chips for a processor chip or SoC may include a controller (e.g., refer to controller (128)) capable of using the logical-physical address mapping of the second memory chip to manage the translation layer of the third memory chip (e.g., flash translation layer function) (e.g., refer to translation layer (130)). The translation layer of the third memory chip may include a logical-physical address mapping such as a copy or derivative of the logical-physical address mapping of the second memory chip.

[0082] Additionally, in some embodiments, a processor chip or SoC connected to memory (e.g., see processor chip (202)) can configure cache policy parameters of the first chip (e.g., write through vs. write back) as well as the buffer and logical-physical address mapping of the second memory chip and the location and size of the cache of the first memory chip by writing data to the first memory chip (e.g., see first memory chip (104)). And, the aforementioned configuration and settings by the processor chip or SoC may be delegated to a second data processing chip so that these operations are removed from the processor chip or SoC (e.g., see memory controller chip (302) illustrated in FIG. 3). For example, a memory having a string of memory chips may have a dedicated controller separate from the processor chip or SoC configured to provide and control the aforementioned configuration and settings for the memory (e.g., see memory controller chip (302)).

[0083] For the purposes of the present disclosure, it should be understood that a memory chip in a string of memory chips may be replaced with a group of similar memory chips so that the string includes a string of groups of similar chips (e.g., see string (402) of groups of memory chips illustrated in FIG. 4). In this example, each group of similar chips is a node of the string. Additionally, in some embodiments, the nodes of the string of memory chips may be composed of a combination of single-chip nodes and multi-chip nodes (not illustrated in the drawings). For example, in a string of memory chips, a first memory chip (e.g., a DRAM chip) may be replaced with a group of similar memory chips (e.g., a group of DRAM chips), a second memory chip (e.g., an NVRAM chip) may be replaced with a group of similar memory chips (e.g., a group of NVRAM chips), a third memory chip (e.g., a flash memory chip) may be replaced with a group of similar memory chips (e.g., a group of flash memory chips), or some combination thereof is possible.

[0084] FIG. 5 illustrates an exemplary portion of an exemplary computing device (500) according to some embodiment of the present disclosure. The computing device (500) may be communicably connected to another computing device via a computer network (502) as illustrated in FIG. 5. The computing device (500) includes at least a bus (504), a processor (506) (e.g., a CPU and / or processor chip (202) illustrated in FIG. 2), a main memory (508), a network interface (510), and a data storage system (512). The bus (504) communicably connects the processor (506), the main memory (508), the network interface (510), and the data storage system (512). A computing device (500) includes a computer system comprising at least a processor (506) communicating with each other via a bus (504) (which may include multiple buses and wiring), a main memory (508) (e.g., read-only memory (ROM), flash memory, DRAM, e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), NVRAM, SRAM, etc.), and a data storage system (512).

[0085] The main memory (508) may include the memory system (100) illustrated in FIG. 1. Additionally, the main memory (508) may include the memory system (400) illustrated in FIG. 4. In some embodiments, the data storage system (512) may include the memory system (100) illustrated in FIG. 1. And, the data storage system (512) may include the memory system (400) illustrated in FIG. 4.

[0086] The processor (506) may represent one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. The processor (506) may be the processor (202) shown in FIG. 2 or may include it. The processor (506) may be a composite instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a Vero log instruction word (VLIW) microprocessor, or a processor implementing another instruction set, or a processor implementing a combination of instruction sets. The processor (506) may also be one or more special-purpose processing devices, for example, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, a processor-in-memory (PIM), etc. The processor (506) may be configured to execute instructions for performing the operations and steps discussed herein. The processor (506) may further include a network interface device, such as a network interface (510), to communicate through one or more communication networks, such as a network (502).

[0087] The data storage system (512) may include a machine-readable storage medium (also referred to as a computer-readable medium) in which one or more sets of instructions or software that implement any one or more of the methodologies or functions described herein are stored. The instructions may also reside in the main memory (508) and / or the processor (506) during execution by the computer system, the main memory (508), and the processor (506) which also constitutes the machine-readable storage medium.

[0088] In exemplary embodiments, the memory, processor, and data storage portions are each depicted as a single portion, but each portion should be considered to comprise a single portion or multiple portions capable of storing instructions and performing respective operations. The term "machine-readable storage medium" is considered to include any medium capable of storing or encoding a set of instructions that is executed by a machine and causes the machine to perform any one or more of the methodologies of the present disclosure. Accordingly, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0089] Referring again to a memory chip having a data mover, FIG. 6 illustrates an exemplary system (600) comprising a memory chip (602) having an integrated data mover (608) according to some embodiment of the present disclosure. In FIG. 6, the memory chip (602) includes a first set of pins (604) configured so that the memory chip (602) can be coupled to a first microchip or device (624) through a first wiring (634). Also as illustrated, the first microchip or device (624) has a set of pins (605) configured so that the first microchip or device (624) can be coupled to the memory chip (602) through the first wiring (634). The memory chip (602) also includes a second set of pins (606) configured so that the memory chip (602) can be coupled to a second microchip or device (626) through a second wiring (636) separate from the first wiring (634). Also as illustrated, the second microchip or device (626) has a set of pins (607) configured to allow the second microchip or device (626) to be coupled to the memory chip (602) through the second wiring (636). The memory chip (602) also includes a data mover (608) configured to facilitate access to the second microchip or device (626) to read data from the second microchip or device (626) and write data to the second microchip or device (626) through the second set of pins (606).

[0090] Generally, the data mover (608) can combine data stored in the memory chip (602) to the second microchip or device (626) using various strategies. This can improve the write performance and durability of the second microchip or device (626). For example, sequential or block access to the memory chip is tens of times faster than random access to the memory chip. In some embodiments, data stored in the memory (610) portion of the memory chip (602) is accessible by or through the first microchip or device (624) via the first pin set (604). And, in such embodiments, the data mover (608) is configured to combine data stored in the memory (610) portion of the memory chip (602) by moving data in blocks to the second microchip or device (626). Thus, the write performance and durability of the second microchip or device (626) are improved.

[0091] Additionally, in these and other embodiments, the blocks may be of a coarser granularity than the data stored in the memory portion (610) of the memory chip (602). A block of a coarser granularity than the pre-blocked data of the memory chip (602), such as the data to be accessed by the first microchip or device, may reduce the frequency of data writing to the second microchip or device.

[0092] In some embodiments such as that illustrated in FIG. 6, data stored in the memory portion (610) of the memory chip (602) may be accessible by or through the first microchip or device (624) via the first set of pins (604). Additionally, when data stored in the memory portion (610) of the memory chip (602) is accessible through the first microchip or device (624), it is accessed by another memory chip or device or processor chip or device (this is not illustrated in FIG. 6 but is illustrated to some extent in FIG. 2 and 3 where the second memory chip (106) acts as the memory chip (602). And, the first microchip or device (624) can not only write data to the memory chip (602) but also read data from the memory chip (602).

[0093] In some embodiments such as that illustrated in FIG. 6, data stored in the portion of memory (630) of the second microchip or device (626) may be accessible by or through the memory chip (602) via the second set of pins (606). Additionally, if data stored in the portion of memory (630) of the second microchip or device (626) is accessible through the memory chip (602), it is accessed by another memory chip or device or processor chip or device (such as the first microchip or device (624)). Furthermore, the memory chip (602) may not only read data from the second microchip or device (626) but also write data to the second microchip or device (626).

[0094] In some embodiments as illustrated in FIG. 6, the data mover (608) is configured to buffer the movement of changes to data stored in a portion (610) of memory of the memory chip (602). Additionally, the data mover (608) is configured to transmit a write request to a second microchip or device (626) in an appropriate size due to the buffering by the data mover (608).

[0095] When the writing to the second microchip or device (626) is of an appropriate size due to buffering by the data mover (608), the second microchip or device can erase blocks according to the writing and program blocks of the second microchip or device without minimal or additional processing in the second microchip or device. This is one exemplary method by which the data mover (608) integrated in the memory chip (602) can improve the writing performance and durability of the second microchip or device. Furthermore, due to buffering by the data mover (608) and when frequent and / or random changes are made to the data of a portion (602) of the memory chip (such as the data of a portion (610) of memory accessible by the first microchip or device), the second microchip or device (626) does not need to be frequently erased and reprogrammed in a manner corresponding to the changes occurring in the memory chip (602).

[0096] Buffering by the data mover (608) is much more advantageous when the second microchip or device (626) is a flash memory chip, because buffering can eliminate or at least limit the effect of write amplification occurring in the flash memory. Write amplification can be reduced or eliminated by buffering, because, through buffering, the write request transmitted by the memory chip (602) can be modified to an appropriate size or granularity expected by the receiving flash memory chip. Thus, the flash memory chip can erase blocks and program blocks according to the write request without the possibility of write duplication, thereby avoiding additional processing in the second microchip or device (626).

[0097] Additionally, the data mover (608) may be configured to bundle the changed addresses in a change to the data stored in the memory portion (610) of the memory chip (602). And, the data mover (608) may be configured to write the bundled changed addresses to another portion of the memory chip (602) to be moved to the second microchip or device (626) via a write request to the second microchip or device (626). Bundling by the data mover (608) can improve buffering by the data mover and the transmission of the write request following the buffering, because the bundling of the changed addresses can be controlled by the data mover to correspond to an appropriate size or granularity expected by the receiving second microchip or device (626).

[0098] In some embodiments such as that illustrated in FIG. 6, the memory chip (602) includes a logical-physical mapping (612) to a second microchip or device (626) configured to use bundled changed addresses as inputs.

[0099] FIG. 7 illustrates an exemplary system (700) comprising a microchip or device having a memory chip (602) illustrated in FIG. 6 according to some embodiment of the present disclosure, as well as a logical-physical mapping (e.g., see logical-physical mapping (712)) for receiving data transmitted from a data carrier and mapping the received data. The system (700) is similar to the system (600) except that the logical-physical mapping (712) for the second microchip or device (626) in the system (700) is provided on the second microchip or device (626). This is instead of providing the logical-physical mapping for the second microchip or device on the memory chip (602) (e.g., see logical-physical mapping (612) illustrated in FIG. 6).

[0100] In an embodiment similar to the system (700), the second microchip or device (626) includes a logical-physical mapping (712) for itself. The logical-physical mapping (712) is configured to use the bundled modified addresses as input when the bundled modified addresses are transmitted from the data mover (608) of the memory chip (602) to the second microchip or device (626) in a write request. In other words, when the bundled modified addresses are received by the second microchip or device (626) from the data mover (608) of the memory chip (602) in a write request to the second microchip or device (626), the logical-physical mapping (712) is configured to use the bundled modified addresses as input.

[0101] FIG. 8 illustrates an exemplary system (800) comprising a memory chip (602) illustrated in FIG. 6, which is shown having encryption and authentication circuitry (e.g., see encryption engine (802) and gatekeeper (804)) according to some embodiments of the present disclosure. As illustrated in FIG. 8, in some embodiments, the memory chip (602) includes an encryption engine (802) configured to protect data to be moved to a second microchip or device (626) for long-term storage. Also, as illustrated, in these embodiments, the memory chip (602) includes a gatekeeper (804) configured to provide an authentication process for accessing secure data stored in the second microchip or device (626). Additionally, the gatekeeper (804) may be configured to decrypt the secure data according to the authentication process. In some other embodiments, the encryption engine may be hosted on another chip or device instead of being hosted on the memory chip (602).

[0102] FIGS. 7 and 8 also illustrate other components exemplified in FIG. 6. For example, FIGS. 7 and 8 illustrate a memory chip (602) comprising a first set of pins (604) configured to allow the memory chip (602) to be coupled to a first microchip or device (624) via a first wiring (634). Also, as illustrated in FIGS. 7 and 8, the first microchip or device (624) has a set of pins (605) configured to allow the first microchip or device (624) to be coupled to the memory chip (602) via the first wiring (634). Also, as illustrated in FIGS. 7 and 8, the memory chip (602) also includes a second set of pins (606) configured to allow the memory chip (602) to be coupled to a second microchip or device (626) via a second wiring (636) separate from the first wiring (634). Also as illustrated, the second microchip or device (626) has a set of pins (607) configured to allow the second microchip or device (626) to be coupled to the memory chip (602) through the second wiring (636). The memory chip (602) also includes a data mover (608) configured to facilitate access to the second microchip or device (626) to read data from the second microchip or device (626) and write data to the second microchip or device (626) through the second set of pins (606).

[0103] In relation to the system illustrated in FIGS. 6 through 8, the memory chip (602) may be an NVRAM chip, and in this embodiment, the memory chip (602) includes a plurality of NVRAM cells. In these examples, the plurality of NVRAM cells may be or include a plurality of 3D XPoint memory cells. Alternatively, the memory chip (602) may be a dynamic DRAM chip, and in this embodiment, the memory chip (602) includes a plurality of DRAM cells. Additionally, the memory chip (602) may be a flash memory chip, and in this embodiment, the memory chip (602) includes a plurality of flash memory cells. In this embodiment, the plurality of flash memory cells may be or include a plurality of NAND-type flash memory cells.

[0104] The second microchip or device (626) may be another memory chip or memory device. In some embodiments, for example, the second microchip or device (626) is a DRAM chip. In some embodiments, for example, the second microchip or device (626) is an NVRAM chip. In some embodiments, for example, the second microchip or device (626) is a flash memory chip (e.g., a NAND flash memory chip).

[0105] Some embodiments may include a system having an intermediate memory chip (e.g., see memory chip (602) illustrated in FIG. 6), a first memory chip (e.g., see first microchip or device (624)), and a second memory chip (e.g., see second microchip or device (626)). And, in such embodiments, the intermediate memory chip includes a first set of pins (e.g., see first set of pins (604)) configured to allow the intermediate memory chip to be coupled to the first memory chip through a first wiring (e.g., see wiring (634)). The intermediate memory chip may also include a second set of pins (e.g., see second set of pins (606)) configured to allow the intermediate memory chip to be coupled to the second memory chip through a second wiring (e.g., see wiring (636)) that is separate from the first wiring. And, the intermediate memory chip may include a data mover (e.g., see data mover (608)) configured to facilitate access to the second memory chip to read data from the second memory chip through a second set of pins and to write data to the second memory chip.

[0106] In such an embodiment, the intermediate memory chip may be an NVRAM chip, and the NVRAM chip includes a plurality of NVRAM cells. Alternatively, the intermediate memory chip may be a DRAM chip, and the DRAM chip includes a plurality of DRAM cells. In these examples, the plurality of NVRAM cells may be or include a plurality of 3D XPoint memory cells.

[0107] Additionally, in this embodiment, the second memory chip may be a flash memory chip, and the flash memory chip includes a plurality of flash memory cells. In this embodiment, the plurality of flash memory cells may be or include a plurality of NAND-type flash memory cells. Alternatively, the second memory chip may be an NVRAM chip, and the NVRAM chip includes a plurality of NVRAM cells. In these examples, the plurality of NVRAM cells may be or include a plurality of 3D XPoint memory cells. Additionally, the second memory chip may be a DRAM chip, and the DRAM chip includes a plurality of DRAM cells.

[0108] Additionally, in this embodiment, the first memory chip may be a DRAM chip, and the DRAM chip includes a plurality of DRAM cells. Alternatively, the first memory chip may be an NVRAM chip, and the NVRAM chip includes a plurality of NVRAM cells. In these examples, the plurality of NVRAM cells may be or include a plurality of 3D XPoint memory cells.

[0109] Some embodiments may include a system having an intermediate memory chip (e.g., see memory chip (602) illustrated in FIG. 6), a second memory chip (e.g., see second microchip or device (626)), and a processor chip such as an SoC (e.g., see first microchip or device (624)). In these embodiments, the intermediate memory chip includes a first set of pins (e.g., see set of first pins (604)) configured to allow the intermediate memory chip to be coupled to the processor chip through a first wiring (e.g., see wiring (634)). Additionally, the intermediate memory chip may include a second set of pins (e.g., see set of pins (606)) configured to allow the intermediate memory chip to be coupled to the second memory chip through a second wiring (e.g., see wiring (636)) that is separate from the first wiring. And, the intermediate memory chip may include a data mover (e.g., see data mover (608)) configured to facilitate access to the second memory chip to read data from the second memory chip and write data to the second memory chip through the second pin set and the second wiring.

[0110] In some embodiments, one or more instances of the memory chip (602) (such as other instances of the memory chip (602) shown in FIGS. 6 through 8) may be used as one or more memory chips in the flexible provisioning of the string (102) of memory chips shown in FIGS. 1 through 3. Additionally, one or more instances of the memory chip (602) may be used as one or more memory chips in the flexible provisioning of the string (402) of memory chips shown in FIG. 4.

[0111] Additionally, a system having an intermediate memory chip (e.g., see memory chip (602) illustrated in FIG. 6), a first memory chip (e.g., see first microchip or device (624)), and a second memory chip (e.g., see second microchip or device (626)) may be included in a string (102) of memory chips illustrated in FIG. 1 to 3. For example, the memory chip (602) may be or include the second memory chip (106), the first microchip or device (624) may be or include the first memory chip (104), and the second microchip or device (626) may be or include the third memory chip (108).

[0112] In some embodiments, the memory chip (602) may be or include the first memory chip (104) of the string of memory chips (102). In such embodiments, for example, the first microchip or device (624) may be or include the processor chip (202) shown in FIG. 2 or the memory controller chip (302) shown in FIG. 3. Also, in such embodiments, the second microchip or device (626) may be or include the second memory chip (106) of the string of memory chips (102).

[0113] In some embodiments, any one or more of the systems (600, 700, 800) may be included in the main memory (508) and / or data storage system (512) illustrated in FIG. 5. In these and other embodiments, the first microchip or device (624) may be a processor (506), a part thereof, or include thereof.

[0114] Similar to the memory chip (602), any other memory chip among the memory chips described herein (e.g., see memory chips (104, 106 and 108)) may include an encryption engine and / or an authentication gatekeeper for protecting data transferred to or through the memory chip (e.g., see encryption engine (802) and gatekeeper (804) illustrated in FIG. 8). Additionally, similar to the memory chip (602), any other chip among the memory chips described herein (e.g., see memory chips (104, 106 and 108)) may include a data mover such as a data mover (608).

[0115] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications may be made without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. Accordingly, the present invention and drawings should be conceived in an exemplary sense rather than a restrictive one.

Claims

Claim 1 A memory chip comprising: a first set of pins configured such that the memory chip can be coupled to a first microchip or device through a first wiring; a second set of pins configured such that the memory chip can be coupled to a second microchip or device through a second wiring separate from the first wiring; and a data mover configured such that the second microchip or device can be accessed through the second set of pins to read data from the second microchip or device and write data to the second microchip or device. Claim 2 In claim 1, the data stored in the portion of the memory chip is accessible by or through the first microchip or device via the first set of pins, the memory chip. Claim 3 In paragraph 2, the memory chip is configured such that the data mover combines the data stored in the portion of the memory chip by moving the data in blocks to the second microchip or device. Claim 4 In paragraph 3, the block is a memory chip having a coarser granularity than the data stored in the portion of the memory chip. Claim 5 In paragraph 4, the data mover is configured to: buffer a change to the data stored in the portion of the memory chip; and send a write request to the second microchip or device with a size expected by the second microchip or device due to the buffering by the data mover. Claim 6 In paragraph 5, the data mover is configured to: bundle the changed addresses of the changes to the data stored in the said portion of the memory chip; and write the bundled changed addresses to another portion of the memory chip to be moved to the second microchip or device through a write request to the second microchip or device. Claim 7 In claim 6, a memory chip comprising a logical-to-physical mapping to the second microchip or device configured to use the bundled modified addresses as inputs. Claim 8 In claim 6, the memory chip, wherein the second microchip or device itself includes a logical-physical mapping configured to use the bundled modified addresses as input when the bundled modified addresses are transmitted as a write request to the second microchip or device. Claim 9 In claim 1, the memory chip is a non-volatile random access memory (NVRAM) chip, and the memory chip comprises a plurality of NVRAM cells. Claim 10 In claim 9, the memory chip, wherein the plurality of NVRAM cells are a plurality of 3D XPoint memory cells. Claim 11 In claim 1, the memory chip is a dynamic random access memory (DRAM) chip, and the memory chip comprises a plurality of DRAM cells. Claim 12 In claim 1, the memory chip is a flash memory chip, and the memory chip comprises a plurality of flash memory cells. Claim 13 In Clause 12, the memory chip, wherein the plurality of flash memory cells are a plurality of NAND-type flash memory cells. Claim 14 A memory chip according to claim 1, comprising an encryption engine configured to secure data to be transferred to the second microchip or device for long-term storage. Claim 15 In claim 14, a memory chip comprising a gatekeeper, wherein the gatekeeper: provides an authentication process for accessing the security data stored in the second microchip or device; and is configured to decrypt the security data according to the authentication process. Claim 16 A system comprising: an intermediate memory chip; a first memory chip; and a second memory chip, wherein the intermediate memory chip comprises: a first pin set configured such that the intermediate memory chip can be coupled to the first memory chip through a first wiring; a second pin set configured such that the intermediate memory chip can be coupled to the second memory chip through a second wiring separate from the first wiring; and a data mover configured such that the second memory chip can be accessed through the second pin set in order to read data from the second memory chip and write data to the second memory chip. Claim 17 In paragraph 16, the intermediate memory chip is a non-volatile random access memory (NVRAM) chip, and the NVRAM chip comprises a plurality of NVRAM cells, in a system. Claim 18 In claim 17, the second memory chip is a flash memory chip, and the flash memory chip comprises a plurality of flash memory cells, in a system. Claim 19 In paragraph 17, the first memory chip is a dynamic random access memory (DRAM) chip, and the DRAM chip comprises a plurality of DRAM cells, in a system. Claim 20 A system comprising: an intermediate memory chip; a second memory chip; and a processor chip, wherein the intermediate memory chip comprises: a first set of pins configured such that the intermediate memory chip can be coupled to the processor chip through a first wiring; a second set of pins configured such that the intermediate memory chip can be coupled to the second memory chip through a second wiring separate from the first wiring; and a data mover configured such that the second memory chip can be accessed through the second set of pins and the second wiring in order to read data from the second memory chip and write data to the second memory chip.

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