Single inductor-multiple output DC-DC converter and control method thereof

Abstract

The present invention relates to a DC / DC converter configured to provide multiple output voltages from an input voltage using a single inductor, and discloses a single inductor-multiple output DC / DC converter and a control method thereof that calculates a sum signal by summing individual error signals of each of the multiple output voltages and can precisely control various outputs using a single inductor through the sum signal and a single error amplifier.

Description

Technology Field

[0001] The present invention relates to a single inductor-multiple output DC-DC converter and a control method thereof, and more specifically, to a single inductor-multiple output DC-DC converter and a control method thereof capable of precisely controlling various outputs with a single inductor through a single error amplifier. Background Technology

[0003] Recently, mobile devices, including wearables, are evolving in the direction of reducing external components to lower material costs and reduce solution size in order to gain competitiveness.

[0004] In particular, for general power management integrated circuits (PMICs) applied to power circuits, one inductor is required for each output, and inductors are the largest and most expensive among the peripheral components of a PMIC.

[0005] As an alternative, there has recently been growing interest in Single Inductor Multiple Output (SIMO), which can produce various outputs from a single inductor. However, in the case of SIMO, since multiple outputs must be controlled simultaneously, there is a problem that complex and sophisticated energy splitting control is required to control which output the inductor current is connected to and when.

[0006] For example, conventional SIMO converters have complex compensation systems as they include an error amplifier for each output, and they have complex control structures such as transferring energy through time division or controlling based on digital methods.

[0007] Accordingly, there is an urgent need for a new structure and control method for a SIMO converter that can precisely control multiple outputs with only one error amplifier. Prior art literature

[0008] Published Patent Application No. 2013-0067344 (Published June 24, 2013) The problem to be solved

[0009] Accordingly, the present invention has been devised to solve the problems of the prior art, and aims to provide a single inductor-multiple output DC-DC converter and a control method thereof that can precisely control various outputs with a single inductor through a single error amplifier.

[0011] The technical problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the present invention belongs from the description below. means of solving the problem

[0013] To achieve the above objective, a single inductor-multiple output DC / DC converter according to the present invention comprises: an error summing unit (wherein N is a natural number greater than or equal to 2) that sums individual error signals between a first to Nth feedback signal fed back from a first to Nth output voltage and a corresponding first to Nth error reference value to output a summing signal; a summing error amplifier that amplifies the error between the summing signal and the summing reference value to output a summing error signal; a comparator that receives the summing error signal, a ramp signal having a switching frequency, and a first to N-1st PWM feedback signal fed back from the first to N-1st output voltage and outputs a first to Nth PWM control signal; and an output switch unit configured to include a plurality of switch elements and a single inductor. and is characterized by including a logic gate driving unit that generates a plurality of gate driving signals to control the switching of the plurality of switch elements from the first to Nth PWM control signals and provides them to the output switch unit.

[0014] The above error summing unit includes N individual error amplifiers that each output individual error signals corresponding to error values ​​between first to N feedback signals fed back from first to N output voltages and corresponding first to N error reference values, and can sum the individual error signals output from each of the N individual error amplifiers to output the summing signal.

[0015] The above comparator may include a first comparator that outputs the first PWM control signal by comparing the summing error signal and the ramp signal; and second to Nth comparators that output the second to Nth PWM control signals respectively by comparing the first to N-1 PWM feedback signals with the corresponding first to N-1 target reference values.

[0016] The first PWM control signal may control the build-up section of the inductor current flowing through the inductor, and each of the second to Nth PWM control signals may control the power section in which the inductor current conducts toward the corresponding first to N-1st output voltage side.

[0017] The output switch unit may include one or more build-up switch elements that are turned on in the build-up section among the plurality of switch elements; and N output switch elements that conduct the inductor current to the first to Nth output voltage side in the power section among the plurality of switch elements.

[0018] At least a portion of the above-mentioned build-up switch element can be turned on during the above-mentioned power interval.

[0019] The logic gate driving unit may be configured to output a plurality of gate driving signals that control the switching of the build-up switch element and the output switch element by performing a logical operation on the first to Nth PWM control signals, wherein the plurality of gate driving signals may be configured to turn on one or more build-up switch elements in a build-up section controlled by the first PWM control signal, turn on N-1 output switch elements corresponding to the first to N-1 output voltage side in a part of the power section by each of the second to Nth PWM control signals, and turn on an output switch element corresponding to the Nth output voltage side in the remaining section of the power section.

[0020] The first PWM control signal above can determine the start and end times of the pulse width according to the comparison result of the summed error signal and the ramp signal.

[0021] The logic gate driving unit may generate the plurality of gate driving signals by performing a logical operation on the first to Nth PWM control signals such that the turn-on period of the output switch element corresponding to the first output voltage side is initiated at the time of termination of the first PWM control signal and terminates at the time when the first PWM feedback signal reaches the first target reference value, the turn-on period of the output switch element corresponding to the Nth output voltage side is initiated at the time of termination of the turn-on period of the output switch element corresponding to the N-1 output voltage side and terminates at the time of initiation of the first PWM control signal, and when N is 3 or greater, the turn-on period of the output switch element corresponding to the k-1 output voltage side is initiated at the time of termination of the turn-on period of the output switch element corresponding to the k-1 output voltage side and terminates at the time when the k-th PWM feedback signal reaches the k-th target reference value (where k is a natural number of 2, …, N-1).

[0022] The first to N-1st feedback signals and the first to N-1st PWM feedback signals are identical to each other, and the first to N-1st error reference values ​​and the first to N-1st target reference values ​​may be identical to each other.

[0023] To achieve the above objective, a control method for a single inductor-multiple output DC / DC converter according to the present invention comprises: (a) a step of summing individual error signals between a first to Nth feedback signal fed back from a first to Nth output voltage and a corresponding first to Nth error reference value to output a summing signal (wherein N is a natural number greater than or equal to 2); (b) a step of amplifying the error between the summing signal and the summing reference value to output a summing error signal; (c) a step of receiving the summing error signal, a ramp signal having a switching frequency, and a first to N-1st PWM feedback signal fed back from the first to N-1st output voltage and outputting a first to Nth PWM control signal; and (d) a step of configuring an output switch section including a plurality of switch elements and a single inductor. and (e) a step of generating a plurality of gate driving signals to control the switching of the plurality of switch elements from the first to Nth PWM control signals and providing them to the output switch unit.

[0024] The above step (a) may be to sum individual error signals that are output in correspondence with error values ​​between the first to Nth feedback signals that are fed back from the first to Nth output voltages and the corresponding first to Nth error reference values, and output the summed signal.

[0025] The above step (c) may include: (c-1) a step of outputting the first PWM control signal by comparing the summing error signal and the ramp signal; and (c-2) a step of outputting the second to Nth PWM control signals by comparing the first to N-1 PWM feedback signals with the corresponding first to N-1 target reference values.

[0026] The first PWM control signal controls the build-up section of the inductor current flowing through the inductor, and each of the second to Nth PWM control signals can control the power section in which the inductor current conducts toward the corresponding first to N-1st output voltage side.

[0027] The output switch unit may include one or more build-up switch elements that are turned on in the build-up section among the plurality of switch elements; and N output switch elements that conduct the inductor current to the first to Nth output voltage side in the power section among the plurality of switch elements.

[0028] The above step (e) may be configured to output a plurality of gate driving signals that control the switching of the build-up switch element and the output switch element by performing a logical operation on the first to Nth PWM control signals, wherein (e-1) a step of turning on one or more build-up switch elements in a build-up section controlled by the first PWM control signal; (e-2) a step of turning on N-1 output switch elements corresponding to the first to N-1 output voltage side in a part section of the power section by each of the second to Nth PWM control signals; and (e-3) a step of turning on an output switch element corresponding to the Nth output voltage side in the remaining section of the power section.

[0029] The first PWM control signal above may determine the start and end times of the pulse width according to the comparison result of the summing error signal and the ramp signal.

[0030] In the above step (e), the turn-on period of the output switch element corresponding to the first output voltage side in the above step (e-2) is initiated at the time of termination of the first PWM control signal and terminated at the time when the first PWM feedback signal reaches the first target reference value, and in the above step (e-3), the turn-on period of the output switch element corresponding to the Nth output voltage side is initiated at the time of termination of the turn-on period of the output switch element corresponding to the N-1 output voltage side and terminated at the time of initiation of the first PWM control signal, and when N is 3 or greater in the above step (e-2), the turn-on period of the output switch element corresponding to the k-th output voltage side is initiated at the time of termination of the turn-on period of the output switch element corresponding to the k-1 output voltage side and terminated at the time when the k-th PWM feedback signal reaches the k-th target reference value (where k is a natural number of 2, …, N-1), and the plurality of gate driving signals are generated by performing a logical operation on the first to Nth PWM control signals. Effects of the invention

[0032] The single inductor-multiple output DC-DC converter and the control method thereof according to the present invention have the effect of precisely controlling various outputs with a single inductor through a single error amplifier. Brief explanation of the drawing

[0034] FIG. 1 is a circuit diagram showing a SIMO DC-DC converter according to the present invention. FIG. 2 is a circuit diagram showing a SIMO DC-DC converter having two outputs according to one embodiment of the present invention. FIG. 3 is an operation waveform diagram of the SIMO DC-DC converter of FIG. 2 according to one embodiment of the present invention. FIG. 4 is a circuit diagram showing a SIMO DC-DC converter having two outputs according to another embodiment of the present invention. FIG. 5 is an operation waveform diagram of the SIMO DC-DC converter of FIG. 4 according to another embodiment of the present invention. Specific details for implementing the invention

[0035] A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. The following detailed description is merely illustrative and illustrates a preferred embodiment of the present invention.

[0037] FIG. 1 is a circuit diagram showing a SIMO DC-DC converter according to the present invention.

[0038] Referring to FIG. 1, the SIMO DC-DC converter according to the present invention is a single inductor-multiple output DC / DC converter configured to provide a plurality of output voltages from an input voltage using a single inductor, comprising: an error summing unit (100) that sums individual error signals between first to N feedback signals (FB_VO1~FB_VON) fed back from first to N output voltages (VO1~VON) and corresponding first to N error reference values ​​(REF_VO1~REF_VON) to output a summing signal (VSUM); a summing error amplifier (200) that amplifies the error between the summing signal (VSUM) and the summing reference value (VREF) to output a summing error signal (VERR); and first to N-1 PWMs fed back from first to N-1 output voltages (VO1~VON-1) that compare the summing error signal (VERR) with a ramp signal (VRAMP) having a predetermined switching frequency. It may be configured to include a comparator (300) that outputs first to Nth PWM control signals (PWM1 to PWMN) by comparing feedback signals (VO1_FB~VON-1_FB) with target reference values.

[0039] In addition, the present invention is characterized by including a logic gate driving unit (400) that generates a plurality of gate driving signals (GD_S1~GD_SX) by performing a logic operation on the first to Nth PWM control signals (PWM1~PWMN), and an output switch unit (500) configured to include a plurality of switch elements and one inductor, wherein the switching of the plurality of switch elements is controlled according to the plurality of gate driving signals (GD_S1~GD_SX) provided by the logic gate driving unit (400).

[0040] At this time, since the present invention provides two or more multiple outputs, N here may be a natural number greater than or equal to 2.

[0041] The output switch unit (500) is configured to include a plurality of switch elements and one inductor, although not shown in the drawing. Among the plurality of switch elements, it may include one or more build-up switch elements that turn on during the build-up section of the inductor current, and N output switch elements that conduct the inductor current to the first to Nth output voltages (VO1~VON) in the power section that transmits the inductor current to the output voltage side.

[0042] The output switch section (500) can be implemented in various structures depending on the number of output voltages or polarity specifications.

[0043] The error summing unit (100) outputs a summing signal (VSUM) by summing a plurality of individual error signals representing error information between the first to Nth feedback signals (FB_VO1~FB_VON) having information of the first to Nth output voltages (VO1~VON) and the first to Nth error reference values ​​(REF_VO1~REF_VON) corresponding to each of the respective.

[0044] Accordingly, the error summing unit (100) is configured to include N individual error amplifiers (110) that output individual error signals corresponding to error values ​​between the first to Nth feedback signals (FB_VO1~FB_VON) fed back from the first to Nth output voltages (VO1~VON) and the corresponding first to Nth error reference values ​​(REF_VO1~REF_VON), and thus can be configured to sum the individual error signals output from each of the N individual error amplifiers (110) and output a summing signal (VSUM).

[0045] Accordingly, since the sum signal (VSUM) represents the total error value of multiple output voltages, it can be used as basic information to control the amount of inductor current built up in the inductor.

[0046] The summing error amplifier (200) compares the summing signal (VSUM) with the summing reference value (VREF) and outputs a summing error signal (VERR) that amplifies the error. Using this configuration, the amount of the controlled summing error signal (VERR) and the amount of the inductor current built up accordingly can be set to a desired level.

[0047] The comparison unit (300) receives a summing error signal (VERR), a ramp signal (VRAMP), first to N-1 PWM feedback signals (VO1_FB~VON-1_FB) and wooden bridge reference values ​​and outputs first to N PWM control signals (PWM1~PWMN).

[0048] The ramp signal (VRAMP) is a signal in the form of a triangular wave or a sawtooth wave having a predetermined frequency, generated through an inductor current or a separate internal generation circuit (not shown in the drawing), and the frequency may determine the switching frequency of the SIMO DC-DC converter of the present invention.

[0049] Referring to FIG. 1, the comparator (300) may include a first comparator (310) that outputs a first PWM control signal (PWM1) by comparing a summing error signal (VERR) and a ramp signal (VRAMP), and second to Nth comparators (320, 330) that output second to Nth PWM control signals (PWM2 to PWMN) respectively by comparing first to N-1 PWM feedback signals (VO1_FB~VON-1_FB) and corresponding first to N-1 target reference values ​​(TG1_REF~TGN-1_REF).

[0050] Here, the first PWM control signal (PWM1) controls the build-up period of the inductor current flowing through the inductor to increase when the summing error signal (VERR) is large and to decrease when the summing error signal (VERR) is small, thereby enabling the inductor current to be built up to the total energy required by the first to Nth output voltages (VO1~VON).

[0051] That is, the first PWM control signal (PWM1) can determine the start and end times of the pulse width that determines the build-up interval based on the comparison result of the summing error signal (VERR) and the ramp signal (VRAMP).

[0052] Additionally, each of the second to Nth PWM control signals (PWM2 to PWMN) may control the power interval in which the inductor current conducts toward the corresponding first to N-1st output voltages (VO1 to VON-1).

[0053] The logic gate driving unit (400) may be configured to output a plurality of gate driving signals (GD_S1~GD_SX) that control the switching of the build-up switch element and the output switch element of the output switch unit (500) by performing a logic operation on the first to Nth PWM control signals (PWM1~PWMN).

[0054] For example, a plurality of gate driving signals (GD_S1~GD_SX) can be generated to turn on one or more build-up switch elements in a build-up section controlled by a first PWM control signal (PWM1) to build up a predetermined inductor current in an inductor, turn on N-1 output switch elements corresponding to the first to N-1 output voltages (VO1~VON-1) in a part of the power section by each of the second to Nth PWM control signals (PWM2~PWMN) to distribute and transmit the inductor current built up to the first to N-1 output voltages (VO1~VON-1), and turn on output switch elements corresponding to the Nth output voltage (VON) in the remaining section of the power section.

[0055] For a power section that transmits inductor current to the first to Nth output voltages (VO1 to VON), the turn-on section of the output switch element corresponding to the first output voltage (VO1) side is initiated at the end of the first PWM control signal (PWM1) that controls the build-up section and is terminated at the time when the first PWM feedback signal (VO1_FB) reaches the first target reference value (TG1_REF), and the turn-on section of the output switch element corresponding to the Nth output voltage (VON) side is initiated at the end of the turn-on section of the output switch element corresponding to the N-1st output voltage (VON-1) side and is terminated at the start of the first PWM control signal (PWM1) that starts the current build-up. The logic gate driving unit (400) may generate a plurality of gate driving signals (GD_S1 to GD_SX) by performing a logical operation on the first to Nth PWM control signals (PWM1 to PWMN).

[0056] Furthermore, in the case of multiple outputs where N is 3 or greater, the logic gate driver (400) may generate a plurality of gate driving signals (GD_S1~GD_SX) by performing a logical operation on the first to Nth PWM control signals (PWM1~PWMN), such that the turn-on period of the output switch element corresponding to the k-th output voltage (VOk) side is initiated at the end of the turn-on period of the output switch element corresponding to the k-1st output voltage (VOk-1) side, and terminates at the time when the k-th PWM feedback signal (VOk_FB) reaches the k-th target reference value (TGk_REF) (where k is a natural number of 2, …, N-1).

[0057] The build-up switch element may be configured to be turned on only during the build-up period and turned off during the remaining period, but depending on the configuration of the output switch section (500), the build-up switch element may be configured to be turned on in at least part of the power section and turned off in the remaining part.

[0058] Additionally, although the first to N-1 feedback signals and first to N-1 error reference values ​​input to the error summing unit (100) and the first to N-1 PWM feedback signals (VO1_FB~VON-1_FB) and first to N-1 target reference values ​​(TG1_REF~TGN-1_REF) input to the comparison unit (300) are described with different names in the above description, according to the embodiment, the first to N-1 feedback signals are identical to the first to N-1 PWM feedback signals (VO1_FB~VON-1_FB), and the first to N-1 error reference values ​​and the first to N-1 target reference values ​​(TG1_REF~TGN-1_REF) are also configured to be identical to each other.

[0059] Hereinafter, the operation of an embodiment of the SIMO DC-DC converter of the present invention having two output voltages will be described.

[0061] FIG. 2 is a circuit diagram showing a SIMO DC-DC converter having two outputs according to one embodiment of the present invention, and FIG. 3 is an operation waveform diagram of the SIMO DC-DC converter of FIG. 2 according to one embodiment of the present invention.

[0062] The SIMO DC-DC converter of FIG. 2 is configured to provide first and second output voltages (VO1, VO2) (Fig. 2(a)), and may be composed of first to fourth switch elements (Q1~Q4) and an inductor (L) such that the first output voltage (VO1) is a positive voltage and the second output voltage (VO2) is a negative voltage (Fig. 2(b)).

[0063] Referring to FIG. 2(b), the first to fourth switch elements (Q1 to Q4) may be configured in a full-bridge structure to form switching terminals (LX1, LX2), and an inductor (L) may be connected to the switching terminals (LX1, LX2).

[0064] Here, the first and fourth switch elements (Q1, Q4) are build-up switch elements for building up the inductor current (IL), the second switch element (Q2) is turned on to conduct the inductor current (IL) to the first output voltage (VO1) side in the power section, and the third switch element (Q3) can be controlled to turn on to conduct the inductor current (IL) to the second output voltage (VO2) side in the power section.

[0065] According to FIG. 3, the first time interval (T1) corresponds to a build-up interval, and the start (SET) and end times of the first PWM control signal (PWM1) are determined based on the comparison result of the summing error signal (VERR) and the ramp signal (VRAMP), and the build-up interval is determined with a pulse width having the first time interval (T1).

[0066] During the first time interval (T1), the first and fourth switch elements (Q1, Q4) corresponding to the build-up switch elements are turned on so that the inductor current (IL) is built up, and when the build-up period of the first time interval (T1) ends, the power interval is started.

[0067] The power interval corresponds to the second and third time intervals (T2, T3), and the second and third switch elements (Q2, Q3) corresponding to the output switch elements are turned on so that the inductor current (IL) is transferred to the first and second output voltages (VO1, VO2) during the interval.

[0068] The second time interval (T2) is a turn-on interval in which the first and second switch elements (Q1, Q2) are turned on and the inductor current (IL) is conducted toward the first output voltage (VO1). It begins at the end of the build-up interval and ends when the first output voltage (VO1) reaches the first output target value (VO1 Target) set as the target value of the first output voltage (VO1).

[0069] Here, the end point of the second time interval (T2) can be determined by a second PWM control signal (PWM2) indicating the point in time when the first PWM feedback signal (VO1_FB) reaches the first target reference value (TG1_REF) in the comparison unit (300).

[0070] The third time interval (T3) is a turn-on interval in which the third and fourth switch elements (Q3, Q4) are turned on and the inductor current (IL) is conducted toward the negative polarity second output voltage (VO2). It begins at the end of the second time interval (T2) and ends at the start of the next first time interval (T1) when the next current build-up begins.

[0071] The third time interval (T3) is determined as the remaining interval excluding the first and second time intervals (T1, T2) in one switching cycle, or the remaining interval excluding the second time interval (T2) in the power interval, and the remaining inductor current (IL), excluding the current delivered to the first output voltage (VO1) side during the second time interval (T2) from the built-up inductor current (IL), is delivered to the second output voltage (VO2) side.

[0072] If the inductor current (IL) is excessively or insufficiently transmitted to the second output voltage (VO2) side during the second time interval (T2), the error is reflected in the summing error signal (VERR), and accordingly, the amount of build-up of the inductor current (IL) in the first time interval (T1) and the second time interval (T2) change, and as a result, the amount of the inductor current (IL) in the third time interval (T3) and the corresponding interval changes, so the second output voltage (VO2) can be regulated to the target second output target value (VO2 Target).

[0074] FIG. 4 is a circuit diagram showing a SIMO DC-DC converter having two outputs according to another embodiment of the present invention, and FIG. 5 is an operation waveform diagram of the SIMO DC-DC converter of FIG. 4 according to another embodiment of the present invention.

[0075] The SIMO DC-DC converter of FIG. 4 is configured to provide first and second output voltages (VO1, VO2) (Fig. 4(a)), and the first and second output voltages (VO1, VO2) may be composed of first to third switch elements (Q1~Q3) and an inductor (L) so that they are positive polarity voltages of different magnitudes (Fig. 4(b)).

[0076] Referring to FIG. 4(b), the first to third switch elements (Q1 to Q3) may be configured to form a single switching terminal (LX1), and an inductor (L) may be connected between the switching terminal (LX1) and the input voltage.

[0077] Here, the first switch element (Q1) is a build-up switch element for building up the inductor current (IL), the second switch element (Q2) is turned on to conduct the inductor current (IL) to the first output voltage (VO1) side in the power section, and the third switch element (Q3) can be controlled to turn on to conduct the inductor current (IL) to the second output voltage (VO2) side in the power section.

[0078] According to FIG. 5, the first time interval (T1) corresponds to a build-up interval, and the start (SET) and end times of the first PWM control signal (PWM1) are determined based on the comparison result of the summing error signal (VERR) and the ramp signal (VRAMP), and the build-up interval is determined with a pulse width having the first time interval (T1).

[0079] During the first time interval (T1), the first switch element (Q1) corresponding to the build-up switch element is turned on so that the inductor current (IL) is built up, and when the build-up period of the first time interval (T1) ends, the power interval is started.

[0080] The power interval corresponds to the second and third time intervals (T2, T3), and the second and third switch elements (Q2, Q3) corresponding to the output switch elements are turned on so that the inductor current (IL) is transferred to the first and second output voltages (VO1, VO2) during the interval.

[0081] The second time interval (T2) is a turn-on interval in which the second switch element (Q2) is turned on and the inductor current (IL) is conducted toward the first output voltage (VO1) of positive polarity, and it begins at the end of the build-up interval and ends when the first output voltage (VO1) reaches the first output target value (VO1 Target) set as the target value of the first output voltage (VO1).

[0082] Here, the end point of the second time interval (T2) can be determined by a second PWM control signal (PWM2) indicating the point in time when the first PWM feedback signal (VO1_FB) reaches the first target reference value (TG1_REF) in the comparison unit (300).

[0083] The third time interval (T3) is a turn-on interval in which the third switch element (Q3) is turned on and the inductor current (IL) is conducted to the second output voltage (VO2) of the opposite positive polarity, and it begins at the end of the second time interval (T2) and ends at the start of the next first time interval (T1) when the next current build-up begins.

[0084] The third time interval (T3) is determined as the remaining interval excluding the first and second time intervals (T1, T2) in one switching cycle, or the remaining interval excluding the second time interval (T2) in the power interval, and the remaining inductor current (IL), excluding the current delivered to the first output voltage (VO1) side during the second time interval (T2) from the built-up inductor current (IL), is delivered to the second output voltage (VO2) side.

[0085] If the inductor current (IL) is excessively or insufficiently transmitted to the second output voltage (VO2) side during the second time interval (T2), the error is reflected in the summing error signal (VERR), and accordingly, the amount of build-up of the inductor current (IL) in the first time interval (T1) and the second time interval (T2) change, and as a result, the amount of the inductor current (IL) in the third time interval (T3) and the corresponding interval changes, so the second output voltage (VO2) can be regulated to the target second output target value (VO2 Target).

[0087] Through the configuration described above, the single inductor-multiple output DC-DC converter and the control method according to the present invention have the effect of precisely controlling various outputs with a single inductor through a single error amplifier.

[0088] Although the present invention has been described and illustrated above based on preferred embodiments to exemplify the principles of the invention, the invention is not limited to the configuration and operation as described and illustrated. The embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the invention is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalents thereof should be interpreted as being included within the scope of the invention. Explanation of the symbols

[0090] 100: Error summation unit 110: Individual error amplifier 200: Summing error amplifier 300: Comparator 310~330: 1st to Nth comparators 400: Logic gate driver 500: Output switch FB_VO1~FB_VON: 1st to Nth feedback signals REF_VO1~REF_VON: 1st to Nth error threshold values VSUM: Sum signal VREF: Sum reference value VRAMP: Ramp signal VERR: Summed error signal VO1_FB~VON-1_FB: 1st to N-1st PWM feedback signals TG1_REF~TGN-1_REF: 1st to N-1st target reference values PWM1~PWMN: 1st to Nth PWM control signals GD_S1~GD_SX: Gate driving signals VO1~VON: 1st to Nth output voltages LX1, LX2: Switching unit Q1~Q4: 1st to 4th switch elements L: Inductor IL: Inductor current VO1 Target, VO2 Target: 1st and 2nd output target values

Claims

Claim 1 A single inductor-multiple output DC / DC converter configured to provide multiple output voltages from an input voltage using a single inductor, comprising: an error summing unit that sums individual error signals between a first to N feedback signal fed back from a first to N output voltage and a corresponding first to N error reference value to output a summing signal (wherein N is a natural number greater than or equal to 2); a summing error amplifier that amplifies the error between the summing signal and the summing reference value to output a summing error signal; a comparator that receives the summing error signal, a ramp signal having a switching frequency, and a first to N-1 PWM feedback signal fed back from the first to N-1 output voltages and outputs a first to N PWM control signal; and an output switch unit configured to include a plurality of switch elements and a single inductor. A single inductor-multiple output DC / DC converter characterized by including a logic gate driving unit that generates a plurality of gate driving signals for controlling the switching of the plurality of switch elements from the first to Nth PWM control signals and provides them to the output switch unit. Claim 2 A single inductor-multiple output DC / DC converter according to claim 1, wherein the error summing unit comprises N individual error amplifiers that each output individual error signals corresponding to error values ​​between first to N feedback signals fed back from first to N output voltages and corresponding first to N error reference values, and sums the individual error signals output from each of the N individual error amplifiers to output the summing signal. Claim 3 A single inductor-multiple output DC / DC converter according to claim 2, wherein the comparison unit comprises: a first comparator that compares the summing error signal and the ramp signal to output the first PWM control signal; and second to N comparators that compare the first to N-1 PWM feedback signals with the corresponding first to N-1 target reference values ​​to output the second to N PWM control signals, respectively. Claim 4 A single inductor-multiple output DC / DC converter according to claim 3, wherein the first PWM control signal controls the build-up section of the inductor current flowing through the inductor, and each of the second to Nth PWM control signals controls the power section in which the inductor current conducts toward the corresponding first to N-1st output voltage side. Claim 5 A single inductor-multiple output DC / DC converter according to claim 4, wherein the output switch unit comprises: one or more build-up switch elements that are turned on in the build-up section among the plurality of switch elements; and N output switch elements among the plurality of switch elements that conduct the inductor current to the first to Nth output voltage side in the power section. Claim 6 A single inductor-multiple output DC / DC converter according to claim 5, characterized in that at least a portion of the build-up switch element is turned on during the power interval. Claim 7 In claim 5, the logic gate driver outputs a plurality of gate driving signals that control the switching of the build-up switch element and the output switch element by performing a logic operation on the first to Nth PWM control signals, wherein the plurality of gate driving signals are configured to turn on one or more build-up switch elements in a build-up section controlled by the first PWM control signal, turn on N-1 output switch elements corresponding to the first to N-1 output voltage side in a part of the power section by each of the second to Nth PWM control signals, and turn on an output switch element corresponding to the Nth output voltage side in the remaining section of the power section, characterized in that the single inductor-multiple output DC / DC converter. Claim 8 A single inductor-multiple output DC / DC converter according to claim 7, wherein the first PWM control signal determines the start and end times of the pulse width based on the comparison result of the summing error signal and the ramp signal. Claim 9 In claim 8, the logic gate driving unit is characterized by generating the plurality of gate driving signals by performing a logical operation on the first to Nth PWM control signals such that the turn-on period of the output switch element corresponding to the first output voltage side is initiated at the time of termination of the first PWM control signal and terminates at the time when the first PWM feedback signal reaches the first target reference value, the turn-on period of the output switch element corresponding to the Nth output voltage side is initiated at the time of termination of the turn-on period of the output switch element corresponding to the N-1 output voltage side and terminates at the time of initiation of the first PWM control signal, and when N is 3 or greater, the turn-on period of the output switch element corresponding to the k-1 output voltage side is initiated at the time of termination of the turn-on period of the output switch element corresponding to the k-1 output voltage side and terminates at the time when the k-th PWM feedback signal reaches the k-th target reference value (wherein k is a natural number of 2, …, N-1). Claim 10 A single inductor-multiple output DC / DC converter according to claim 3, characterized in that the first to N-1 feedback signals and the first to N-1 PWM feedback signals are identical to each other, and the first to N-1 error reference values ​​and the first to N-1 target reference values ​​are identical to each other. Claim 11 A control method for a single inductor-multiple output DC / DC converter, comprising: (a) a step of summing individual error signals between a first to Nth feedback signal fed back from a first to Nth output voltage and a corresponding first to Nth error reference value to output a summing signal (wherein N is a natural number greater than or equal to 2); (b) a step of amplifying the error between the summing signal and the summing reference value to output a summing error signal; (c) a step of receiving the summing error signal, a ramp signal having a switching frequency, and a first to N-1st PWM feedback signal fed back from the first to N-1st output voltages, and outputting a first to Nth PWM control signal; (d) a step of configuring an output switch unit including a plurality of switch elements and a single inductor; and (e) a step of generating a plurality of gate driving signals for controlling the switching of the plurality of switch elements from the first to Nth PWM control signal and providing them to the output switch unit. Claim 12 A control method for a single inductor-multiple output DC / DC converter according to claim 11, wherein step (a) is characterized by summing individual error signals output in correspondence with error values ​​between first to N feedback signals fed back from first to N output voltages and corresponding first to N error reference values, and outputting the summed signal. Claim 13 A control method for a single inductor-multiple output DC / DC converter according to claim 12, wherein step (c) comprises: (c-1) a step of outputting the first PWM control signal by comparing the summed error signal and the ramp signal; and (c-2) a step of outputting the second to Nth PWM control signals by comparing the first to N-1 PWM feedback signals with the corresponding first to N-1 target reference values. Claim 14 A control method for a single inductor-multiple output DC / DC converter according to claim 13, wherein the first PWM control signal controls the build-up section of the inductor current flowing through the inductor, and each of the second to Nth PWM control signals controls the power section in which the inductor current conducts toward the corresponding first to N-1st output voltage side. Claim 15 A control method for a single inductor-multiple output DC / DC converter according to claim 14, wherein the output switch portion comprises: one or more build-up switch elements that are turned on in the build-up section among the plurality of switch elements; and N output switch elements among the plurality of switch elements that conduct the inductor current in the power section to the first to Nth output voltage side. Claim 16 In claim 15, the above step (e) is configured to output a plurality of gate driving signals that control the switching of the build-up switch element and the output switch element by performing a logical operation on the first to Nth PWM control signals, wherein (e-1) a step of turning on one or more of the build-up switch elements in a build-up section controlled by the first PWM control signal; (e-2) a step of turning on N-1 output switch elements corresponding to the first to N-1 output voltage side in a part section of the power section by each of the second to Nth PWM control signals; and (e-3) a step of turning on the output switch elements corresponding to the Nth output voltage side in the remaining section of the power section, characterized in that it comprises a control method for a single inductor-multiple output DC / DC converter. Claim 17 A control method for a single inductor-multiple output DC / DC converter according to claim 16, wherein the first PWM control signal determines the start and end times of the pulse width according to the comparison result of the summing error signal and the ramp signal. Claim 18 In claim 17, the above step (e) generates the plurality of gate driving signals by performing a logical operation on the first to Nth PWM control signals such that, in the above step (e-2), the turn-on period of the output switch element corresponding to the first output voltage side is initiated at the time of termination of the first PWM control signal and terminates at the time when the first PWM feedback signal reaches the first target reference value; in the above step (e-3), the turn-on period of the output switch element corresponding to the Nth output voltage side is initiated at the time of termination of the turn-on period of the output switch element corresponding to the N-1 output voltage side and terminates at the time of initiation of the first PWM control signal; and when N is 3 or greater in the above step (e-2), the turn-on period of the output switch element corresponding to the kth output voltage side is initiated at the time of termination of the turn-on period of the output switch element corresponding to the k-1 output voltage side and terminates at the time when the kth PWM feedback signal reaches the kth target reference value (where k is a natural number of 2, …, N-1). A control method for a single inductor-multiple output DC / DC converter characterized by the following.

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