Integrated semiconductor device based on Diamond and nitride including heat dissipation layer, and method of manufacturing

Abstract

The present invention relates to a diamond and nitride-based semiconductor integrated device including a heat dissipation layer and a method for manufacturing such a device, and more specifically, to a method for manufacturing a semiconductor integrated device applicable to an electrical circuit including a CMOS circuit by forming a p-type diamond FET utilizing 2 DHG channels and an n-type nitride FET utilizing 2 DEG channels on a single substrate layer and electrically connecting them, which corresponds to a method for manufacturing a high-voltage, high-frequency semiconductor device utilizing the wide bandgap characteristics of diamond and nitride, and which prevents degradation of the device by utilizing the excellent heat dissipation characteristics of diamond and can manufacture a high-reliability semiconductor device.

Description

Technology Field

[0001] The present invention relates to a diamond and nitride-based semiconductor integrated device including a heat dissipation layer and a method for manufacturing thereof, and more specifically, to a semiconductor integrated device including a heat dissipation layer and a method for manufacturing thereof, wherein a p-type diamond FET utilizing 2DHG channels and an n-type nitride FET utilizing 2DEG channels are formed on a single substrate layer and electrically connected to provide a semiconductor integrated device applicable to an electrical circuit including a CMOS circuit. Background Technology

[0003] CMOS (complementary metal-oxide semiconductor) is a semiconductor device manufactured such that P-channel FETs and N-channel FETs are placed adjacently on a single chip, with the gates of the P-channel FETs and N-channel FETs connected to the inputs and the drains connected to the outputs, allowing the two FETs to operate complementarily. CMOS has the advantage of low power consumption and is used as a switching device in most logic circuits.

[0004] Conventional CMOS devices were mostly based on silicon (Si), but as device miniaturization progressed, problems such as increased power consumption and heat generation occurred. In addition, due to the characteristics of silicon, conventional silicon-based CMOS devices have the problem of being difficult to utilize as ultra-high voltage and ultra-high frequency devices.

[0005] However, the electric vehicle, 5G, and aerospace sectors, where the market is currently expanding rapidly, require semiconductor devices capable of operating in high-voltage, high-temperature, and high-frequency environments. Accordingly, there is a demand for new semiconductor devices to replace silicon-based devices.

[0006] In other words, there is a demand for semiconductor devices and manufacturing technologies that possess excellent withstand voltage characteristics, can prevent device degradation due to high temperatures, and can operate in extreme environments such as space. The problem to be solved

[0008] The present invention aims to provide a diamond and nitride-based semiconductor integrated device including a heat dissipation layer and a method for manufacturing such a semiconductor integrated device with improved economic efficiency by preventing device degradation through rapid dissipation of high heat generated during device operation by including a heat dissipation layer composed of diamond. means of solving the problem

[0010] To solve the above problems, one embodiment of the present invention comprises a nitride and diamond-based semiconductor integrated circuit, the nitride and diamond-based semiconductor integrated circuit comprising: a substrate layer; a nitride FET formed in a portion of the substrate layer; and a diamond FET formed in another portion of the substrate layer, wherein the nitride FET comprises aluminum gallium nitride (Al) with a different detailed composition. x Ga 1-x A first multilayer comprising a plurality of layers made of N); a first insulating layer disposed on the first multilayer; and a first electrode; wherein the diamond FET comprises aluminum gallium nitride (Al) having a different detailed composition x Ga 1-x A semiconductor integrated device is provided that includes a second multilayer comprising a plurality of layers made of N; a second insulating layer disposed on the second multilayer; a second diamond layer disposed on the second insulating layer; and a second electrode formed on the second diamond layer, wherein the semiconductor integrated device electrically connects the first electrode and the second electrode to form an integrated circuit.

[0012] In some embodiments of the present invention, the first multilayer of the nitride FET comprises a first buffer layer; a first channel layer disposed over the first buffer layer; a first barrier layer disposed over the first channel layer; and a first capping layer disposed over the first barrier layer; and the second multilayer of the diamond FET may comprise a second buffer layer; a second channel layer disposed over the second buffer layer; a second barrier layer disposed over the second channel layer; and a second capping layer disposed over the second barrier layer.

[0014] In some embodiments of the present invention, the first buffer layer, first channel layer, first barrier layer, and first capping layer of the nitride FET are each Al x Ga 1-x Aluminum gallium nitride represented by the chemical formula N, comprising aluminum gallium nitride (Al) included in each of the two layers disposed adjacent to each other among the first channel layer, the first barrier layer, and the first capping layer. x Ga 1-x N) has different x values, and the aluminum gallium nitride (Al) included in the first channel layer x Ga 1-x The x value of N) is the aluminum gallium nitride (Al) included in the first barrier layer. x Ga 1-x The second buffer layer, second channel layer, second barrier layer, and second capping layer of the diamond FET are each smaller than the x value of N), and Al x Ga 1-x Aluminum gallium nitride represented by the chemical formula N, comprising aluminum gallium nitride (Al) included in each of the two layers arranged adjacent to each other among the second channel layer, the second barrier layer, and the second capping layer. x Ga 1-x N) has different x values, and the aluminum gallium nitride (Al) included in the second channel layer x Ga 1-x The x value of N) is the aluminum gallium nitride (Al) included in the second barrier layer. x Ga 1-x The aluminum gallium nitride (Al N) is smaller than the x value of N and is included in the nitride FET and diamond FET, respectively. x Ga 1-x The x value of N) can be from 0.1 to 99.9.

[0016] In some embodiments of the present invention, the nitride FET may further include a first diamond layer disposed on the first insulating layer.

[0018] In some embodiments of the present invention, the first electrode of the nitride FET may be formed by etching a portion of the first insulating layer and depositing a metal on the exposed first capping layer.

[0019] In some embodiments of the present invention, the first insulating layer and the second insulating layer are each SiN y It may include one or more of SiO2.

[0020] In some embodiments of the present invention, the diamond FET further comprises an oxide film layer formed on the second diamond layer; and the oxide film layer may comprise one or more of Al2O3, SiO2, HfO2, MoO3, V2O5, and WO3.

[0021] In some embodiments of the present invention, the first diamond layer may be formed by applying a diamond seed on the first insulating layer and growing it by chemical vapor deposition (CVD) at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C, and the second diamond layer may be formed by applying a diamond seed on the second insulating layer and growing it by chemical vapor deposition (CVD) at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C.

[0022] In some embodiments of the present invention, the substrate layer is any one of Al2O3, Si, SiC, and Nitride-based substrates, and the first buffer layer, the second buffer layer, the first channel layer, the second channel layer, the first barrier layer, the second barrier layer, the first capping layer, and the second capping layer may each be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C.

[0023] In some embodiments of the present invention, the first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from the first source and the first gate, and the nitride FET may further comprise a p-aluminum gallium nitride layer formed between the first gate and the first capping layer.

[0024] In some embodiments of the present invention, the first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from the first source and the first gate, and the nitride FET further comprises an oxide film layer formed between the first gate and the first capping layer; and the oxide film layer may comprise one or more of Al2O3, SiO2, HfO2, MoO3, V2O5, and WO3.

[0026] To solve the above problems, one embodiment of the present invention is a method for manufacturing a semiconductor integrated device based on nitride and diamond, comprising: a substrate layer preparation step of preparing a substrate layer; a nitride FET formation step of forming a nitride FET in a part region on the substrate layer; and a diamond FET formation step of forming a diamond FET in another region on the substrate layer; wherein the nitride FET formation step comprises aluminum gallium nitride (Al) with a different detailed composition x Ga 1-x A first multilayer forming step comprising a plurality of layers made of N) for forming a first multilayer; a first insulating layer placement step for placing a first insulating layer on the first multilayer; and a first electrode forming step; wherein the diamond FET forming step comprises aluminum gallium nitride (Al) with different detailed compositions x Ga 1-xA method for manufacturing a semiconductor integrated device is provided, comprising: a second multilayer forming step for forming a second multilayer including a plurality of layers made of N; a second insulating layer placement step for placing a second insulating layer on the second multilayer; a second diamond layer placement step for placing a second diamond layer on the second insulating layer; and a second electrode forming step for forming a second electrode on the second diamond layer; wherein the semiconductor integrated device electrically connects the first electrode and the second electrode to form an integrated circuit.

[0027] In some embodiments of the present invention, the nitride FET forming step may further include a first diamond layer placement step of placing a first diamond layer on the first insulating layer.

[0029] In some embodiments of the present invention, the first multilayer forming step further comprises a detailed step of a first buffer layer placement step; a first channel layer placement step of placing a first channel layer on the first buffer layer; a first barrier layer placement step of placing a first barrier layer on the first channel layer; and a first capping layer placement step of placing a first capping layer on the first barrier layer; and the second multilayer forming step may further comprise a detailed step of a second buffer layer placement step; a second channel layer placement step of placing a second channel layer on the second buffer layer; a second barrier layer placement step of placing a second barrier layer on the second channel layer; and a second capping layer placement step of placing a second capping layer on the second barrier layer. Effects of the invention

[0031] According to one embodiment of the present invention, a semiconductor integrated device includes a first diamond layer capable of acting as a heat dissipation layer, thereby improving heat resistance performance and preventing degradation due to high temperature during device operation, which extends the lifespan of the semiconductor integrated device and enables operation in extreme environments such as high temperature, thereby improving economic efficiency.

[0032] According to one embodiment of the present invention, a semiconductor integrated device can improve the usability of the device by using an ultrawide bandgap material to improve the breakdown voltage characteristics of the semiconductor integrated device.

[0033] According to one embodiment of the present invention, each of the first multilayer and the second multilayer is composed of a plurality of layers, and the plurality of layers include aluminum gallium nitride having different detailed compositions, thereby forming a two-dimensional electric gas inside to improve electron mobility and reduce switching losses, thereby enabling the effect of improving the electrical performance of a semiconductor integrated device.

[0034] According to one embodiment of the present invention, the first insulating layer and the second insulating layer are SiN y By including one or more of SiO2, an environment is provided where a diamond thin film can be deposited on the upper side, thereby enabling the formation of a first diamond layer and a second diamond layer, which can have the effect of improving the manufacturing convenience of a semiconductor integrated device.

[0035] According to one embodiment of the present invention, a diamond FET can improve hole mobility by including a channel composed of two-dimensional hole gas, thereby exhibiting the effect of improving the performance of a semiconductor integrated device.

[0036] According to one embodiment of the present invention, the semiconductor integrated device can expand the application range of the semiconductor integrated device by controlling whether it is in e-mode and d-mode through a stacked structure of nitride FETs and diamond FETs. Brief explanation of the drawing

[0038] FIG. 1 illustrates a schematic diagram of a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 2 schematically illustrates a method for manufacturing a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 3 schematically illustrates a nitride FET formation step according to one embodiment of the present invention. FIG. 4 schematically illustrates the first multilayer formation step of the nitride FET formation step according to one embodiment of the present invention. FIG. 5 schematically illustrates a diamond FET formation step according to one embodiment of the present invention. FIG. 6 schematically illustrates the second multilayer formation step of the diamond FET formation step according to one embodiment of the present invention. FIG. 7 schematically illustrates the structure of a semiconductor integrated device including an oxide film layer according to one embodiment of the present invention. FIG. 8 schematically illustrates the process of forming a two-dimensional hole gas according to one embodiment of the present invention. FIG. 9 schematically illustrates the process of forming a two-dimensional electron gas according to one embodiment of the present invention. FIG. 10 schematically illustrates a diamond FET according to one embodiment of the present invention and the voltage-current characteristics of the diamond FET. FIG. 11 schematically illustrates a semiconductor integrated device and the voltage-drain current characteristics of the semiconductor integrated device according to one embodiment of the present invention. FIG. 12 schematically illustrates the structure of a semiconductor integrated device further comprising a p-aluminum nitride gallium layer according to one embodiment of the present invention. FIG. 13 schematically illustrates the structure of a semiconductor integrated device further comprising an oxide film layer according to one embodiment of the present invention. Specific details for implementing the invention

[0039] Hereinafter, various embodiments and / or aspects are disclosed with reference to the drawings. For illustrative purposes, numerous specific details are disclosed in the following description to aid in a general understanding of one or more aspects. However, it will also be recognized by those skilled in the art that these aspects may be practiced without such specific details. The following description and the accompanying drawings describe specific exemplary aspects of one or more aspects in detail. However, these aspects are exemplary, and some of the various methods in the principles of the various aspects may be used, and the description is intended to include all such aspects and their equivalents.

[0040] In addition, various aspects and features will be presented by a system that may include multiple devices, components and / or modules, etc. It should also be understood and recognized that various systems may include additional devices, components and / or modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in relation to the drawings.

[0041] As used herein, terms such as "examples," "examples," "aspects," "examples," etc., may not be interpreted as implying that any aspect or design described is better or more advantageous than other aspects or designs.

[0042] Additionally, the terms “comprising” and / or “comprising” should be understood to mean that the relevant feature and / or component is present, but not to exclude the presence or addition of one or more other features, components and / or groups thereof.

[0043] Additionally, terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0044] Furthermore, in the embodiments of the present invention, all terms used herein, including technical or scientific terms, unless otherwise defined, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the embodiments of the present invention.

[0046] CMOS is a switching device primarily used in logic circuits due to its low power consumption, and conventional CMOS was manufactured based on silicon. However, as device miniaturization progressed, conventional silicon-based CMOS faced issues such as increased power consumption and heat generation, and problems arose regarding its difficulty in being applied as ultra-high voltage and ultra-high frequency devices required by the market.

[0047] To solve this, the present invention proposes a semiconductor integrated device (1) including a heat dissipation layer and a method for manufacturing the same, in which conventional silicon is replaced with diamond and nitride materials.

[0048] More specifically, in the present invention, diamond and gallium aluminum nitride (Al), which are Ultra Wide Band-Gap (UWBG) materials x Ga 1-x A semiconductor integrated device (1) corresponding to a CMOS structure can be manufactured by forming a diamond FET (3000) and a nitride FET (2000) based on N on a single substrate layer (1000). The diamond FET (3000) may correspond to a p-channel FET, and the nitride FET (2000) may correspond to an N-channel FET. Additionally, a first diamond layer (2300), which is a heat dissipation layer, may be disposed on the upper side of the nitride FET (2000).

[0049] With this configuration, the semiconductor integrated circuit (1) can dissipate heat more effectively than conventional silicon-based CMOS, making it easy to operate even in high-temperature environments, and diamond and aluminum gallium nitride (Al x Ga 1-x Due to the wide bandgap of N), it can be applied as an ultra-high voltage and ultra-high frequency device.

[0051] That is, according to one embodiment of the present invention, the semiconductor integrated device (1) includes a first diamond layer (2300) and a second diamond layer (3300) that can act as heat dissipation layers, thereby improving heat resistance performance and preventing deterioration due to high temperature during device operation, thereby extending the lifespan of the semiconductor integrated device (1) and enabling operation in extreme environments such as high temperature, so as to improve economic efficiency.

[0052] In addition, by using an ultrawide bandgap material to improve the withstand voltage characteristics of the semiconductor integrated device (1), the usability of the device can be improved.

[0054] Hereinafter, a diamond and nitride-based semiconductor integrated device (1) including a heat dissipation layer according to one embodiment of the present invention and a method for manufacturing it will be described in detail.

[0056] FIG. 1 illustrates a schematic diagram of a semiconductor integrated circuit (1) according to one embodiment of the present invention.

[0058] A nitride and diamond-based semiconductor integrated device (1) according to one embodiment of the present invention comprises a substrate layer (1000); a nitride FET (2000) formed in a portion of the substrate layer (1000); and a diamond FET (3000) formed in another portion of the substrate layer (1000); wherein the nitride FET (2000) comprises aluminum gallium nitride (Al) with a different detailed composition. x Ga 1-x A first multilayer (2100) comprising a plurality of layers made of N); a first insulating layer (2200) disposed on the first multilayer (2100); and a first electrode (2400); wherein the diamond FET (3000) comprises aluminum gallium nitride (Al) having a different detailed composition x Ga 1-x A second multilayer (3100) comprising a plurality of layers made of N); a second insulating layer (3200) disposed on the second multilayer (3100); a second diamond layer (3300) disposed on the second insulating layer (3200); and a second electrode (3400) formed on the second diamond layer (3300); wherein the semiconductor integrated device (1) may be a semiconductor integrated device (1) that forms an integrated circuit by electrically connecting the first electrode (2400) and the second electrode (3400).

[0059] According to one embodiment of the present invention, the nitride FET (2000) may further include a first diamond layer (2300) disposed on the first insulating layer (2200).

[0060] Additionally, according to one embodiment of the present invention, the first multilayer (2100) of the nitride FET (2000) comprises: a first buffer layer (2110); a first channel layer (2120) disposed on the first buffer layer (2110); a first barrier layer (2130) disposed on the first channel layer (2120); and a first capping layer (2140) disposed on the first barrier layer (2130); and the second multilayer (3100) of the diamond FET (3000) may comprise: a second buffer layer (3110); a second channel layer (3120) disposed on the second buffer layer (3110); a second barrier layer (3130) disposed on the second channel layer (3120); and a second capping layer (3140) disposed on the second barrier layer (3130).

[0061] According to one embodiment of the present invention, the first electrode (2400) includes a first source (2410), a first gate (2420) formed spaced apart from the first source (2410), and a first drain (2430) formed spaced apart from the first source (2410) and the first gate (2420), and the second electrode (3400) may include a second source (3410), a second gate (3420) formed spaced apart from the second source (3410), and a second drain (3430) formed spaced apart from the second source (3410) and the second gate (3420).

[0063] As illustrated in FIG. 1, a semiconductor integrated device (1) according to one embodiment of the present invention may include a nitride FET (2000) and a diamond FET (3000) that share a single substrate layer (1000), and the nitride FET (2000) and the diamond FET (3000) may be arranged adjacent to each other on the substrate layer (1000). However, the nitride FET (2000) and the diamond FET (3000) may be arranged adjacent to each other but do not come into contact with each other, and may be arranged spaced apart by a predetermined distance in a horizontal direction with respect to the substrate layer (1000).

[0064] According to one embodiment of the present invention, the nitride FET (2000) may include a first multilayer (2100) comprising a first buffer layer (2110), a first channel layer (2120), a first barrier layer (2130), and a first capping layer (2140), a first insulating layer (2200) disposed on the first multilayer (2100), a first diamond layer (2300) disposed on the first insulating layer (2200), and a first electrode (2400). At this time, each of the first buffer layer (2110), the first channel layer (2120), the first barrier layer (2130), and the first capping layer (2140) included in the first multilayer (2100) is aluminum gallium nitride (Al x Ga 1-x The detailed composition of the aluminum gallium nitride included in the first buffer layer (2110), the first channel layer (2120), the first barrier layer (2130), and the first capping layer (2140) may differ from one another.

[0066] According to one embodiment of the present invention, the first electrode (2400) of the nitride FET (2000) may be formed by etching a portion of the first insulating layer (2200) and depositing a metal on the exposed first capping layer (2140), and the first diamond layer (2300) may be disposed on the upper side of the first insulating layer (2200) from which a portion has been etched.

[0068] Specifically, the first electrode (2400) may be disposed on a portion of the first capping layer (2140), and the first insulating layer (2200) may be disposed on another portion of the first capping layer (2140) where the first electrode (2400) is not disposed. Additionally, according to one embodiment of the present invention, the first diamond layer (2300) may be disposed on the upper side of the first insulating layer (2200) but may not be disposed on the upper side of the first electrode (2400). The first electrode (2400) disposed on the capping layer may include a first source (2410), a first gate (2420), and a first drain (2430). The first gate (2420) may be formed spaced apart from the first source (2410), and the first drain (2430) may be formed spaced apart from the first gate (2420) and the first source (2410).

[0070] Meanwhile, the diamond FET (3000) may include a second multilayer (3100) comprising a second buffer layer (3110), a second channel layer (3120), a second barrier layer (3130), and a second capping layer (3140). The second multilayer (3100), like the first multilayer (2100), is each made of aluminum gallium nitride (Al x Ga 1-x It includes a second buffer layer (3110), a second channel layer (3120), a second barrier layer (3130), and a second capping layer (3140) including N, and the detailed composition of the aluminum gallium nitride included in each of the second buffer layer (3110), the second channel layer (3120), the second barrier layer (3130), and the second capping layer (3140) may differ from one another.

[0071] Additionally, the diamond FET (3000) may include a second insulating layer (3200) disposed on the second multilayer (3100), a second diamond layer (3300) disposed on the second insulating layer (3200), and a second electrode (3400) formed in a portion of the second diamond layer (3300). At this time, the second electrode (3400) may include a second source (3410), a second gate (3420), and a second drain (3430), wherein the second gate (3420) is formed spaced apart from the second electrode (3400), and the second drain (3430) is formed spaced apart from the second gate (3420) and the second electrode (3400).

[0072] The second gate (3420) included in the second electrode (3400) can be electrically connected to the first gate (2420) included in the first electrode (2400), and the second drain (3430) can be electrically connected to the first drain (2430) to form the semiconductor integrated device (1) in which an integrated circuit is formed.

[0074] According to one embodiment of the present invention, the first buffer layer (2110), the first channel layer (2120), the first barrier layer (2130), and the first capping layer (2140) of the nitride FET (2000) are each made of Al x Ga 1-x Aluminum gallium nitride represented by the chemical formula N, comprising aluminum gallium nitride (Al) included in each of the two layers arranged adjacent to each other among the first channel layer (2120), the first barrier layer (2130), and the first capping layer (2140). x Ga 1-x N) has different x values, and the aluminum gallium nitride (Al) included in the first channel layer (2120) has different x values. x Ga 1-x The x value of N) is aluminum gallium nitride (Al) included in the first barrier layer (2130). x Ga 1-xThe second buffer layer (3110), second channel layer (3120), second barrier layer (3130), and second capping layer (3140) of the diamond FET (3000) are each smaller than the x value of N), and each is made of Al x Ga 1-x Aluminum gallium nitride represented by the chemical formula N, comprising aluminum gallium nitride (Al) included in each of the two layers arranged adjacent to each other among the second channel layer (3120), the second barrier layer (3130), and the second capping layer (3140). x Ga 1-x N) has different x values, and the aluminum gallium nitride (Al) included in the second channel layer (3120) x Ga 1-x The x value of N) is aluminum gallium nitride (Al) included in the second barrier layer (3130). x Ga 1-x The aluminum gallium nitride (Al N) is smaller than the x value of N and is included in the nitride FET (2000) and the diamond FET (3000), respectively. x Ga 1-x The x value of N) can be from 0.1 to 99.9.

[0076] Specifically, the aluminum gallium nitride included in each of the first multilayer (2100) and second multilayer (3100) of the nitride FET (2000) and diamond FET (3000) is Al x Ga 1-x It can be expressed as N, and x can be one of positive numbers between 0.1 and 99.9. Since the aluminum and gallium content contained in the aluminum gallium nitride varies depending on the value of x, the detailed composition of the aluminum gallium nitride may differ from layer to layer.

[0077] As described above, the detailed composition of the aluminum gallium nitride included in each of the first buffer layer (2110), the first channel layer (2120), the first barrier layer (2130), and the first capping layer (2140) may differ from one another. That is, each of the first buffer layer (2110), the first channel layer (2120), the first barrier layer (2130), and the first capping layer (2140) may include aluminum gallium nitride having different x values. Additionally, in the case of two layers arranged adjacent to each other among the first channel layer (2120), the first barrier layer (2130), and the first capping layer (2140), the aluminum gallium included in each layer may have different x values, and the x value of the aluminum gallium included in the first channel layer (2120) may be smaller than the x value of the aluminum gallium included in the first barrier layer (2130).

[0078] For example, the x value of the aluminum gallium nitride included in the first buffer layer (2110) may be referred to as x1, the x value of the aluminum gallium nitride included in the first channel layer (2120) may be referred to as x2, the x value of the aluminum gallium nitride included in the first barrier layer (2130) may be referred to as x3, and the x value of the aluminum gallium nitride included in the first capping layer (2140) may be referred to as x4. At this time, the x2 of the first channel layer (2120) and the x3 of the first barrier layer (2130) placed above the first channel layer (2120) may not have the same value and may be different from each other. Similarly, the x3 and the x4 may have different values, and for all the aforementioned cases, the value of the x2 may be smaller than the x3. Furthermore, according to one embodiment of the present invention, the value of the x2 may be smaller than the x3 and the x4. That is, x2, x3, and x4 are x2 <x3, 및 x2<x4로 기재되는 부등식을 만족할 수 있다.

[0079] However, provided that the aforementioned conditions are satisfied, two layers that are not adjacent to each other may have the same x value. For example, if x1 and x2 have different values, x3 and x4 have different values, and x2 has a value smaller than x3 and x4, then x1 may have the same value as either x3 or x4.

[0080] Meanwhile, according to one embodiment of the present invention, the x value of the aluminum gallium nitride included in the first buffer layer (2110) may be less than or equal to the x value of the aluminum gallium nitride included in the first channel layer (2120). For example, when x2 and x3 have different values ​​and x3 and x4 have different values, x1 and x2 may have the same or different values. That is, x1 and x2 may satisfy the inequality described as x1 ≤ x2.

[0082] Likewise, the detailed composition of the aluminum gallium nitride included in each of the second buffer layer (3110), second channel layer (3120), second barrier layer (3130), and second capping layer (3140) may differ from each other for each layer. That is, each of the second buffer layer (3110), second channel layer (3120), second barrier layer (3130), and second capping layer (3140) may include aluminum gallium nitride having different x values. Additionally, in the case of two layers arranged adjacent to each other among the second channel layer (3120), the second barrier layer (3130), and the second capping layer (3140), the aluminum gallium included in each layer may have different x values, and the x value of the aluminum gallium included in the second channel layer (3120) may be smaller than the x value of the aluminum gallium included in the second barrier layer (3130).

[0083] When the x value of the aluminum gallium nitride included in the second buffer layer (3110) is referred to as x5, the x value of the aluminum gallium nitride included in the second channel layer (3120) is referred to as x6, the x value of the aluminum gallium nitride included in the second barrier layer (3130) is referred to as x7, and the x value of the aluminum gallium nitride included in the second capping layer (3140) is referred to as x8, the x6 of the second channel layer (3120) and the x7 of the second barrier layer (3130) placed above the second channel layer (3120) may have different values. Additionally, the x7 and the x8 may have different values, and for all the aforementioned cases, the value of the x6 may be smaller than the x7. Furthermore, according to one embodiment of the present invention, the value of the x6 may be smaller than the x7 and the x8. That is, x6, x7, and x8 are x6 <x7, x6<x8로 기재되는 부등식을 만족시킬 수 있다.

[0084] However, provided that the above conditions are satisfied, the x values ​​of two layers that are not adjacent to each other may be the same. For example, if x5 and x6 have different values, x7 and x8 have different values, and x6 has a value smaller than x7 and x8, then x5 may have the same value as either x7 or x8.

[0085] Meanwhile, according to one embodiment of the present invention, the x value of the aluminum gallium included in the second buffer layer (3110) may be less than or equal to the x value of the aluminum gallium included in the second channel layer (3120). For example, when x6 and x7 have different values ​​and x7 and x8 have different values, x5 and x6 may have the same or different values. That is, x5 and x6 may satisfy the inequality described as x5 ≤ x6.

[0087] According to one embodiment of the present invention, the first buffer layer (2110) and the second buffer layer (3110), the first channel layer (2120) and the second channel layer (3120), the first barrier layer (2130) and the second barrier layer (3130), and the first capping layer (2140) and the second capping layer (3140) may each include aluminum gallium nitride having corresponding x values. That is, x1 may have a value corresponding to x5, x2 and x6 may have corresponding values, x3 and x7 may have corresponding values, and x4 and x8 may have corresponding values. In other words, x1 and x5 may have the same value, x2 and x6 may have the same value, x3 and x7 may have the same value, and x4 and x8 may have the same value.

[0088] Each of the first multilayer (2100) and the second multilayer (3100) is composed of a plurality of layers containing aluminum gallium nitride with different detailed compositions, thereby forming a single layer composed of a two-dimensional electron gas (E) inside the plurality of layers. The two-dimensional electron gas (E) is a structure in which electrons are arranged at a high density within a specific area range, and electrons can move at a high speed within the region of the two-dimensional electron gas (E). A more detailed description of the two-dimensional electron gas (E) will be provided in the drawings described later.

[0090] That is, according to one embodiment of the present invention, each of the first multilayer (2100) and the second multilayer (3100) is composed of a plurality of layers, and the plurality of layers include aluminum gallium nitride having different detailed compositions, thereby forming a two-dimensional electric gas inside and having the effect of improving the performance of the semiconductor integrated device (1).

[0092] According to one embodiment of the present invention, the first insulating layer (2200) and the second insulating layer (3200) are each SiN y It may include one or more of SiO2.

[0094] Specifically, the first insulating layer (2200) is SiN y It includes one or more of SiO2 and can be disposed on the first capping layer (2140) included in the first multilayer (2100) of the nitride FET (2000). In addition, the second insulating layer (3200) is SiN y It may include one or more of SiO2 and be disposed on the second capping layer (3140) included in the second multilayer (3100) of the diamond FET (3000). SiN y y of can be from 0.001 to 99.999, and SiN included in the first insulating layer (2200) y and SiN included in the second insulating layer (3200) y They can have corresponding compositions. That is, SiN included in the first insulating layer (2200). y and SiN included in the second insulating layer (3200) y The y-values ​​of can be identical to each other. The above SiN y The first insulating layer and the second insulating layer, which include the above, perform the role of enabling the deposition of a diamond thin film, so that the first diamond layer and the second diamond layer can each be disposed on the first insulating layer and the second insulating layer, respectively.

[0096] That is, the first insulating layer (2200) and the second insulating layer (3200) are SiN y By including one or more of SiO2, an environment is provided where a diamond thin film can be deposited on the upper side, thereby enabling the formation of a first diamond layer (2300) and a second diamond layer (3300), which can be achieved to improve the manufacturing convenience of the semiconductor integrated device (1).

[0098] According to one embodiment of the present invention, the first diamond layer (2300) and the second diamond layer (3300) may include diamond. Generally, diamond is a material that has higher heat dissipation characteristics than metallic materials such as copper or aluminum. That is, the semiconductor integrated device (1) according to one embodiment of the present invention can be used as a heat dissipation layer to discharge heat generated when operating the semiconductor integrated device (1) by placing the first diamond layer (2300) and the second diamond layer (3300) on the upper side, and the first diamond layer (2300) and the second diamond layer (3300) operating as the heat dissipation layer can prevent heat-induced deterioration of the semiconductor integrated device (1) by diffusing heat to the outside so that the inside of the semiconductor integrated device (1) is not maintained at a high temperature.

[0100] That is, the first diamond layer (2300) and the second diamond layer (3300) according to one embodiment of the present invention can act as heat dissipation layers, thereby having the effect of improving the lifespan of the semiconductor integrated device (1).

[0102] FIG. 2 schematically illustrates a method for manufacturing a semiconductor integrated device (1) according to one embodiment of the present invention.

[0104] According to one embodiment of the present invention, a method for manufacturing a semiconductor integrated device (1) based on nitride and diamond may include: a substrate layer preparation step (S10) for preparing a substrate layer (1000); a nitride FET formation step (S20) for forming a nitride FET (2000) in a portion of the substrate layer (1000); and a diamond FET formation step (S30) for forming a diamond FET (3000) in another portion of the substrate layer (1000).

[0105] According to one embodiment of the present invention, the substrate layer (1000) may be any one of Al2O3, Si, SiC, and Nitride-based substrates.

[0107] As illustrated in FIG. 2, the method for manufacturing the semiconductor integrated device (1) may include a substrate layer preparation step (S10) in which one of Al2O3, Si, SiC, and Nitride-based substrates is selected and prepared. By performing the substrate layer preparation step (S10), a substrate layer (1000) on which the nitride FET (2000) and the diamond FET (3000) are to be formed may be prepared. After the substrate layer preparation step (S10) is performed, in one embodiment of the present invention, a nitride FET formation step (S20) may be performed to form the nitride FET (2000) on a portion of the substrate layer (1000), and a diamond FET formation step (S30) may be performed to form the diamond FET (3000) on another portion of the substrate layer (1000) where the nitride FET (2000) is not formed. A more detailed description of each of the above nitride FET formation step (S20) and diamond FET formation step (S30) will be provided in the drawings described later.

[0109] FIG. 3 schematically illustrates a nitride FET formation step (S20) according to one embodiment of the present invention, and FIG. 4 schematically illustrates a first multilayer formation step (S21) of the nitride FET formation step (S20) according to one embodiment of the present invention.

[0111] According to one embodiment of the present invention, the nitride FET formation step (S20) comprises aluminum gallium nitride (Al) with a different detailed composition. x Ga 1-x The method may include detailed steps of: a first multilayer forming step (S21) for forming a first multilayer (2100) comprising a plurality of layers made of N); a first insulating layer placement step (S22) for placing a first insulating layer (2200) on the first multilayer (2100); and a first electrode forming step (S24).

[0112] According to one embodiment of the present invention, the nitride FET forming step may further include a detailed step of a first diamond layer placement step (S23) of placing a first diamond layer (2300) on the first insulating layer (2200).

[0113] Additionally, according to one embodiment of the present invention, the first multilayer forming step (S21) may further include detailed steps of: a first buffer layer placement step (S21-1); a first channel layer placement step (S21-2) for placing a first channel layer (2120) on the first buffer layer (2110); a first barrier layer placement step (S21-3) for placing a first barrier layer (2130) on the first channel layer (2120); and a first capping layer placement step (S21-4) for placing a first capping layer (2140) on the first barrier layer (2130).

[0115] As illustrated in FIGS. 3 and 4, the nitride FET forming step (S20) includes a first multilayer forming step (S21), a first insulating layer placement step (S22), a first diamond layer placement step (S23), and a first electrode forming step (S24), and the first multilayer forming step (S21) may include a first buffer layer placement step (S21-1), a first channel layer placement step (S21-2), a first barrier layer placement step (S21-3), and a first capping layer placement step (S21-4).

[0117] According to one embodiment of the present invention, the first buffer layer (2110), the first channel layer (2120), the first barrier layer (2130), and the first capping layer (2140) can each be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C.

[0118] According to one embodiment of the present invention, the first buffer layer (2110) may be formed with a thickness of 1 to 2 μm, the first channel layer (2120) may be formed with a thickness of 100 to 500 nm, the first barrier layer (2130) may be formed with a thickness of 100 to 300 nm, and the first capping layer (2140) may be formed with a thickness of 100 to 200 nm.

[0120] Specifically, the nitride FET formation step (S20) can place the first buffer layer (2110) on the substrate layer (1000) by performing the first buffer layer placement step (S21-1), which corresponds to the first step of the first multilayer formation step (S21). Preferably, the first buffer layer (2110) can be formed at a growth rate of 0.01 to 1000 μm / hr when a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C are applied, and can have a thickness of 1 to 2 μm.

[0121] When the first buffer layer (2110) is formed, a first channel layer placement step (S21-2) of placing the first channel layer (2120) on the first buffer layer (2110) may be performed. Preferably, the first channel layer (2120) may be formed with a thickness of 100 to 500 nm, and the formation conditions of the first channel layer (2120) may correspond to the formation conditions of the first buffer layer (2110), such as a pressure of 0 to 1000 torr, a temperature of 400 to 1500°C, and a growth rate of 0.01 to 1000 μm / hr.

[0122] A first barrier layer placement step (S21-3) may be performed in which a first barrier layer (2130) having a thickness of 100 to 300 nm is placed on top of the first channel layer (2120), and the formation conditions of the first barrier layer (2130) may correspond to the formation conditions of the first channel layer (2120).

[0123] The first capping layer (2140) disposed on the first barrier layer (2130) can be formed by performing the first capping layer placement step (S21-4), and the formation conditions of the first capping layer (2140) correspond to the formation conditions of the first barrier layer (2130), and the first capping layer (2140) may have a thickness of 100 to 200 nm. That is, the formation conditions of each of the first buffer layer (2110), the first channel layer (2120), the first barrier layer (2130), and the first capping layer (2140) include pressure, temperature, and growth rate, and the respective formation conditions including pressure, temperature, and growth rate may be identical to each other.

[0124] According to one embodiment of the present invention, the first buffer layer placement step (S21-1), the first channel layer placement step (S21-2), the first barrier layer placement step (S21-3), and the first capping layer placement step (S21-4) may be performed by a thin film deposition process including chemical vapor deposition (CVD). As described above, each of the first buffer layer (2110), the first channel layer (2120), the first barrier layer (2130), and the first capping layer (2140) may include gallium aluminum nitride with different detailed compositions, and the formation conditions of the first buffer layer (2110), the first channel layer (2120), the first barrier layer (2130), and the first capping layer (2140) may correspond to each other with respect to pressure conditions, temperature conditions, and growth rate conditions.

[0126] In the first multilayer formation step (S21), the first capping layer placement step (S21-4) is performed, thereby allowing the first multilayer (2100) of the nitride FET (2000) to be formed on the substrate layer (1000). The first insulating layer placement step (S22) in which the first insulating layer (2200) is placed on the first multilayer (2100) may be performed, and the first diamond layer placement step (S23) in which the first diamond layer (2300) is placed on the first insulating layer (2200) may be performed. As described above, the first insulating layer (2200) is SiN y By including one or more of SiO2, an environment can be provided where a diamond thin film can be deposited on the upper side. That is, the first insulating layer (2200) can serve as a base layer for the growth of the first diamond layer (2300).

[0128] According to one embodiment of the present invention, the first diamond layer (2300) can be formed by applying a diamond seed on the first insulating layer (2200) and growing it by chemical vapor deposition (CVD) at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C.

[0130] Specifically, the first diamond layer placement step (S23) can be performed by applying the diamond seed onto the first insulating layer (2200) and growing the diamond seed by the chemical vapor deposition method to form the first diamond layer (2300). The first diamond layer placement step (S23) can be performed under atmospheric conditions including methane (CH4), oxygen (O2), argon (Ar), nitrogen (N2), and hydrogen (H2) gases.

[0132] Meanwhile, when the first diamond layer placement step (S23) is completed, a first electrode formation step (S24) for forming the first electrode (2400) may be performed. As described above, the first electrode (2400) includes a first source (2410), a first gate (2420), and a first drain (2430), and can be formed by etching a portion of the first diamond layer (2300) and the first insulating layer (2200) to expose a first capping layer (2140) and depositing a metal on the exposed first capping layer (2140). That is, the first electrode formation step (S24) includes a process of etching a portion of the first diamond layer (2300) and the first insulating layer (2200) to correspond to the shape of the first electrode (2400), and when the etching of the first diamond layer (2300) and the first insulating layer (2200) is completed and a portion of the upper side of the first capping layer (2140) is exposed, a process of depositing metal on a portion of the upper side of the exposed first capping layer (2140) can be performed to form the first electrode (2400).

[0134] FIG. 5 schematically illustrates a diamond FET formation step (S30) according to one embodiment of the present invention, and FIG. 6 schematically illustrates a second multilayer formation step (S31) of the diamond FET formation step (S30) according to one embodiment of the present invention.

[0136] According to one embodiment of the present invention, the diamond FET forming step (S30) comprises aluminum gallium nitride (Al) with a different detailed composition. x Ga 1-xA method for manufacturing a semiconductor integrated device (1) is provided, comprising: a second multilayer forming step (S31) for forming a second multilayer (3100) comprising a plurality of layers made of N); a second insulating layer placement step (S32) for placing a second insulating layer (3200) on the second multilayer (3100); a second diamond layer placement step (S33) for placing a second diamond layer (3300) on the second insulating layer (3200); and a second electrode forming step (S34) for forming a second electrode (3400) on the second diamond layer (3300); wherein the semiconductor integrated device (1) electrically connects the first electrode (2400) and the second electrode (3400) to form an integrated circuit.

[0137] Additionally, according to one embodiment of the present invention, the second multilayer forming step (S31) may include: a second buffer layer placement step (S31-1); a second channel layer placement step (S31-2) for placing a second channel layer (3120) on the second buffer layer (3110); a second barrier layer placement step (S31-3) for placing a second barrier layer (3130) on the second channel layer (3120); and a second capping layer placement step (S31-4) for placing a second capping layer (3140) on the second barrier layer (3130).

[0139] As illustrated in FIGS. 5 and 6, the nitride FET forming step (S20) includes a second multilayer forming step (S31), a second insulating layer placement step (S32), a second diamond layer placement step (S33), and a second electrode forming step (S34), and the second multilayer forming step (S31) may include a second buffer layer placement step (S31-1), a second channel layer placement step (S31-2), a second barrier layer placement step (S31-3), and a second capping layer placement step (S31-4).

[0141] According to one embodiment of the present invention, the second buffer layer (3110), the second channel layer (3120), the second barrier layer (3130), and the second capping layer (3140) can each be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C.

[0142] According to one embodiment of the present invention, the second buffer layer (3110) may be formed with a thickness of 1 to 2 μm, the second channel layer (3120) may be formed with a thickness of 100 to 500 nm, the second barrier layer (3130) may be formed with a thickness of 100 to 300 nm, and the second capping layer (3140) may be formed with a thickness of 100 to 200 nm.

[0144] Specifically, the diamond FET formation step (S30) can place the second buffer layer (3110) on the substrate layer (1000) by performing the second buffer layer placement step (S31-1), which corresponds to the first step of the second multilayer formation step (S31). Preferably, the second buffer layer (3110) can be formed at a growth rate of 0.01 to 1000 μm / hr when a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C are applied, and can have a thickness of 1 to 2 μm.

[0145] When the second buffer layer (3110) is formed, a second channel layer placement step (S31-2) may be performed to place the second channel layer (3120) on the second buffer layer (3110). Preferably, the second channel layer (3120) may be formed with a thickness of 100 to 500 nm, and the formation conditions of the second channel layer (3120) may correspond to the formation conditions of the second buffer layer (3110), such as a pressure of 0 to 1000 torr, a temperature of 400 to 1500°C, and a growth rate of 0.01 to 1000 μm / hr.

[0146] A second barrier layer placement step (S31-3) may be performed in which a second barrier layer (3130) having a thickness of 100 to 300 nm is placed on top of the second channel layer (3120), and the formation conditions of the second barrier layer (3130) may correspond to the formation conditions of the second channel layer (3120). A second capping layer (3140) placed on top of the second barrier layer (3130) may be formed by performing the second capping layer placement step (S31-4), and the formation conditions of the second capping layer (3140) may correspond to the formation conditions of the second barrier layer (3130), and the second capping layer (3140) may have a thickness of 100 to 200 nm.

[0147] That is, the respective formation conditions of the second buffer layer (3110), the second channel layer (3120), the second barrier layer (3130), and the second capping layer (3140) include pressure, temperature, and growth rate, and the respective formation conditions including pressure, temperature, and growth rate may be the same as each other.

[0149] According to one embodiment of the present invention, the second buffer layer placement step (S31-1), the second channel layer placement step (S31-2), the second barrier layer placement step (S31-3), and the second capping layer placement step (S31-4) may be performed by a thin film deposition process including chemical vapor deposition (CVD). As described above, each of the second buffer layer (3110), the second channel layer (3120), the second barrier layer (3130), and the second capping layer (3140) may include gallium aluminum nitride with different detailed compositions, and the formation conditions of the second buffer layer (3110), the second channel layer (3120), the second barrier layer (3130), and the second capping layer (3140) may correspond to each other with respect to pressure conditions, temperature conditions, and growth rate conditions.

[0151] By performing the second capping layer placement step (S31-4), the second multilayer (3100) of the diamond FET (3000) can be formed on the substrate layer (1000). The second insulating layer placement step (S32) in which the second insulating layer (3200) is placed on the second multilayer (3100) can be performed, and the second diamond layer placement step (S33) in which the second diamond layer (3300) is placed on the second insulating layer (3200) can be performed. As described above, the second insulating layer (3200) is SiN y By including one or more of SiO2, an environment can be provided where a diamond thin film can be deposited on the upper side. That is, the second insulating layer (3200) can serve as a base layer for the growth of the second diamond layer (3300).

[0153] According to one embodiment of the present invention, the second diamond layer (3300) can be formed by applying a diamond seed on the second insulating layer (3200) and growing it by chemical vapor deposition (CVD) at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C.

[0155] Specifically, the second diamond layer placement step (S33) can be performed by applying the diamond seed onto the second insulating layer (3200) and growing the diamond seed by the chemical vapor deposition method to form the second diamond layer (3300). The second diamond layer placement step (S33) can be performed under atmospheric conditions including methane (CH4), oxygen (O2), argon (Ar), nitrogen (N2), and hydrogen (H2) gases.

[0156] In addition, according to one embodiment of the present invention, in the second diamond layer placement step (S33), a hydrogen plasma treatment step of treating the second diamond layer (3300) with hydrogen plasma may be further performed. A more detailed description of the hydrogen plasma treatment will be provided in the drawings described later.

[0158] When the second diamond layer placement step (S33) is completed, a second electrode formation step (S34) for forming the second electrode (3400) may be performed. As described above, the second electrode (3400) may be formed on the second diamond layer (3300) and may include the second source (3410), the second gate (3420), and the second drain (3430). The second drain (3430) may be electrically connected to the first drain (2430) of the first electrode (2400), and the second gate (3420) may be electrically connected to the first gate (2420) to form the semiconductor integrated device (1) in which an integrated circuit is formed.

[0160] According to one embodiment of the present invention, the first multilayer formation step (S21) and the second multilayer formation step (S31) may be performed simultaneously. Specifically, the first buffer layer placement step (S21-1) and the second buffer layer placement step (S31-1) may be performed simultaneously as corresponding buffer layer placement steps, and the first channel layer placement step (S21-2) and the second channel layer placement step (S31-2) may also be performed simultaneously as corresponding channel layer placement steps, and the first barrier layer placement step (S21-3) and the second barrier layer placement step (S31-3) may be performed simultaneously as corresponding barrier layer placement steps, and the first capping layer placement step (S21-4) and the second capping layer placement step (S31-4) may be performed simultaneously as corresponding capping layer placement steps. That is, the first buffer layer placement step (S21-1) and the second buffer layer placement step (S31-1) may be the same buffer layer placement step, the first channel layer placement step (S21-2) and the second channel layer placement step (S31-2) may be the same channel layer placement step, the first barrier layer placement step (S21-3) and the second barrier layer placement step (S31-3) may be the same barrier layer placement step, and the first capping layer placement step (S21-4) and the second capping layer placement step (S31-4) may be the same capping layer placement step.

[0161] Each layer formed by the buffer layer placement step, channel layer placement step, barrier layer placement step, and capping layer placement step may be a single connected layer rather than separate layers separated as the first multilayer (2100) and the second multilayer (3100). For example, the layer formed by the buffer layer placement step may be a single buffer layer formed by combining the first buffer layer (2110) and the second buffer layer (3110), rather than two layers separated as the first buffer layer (2110) and the second buffer layer (3110). That is, the first multilayer (2100) and the second multilayer (3100) formed by the buffer layer placement step, channel layer placement step, barrier layer placement step, and capping layer placement step may be a single connected layer. In addition, the above-mentioned single layer can be separated into a first layer (2100) and a second layer (3100) that are placed adjacent to each other by an etching process after being formed.

[0163] FIG. 7 schematically illustrates the structure of a semiconductor integrated device (1) including an oxide film layer (O) according to one embodiment of the present invention.

[0165] According to one embodiment of the present invention, the diamond FET (3000) further comprises an oxide film layer (O) formed on the second diamond layer (3300); and the oxide film layer (O) may comprise one or more of Al2O3, SiO2, HfO2, MoO3, V2O5, and WO3.

[0166] According to one embodiment of the present invention, the first diamond layer (2300) and the second diamond layer (3300) may be subjected to hydrogen plasma treatment on their upper sides by applying a plasma power of 0.5 to 100 KW in an environment with a hydrogen content of 0.1 to 50%, and an oxide film layer (O) may be disposed on the upper side of the hydrogen plasma-treated second diamond layer (3300).

[0168] FIG. 7(a) schematically illustrates a top view of a semiconductor integrated device (1) including the oxide layer (O), and FIG. 7(b) schematically illustrates a front view of a semiconductor integrated device (1) including the oxide layer (O).

[0170] As illustrated in FIG. 7(a) and FIG. 7(b), a semiconductor integrated device (1) according to one embodiment of the present invention may further include an oxide layer (O) between the second diamond layer (3300) and the second electrode (3400). Hereinafter, the semiconductor integrated device (1) including the oxide layer (O) is referred to as Example #1.

[0172] As described above, the hydrogen plasma treatment may be further performed on the second diamond layer (3300) included in the above Example #1 during the second diamond layer placement step (S33). The hydrogen plasma treatment may be performed by placing the above Example #1 inside a plasma treatment apparatus including the chemical vapor deposition (CVD) method during the second diamond layer placement step (S33), and applying a plasma power of 0.5 to 100 KW in an environment with a hydrogen content of 0.1 to 50%.

[0173] As described above, the second diamond layer (3300) comprises diamond, and the diamond corresponds to a single-component material composed of carbon. That is, the second diamond layer (3300) according to one embodiment of the present invention comprises carbon atoms on its surface, and when the hydrogen plasma treatment is performed on the second diamond layer (3300), the carbon atoms included on the surface of the second diamond layer (3300) are combined with hydrogen atoms by the hydrogen plasma, thereby modifying the surface of the second diamond layer (3300). The oxide film layer (O) can be deposited on the second diamond layer (3300) with the surface modified in this manner, and the oxide film layer (O) may comprise one or more of Al2O3, SiO2, HfO2, MoO3, V2O5, and WO3.

[0174] By the above hydrogen plasma treatment and the arrangement of the oxide film layer (O), a two-dimensional hole gas (H) (2DHG, 2 Dimensional Hole Gas) composed of holes can be formed inside the second diamond layer (3300) of Example #1. As shown in FIG. 7(b), the two-dimensional hole gas (H) can be arranged inside the second diamond layer (3300) adjacent to the interface between the second diamond layer (3300) and the oxide film layer (O). A more detailed description of the two-dimensional hole gas (H) will be provided in the drawings described later.

[0176] FIG. 8 schematically illustrates the process of forming a two-dimensional hole gas (H) according to one embodiment of the present invention.

[0178] FIG. 8(a) schematically illustrates the band structure of the second diamond layer (3300) in which the hydrogen plasma treatment is not performed, FIG. 8(b) schematically illustrates the band structure of the second diamond layer (3300) in which the hydrogen plasma treatment is performed, and FIG. 8(c) schematically illustrates the band structure in which the oxide film layer (O) is placed on the second diamond layer (3300) in which the hydrogen plasma treatment is performed.

[0180] As described above, according to one embodiment of the present invention, the second diamond layer (3300) is treated with hydrogen plasma, and an oxide film layer (O) is disposed on the upper side, thereby forming a two-dimensional hole gas (H) (2DHG, 2 Dimensional Hole Gas) composed of holes that is disposed adjacent to the interface between the second diamond layer (3300) and the oxide film layer (O) on the inner side of the second diamond layer (3300).

[0181] As shown in FIG. 8(a), when hydrogen plasma treatment is not performed on the second diamond layer (3300), the second diamond layer (3300) may have an unbent band structure. However, when hydrogen plasma treatment is performed on the second diamond layer (3300), the surface of the second diamond layer (3300) may be modified by the combination of a plurality of carbon atoms disposed on the upper surface of the second diamond layer (3300) with a plurality of hydrogen atoms through the hydrogen plasma treatment, and a band bending phenomenon may occur as shown in FIG. 8(b).

[0182] The plurality of hydrogen atoms disposed on the modified surface of the second diamond layer (3300) may have an electrical attraction, and the plurality of electrons disposed on the inner side of the second diamond layer (3300) may move toward the modified surface of the second diamond layer (3300) by the plurality of hydrogen atoms. At this time, the plurality of electrons moving due to the electrical attraction of the plurality of hydrogen atoms may be limited to electrons disposed on the inner side adjacent to the modified surface of the second diamond layer (3300). As the plurality of electrons move toward the modified surface of the second diamond layer (3300), a plurality of holes may be formed on the inner side of the second diamond layer (3300) where the plurality of electrons were previously disposed. That is, a plurality of holes may be disposed on the inner side adjacent to the modified surface of the second diamond layer (3300).

[0183] Meanwhile, the oxide film layer (O) can be further disposed on the second diamond layer (3300) on which the hydrogen plasma treatment has been performed to form Example #1. As shown in FIG. 8(c), in the case of Example #1, the band of the second diamond layer (3300) may have a more curved shape than in FIG. 8(b). Due to the electromagnetic attraction between a plurality of hydrogen atoms disposed on the surface of the second diamond layer (3300) and the oxide film layer (O), a large number of electrons disposed inside the second diamond layer (3300) move toward the oxide film layer (O), thereby allowing a larger number of holes to be disposed inside the second diamond layer (3300) than in FIG. 8(b). That is, a layer composed of holes can be formed within a certain distance range from the surface of the second diamond layer (3300), and the layer composed of holes corresponds to the two-dimensional hole gas (H).

[0184] The above two-dimensional hole gas (H) can operate as a channel through which holes can move within the diamond FET (3000). Since the above two-dimensional hole gas (H) is formed inside the diamond FET (3000) of Example #1 even when no voltage is applied to the second electrode (3400), the diamond FET (3000) of Example #1 can function as a D-mode P-channel FET that maintains an always-on state by including a channel through which holes can move even when no voltage is applied.

[0186] That is, the diamond FET (3000) according to one embodiment of the present invention can improve hole mobility by including a channel composed of a two-dimensional hole gas (H), thereby having the effect of improving the performance of the semiconductor integrated device (1).

[0188] FIG. 9 schematically illustrates the process of forming a two-dimensional electron gas (E) according to one embodiment of the present invention.

[0190] FIG. 9(a) illustrates the band structure of each of the first channel layer (2120) and the first barrier layer (2130) according to one embodiment of the present invention, and FIG. 9(b) illustrates the band bending phenomenon occurring in the first barrier layer (2130) when the first barrier layer (2130) is placed on the first channel layer (2120).

[0192] According to one embodiment of the present invention, the first channel layer (2120) may include a two-dimensional electron gas (E) (2DEG, 2 Dimensional Electron Gas) composed of electrons in an inner region of the first channel layer (2120) adjacent to an upper interface where the first barrier layer (2130) is disposed, and the second channel layer (3120) may include a two-dimensional electron gas (E) composed of electrons in an inner region of the second channel layer (3120) adjacent to an upper interface where the second barrier layer (3130) is disposed.

[0194] As described above, the first channel layer (2120) and the first barrier layer (2130) may include aluminum gallium nitride having different detailed compositions. In addition, according to one embodiment of the present invention, aluminum gallium nitride (Al) included in the first channel layer (2120) x Ga 1-x The x value corresponding to the aluminum composition of N) is aluminum gallium nitride (Al) included in the first barrier layer (2130). x Ga 1-x It can have a value smaller than the x value of N).

[0195] As illustrated in FIG. 9(a), when the detailed composition of the gallium aluminum nitride contained in each of the first channel layer (2120) and the first barrier layer (2130) is different, and thus the first channel layer (2120) and the first barrier layer (2130) are not arranged adjacent to each other but exist as separate layers, the Fermi energy level (E) of the first channel layer (2120) fThe Fermi energy levels of the first barrier layer (2130) and the above barrier layer (2130) can be placed at different locations.

[0196] Meanwhile, as illustrated in FIG. 9(b), when the first barrier layer (2130) is placed on the first channel layer (2120), the Fermi energy level of the first channel layer (2120) and the Fermi energy level of the first barrier layer (2130) have a tendency to align at corresponding positions, so a band bending phenomenon may occur at the interface where the first channel layer (2120) and the first barrier layer (2130) are placed adjacent to each other. Due to the band bending phenomenon, a quantum well may be formed between the first barrier layer (2130) and the first channel layer (2120). Electrons that have crossed over to the interface between the first barrier layer (2130) and the first channel layer (2120) are trapped in the quantum well, and thus a two-dimensional electron gas (E) in which a plurality of electrons are placed may be formed in the region where the quantum well is formed. The above two-dimensional electron gas (E) may exist in the form of a layer that is positioned inside the interface of the first channel layer (2120) bonded with the first barrier layer (2130) and can only move in a horizontal direction relative to the surface of the first channel layer (2120), thereby operating as a channel through which electrons move and allowing current to flow in the first channel layer (2120).

[0197] The above two-dimensional electron gas (E) is formed inside the nitride FET (2000) included in Example #1 even when no voltage is applied to the first electrode (2400). That is, the nitride FET (2000) can function as a D-mode N-channel FET that maintains an always-on state by including a channel through which electrons can move even when no voltage is applied to the first electrode (2400).

[0199] That is, the first channel layer (2120) according to one embodiment of the present invention can have the effect of improving electrical conductivity by including the two-dimensional electron gas (E).

[0200] In addition, the nitride FET (2000) according to one embodiment of the present invention can improve the electrical performance of the semiconductor integrated device (1) by improving electron mobility and reducing switching losses through the two-dimensional electron gas (E).

[0202] FIG. 10 schematically illustrates a diamond FET (3000) according to one embodiment of the present invention and the voltage-current characteristics of the diamond FET (3000), and FIG. 11 schematically illustrates a nitride FET (2000) according to one embodiment of the present invention and the voltage-current characteristics of the nitride FET (2000).

[0204] FIG. 10(a) illustrates a diamond FET (3000) according to one embodiment of the present invention, and FIG. 10(b) illustrates the current-voltage characteristic measurement results of the diamond FET (3000).

[0206] The diamond FET (3000) included in the above embodiment #1 may have a shape as shown in FIG. 10(a). Additionally, as shown in FIG. 10(b), the diamond FET (3000) has a drain-source voltage (V) applied to the second drain (3430). DS When the value increases, it can be confirmed that it has the characteristics of a typical P-channel FET, which exhibits a linear region where the current flowing through the channel increases up to a certain value, and a saturation region where the current no longer increases from the moment the drain-source voltage exceeds a certain value.

[0208] FIG. 11(a) illustrates a nitride FET (2000) according to one embodiment of the present invention, and FIG. 11(b) illustrates the current-voltage characteristic measurement results of the nitride FET (2000).

[0209] The nitride FET (2000) included in the above Example #1 may have a shape as shown in FIG. 11(a). Additionally, as shown in FIG. 11(b), the nitride FET (2000) has a drain-source voltage (V) applied to the first drain (2430). DS When the drain-source voltage increases, it can be confirmed that it has the characteristics of a typical N-channel FET, which exhibits a linear region where the drain current increases up to a certain value, and a saturation region where the increase in the drain current decreases rapidly from the moment the drain-source voltage exceeds a certain value.

[0210] Accordingly, the semiconductor integrated circuit (1) according to one embodiment of the present invention includes characteristics corresponding to conventionally used CMOS, so it can be used as a substitute for conventional CMOS.

[0212] FIG. 12 schematically illustrates the structure of a semiconductor integrated device (1) further comprising a p-aluminum nitride gallium layer (2141) according to one embodiment of the present invention, and FIG. 13 schematically illustrates the structure of a semiconductor integrated device (1) further comprising an oxide film layer (O) according to one embodiment of the present invention.

[0214] According to one embodiment of the present invention, the nitride FET (2000) may further include a p-aluminum gallium nitride layer (2141) formed between the first gate (2420) and the first capping layer (2140).

[0215] Additionally, according to one embodiment of the present invention, the nitride FET (2000) may further include an oxide layer (O) formed between the first gate (2420) and the first capping layer (2140).

[0217] As described above, the above embodiment #1 includes the two-dimensional electron gas (E) and two-dimensional hole gas (H), and the nitride FET (2000) and diamond FET (3000) can each operate as a d-mode N-channel FET and a d-mode P-channel FET, respectively, in an always-on state. Meanwhile, in the present invention, in addition to the semiconductor integrated device (1) in an always-on state, a semiconductor integrated device (1) utilizing an e-mode FET in an always-off state is formed, thereby manufacturing a plurality of embodiments of semiconductor integrated devices (1) that can be applied in parallel with each other, and these embodiments are illustrated in FIGS. 12 and 13.

[0219] FIG. 12(a) schematically illustrates a top view of a semiconductor integrated device (1) further comprising a p-aluminum nitride gallium layer (2141) according to one embodiment of the present invention, and FIG. 12(b) schematically illustrates a front view of a semiconductor integrated device (1) further comprising a p-aluminum nitride gallium layer (2141) according to one embodiment of the present invention.

[0221] Hereinafter, a semiconductor integrated device (1) further comprising a p-aluminum nitride gallium layer (2141) according to one embodiment of the present invention will be referred to as Example #2.

[0222] As illustrated in FIG. 12(a) and FIG. 12(b), according to one embodiment of the present invention, the nitride FET (2000) may further include a p-aluminum gallium nitride layer (2141) formed on the upper side of the first barrier layer (2130) without including the first capping layer (2140). Additionally, the diamond FET (3000) may not include the second capping layer (3140), and the oxide layer (O) may be formed only on the lower side of the second gate (3420).

[0223] According to one embodiment of the present invention, the embodiment #2 may further include a p-aluminum gallium nitride layer (2141) between the first gate (2420) and the first barrier layer (2130). Additionally, the diamond FET (3000) of the embodiment #2 may further include an oxide layer (O) formed between the second diamond layer (3300) and the second gate (3420).

[0224] The p-aluminum gallium nitride layer (2141) may include p-type doped aluminum gallium nitride. Additionally, the p-aluminum gallium nitride layer (2141) can form a state in which a preset voltage is applied to the first gate (2420) of Example #2 even when no external voltage is applied, by acting as an internal negative battery for the nitride FET (2000).

[0225] That is, the channel formed by the two-dimensional electron gas (E) included in the nitride FET (2000) of Example #2 can be switched to an off state by the p-aluminum gallium nitride layer (2141). Therefore, the nitride FET (2000) of Example #2 operates as an e-mode N-channel FET in which the channel is always off and becomes on when an external voltage is applied, and the diamond FET (3000) included in Example #2 can operate as a d-mode P-channel FET in which the channel is always on.

[0227] Meanwhile, FIG. 13(a) schematically illustrates a top view of a semiconductor integrated device (1) further including an oxide layer (O) according to one embodiment of the present invention, and FIG. 13(b) schematically illustrates a front view of a semiconductor integrated device (1) further including an oxide layer (O).

[0229] As illustrated in FIG. 13(a) and FIG. 13(b), a semiconductor integrated device (1) according to one embodiment of the present invention may form an oxide layer (O) on the upper side of the partially etched first barrier layer (2130) after partially etching the first insulating layer (2200), the first capping layer (2140), and the first barrier layer (2130), and may form a first gate (2420) on the oxide layer (O). The first source (2410) and the first drain (2430) may be formed on the partially etched first capping layer (2140). Hereinafter, the semiconductor integrated device (1) illustrated in FIG. 13 will be referred to as Example #3.

[0230] As described above, the nitride FET (2000) of Example #3 further includes an oxide layer (O) between the first gate (2420) and the first barrier layer (2130), and the diamond FET (3000) of Example #3 may further include an oxide layer (O) formed between the second diamond layer (3300) and the second gate (3420).

[0231] As described above, the two-dimensional hole gas (H) can be formed inside the diamond FET (3000) and operate as a channel through which holes can move even when no voltage is applied to the second electrode (3400). The diamond FET (3000) of Example #3 includes an oxide layer (O) and includes a two-dimensional hole gas (H) formed inside the second diamond layer (3300). Accordingly, the diamond FET (3000) of Example #3 can function as a D-mode P-channel FET that maintains an always-on state.

[0232] Meanwhile, the oxide layer (O) included between the first gate (2420) and the first barrier layer (2130) of the nitride FET (2000) may not function as an internal negative battery for the nitride FET (2000), unlike the p-aluminum gallium nitride layer (2141) described in FIG. 12. Therefore, the two-dimensional electron gas (E) formed inside the first channel layer (2120) of Example #3 can operate as a channel through which electrons can move. That is, the nitride FET (2000) of Example #3 can operate as a d-mode N-channel FET that maintains an always-on state.

[0234] A semiconductor integrated device (1) according to one embodiment of the present invention can have the effect of expanding the application range of the semiconductor integrated device (1) by controlling whether it is in e-mode and d-mode through the stacked structure of the nitride FET (2000) and the diamond FET (3000).

[0236] According to one embodiment of the present invention, a semiconductor integrated device includes a first diamond layer capable of acting as a heat dissipation layer, thereby improving heat resistance performance and preventing degradation due to high temperature during device operation, which extends the lifespan of the semiconductor integrated device and enables operation in extreme environments such as high temperature, thereby providing an effect of improving economic efficiency.

[0237] According to one embodiment of the present invention, a semiconductor integrated device can improve the usability of the device by using an ultrawide bandgap material to improve the breakdown voltage characteristics of the semiconductor integrated device.

[0238] According to one embodiment of the present invention, each of the first multilayer and the second multilayer is composed of a plurality of layers, and the plurality of layers include aluminum gallium nitride having different detailed compositions, thereby forming a two-dimensional electric gas inside to improve the performance of the semiconductor integrated device.

[0239] According to one embodiment of the present invention, the first insulating layer and the second insulating layer are SiN y By including one or more of SiO2, an environment is provided where a diamond thin film can be deposited on the upper side, thereby enabling the formation of a first diamond layer and a second diamond layer, which can have the effect of improving the manufacturing convenience of a semiconductor integrated device.

[0240] According to one embodiment of the present invention, a diamond FET can improve hole mobility by including a channel composed of two-dimensional hole gas, thereby exhibiting the effect of improving the performance of a semiconductor integrated device.

[0241] According to one embodiment of the present invention, the first channel layer can have the effect of improving electrical conductivity by including a two-dimensional electron gas.

[0242] According to one embodiment of the present invention, a nitride FET can improve the electrical performance of a semiconductor integrated device by improving electron mobility and reducing switching losses through a two-dimensional electron gas.

[0243] According to one embodiment of the present invention, the semiconductor integrated device can expand the application range of the semiconductor integrated device by controlling whether it is in e-mode and d-mode through a stacked structure of nitride FETs and diamond FETs.

[0245] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents. Therefore, other implementations, other embodiments, and equivalents to the claims below are also within the scope of the claims. Explanation of the symbols

[0247] 1 : Semiconductor integrated circuit 1000 : Substrate layer 2000 : Nitride FET 2100 : First multilayer 2110: 1st buffer layer 2120: 1st channel layer 2130: First barrier layer 2140: First capping layer 2141 : p-Gallium aluminum nitride layer 2200 : First insulating layer 2300: First diamond layer 2400: First electrode 2410: Source 1 2420: Gate 1 2430: 1st Drain 3000: Diamond FET 3100 : 2nd Multilayer 3110 : 2nd Buffer Layer 3120: Second channel layer 3130: Second barrier layer 3140 : Second capping layer 3200 : Second insulation layer 3300 : Second diamond layer 3400 : Second electrode 3410 : Second Source 3420 : Second Gate 3430 : 2nd Drain O: Oxide layer E: Two-dimensional electron gas H: 2D hole gas S10: Substrate layer preparation step S20: Nitride FET formation step S21: First multilayer formation step S21-1: First buffer layer placement step S21-2: First channel layer placement step S21-3: First barrier layer placement step S21-4: First capping layer placement step S22: First insulation layer placement step S23: First diamond layer placement step S24: First electrode formation step S30: Diamond FET formation step S31: Second multilayer formation step S31-1: Second buffer layer placement step S31-2: Second channel layer placement step S31-3: Second barrier layer placement step S31-4: Second capping layer placement step S32: Second insulation layer placement step S33: Second diamond layer placement step S34: Second electrode formation step

Claims

Claim 1 A nitride and diamond-based semiconductor integrated circuit comprises: a substrate layer; a nitride FET formed in a portion of the substrate layer; and a diamond FET formed in another portion of the substrate layer; wherein the nitride FET comprises aluminum gallium nitride (Al) with a different detailed composition. x Ga 1-x A first multilayer comprising a plurality of layers made of N); a first insulating layer disposed on the first multilayer; and a first electrode; wherein the diamond FET comprises aluminum gallium nitride (Al) having a different detailed composition x Ga 1-x A semiconductor integrated device comprising: a second multilayer including a plurality of layers made of N; a second insulating layer disposed on the second multilayer; a second diamond layer disposed on the second insulating layer; and a second electrode formed on the second diamond layer; wherein the semiconductor integrated device electrically connects the first electrode and the second electrode to form an integrated circuit, the second diamond layer includes diamond, and when hydrogen plasma treatment is performed and an oxide film layer is formed thereon, a two-dimensional hole gas (2DHG) is formed inside. Claim 2 A semiconductor integrated device according to claim 1, wherein the first multilayer of the nitride FET comprises: a first buffer layer; a first channel layer disposed on the first buffer layer; a first barrier layer disposed on the first channel layer; and a first capping layer disposed on the first barrier layer; and the second multilayer of the diamond FET comprises: a second buffer layer; a second channel layer disposed on the second buffer layer; a second barrier layer disposed on the second channel layer; and a second capping layer disposed on the second barrier layer. Claim 3 In claim 2, the first buffer layer, first channel layer, first barrier layer, and first capping layer of the nitride FET are each Al x Ga 1-x Aluminum gallium nitride represented by the chemical formula N, comprising aluminum gallium nitride (Al) included in each of the two layers disposed adjacent to each other among the first channel layer, the first barrier layer, and the first capping layer. x Ga 1-x N) has different x values, and the aluminum gallium nitride (Al) included in the first channel layer x Ga 1-x The x value of N) is the aluminum gallium nitride (Al) included in the first barrier layer. x Ga 1-x The second buffer layer, second channel layer, second barrier layer, and second capping layer of the diamond FET are each smaller than the x value of N), and Al x Ga 1-x Aluminum gallium nitride represented by the chemical formula N, comprising aluminum gallium nitride (Al) included in each of the two layers disposed adjacent to each other among the second channel layer, the second barrier layer, and the second capping layer. x Ga 1-x N) has different x values, and the aluminum gallium nitride (Al) included in the second channel layer x Ga 1-x The x value of N) is the aluminum gallium nitride (Al) included in the second barrier layer. x Ga 1-x The aluminum gallium nitride (Al) contained in the nitride FET and diamond FET, respectively, is smaller than the x value of N) x Ga 1-x A semiconductor integrated circuit in which the x value of N) is 0.1 to 99.

9. Claim 4 A semiconductor integrated device according to claim 1, wherein the nitride FET further comprises a first diamond layer disposed on the first insulating layer. Claim 5 A semiconductor integrated device according to claim 2, wherein the first electrode of the nitride FET is formed by etching a portion of the first insulating layer and depositing a metal on the exposed first capping layer. Claim 6 In claim 1, the first insulating layer and the second insulating layer are each SiN y A semiconductor integrated device comprising one or more of and SiO2. Claim 7 A semiconductor integrated device according to claim 1, wherein the oxide film layer comprises one or more of Al2O3, SiO2, HfO2, MoO3, V2O5, and WO3. Claim 8 A semiconductor integrated device according to claim 4, wherein the first diamond layer is formed by applying a diamond seed on the first insulating layer and growing it by chemical vapor deposition (CVD) at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C, and the second diamond layer is formed by applying a diamond seed on the second insulating layer and growing it by chemical vapor deposition (CVD) at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C. Claim 9 A semiconductor integrated device according to claim 2, wherein the substrate layer is any one of Al2O3, Si, SiC, and a nitride-based substrate, and the first buffer layer, the second buffer layer, the first channel layer, the second channel layer, the first barrier layer, the second barrier layer, the first capping layer, and the second capping layer are each formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C. Claim 10 A semiconductor integrated device according to claim 2, wherein the first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from the first source and the first gate, and the nitride FET further comprises a p-aluminum gallium nitride layer formed between the first gate and the first capping layer. Claim 11 A semiconductor integrated device according to claim 2, wherein the first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from the first source and the first gate, and the nitride FET further comprises an oxide film layer formed between the first gate and the first capping layer, wherein the oxide film layer comprises one or more of Al2O3, SiO2, HfO2, MoO3, V2O5, and WO3. Claim 12 A method for manufacturing a semiconductor integrated device based on nitride and diamond, comprising: a substrate layer preparation step for preparing a substrate layer; a nitride FET formation step for forming a nitride FET in a portion of the substrate layer; and a diamond FET formation step for forming a diamond FET in another portion of the substrate layer; wherein the nitride FET formation step comprises aluminum gallium nitride (Al) with a different detailed composition. x Ga 1-x A first multilayer forming step comprising a plurality of layers made of N) for forming a first multilayer; a first insulating layer placement step for placing a first insulating layer on the first multilayer; and a first electrode forming step; wherein the diamond FET forming step comprises aluminum gallium nitride (Al) with different detailed compositions x Ga 1-x A method for manufacturing a semiconductor integrated device comprising: a second multilayer forming step for forming a second multilayer including a plurality of layers made of N; a second insulating layer placement step for placing a second insulating layer on the second multilayer; a second diamond layer placement step for placing a second diamond layer on the second insulating layer; and a second electrode forming step for forming a second electrode on the second diamond layer; wherein the semiconductor integrated device forms an integrated circuit by electrically connecting the first electrode and the second electrode, the second diamond layer includes diamond, and when hydrogen plasma treatment is performed and an oxide film layer is formed thereon, a two-dimensional hole gas (2DHG) is formed inside. Claim 13 A method for manufacturing a semiconductor integrated device according to claim 12, wherein the nitride FET forming step further comprises a first diamond layer placement step of placing a first diamond layer on the first insulating layer. Claim 14 A method for manufacturing a semiconductor integrated device according to claim 12, wherein the first multilayer forming step comprises: a first buffer layer placement step; a first channel layer placement step for placing a first channel layer on the first buffer layer; a first barrier layer placement step for placing a first barrier layer on the first channel layer; and a first capping layer placement step for placing a first capping layer on the first barrier layer; and the second multilayer forming step comprises: a second buffer layer placement step; a second channel layer placement step for placing a second channel layer on the second buffer layer; a second barrier layer placement step for placing a second barrier layer on the second channel layer; and a second capping layer placement step for placing a second capping layer on the second barrier layer.

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