Integrated Device Based on Diamond and Nitride Formed on Diamond Substrates, and Method of Manufacturing

Abstract

The present invention relates to a diamond and nitride-based integrated device formed on a diamond substrate and a method for manufacturing thereof. More specifically, by using a diamond substrate layer containing diamond as a substrate for the semiconductor integrated device, the invention provides a semiconductor integrated device with improved heat dissipation performance and enhanced productivity by shortening the manufacturing process. In other words, the invention relates to a method for fabricating high-voltage, high-frequency semiconductor devices utilizing the wide bandgap characteristics of diamond and nitride, wherein the excellent heat dissipation characteristics of diamond are utilized to prevent device degradation and enable the fabrication of high-reliability semiconductor devices, and to a diamond and nitride-based integrated device formed on a diamond substrate and a method for manufacturing thereof.

Description

Technology Field

[0001] The present invention relates to a diamond and nitride-based integrated device formed on a diamond substrate and a method for manufacturing thereof, and more specifically, to a diamond and nitride-based integrated device formed on a diamond substrate and a method for manufacturing thereof, wherein the heat dissipation performance is improved and the manufacturing process is shortened to provide a semiconductor integrated device with improved productivity by using a diamond substrate layer containing diamond as a substrate for the semiconductor integrated device. Background Technology

[0003] CMOS (complementary metal-oxide semiconductor) is a semiconductor device manufactured such that P-channel FETs and N-channel FETs are placed adjacently on a single chip, with the gates of the P-channel FETs and N-channel FETs connected to the inputs and the drains connected to the outputs, allowing the two FETs to operate complementarily. CMOS has the advantage of low power consumption and is used as a switching device in most logic circuits.

[0004] Conventional CMOS devices were mostly based on silicon (Si), but due to the characteristics of silicon, conventional silicon-based CMOS devices were difficult to use for high-speed switching, ultra-high voltage, and ultra-high frequency applications, and as device miniaturization progressed, problems such as increased power consumption and intensified heat generation occurred.

[0005] However, the electric vehicle, 5G, and aerospace sectors, where the market is currently expanding rapidly, require semiconductor devices capable of operating in high-voltage and high-frequency environments, possessing high-speed switching performance, and being continuously usable in high-temperature environments. Accordingly, there is a demand for new semiconductor devices to replace silicon-based devices.

[0006] In other words, there is a demand for semiconductor devices and manufacturing technologies capable of operating in extreme environments such as space, by having excellent withstand voltage characteristics, operating at high speeds, and preventing device degradation due to high temperatures. The problem to be solved

[0008] The present invention aims to provide a diamond and nitride-based integrated device formed on a diamond substrate and a method for manufacturing such a semiconductor integrated device that has improved heat dissipation performance and improved productivity by shortening the manufacturing process by using a diamond substrate layer containing diamond as a substrate for the semiconductor integrated device. means of solving the problem

[0010] To solve the above problems, one embodiment of the present invention provides a semiconductor integrated device comprising: a diamond substrate layer including diamond; a nitride semiconductor device formed on the diamond substrate layer; and a diamond semiconductor device; wherein the nitride semiconductor device comprises: a buffer layer disposed on the diamond substrate layer; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer; a capping layer disposed on the barrier layer; and a first electrode disposed on the capping layer; and wherein the diamond semiconductor device comprises: a second electrode disposed on the diamond substrate layer; and the first electrode and the second electrode are electrically connected to form an integrated circuit.

[0011] In some embodiments of the present invention, the diamond semiconductor device further comprises an oxide film layer disposed on the diamond substrate layer, and the second electrode may be disposed on the oxide film layer.

[0012] In some embodiments of the present invention, the nitride semiconductor device is gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (Al x Ga 1-x Includes 1 or more of N), and Al x Ga 1-x The x value of the above aluminum gallium nitride, represented by the chemical formula of N, can be from 0.1 to 99.9.

[0013] In some embodiments of the present invention, the nitride semiconductor device is the aluminum gallium (Al nitride)x Ga 1-x In the case of including N), aluminum gallium nitride (Al) included in each of the two layers disposed adjacent to each other among the channel layer, barrier layer, and capping layer. x Ga 1-x N) has different x values, and the aluminum gallium nitride (Al) included in the channel layer x Ga 1-x The x value of N) is the aluminum gallium nitride (Al) included in the barrier layer. x Ga 1-x It can be smaller than the x value of N).

[0014] In some embodiments of the present invention, the first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from the first source and the first gate, and the nitride semiconductor device may further comprise a p-aluminum gallium nitride layer formed between the first gate and the capping layer.

[0015] In some embodiments of the present invention, the second electrode comprises a second source, a second gate formed spaced apart from the second source, and a second drain formed spaced apart from the second source and the second gate, and the diamond semiconductor device may further comprise an n-diamond layer formed on the diamond substrate layer; a p-diamond layer formed between the n-diamond layer and the second source, and between the n-diamond layer and the second drain, respectively; and an oxide layer formed between the n-diamond layer and the second gate.

[0016] In some embodiments of the present invention, the nitride semiconductor device may further include a diamond layer formed between the diamond substrate layer and the buffer layer.

[0017] In some embodiments of the present invention, the nitride semiconductor device may be formed by chemical vapor deposition (CVD) and may be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C.

[0018] In some embodiments of the present invention, the diamond substrate layer may be formed by chemical vapor deposition (CVD) on a substrate comprising any one of Si, Al2O3, SiC, GaN, AlN, and Ga2O3, and may be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C.

[0019] In some embodiments of the present invention, the substrate includes a metal buffer layer disposed on the upper side, the metal buffer layer includes one or more of iridium (Ir), ruthenium (Ru), Al2O3, YSZ, and SrTiO3, and the diamond substrate layer may be disposed on the metal buffer layer.

[0020] In order to solve the above problems, one embodiment of the present invention comprises a method for manufacturing a semiconductor integrated device, the method comprising: a substrate layer preparation step of preparing a diamond substrate layer including diamond; a nitride semiconductor device formation step of forming a nitride semiconductor device on the diamond substrate layer; and a diamond semiconductor device formation step of forming a diamond semiconductor device on the diamond substrate layer; wherein the nitride semiconductor device formation step comprises: a buffer layer placement step of placing a buffer layer on the diamond substrate layer; a channel layer placement step of placing a channel layer on the buffer layer; a barrier layer placement step of placing a barrier layer on the channel layer; a capping layer placement step of placing a capping layer on the barrier layer; and a first electrode placement step of placing a first electrode on the capping layer. The present invention provides a method for manufacturing a semiconductor integrated device, wherein the diamond semiconductor device formation step comprises a second electrode placement step of placing a second electrode on the diamond substrate layer, and the semiconductor integrated device forms an integrated circuit by electrically connecting the first electrode and the second electrode. Effects of the invention

[0022] According to one embodiment of the present invention, a semiconductor integrated device can improve the withstand voltage characteristics and switching characteristics of the semiconductor integrated device by including an ultrawide bandgap material, thereby exhibiting the effect of expanding the usability of the device.

[0023] According to one embodiment of the present invention, by using a diamond substrate layer containing diamond, the semiconductor integrated device can improve heat dissipation performance and prevent degradation caused by high temperatures during device operation, thereby extending the lifespan of the semiconductor integrated device and enabling operation in extreme environments such as high temperatures, which can then produce the effect of improving economic efficiency.

[0024] According to one embodiment of the present invention, the diamond substrate layer can improve the heat resistance performance of the semiconductor integrated device by maximizing the contact area with the outside by using the entire area corresponding to the lower surface of the semiconductor integrated device as a heat dissipation layer.

[0025] According to one embodiment of the present invention, a nitride semiconductor device has a multilayer structure including a buffer layer, a channel layer, a barrier layer, and a capping layer, and each of the buffer layer, channel layer, barrier layer, and capping layer includes aluminum gallium nitride having different detailed compositions, thereby forming a two-dimensional electric gas inside the channel layer to improve the performance of the semiconductor integrated device.

[0026] According to one embodiment of the present invention, by using a diamond substrate layer as a substrate layer, the semiconductor integrated device can minimize the number of steps included in the diamond semiconductor device formation step, thereby reducing process time and improving productivity.

[0027] According to one embodiment of the present invention, by using a portion of the diamond substrate layer as a diamond semiconductor device, the semiconductor integrated device can minimize the size of the diamond semiconductor device and lighten the semiconductor integrated device, thereby improving economic efficiency.

[0028] According to one embodiment of the present invention, a diamond semiconductor device can improve hole mobility by including a channel composed of a two-dimensional hole gas, thereby exhibiting the effect of improving the performance of a semiconductor integrated device.

[0029] According to one embodiment of the present invention, the semiconductor integrated device can expand the range of application of the semiconductor integrated device by controlling whether it is in e-mode and d-mode through a stacked structure of a nitride semiconductor device and a diamond semiconductor device. Brief explanation of the drawing

[0031] FIG. 1 illustrates a schematic diagram of a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 2 schematically illustrates a method for manufacturing a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 3 schematically illustrates a step for forming a nitride semiconductor device according to one embodiment of the present invention. FIG. 4 schematically illustrates a diamond semiconductor device formation step according to one embodiment of the present invention. FIG. 5 schematically illustrates the structure of a semiconductor integrated device including an oxide film layer according to one embodiment of the present invention. FIG. 6 schematically illustrates the process of forming a two-dimensional hole gas according to one embodiment of the present invention. FIG. 7 schematically illustrates the process of forming a two-dimensional electron gas according to one embodiment of the present invention. FIG. 8 schematically illustrates the structure of a semiconductor integrated device further comprising a doped diamond multilayer structure according to one embodiment of the present invention. FIG. 9 schematically illustrates the structure of a semiconductor integrated device further comprising a diamond layer and a p-gallium aluminum nitride layer according to one embodiment of the present invention. FIG. 10 schematically illustrates the structure of a semiconductor integrated device according to one embodiment of the present invention, further comprising a diamond layer, a p-gallium aluminum nitride layer, and a doped diamond multilayer structure. Specific details for implementing the invention

[0032] Hereinafter, various embodiments and / or aspects are disclosed with reference to the drawings. For illustrative purposes, numerous specific details are disclosed in the following description to aid in a general understanding of one or more aspects. However, it will also be recognized by those skilled in the art that these aspects may be practiced without such specific details. The following description and the accompanying drawings describe specific exemplary aspects of one or more aspects in detail. However, these aspects are exemplary, and some of the various methods in the principles of the various aspects may be used, and the description is intended to include all such aspects and their equivalents.

[0033] In addition, various aspects and features will be presented by a system that may include multiple devices, components and / or modules, etc. It should also be understood and recognized that various systems may include additional devices, components and / or modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in relation to the drawings.

[0034] As used herein, terms such as "examples," "examples," "aspects," "examples," etc., may not be interpreted as implying that any aspect or design described is better or more advantageous than other aspects or designs.

[0035] Additionally, the terms “comprising” and / or “comprising” should be understood to mean that the relevant feature and / or component is present, but not to exclude the presence or addition of one or more other features, components and / or groups thereof.

[0036] Additionally, terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0037] Furthermore, in the embodiments of the present invention, all terms used herein, including technical or scientific terms, unless otherwise defined, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the embodiments of the present invention.

[0039] CMOS is a switching device primarily used in logic circuits due to its low power consumption, and conventional CMOS is manufactured based on silicon. However, conventional silicon-based CMOS has the problem that it is difficult to apply as a high-speed switching, ultra-high voltage, and ultra-high frequency device required by the market, and as the miniaturization of the device progresses, problems of increased power consumption and intensified heat generation have occurred.

[0040] To solve this, the present invention proposes a diamond and nitride-based integrated device formed on a diamond substrate and a manufacturing method, wherein the conventional silicon is replaced with a diamond and nitride material and a heat dissipation layer is formed using a diamond substrate layer (1000).

[0041] More specifically, in the present invention, diamond and gallium aluminum nitride (Al), which are Ultra Wide Band-Gap (UWBG) materials having a band gap wider than silicon, x Ga 1-x A semiconductor integrated device (1) corresponding to a CMOS structure can be manufactured by forming a diamond semiconductor device (3000) and a nitride semiconductor device (2000) based on N) on a single diamond substrate layer (1000). At this time, the diamond substrate layer (1000) can be used as a part of the diamond semiconductor device (3000) and as a heat dissipation layer of the semiconductor integrated device (1). The diamond semiconductor device (3000) formed in this way can correspond to a p-channel FET, and the nitride semiconductor device (2000) can correspond to an N-channel FET.

[0042] With this configuration, the semiconductor integrated device (1) has higher heat dissipation characteristics than conventional silicon-based CMOS, can operate in a high-temperature environment, can be applied as a high-voltage device and high-speed switching is possible, and the device can be made lighter by utilizing the diamond substrate layer (1000).

[0044] That is, according to one embodiment of the present invention, the semiconductor integrated device (1) includes an ultrawide bandgap material, thereby improving the withstand voltage characteristics and switching characteristics of the semiconductor integrated device (1) and thereby having the effect of expanding the usability of the device.

[0045] In addition, according to one embodiment of the present invention, the semiconductor integrated device (1) can improve heat dissipation performance by using a diamond substrate layer (1000) including diamond, and by preventing deterioration caused by high temperature during device operation, the lifespan of the semiconductor integrated device (1) can be extended, and the effect of improving economic efficiency can be achieved by enabling operation in extreme environments such as high temperature.

[0046] According to one embodiment of the present invention, the diamond substrate layer (1000) is used as a substrate layer of the semiconductor integrated device (1) and at the same time as a part of the diamond semiconductor device (3000), thereby making the semiconductor integrated device (1) lighter and shortening the manufacturing steps of the semiconductor integrated device (1), thereby producing the effect of improving productivity.

[0048] Hereinafter, a diamond and nitride-based integrated circuit formed on a diamond substrate and a manufacturing method according to one embodiment of the present invention will be described in detail.

[0050] FIG. 1 illustrates a schematic diagram of a semiconductor integrated device (1) according to one embodiment of the present invention.

[0052] A semiconductor integrated device (1) according to one embodiment of the present invention comprises: a diamond substrate layer (1000) including diamond; a nitride semiconductor device (2000) formed on the diamond substrate layer (1000); and a diamond semiconductor device (3000); wherein the nitride semiconductor device (2000) comprises: a buffer layer (2100) disposed on the diamond substrate layer (1000); a channel layer (2200) disposed on the buffer layer (2100); a barrier layer (2300) disposed on the channel layer (2200); and a capping layer (2400) disposed on the barrier layer (2300). and a first electrode (2500) disposed on the capping layer (2400); and the diamond semiconductor device (3000) includes a second electrode (3100) disposed on the diamond substrate layer (1000), and the first electrode (2500) and the second electrode (3100) can be electrically connected to form an integrated circuit.

[0053] According to one embodiment of the present invention, the first electrode (2500) includes a first source (2510), a first gate (2520) formed spaced apart from the first source (2510), and a first drain (2530) formed spaced apart from the first source (2510) and the first gate (2520), and the second electrode (3100) may include a second source (3110), a second gate (3120) formed spaced apart from the second source (3110), and a second drain (3130) formed spaced apart from the second source (3110) and the second gate (3120).

[0055] As illustrated in FIG. 1, a semiconductor integrated device (1) according to one embodiment of the present invention may include a nitride semiconductor device (2000) and a diamond semiconductor device (3000) that share a diamond substrate layer (1000), and the nitride semiconductor device (2000) and the diamond semiconductor device (3000) may be arranged adjacent to each other on the diamond substrate layer (1000). However, the nitride semiconductor device (2000) and the diamond semiconductor device (3000) may be arranged adjacent to each other but do not come into contact with each other, and may be arranged spaced apart by a predetermined distance in a horizontal direction with respect to the diamond substrate layer (1000).

[0057] The above diamond substrate layer (1000) may include diamond. Generally, diamond is a material that has higher heat dissipation characteristics than metallic materials such as copper or aluminum. That is, the semiconductor integrated device (1) according to one embodiment of the present invention may include a heat dissipation function that discharges heat generated when operating the semiconductor integrated device (1) to the outside by using the diamond substrate layer (1000) containing diamond as a substrate layer.

[0058] That is, the diamond substrate layer (1000) can function as a substrate layer and a heat dissipation layer within the semiconductor integrated device (1). The diamond substrate layer (1000) functioning as a heat dissipation layer diffuses heat to the outside, thereby preventing the inside of the semiconductor integrated device (1) from being maintained at a high temperature, and thus preventing the degradation of the device caused by the operating heat of the semiconductor integrated device (1).

[0060] That is, the diamond substrate layer (1000) according to one embodiment of the present invention can act as a heat dissipation layer, thereby having the effect of improving the lifespan of the semiconductor integrated device (1).

[0061] In addition, the diamond substrate layer (1000) according to one embodiment of the present invention can improve the heat resistance performance of the semiconductor integrated element (1) by using the entire area corresponding to the lower surface of the semiconductor integrated element (1) as a heat dissipation layer to maximize the area in contact with the outside.

[0063] The above nitride semiconductor device (2000) may include a buffer layer (2100), a channel layer (2200), a barrier layer (2300), a capping layer (2400), and a first electrode (2500). The buffer layer (2100) may be disposed in a portion of the diamond substrate layer (1000), the channel layer (2200) may be disposed on the buffer layer (2100), the barrier layer (2300) may be disposed on the channel layer (2200), and the capping layer (2400) may be disposed on the barrier layer (2300). The first electrode (2500) may be disposed on the upper side of the capping layer (2400), but may not be disposed over the entire capping layer (2400), but may be formed only in a portion of the upper side of the capping layer (2400). Additionally, the first electrode (2500) includes a first source (2510), a first gate (2520), and a first drain (2530), and each of the first source (2510), the first gate (2520), and the first drain (2530) may be spaced apart from each other by a predetermined distance in a horizontal direction with respect to the upper surface of the capping layer (2400).

[0064] Meanwhile, the diamond semiconductor device (3000) may include a portion of the diamond substrate layer (1000) where the nitride semiconductor device (2000) is not formed and may include a second electrode (3100). The second electrode (3100) may include a second source (3110), a second gate (3120), and a second drain (3130), and may be positioned on the upper side of a portion of the diamond substrate layer (1000) where the nitride semiconductor device (2000) is not formed. The second source (3110), the second gate (3120), and the second drain (3130) may be positioned spaced apart from each other by a predetermined distance in a horizontal direction with respect to the upper surface of the diamond substrate layer (1000).

[0065] The second gate (3120) included in the second electrode (3100) can be electrically connected to the first gate (2520) included in the first electrode (2500), and the second drain (3130) can be electrically connected to the first drain (2530) to form the semiconductor integrated device (1) in which an integrated circuit is formed.

[0067] According to one embodiment of the present invention, the nitride semiconductor device (2000) comprises gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (Al x Ga 1-x Includes 1 or more of N), and Al x Ga 1-x The x value of the above aluminum gallium nitride, represented by the chemical formula of N, can be from 0.1 to 99.9.

[0068] In addition, according to one embodiment of the present invention, the nitride semiconductor device (2000) is the aluminum gallium nitride (Al x Ga 1-x In the case of including N), aluminum gallium nitride (Al) included in each of the two layers arranged adjacent to each other among the channel layer (2200), barrier layer (2300), and capping layer (2400). x Ga 1-x N) has different x values, and the aluminum gallium nitride (Al) included in the channel layer (2200) x Ga 1-x The x value of N) is aluminum gallium nitride (Al) included in the barrier layer (2300). x Ga 1-x It can be smaller than the x value of N).

[0070] Specifically, the nitride semiconductor device (2000) comprises gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (Al x Ga 1-x It may include one or more of N). When the nitride semiconductor device (2000) includes aluminum gallium nitride, the aluminum gallium nitride is Al x Ga 1-xIt can be expressed by the chemical formula of N, and x included in the chemical formula may be one of positive numbers between 0.1 and 99.9. Since the aluminum and gallium content included in the aluminum gallium nitride varies depending on the value of x, the detailed composition of the aluminum gallium nitride may differ from layer to layer.

[0071] More specifically, when the nitride semiconductor device (2000) includes aluminum gallium nitride, the detailed composition of the aluminum gallium nitride included in each of the buffer layer (2100), channel layer (2200), barrier layer (2300), and capping layer (2400) may differ from one another. That is, each of the buffer layer (2100), channel layer (2200), barrier layer (2300), and capping layer (2400) may include aluminum gallium nitride having different x values, and in the case of two layers arranged adjacent to each other among the channel layer (2200), barrier layer (2300), and capping layer (2400), the aluminum gallium nitride included in each layer may have different x values. Additionally, the x value of the aluminum gallium nitride included in the channel layer (2200) may be smaller than the x value of the aluminum gallium nitride included in the buffer layer (2100) and the capping layer (2400).

[0072] For example, the x value of the aluminum gallium nitride contained in the buffer layer (2100) may be referred to as x1, the x value of the aluminum gallium nitride contained in the channel layer (2200) may be referred to as x2, the x value of the aluminum gallium nitride contained in the barrier layer (2300) may be referred to as x3, and the x value of the aluminum gallium nitride contained in the capping layer (2400) may be referred to as x4. In this case, x2 of the channel layer (2200) and x3 of the barrier layer (2300) placed above the channel layer (2200) are not the same value and may have different values. Similarly, x3 and x4 may have different values, and for all the aforementioned cases, the value of x2 may be smaller than x3. Furthermore, according to one embodiment of the present invention, the value of x2 may be smaller than x3 and x4. That is, x2, x3, and x4 are x2 <x3, 및 x2<x4로 기재되는 부등식을 만족할 수 있다.

[0073] However, provided that the aforementioned conditions are satisfied, two layers that are not adjacent to each other may have the same x value. For example, if x1 and x2 have different values, x3 and x4 have different values, and x2 has a value smaller than x3 and x4, then x1 may have the same value as either x3 or x4.

[0074] Meanwhile, according to one embodiment of the present invention, the x value of the aluminum gallium nitride included in the buffer layer (2100) may be less than or equal to the x value of the aluminum gallium nitride included in the channel layer (2200). For example, when x2 and x3 have different values ​​and x3 and x4 have different values, x1 and x2 may have the same or different values. That is, x1 and x2 may satisfy the inequality described as x1 ≤ x2.

[0076] The above nitride semiconductor device (2000) is composed of a buffer layer (2100), a channel layer (2200), a barrier layer (2300), and a capping layer (2400) each containing aluminum gallium nitride with different detailed compositions, thereby forming a layer composed of a two-dimensional electron gas (E) inside the channel layer (2200). The two-dimensional electron gas (E) is a structure in which electrons are arranged at a high density within a specific area range, and electrons can move at a high speed within the region of the two-dimensional electron gas (E). A more detailed description of the two-dimensional electron gas (E) will be provided in the drawings described later.

[0078] That is, a nitride semiconductor device (2000) according to one embodiment of the present invention has a multilayer structure including a buffer layer (2100), a channel layer (2200), a barrier layer (2300), and a capping layer (2400), and each of the buffer layer (2100), the channel layer (2200), the barrier layer (2300), and the capping layer (2400) includes aluminum gallium nitride having different detailed compositions, thereby forming a two-dimensional electric gas inside the channel layer (2200) and thereby producing an effect that improves the performance of the semiconductor integrated device (1).

[0080] FIG. 2 schematically illustrates a method for manufacturing a semiconductor integrated device (1) according to one embodiment of the present invention.

[0082] According to one embodiment of the present invention, a method for manufacturing a semiconductor integrated device (1) may include: a substrate layer preparation step (S10) of preparing a diamond substrate layer (1000) including diamond; a nitride semiconductor device formation step (S20) of forming a nitride semiconductor device (2000) on the diamond substrate layer (1000); and a diamond semiconductor device formation step (S30) of forming a diamond semiconductor device (3000) on the diamond substrate layer (1000).

[0083] According to one embodiment of the present invention, the diamond substrate layer (1000) is formed by chemical vapor deposition (CVD) on a substrate comprising any one of Si, Al2O3, SiC, GaN, AlN, and Ga2O3, and can be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C.

[0084] Additionally, according to one embodiment of the present invention, the substrate includes a metal buffer layer (2100) disposed on the upper side, and the metal buffer layer (2100) includes one or more of iridium (Ir), ruthenium (Ru), Al2O3, YSZ, and SrTiO3, and the diamond substrate layer (1000) may be disposed on the metal buffer layer (2100).

[0086] As illustrated in FIG. 2, the method for manufacturing the semiconductor integrated device (1) may include a substrate layer preparation step (S10), a nitride semiconductor device formation step (S20), and a diamond semiconductor device formation step (S30).

[0087] Specifically, in the substrate layer preparation step (S10), a diamond substrate layer (1000) including diamond can be prepared. Although not shown in the drawing, the substrate layer preparation step (S10) can be performed by preparing a substrate including any one of Si, Al2O3, SiC, GaN, AlN, and Ga2O3, placing a metal buffer layer (2100) for depositing the diamond substrate layer (1000) on the substrate, and placing the diamond substrate layer (1000) on the metal buffer layer (2100).

[0088] The metal buffer layer (2100) may include one or more of iridium (Ir), ruthenium (Ru), Al2O3, YSZ, and SrTiO3. By including one or more of iridium (Ir), ruthenium (Ru), Al2O3, YSZ, and SrTiO3, the metal buffer layer (2100) can provide an environment where a diamond thin film can be deposited on the upper side. That is, the metal buffer layer (2100) can reduce the lattice mismatch between the diamond substrate layer (1000) and the substrate and serve as a base layer for the growth of the diamond substrate layer (1000).

[0089] After a metal buffer layer (2100) is disposed on the upper side of the substrate, a diamond substrate layer (1000) may be disposed on the metal buffer layer (2100). The diamond substrate layer (1000) may be prepared by growing the diamond on the metal buffer layer (2100) by chemical vapor deposition (CVD). At this time, the diamond substrate layer (1000) may be formed on the upper side of the metal buffer layer (2100) at a growth rate of 0.01 to 1000 μm / hr under atmospheric conditions including methane (CH4), oxygen (O2), argon (Ar), nitrogen (N2), and hydrogen (H2) gases, a pressure of 0 to 1000 torr, and a temperature of 100 to 1500°C.

[0091] By performing the above substrate layer preparation step (S10), a diamond substrate layer (1000) on which the nitride semiconductor device (2000) and the diamond semiconductor device (3000) are to be formed can be prepared. After the above substrate layer preparation step (S10) is performed, in one embodiment of the present invention, a nitride semiconductor device formation step (S20) for forming the nitride semiconductor device (2000) on a portion of the diamond substrate layer (1000) can be performed, and a diamond semiconductor device formation step (S30) for forming the diamond semiconductor device (3000) on other portions of the diamond substrate layer (1000) where the nitride semiconductor device (2000) is not formed can be performed, respectively.

[0092] According to one embodiment of the present invention, the execution order of the nitride semiconductor device formation step (S20) and the diamond semiconductor device formation step (S30) may not be fixed. In other words, the diamond semiconductor device formation step (S30) may be performed after the nitride semiconductor device formation step (S20), or the nitride semiconductor device formation step (S20) may be performed after the diamond semiconductor device formation step (S30), or the nitride semiconductor device formation step (S20) and the diamond semiconductor device formation step (S30) may each be performed individually and simultaneously.

[0093] A more detailed description of each of the above-mentioned nitride semiconductor device formation step (S20) and diamond semiconductor device formation step (S30) will be provided in the drawings described later.

[0095] FIG. 3 schematically illustrates a nitride semiconductor device formation step (S20) according to one embodiment of the present invention.

[0097] According to one embodiment of the present invention, the nitride semiconductor device forming step (S20) may include: a buffer layer placement step (S21) of placing a buffer layer (2100) on the diamond substrate layer (1000); a channel layer placement step (S22) of placing a channel layer (2200) on the buffer layer (2100); a barrier layer placement step (S23) of placing a barrier layer (2300) on the channel layer (2200); a capping layer placement step (S24) of placing a capping layer (2400) on the barrier layer (2300); and a first electrode placement step (S25) of placing a first electrode (2500) on the capping layer (2400).

[0098] According to one embodiment of the present invention, the nitride semiconductor device (2000) can be formed by chemical vapor deposition (CVD) and can be formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C.

[0099] According to one embodiment of the present invention, the buffer layer (2100) may be formed with a thickness of 1 to 2 μm, the channel layer (2200) may be formed with a thickness of 100 to 500 nm, the barrier layer (2300) may be formed with a thickness of 100 to 300 nm, and the capping layer (2400) may be formed with a thickness of 100 to 200 nm.

[0101] As illustrated in FIG. 3, the nitride semiconductor device formation step (S20) may include a buffer layer placement step (S21), a channel layer placement step (S22), a barrier layer placement step (S23), a capping layer placement step (S24), and a first electrode placement step (S25).

[0102] Specifically, the nitride semiconductor formation step may place the buffer layer (2100) in a portion of the diamond substrate layer (1000) by performing the buffer layer placement step (S21). As described above, the diamond substrate layer (1000) may be a substrate containing diamond. The buffer layer (2100) may have a thickness of 1 to 2 μm by being formed at a growth rate of 0.01 to 1000 μm / hr when a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C are applied.

[0103] When the buffer layer (2100) is formed, the channel layer placement step (S22) of placing the channel layer (2200) on the buffer layer (2100) may be performed. Preferably, the channel layer (2200) may be formed at a growth rate of 0.01 to 1000 μm / hr when a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C are applied, and the thickness of the channel layer (2200) is preferably 100 to 500 nm. The formation conditions of the channel layer (2200), including pressure, temperature, and growth rate, may correspond to the formation conditions of the buffer layer (2100).

[0104] When the placement of the channel layer (2200) is completed, the barrier layer placement step (S23) of placing the barrier layer (2300) on the channel layer (2200) may be performed. The formation conditions of the barrier layer placement step (S23) may correspond to the formation conditions of the buffer layer (2100) and the channel layer (2200), and preferably, the barrier layer (2300) having a thickness of 100 to 300 nm is formed by forming it at a growth rate of 0.01 to 1000 μm / hr when a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C are applied.

[0105] The capping layer (2400) can be placed on the barrier layer (2300) by performing the capping layer placement step (S24). The capping layer placement step (S24) can form the capping layer (2400) at a growth rate of 0.01 to 1000 μm / hr when a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C are applied, and the thickness of the capping layer (2400) can be 100 to 200 nm. The formation conditions of the capping layer (2400), including pressure, temperature, and growth rate, may correspond to the formation conditions of the buffer layer (2100), channel layer (2200), and barrier layer (2300). That is, the pressure, temperature, and growth rate included in the formation conditions of each of the buffer layer (2100), channel layer (2200), barrier layer (2300), and capping layer (2400) may be the same as each other.

[0106] According to one embodiment of the present invention, the buffer layer placement step (S21), channel layer placement step (S22), barrier layer placement step (S23), and capping layer placement step (S24) may be performed by a thin film deposition process including chemical vapor deposition (CVD). As described above, each of the buffer layer (2100), channel layer (2200), barrier layer (2300), and capping layer (2400) may include gallium aluminum nitride with different detailed compositions, and the formation conditions of the buffer layer (2100), channel layer (2200), barrier layer (2300), and capping layer (2400) may correspond to each other with respect to pressure, temperature, and growth rate.

[0108] When the capping layer placement step (S24) is completed, the first electrode placement step (S25) of placing the first electrode (2500) on the capping layer (2400) may be performed. The first electrode (2500) may be formed by depositing a metal on a portion of the capping layer (2400), and the other portion of the capping layer (2400) where the first electrode (2500) is not placed may be exposed to the outside. As described above, the first electrode (2500) may include a first source (2510), a first gate (2520), and a first drain (2530), and each of the first source (2510), the first gate (2520), and the first drain (2530) may be spaced apart from each other by a predetermined distance in a horizontal direction with respect to the upper surface of the capping layer (2400).

[0110] FIG. 4 schematically illustrates a diamond semiconductor device formation step (S30) according to one embodiment of the present invention.

[0112] According to one embodiment of the present invention, in the diamond semiconductor device formation step (S30), a hydrogen plasma treatment step of treating the diamond substrate layer (1000) with hydrogen plasma may be further performed.

[0113] According to one embodiment of the present invention, the diamond semiconductor device forming step (S30) includes a second electrode placement step (S31) of placing a second electrode (3100) on the diamond substrate layer (1000); and the semiconductor integrated device (1) can form an integrated circuit by electrically connecting the first electrode (2500) and the second electrode (3100).

[0115] As described above, in the substrate layer preparation step (S10), the diamond substrate layer (1000) can be prepared by forming it on the upper side of the metal buffer layer (2100) at a growth rate of 0.01 to 1000 μm / hr under atmospheric conditions including methane (CH4), oxygen (O2), argon (Ar), nitrogen (N2), and hydrogen (H2) gases, a pressure of 0 to 1000 torr, and a temperature of 100 to 1500°C.

[0116] Although not illustrated in the drawings, the diamond semiconductor device formation step (S30) may further perform a hydrogen plasma treatment step in which hydrogen plasma treatment is performed on the upper side of a portion of the diamond substrate layer (1000) prepared in the substrate layer preparation step (S10) where the nitride semiconductor device (2000) is not formed. A more detailed description of the hydrogen plasma treatment step will be provided in the drawings described later.

[0118] As illustrated in FIG. 4, in the diamond semiconductor device formation step (S30), a second electrode placement step (S31) for forming the electrode on the diamond substrate layer (1000) may be performed. The second electrode (3100) may be formed in a portion of the diamond substrate layer (1000), and other areas of the diamond substrate layer (1000) where the second electrode (3100) and the nitride semiconductor device (2000) are not placed may be exposed to the outside. By exposing other areas of the diamond substrate layer (1000) where the second electrode (3100) and the nitride semiconductor device (2000) are not placed to the outside, heat generated when the semiconductor integrated device (1) is operated can be released to the outside.

[0119] Additionally, as described above, the second electrode (3100) may include the second source (3110), the second gate (3120), and the second drain (3130). The second drain (3130) may be electrically connected to the first drain (2530) of the first electrode (2500), and the second gate (3120) may be electrically connected to the first gate (2520) to form the semiconductor integrated device (1) in which an integrated circuit is formed.

[0120] According to one embodiment of the present invention, the second electrode placement step (S31) can be performed simultaneously as a step corresponding to the first electrode placement step (S25).

[0122] The semiconductor integrated device (1) according to one embodiment of the present invention can reduce process time and improve productivity by using the diamond substrate layer (1000) as a substrate layer, thereby minimizing the number of steps included in the diamond semiconductor device formation step (S30).

[0123] In addition, the semiconductor integrated device (1) according to one embodiment of the present invention can achieve the effect of improving economic efficiency by minimizing the size of the diamond semiconductor device (3000) and making the semiconductor integrated device (1) lighter by using a part of the diamond substrate layer (1000) as a diamond semiconductor device (3000).

[0125] FIG. 5 schematically illustrates the structure of a semiconductor integrated device (1) including an oxide film layer (O) according to one embodiment of the present invention.

[0127] According to one embodiment of the present invention, the diamond semiconductor device (3000) further comprises an oxide film layer (O) disposed on the diamond substrate layer (1000), and the second electrode (3100) may be disposed on the oxide film layer (O).

[0128] In addition, according to one embodiment of the present invention, the upper side of the diamond substrate layer (1000) is treated with hydrogen plasma by applying a plasma power of 0.5 to 100 KW in an environment with a hydrogen content of 0.1 to 50%, and an oxide film layer (O) may be disposed on the upper side of the hydrogen plasma-treated diamond substrate layer (1000).

[0129] According to one embodiment of the present invention, the diamond substrate layer (1000) may include a two-dimensional hole gas (H) (2DHG, 2 Dimensional Hole Gas) composed of holes in an inner region of the diamond substrate layer (1000) adjacent to the upper interface where the oxide film layer (O) is disposed.

[0131] FIG. 5(a) schematically illustrates a top view of a semiconductor integrated device (1) including the oxide layer (O), and FIG. 5(b) schematically illustrates a front view of a semiconductor integrated device (1) including the oxide layer (O).

[0133] As illustrated in FIG. 5(a) and FIG. 5(b), a semiconductor integrated device (1) according to one embodiment of the present invention may further include a diamond layer (3200) formed on the upper side of the diamond substrate layer (1000), and may further include an oxide film layer (O) formed between the diamond layer (3200) and the second electrode (3100). Hereinafter, the semiconductor integrated device (1) including the oxide film layer (O) illustrated in FIG. 5 is referred to as Example #1.

[0135] In the above Example #1, a diamond layer formation step may be performed first to further form the diamond layer (3200) on the diamond substrate layer (1000) before the second electrode placement step (S31) is performed in the diamond semiconductor device formation step (S30). The aforementioned hydrogen plasma treatment step may be further performed on the diamond layer (3200) of Example #1 formed in the diamond layer formation step. The hydrogen plasma treatment step may be performed on Example #1 by placing Example #1 inside a plasma treatment apparatus including the chemical vapor deposition (CVD) method and applying a plasma power of 0.5 to 100 KW in an environment with a hydrogen content of 0.1 to 50%.

[0136] The diamond layer (3200) and the diamond substrate layer (1000) may likewise contain diamond. As previously mentioned, the diamond corresponds to a single-component material composed of carbon. That is, the diamond substrate layer (1000) and the diamond layer (3200) contain carbon atoms on their surfaces. Therefore, when the hydrogen plasma treatment is performed on the diamond layer (3200), the surface of the diamond layer (3200) may be modified by the carbon atoms contained on the surface of the diamond layer (3200) being combined with hydrogen atoms by the hydrogen plasma. The oxide film layer (O) may be partially deposited on the diamond layer (3200) with the modified surface. According to one embodiment of the present invention, the oxide film layer (O) may include any one of Al2O3, SiO2, HfO2, MoO3, V2O5, and WO3.

[0137] By the above hydrogen plasma treatment and the arrangement of the oxide film layer (O), a two-dimensional hole gas (H) (2DHG, 2 Dimensional Hole Gas) composed of holes can be formed inside the diamond layer (3200) of Example #1. As shown in FIG. 5(b), the two-dimensional hole gas (H) can be arranged inside the diamond layer (3200) adjacent to the interface between the diamond layer (3200) and the oxide film layer (O). A more detailed description of the two-dimensional hole gas (H) will be provided in the drawings described later.

[0139] FIG. 6 schematically illustrates the process of forming a two-dimensional hole gas (H) according to one embodiment of the present invention.

[0141] FIG. 6(a) schematically illustrates the band structure of the diamond substrate layer (1000) in which the hydrogen plasma treatment is not performed, FIG. 6(b) schematically illustrates the band structure of the diamond substrate layer (1000) in which the hydrogen plasma treatment is performed, and FIG. 6(c) schematically illustrates the band structure in which the oxide film layer (O) is disposed on the diamond substrate layer (1000) in which the hydrogen plasma treatment is performed.

[0143] As described above, the diamond substrate layer (1000) according to one embodiment of the present invention is treated with hydrogen plasma, and an oxide film layer (O) is disposed on the upper side, so that a two-dimensional hole gas (H) (2DHG, 2 Dimensional Hole Gas) composed of holes is disposed adjacent to the interface between the diamond substrate layer (1000) and the oxide film layer (O) and can be formed on the inner side of the diamond substrate layer (1000).

[0145] As shown in FIG. 6(a), when hydrogen plasma treatment is not performed on the diamond substrate layer (1000), the diamond substrate layer (1000) may have an unbent band structure. However, when hydrogen plasma treatment is performed on the diamond substrate layer (1000), the surface of the diamond substrate layer (1000) may be modified by the combination of a plurality of carbon atoms disposed on the upper surface of the diamond substrate layer (1000) with a plurality of hydrogen atoms through the hydrogen plasma treatment, and a band bending phenomenon may occur as shown in FIG. 6(b).

[0146] The plurality of hydrogen atoms disposed on the modified surface of the diamond substrate layer (1000) may have an electrical attraction, and the plurality of electrons disposed on the inner side of the diamond substrate layer (1000) may move toward the modified surface of the diamond substrate layer (1000) by means of the plurality of hydrogen atoms. At this time, the plurality of electrons moving due to the electrical attraction of the plurality of hydrogen atoms may be limited to electrons disposed on the inner side adjacent to the modified surface of the diamond substrate layer (1000). As the plurality of electrons move toward the modified surface of the diamond substrate layer (1000), a plurality of holes may be formed on the inner side of the diamond substrate layer (1000) where the plurality of electrons were previously disposed. That is, a plurality of holes may be disposed on the inner side adjacent to the modified surface of the diamond substrate layer (1000).

[0147] Meanwhile, the above Example #1 can be formed by further disposing of the oxide film layer (O) on the diamond substrate layer (1000) on which the above hydrogen plasma treatment has been performed. As shown in FIG. 6(c), in the case of Example #1, the band of the diamond substrate layer (1000) may have a more curved shape than in FIG. 6(b). Due to the electromagnetic attraction between a plurality of hydrogen atoms disposed on the surface of the diamond substrate layer (1000) and the oxide film layer (O), a plurality of electrons disposed inside the diamond substrate layer (1000) move toward the oxide film layer (O), thereby allowing a larger amount of a plurality of holes to be disposed inside the diamond substrate layer (1000) than in FIG. 6(b). That is, by the above hydrogen plasma treatment and the arrangement of the oxide film layer (O), a layer composed of holes can be formed within a certain distance range from the surface of the diamond substrate layer (1000), and the layer composed of holes corresponds to the two-dimensional hole gas (H).

[0148] The above two-dimensional hole gas (H) can operate as a channel through which holes can move within the diamond semiconductor device (3000). Since the above two-dimensional hole gas (H) is formed inside the diamond semiconductor device (3000) of Example #1 even when no voltage is applied to the second electrode (3100), the diamond semiconductor device (3000) of Example #1 can function as a D-mode P-channel FET that maintains an always-on state by including a channel through which holes can move even when no voltage is applied.

[0149] According to one embodiment of the present invention, when the hydrogen plasma treatment is performed on the diamond layer (3200) and the oxide film layer (O) is disposed on the upper side of the diamond layer (3200), the diamond layer (3200) may have a channel composed of the two-dimensional hole gas (H) formed inside, similar to the diamond layer (3200) shown in FIG. 6.

[0151] That is, the diamond semiconductor device (3000) according to one embodiment of the present invention can improve hole mobility by including a channel composed of a two-dimensional hole gas (H), thereby producing the effect of improving the performance of the semiconductor integrated device (1).

[0153] FIG. 7 schematically illustrates the process of forming a two-dimensional electron gas (E) according to one embodiment of the present invention.

[0155] FIG. 7(a) illustrates the band structure of each of the channel layer (2200) and the barrier layer (2300) according to one embodiment of the present invention, and FIG. 7(b) illustrates the band bending phenomenon occurring in the barrier layer (2300) when the barrier layer (2300) is placed on the channel layer (2200).

[0157] According to one embodiment of the present invention, the channel layer (2200) may include a two-dimensional electron gas (E) (2DEG, 2 Dimensional Electron Gas) composed of electrons in an inner region of the channel layer (2200) adjacent to an upper interface where a barrier layer (2300) is disposed.

[0159] As described above, the channel layer (2200) and the barrier layer (2300) may include aluminum gallium nitride having different detailed compositions. In addition, according to one embodiment of the present invention, aluminum gallium nitride (Al) included in the channel layer (2200) x Ga 1-x The x value corresponding to the aluminum composition of N) is aluminum gallium nitride (Al) included in the barrier layer (2300). x Ga 1-x It can have a value smaller than the x value of N).

[0160] As illustrated in FIG. 7(a), when the detailed composition of the aluminum gallium nitride contained in each of the channel layer (2200) and the barrier layer (2300) is different, and the channel layer (2200) and the barrier layer (2300) are not placed adjacent to each other but exist as separate layers, the Fermi energy level (Ef) of the channel layer (2200) and the Fermi energy level of the barrier layer (2300) may be placed at different locations.

[0161] Meanwhile, as illustrated in FIG. 7(b), when the barrier layer (2300) is placed on top of the channel layer (2200), the Fermi energy level of the channel layer (2200) and the Fermi energy level of the barrier layer (2300) have a tendency to align at corresponding positions, so a band bending phenomenon may occur at the interface where the channel layer (2200) and the barrier layer (2300) are placed adjacent to each other.

[0162] Due to the above band bending phenomenon, a quantum well may be formed between the barrier layer (2300) and the channel layer (2200). Electrons that have crossed over to the interface between the barrier layer (2300) and the channel layer (2200) are trapped in the quantum well, thereby forming a two-dimensional electron gas (E) in which a plurality of electrons are disposed in the region where the quantum well is formed. The two-dimensional electron gas (E) may exist in the form of a single layer that is disposed on the inner side of the interface between the barrier layer (2300) and the channel layer (2200) and can only move in a horizontal direction relative to the surface of the channel layer (2200), and thereby operates as a channel through which electrons move, allowing current to flow in the channel layer (2200).

[0163] The above two-dimensional electron gas (E) is formed inside the nitride semiconductor device (2000) included in Example #1 even when no voltage is applied to the first electrode (2500). That is, the nitride semiconductor device (2000) can function as a D-mode N-channel FET that maintains an always-on state by including a channel through which electrons can move even when no voltage is applied to the first electrode (2500).

[0165] That is, the channel layer (2200) according to one embodiment of the present invention can have the effect of improving electrical conductivity by including the two-dimensional electron gas (E).

[0166] In addition, the nitride semiconductor device (2000) according to one embodiment of the present invention can improve electron mobility and reduce switching losses by the two-dimensional electron gas (E), thereby improving the electrical performance of the semiconductor integrated device (1).

[0168] FIG. 8 schematically illustrates the structure of a semiconductor integrated device (1) further comprising a diamond layer (2600) and a doped diamond multilayer structure according to one embodiment of the present invention, FIG. 9 schematically illustrates the structure of a semiconductor integrated device (1) further comprising a p-aluminum gallium nitride layer (2410) according to one embodiment of the present invention, and FIG. 10 schematically illustrates the structure of a semiconductor integrated device (1) further comprising a diamond layer (2600), a p-aluminum gallium nitride layer (2410), and a doped diamond multilayer structure according to one embodiment of the present invention.

[0170] According to one embodiment of the present invention, the diamond semiconductor device (3000) may further include: an n-diamond layer (3300) formed on the diamond substrate layer (1000); a p-diamond layer (3310) formed between the n-diamond layer (3300) and the second source (3110), and between the n-diamond layer (3300) and the second drain (3130), respectively; and an oxide layer (O) formed between the n-diamond layer (3300) and the second gate (3120).

[0171] Additionally, according to one embodiment of the present invention, the nitride semiconductor device (2000) may further include a p-aluminum gallium nitride layer (2410) formed between the first gate (2520) and the capping layer (2400); and the nitride semiconductor device (2000) may further include a diamond layer (2600) formed between the diamond substrate layer (1000) and the buffer layer (2100).

[0173] As described above, the above embodiment #1 includes the two-dimensional electron gas (E) and the two-dimensional hole gas (H), and the nitride semiconductor device (2000) and the diamond semiconductor device (3000) can each operate as a d-mode N-channel FET and a d-mode P-channel FET, respectively, in an always-on state. Meanwhile, in the present invention, in addition to the semiconductor integrated device (1) in an always-on state, a semiconductor integrated device (1) utilizing an e-mode FET in an always-off state is formed, thereby manufacturing a plurality of embodiments of semiconductor integrated devices (1) that can be applied in parallel with each other, and these embodiments are illustrated in FIGS. 8, 9, and 10.

[0175] FIG. 8(a) schematically illustrates a top view of a semiconductor integrated device (1) further comprising a diamond layer (2600) and a doped diamond multilayer structure according to one embodiment of the present invention, and FIG. 8(b) schematically illustrates a front view of a semiconductor integrated device (1) further comprising a diamond layer (2600) and the doped diamond multilayer structure.

[0177] As illustrated in FIG. 8 (a) and FIG. 8 (b), a semiconductor integrated device (1) according to one embodiment of the present invention may include the nitride semiconductor device (2000) further comprising the oxide layer (O), and the diamond semiconductor device (3000) further comprising the doped diamond multilayer structure including the diamond layer (3200), n-diamond layer (3300), p-diamond layer (3310), and oxide layer (O). Hereinafter, the semiconductor integrated device (1) further comprising the diamond layer (2600) and the doped diamond multilayer structure shown in FIG. 8 will be referred to as Example #2.

[0178] Specifically, the nitride semiconductor device (2000) of Example #2 may further include the oxide layer (O) disposed between the etched barrier layer (2300) and the first gate (2520), wherein the capping layer (2400) and the barrier layer (2300) are partially etched. According to one embodiment of the present invention, the oxide layer (O) may perform the role of a gate oxide with respect to the first gate (2520).

[0179] Meanwhile, the diamond semiconductor device (3000) of Example #2 above may further include the diamond layer (3200) disposed on the diamond substrate layer (1000). Additionally, the n-diamond layer (3300) may be further formed on the diamond layer (3200), and the device may further include a p-diamond layer (3310) formed between the n-diamond layer (3300) and the second source (3110), and between the n-diamond layer (3300) and the second drain (3130), respectively, and an oxide layer (O) formed between the n-diamond layer (3300) and the second gate (3120).

[0180] The n-diamond layer (3300) may include a diamond doped with the n-type, and the p-diamond layer (3310) may include a diamond doped with the p-type. According to one embodiment of the present invention, the p-diamond layer (3310) may include a diamond heavily doped with a p-type doping material. The oxide layer (O) disposed between the n-diamond layer (3300) and the second gate (3120) may serve as an insulating layer that prevents the movement of charge. When the diamond semiconductor device (3000) further includes the n-diamond layer (3300), the p-diamond layer (3310), and the oxide layer (O), the hydrogen plasma treatment may not be performed on the diamond substrate layer (1000) and the diamond layer (3200). Accordingly, the two-dimensional hole gas (H) may not be formed in the diamond semiconductor device (3000) included in Example #2 above.

[0181] That is, in the diamond semiconductor device (3000) of the above embodiment #2, there is no channel through which holes can move when no voltage is applied to the second gate (3120), so the diamond semiconductor device (3000) included in the above embodiment #2 can operate as an e-mode P-channel FET that is always off. When an external voltage is applied to the above embodiment #2, the diamond semiconductor device (3000) can induce a flow of holes by forming a channel through which holes can move inside.

[0182] Meanwhile, the nitride semiconductor device (2000) included in the above embodiment #2 has a structure corresponding to the above embodiment #1, so it can operate as a d-mode N-channel FET in which the channel formed by the two-dimensional electron gas (E) is always in an on state.

[0183] That is, a semiconductor integrated device (1) according to one embodiment of the present invention may include a nitride semiconductor device (2000) that performs the role of a d-mode N-channel FET and a diamond semiconductor device (3000) that performs the role of an e-mode P-channel FET.

[0185] FIG. 9(a) schematically illustrates a top view of a semiconductor integrated device (1) further comprising a p-aluminum nitride gallium layer (2410) according to one embodiment of the present invention, and FIG. 9(b) schematically illustrates a front view of a semiconductor integrated device (1) further comprising a p-aluminum nitride gallium layer (2410) according to one embodiment of the present invention.

[0187] Hereinafter, a semiconductor integrated device (1) further comprising a p-aluminum nitride gallium layer (2410) according to one embodiment of the present invention shown in FIG. 9 will be referred to as Example #3.

[0188] As illustrated in FIGS. 9(a) and FIGS. 9(b), the embodiment #3 has a structure corresponding to the embodiment #1, but may not include the capping layer (2400). Additionally, it may further include a p-aluminum gallium nitride layer (2410) disposed between the first gate (2520) and the barrier layer (2300).

[0189] The p-aluminum gallium nitride layer (2410) may include p-type doped aluminum gallium nitride. Additionally, the p-aluminum gallium nitride layer (2410) can perform the role of an internal negative battery for the nitride semiconductor device (2000), thereby forming a state in which a preset voltage is applied to the nitride semiconductor device (2000) of Example #3 even when no external voltage is applied to the first gate (2520) of Example #3.

[0190] That is, the channel formed by the two-dimensional electron gas (E) included in the nitride semiconductor device (2000) of the above embodiment #3 can be switched to an off state by the p-aluminum gallium nitride layer (2410). Therefore, the nitride semiconductor device (2000) of the above embodiment #3 can operate as an e-mode N-channel FET in which the channel formed by the two-dimensional electron gas (E) in the channel layer (2200) is always in an off state and becomes on only when an external voltage is applied. Meanwhile, the diamond semiconductor device (3000) included in the above embodiment #3 has a structure corresponding to the above embodiment #1, so it can operate as a d-mode P-channel FET in which the channel formed by the two-dimensional hole gas (H) is always in an on state.

[0191] That is, a semiconductor integrated device (1) according to one embodiment of the present invention may include a nitride semiconductor device (2000) that performs the role of an e-mode N-channel FET and a diamond semiconductor device (3000) that performs the role of a d-mode P-channel FET.

[0193] FIG. 10(a) schematically illustrates a top view of a semiconductor integrated device (1) further comprising a diamond layer (2600), a p-aluminum nitride gallium layer (2410), and a doped diamond multilayer structure according to one embodiment of the present invention, and FIG. 10(b) schematically illustrates a front view of a semiconductor integrated device (1) further comprising a diamond layer (2600), a p-aluminum nitride gallium layer (2410), and a doped diamond multilayer structure.

[0195] As illustrated in FIG. 10 (a) and FIG. 10 (b), a semiconductor integrated device (1) according to one embodiment of the present invention may include a nitride semiconductor device (2000) further comprising the p-aluminum nitride gallium layer (2410), and a diamond semiconductor device (3000) comprising the doped diamond multilayer structure including the diamond layer (3200), n-diamond layer (3300), p-diamond layer (3310), and oxide layer (O). Hereinafter, the semiconductor integrated device (1) further comprising the diamond layer (2600), p-aluminum nitride gallium layer (2410), and doped diamond multilayer structure shown in FIG. 10 will be referred to as Example #4.

[0196] As described above, when the p-aluminum gallium nitride layer (2410) is further included between the first gate (2520) and the barrier layer (2300) of the nitride semiconductor device (2000), the nitride semiconductor device (2000) can operate as an e-mode N-channel FET in Example #4.

[0197] Additionally, the diamond semiconductor device (3000) further comprises the doped diamond multilayer structure including the diamond layer (3200), n-diamond layer (3300), p-diamond layer (3310), and oxide layer (O), and when the hydrogen plasma treatment performed in Example #1 is not performed, the diamond semiconductor device (3000) can operate as an e-mode P-channel FET in Example #4.

[0198] That is, a semiconductor integrated device (1) according to one embodiment of the present invention may include a nitride semiconductor device (2000) that performs the role of an e-mode N-channel FET and a diamond semiconductor device (3000) that performs the role of an e-mode P-channel FET.

[0200] Accordingly, the semiconductor integrated device (1) according to one embodiment of the present invention can have the effect of expanding the application range of the semiconductor integrated device (1) by controlling whether it is in e-mode and d-mode through the stacked structure of the nitride semiconductor device (2000) and the diamond semiconductor device (3000).

[0202] According to one embodiment of the present invention, a semiconductor integrated device can improve the withstand voltage characteristics and switching characteristics of the semiconductor integrated device by including an ultrawide bandgap material, thereby exhibiting the effect of expanding the usability of the device.

[0203] According to one embodiment of the present invention, by using a diamond substrate layer containing diamond, the semiconductor integrated device can improve heat dissipation performance and prevent degradation caused by high temperatures during device operation, thereby extending the lifespan of the semiconductor integrated device and enabling operation in extreme environments such as high temperatures, which can then produce the effect of improving economic efficiency.

[0204] According to one embodiment of the present invention, the diamond substrate layer can improve the heat resistance performance of the semiconductor integrated device by maximizing the contact area with the outside by using the entire area corresponding to the lower surface of the semiconductor integrated device as a heat dissipation layer.

[0205] According to one embodiment of the present invention, the diamond substrate layer is used as a substrate layer of a semiconductor integrated device and simultaneously as part of a diamond semiconductor device, thereby enabling the semiconductor integrated device to be made lighter and the manufacturing steps of the semiconductor integrated device to be shortened, thereby improving productivity.

[0206] According to one embodiment of the present invention, a nitride semiconductor device has a multilayer structure including a buffer layer, a channel layer, a barrier layer, and a capping layer, and each of the buffer layer, channel layer, barrier layer, and capping layer includes aluminum gallium nitride having different detailed compositions, thereby forming a two-dimensional electric gas inside the channel layer to improve the performance of the semiconductor integrated device.

[0207] According to one embodiment of the present invention, by using a diamond substrate layer as a substrate layer, the semiconductor integrated device can minimize the number of steps included in the diamond semiconductor device formation step, thereby reducing process time and improving productivity.

[0208] According to one embodiment of the present invention, by using a portion of the diamond substrate layer as a diamond semiconductor device, the semiconductor integrated device can minimize the size of the diamond semiconductor device and lighten the semiconductor integrated device, thereby improving economic efficiency.

[0209] According to one embodiment of the present invention, a diamond semiconductor device can improve hole mobility by including a channel composed of a two-dimensional hole gas, thereby exhibiting the effect of improving the performance of a semiconductor integrated device.

[0210] According to one embodiment of the present invention, the channel layer can have the effect of improving electrical conductivity by including a two-dimensional electron gas.

[0211] According to one embodiment of the present invention, a nitride semiconductor device can improve electron mobility and reduce switching losses by means of a two-dimensional electron gas, thereby exhibiting the effect of improving the electrical performance of a semiconductor integrated device.

[0212] According to one embodiment of the present invention, the semiconductor integrated device can expand the range of application of the semiconductor integrated device by controlling whether it is in e-mode and d-mode through a stacked structure of a nitride semiconductor device and a diamond semiconductor device.

[0214] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents. Therefore, other implementations, other embodiments, and equivalents to the claims below are also within the scope of the claims. Explanation of the symbols

[0217] 1 : Semiconductor integrated circuit 1000 : Diamond substrate layer 2000: Nitride semiconductor device 2100: Buffer layer 2200: Channel layer 2300: Barrier layer 2400: Capping layer 2410: p-gallium aluminum nitride layer 2500: 1st electrode 2510: 1st source 2520 : 1st Gate 2530 : 1st Drain 3000 : Diamond semiconductor device 3100 : Second electrode 3110 : Second source 3120 : 2nd Gate 3130 : 2nd Drain 3200 : n-diamond layer 3210 : p-diamond layer 3220 : Oxide layer S10 : Substrate layer preparation step S20: Nitride semiconductor device formation step S21: Buffer layer placement step S22: Channel layer placement step S23: Barrier layer placement step S24: Capping layer placement step S25: First electrode placement step S30: Diamond semiconductor device formation step S31: Second electrode placement step O: Oxide layer E: Two-dimensional electron gas H: 2D hole gas

Claims

Claim 1 A semiconductor integrated device comprising: a diamond substrate layer including diamond; a nitride semiconductor device formed on the diamond substrate layer; and a diamond semiconductor device; wherein the nitride semiconductor device comprises: a buffer layer disposed on the diamond substrate layer; a channel layer disposed on the buffer layer; a barrier layer disposed on the channel layer; a capping layer disposed on the barrier layer; and a first electrode disposed on the capping layer; wherein the diamond semiconductor device comprises: a second electrode disposed on the diamond substrate layer; and the first electrode and the second electrode are electrically connected to form an integrated circuit, wherein the diamond substrate layer includes diamond, and when hydrogen plasma treatment is performed and an oxide film layer is formed thereon, a two-dimensional hole gas (2DHG) is formed inside. Claim 2 A semiconductor integrated device according to claim 1, wherein the second electrode is disposed on the oxide film layer. Claim 3 In claim 1, the nitride semiconductor device comprises gallium nitride (GaN), aluminum nitride (AlN), and aluminum gallium nitride (Al x Ga 1-x Includes 1 or more of N), and Al x Ga 1-x A semiconductor integrated device in which the x value of the above-mentioned aluminum gallium nitride, represented by the chemical formula of N, is 0.1 to 99.

9. Claim 4 In claim 3, the nitride semiconductor device is the aluminum gallium nitride (Al x Ga 1-x In the case of including N), aluminum gallium nitride (Al) included in each of the two layers disposed adjacent to each other among the channel layer, barrier layer, and capping layer. x Ga 1-x N) has different x values, and the aluminum gallium nitride (Al) included in the channel layer x Ga 1-x The x value of N) is the aluminum gallium nitride (Al) included in the barrier layer. x Ga 1-x A semiconductor integrated circuit smaller than the x value of N. Claim 5 A semiconductor integrated device according to claim 1, wherein the first electrode comprises a first source, a first gate formed spaced apart from the first source, and a first drain formed spaced apart from the first source and the first gate, and the nitride semiconductor device further comprises a p-aluminum gallium nitride layer formed between the first gate and the capping layer. Claim 6 A semiconductor integrated device according to claim 1, wherein the second electrode comprises a second source, a second gate formed spaced apart from the second source, and a second drain formed spaced apart from the second source and the second gate, and the diamond semiconductor device further comprises: an n-diamond layer formed on the diamond substrate layer; a p-diamond layer formed between the n-diamond layer and the second source, and between the n-diamond layer and the second drain, respectively; and an oxide film layer formed between the n-diamond layer and the second gate. Claim 7 A semiconductor integrated device according to claim 1, wherein the nitride semiconductor device further comprises a diamond layer formed between the diamond substrate layer and the buffer layer. Claim 8 A semiconductor integrated device according to claim 1, wherein the nitride semiconductor device is formed by chemical vapor deposition (CVD) and formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 400 to 1500°C. Claim 9 A semiconductor integrated device according to claim 1, wherein the diamond substrate layer is formed by chemical vapor deposition (CVD) on a substrate comprising any one of Si, Al2O3, SiC, GaN, AlN, and Ga2O3, and is formed at a growth rate of 0.01 to 1000 μm / hr under conditions of a pressure of 0 to 1000 torr and a temperature of 100 to 1500°C. Claim 10 A semiconductor integrated device according to claim 9, wherein the substrate comprises a metal buffer layer disposed on the upper side, the metal buffer layer comprises one or more of iridium (Ir), ruthenium (Ru), Al2O3, YSZ, and SrTiO3, and the diamond substrate layer disposed on the metal buffer layer. Claim 11 A method for manufacturing a semiconductor integrated device comprises: a substrate layer preparation step of preparing a diamond substrate layer including diamond; a nitride semiconductor device formation step of forming a nitride semiconductor device on the diamond substrate layer; and a diamond semiconductor device formation step of forming a diamond semiconductor device on the diamond substrate layer; wherein the nitride semiconductor device formation step comprises: a buffer layer placement step of placing a buffer layer on the diamond substrate layer; a channel layer placement step of placing a channel layer on the buffer layer; a barrier layer placement step of placing a barrier layer on the channel layer; a capping layer placement step of placing a capping layer on the barrier layer; and a first electrode placement step of placing a first electrode on the capping layer. A method for manufacturing a semiconductor integrated device, comprising: a diamond semiconductor device formation step including a second electrode placement step of placing a second electrode on the diamond substrate layer; wherein the semiconductor integrated device forms an integrated circuit by electrically connecting the first electrode and the second electrode, and wherein the diamond substrate layer includes diamond, and when hydrogen plasma treatment is performed and an oxide film layer is formed thereon, a two-dimensional hole gas (2DHG) is formed inside.

Images