Display device

Abstract

A display device is provided. The display device comprises a light-emitting element disposed on a substrate, a first transistor controlling a driving current flowing through the light-emitting element, a second transistor supplying a data voltage to the source electrode of the first transistor, a third-1 transistor and a third-2 transistor connected in series between the gate electrode of the first transistor and the drain electrode of the first transistor, a first metal layer disposed on the substrate including the gate electrode of the third-1 transistor and the gate electrode of the third-2 transistor, a hydrogen passivation layer disposed on the first metal layer, semiconductor regions of the first transistor, the third-1 transistor, and the third-2 transistor disposed on the hydrogen passivation layer, a capping layer disposed on the semiconductor region of the first transistor, the gate electrode of the first transistor disposed on the capping layer, a first bias electrode disposed on the same layer as the gate electrode of the first transistor and overlapping with the semiconductor region of the third-1 transistor, and a second bias electrode disposed on the same layer as the first bias electrode and overlapping with the semiconductor region of the third-2 transistor.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being applied to various electronic devices such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions. By including light-emitting elements in which each pixel of the display panel can emit light independently, the display device can display images without a backlight unit that provides light to the display panel.

[0003] The display device includes a plurality of pixels, data lines and gate lines connected to the plurality of pixels, a data driver that supplies a data voltage to the data lines, and a gate driver that supplies a gate signal to the gate lines. The data driver and the gate driver can drive the plurality of pixels according to a predetermined frequency. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device capable of improving the driving range of a first transistor and improving the leakage current characteristics and low-frequency characteristics of transistors electrically connected to the gate electrode of the first transistor.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem comprises: a light-emitting element disposed on a substrate; a first transistor controlling a driving current flowing through the light-emitting element; a second transistor supplying a data voltage to the source electrode of the first transistor; a third-1 transistor and a third-2 transistor connected in series between the gate electrode of the first transistor and the drain electrode of the first transistor; a first metal layer disposed on the substrate and including the gate electrode of the third-1 transistor and the gate electrode of the third-2 transistor; a hydrogen passivation layer disposed on the first metal layer; semiconductor regions of the first transistor, the third-1 transistor, and the third-2 transistor disposed on the hydrogen passivation layer; a capping layer disposed on the semiconductor region of the first transistor; a gate electrode of the first transistor disposed on the capping layer; a first bias electrode disposed on the same layer as the gate electrode of the first transistor and overlapping with the semiconductor region of the third-1 transistor; and a second bias electrode disposed on the same layer as the first bias electrode and overlapping with the semiconductor region of the third-2 transistor. Includes a bias electrode.

[0007] The hydrogen passivation layer can directly contact the lower surface of the semiconductor region of each of the first transistor, the third-1 transistor, and the third-2 transistor.

[0008] The first and second bias electrodes are electrically connected to a driving voltage line to receive a driving voltage.

[0009] The above display device may further include a 4-1 transistor and a 4-2 transistor connected in series between the gate electrode of the first transistor and a first initialization voltage line, and a second metal layer disposed on the same layer as the first metal layer and including the gate electrode of the 4-1 transistor and the gate electrode of the 4-2 transistor.

[0010] The gate electrode of the second transistor receives a first gate signal from a first gate line, and the first metal layer can receive a second gate signal different from the first gate signal from a second gate line.

[0011] The second metal layer can receive a third gate signal different from the first and second gate signals from the third gate line.

[0012] The display device may further include a third bias electrode disposed on the same layer as the second bias electrode and overlapping with the semiconductor region of the 4-1 transistor, and a fourth bias electrode disposed on the same layer as the third bias electrode and overlapping with the semiconductor region of the 4-2 transistor.

[0013] The third and fourth bias electrodes are electrically connected to a driving voltage line to receive a driving voltage.

[0014] The above display device may further include a fifth transistor disposed between the source electrode of the first transistor and a driving voltage line, a sixth transistor disposed between the drain electrode of the first transistor and the light-emitting element, and a seventh transistor disposed between the first electrode of the light-emitting element and a second initialization voltage line.

[0015] The above display device may further include an eighth transistor disposed between the source electrode and the bias voltage line of the first transistor.

[0016] The first transistor includes a protrusion formed on the semiconductor region, source electrode, and drain electrode of the first transistor, and the capping layer can cover the protrusion of the first transistor.

[0017] The above display device further includes a gate insulating film disposed between the capping layer and the gate electrode of the first transistor, wherein the capping layer includes a silicon oxide layer or an amorphous silicon layer, and the gate insulating film may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0018] A display device according to one embodiment for solving the above problem comprises: a light-emitting element disposed on a substrate; a first transistor controlling a driving current flowing through the light-emitting element; a second transistor supplying a data voltage to the source electrode of the first transistor; a third-1 transistor and a third-2 transistor connected in series between the gate electrode of the first transistor and the drain electrode of the first transistor; a first metal layer disposed on the substrate and including the gate electrode of the third-1 transistor and the gate electrode of the third-2 transistor; a hydrogen passivation layer disposed on the first metal layer; semiconductor regions of the first transistor, the third-1 transistor, and the third-2 transistor disposed on the hydrogen passivation layer; a capping layer disposed on the semiconductor region of the first transistor; a gate electrode of the first transistor disposed on the capping layer; a first bias electrode disposed on the same layer as the gate electrode of the first transistor and overlapping with the semiconductor region of the third-1 transistor; and a first bias electrode disposed on the same layer as the first bias electrode and overlapping with the semiconductor region of the third-2 transistor, and the It includes a second bias electrode electrically connected to the first metal layer.

[0019] The first bias electrode is electrically connected to a driving voltage line to receive a driving voltage.

[0020] The gate electrode of the second transistor receives a first gate signal from a first gate line, and the first metal layer and the second bias electrode can receive a second gate signal different from the first gate signal from a second gate line.

[0021] The above display device may further include a second metal layer disposed on the same layer as the first metal layer and overlapping with the semiconductor region of the first transistor.

[0022] The second metal layer above is electrically connected to a driving voltage line and can receive a driving voltage.

[0023] A display device of one embodiment for solving the above problem comprises a light-emitting element disposed on a substrate, a first transistor controlling a driving current flowing through the light-emitting element, a second transistor supplying a data voltage to the source electrode of the first transistor, a third-1 transistor and a third-2 transistor connected in series between the gate electrode of the first transistor and the drain electrode of the first transistor, a first metal layer disposed on the substrate including the gate electrode of the third-1 transistor and the gate electrode of the third-2 transistor, semiconductor regions of the first transistor, the third-1 transistor, and the third-2 transistor disposed on the first metal layer, a gate electrode of the first transistor disposed on the semiconductor region of the first transistor, and a first bias electrode disposed on the same layer as the gate electrode of the first transistor, overlapping with the semiconductor region of the third-1 transistor, and electrically connected to a driving voltage line, wherein the gate electrode of the first transistor is electrically connected to the source electrode of the third-1 transistor disposed on the same layer as the semiconductor region of the third-1 transistor.

[0024] The apparatus further comprises a 4-1 transistor and a 4-2 transistor connected in series between the gate electrode of the 1 transistor and a first initialization voltage line, and a second metal layer disposed on the same layer as the 1 metal layer and including the gate electrode of the 4-1 transistor and the gate electrode of the 4-2 transistor, wherein the gate electrode of the 1 transistor can be electrically connected to the source electrode of the 4-1 transistor disposed on the same layer as the semiconductor region of the 4-1 transistor.

[0025] The above display device may further include a third metal layer disposed on the same layer as the first metal layer, overlapping with the semiconductor region of the first transistor, and electrically connected to a driving voltage line.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0027] According to the display device of the embodiments, the driving range of the first transistor can be improved by including a capping layer covering a protrusion of the first transistor. Transistors electrically connected to the gate electrodes of the first transistors may include a gate electrode disposed below the semiconductor region and a bias electrode disposed on the semiconductor region, and a hydrogen passivation layer may be in direct contact with the lower surface of the semiconductor region. Accordingly, by including a hydrogen passivation layer, the display device can eliminate interfacial defects of the transistors electrically connected to the gate electrodes of the first transistors, thereby improving leakage current characteristics and low frequency characteristics.

[0028] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0029] FIG. 1 is a perspective view showing a display device according to one embodiment. FIG. 2 is a cross-sectional view showing a display device according to one embodiment. FIG. 3 is a plan view showing a display portion of a display device according to one embodiment. FIG. 4 is a block diagram showing a display panel and a display driving unit according to one embodiment. FIG. 5 is a circuit diagram showing a pixel of a display device according to one embodiment. Figure 6 is a waveform of the signals supplied to the pixel shown in Figure 5. FIG. 7 is a cross-sectional view showing a part of a display device according to one embodiment. FIG. 8 is a cross-sectional view showing another part of a display device according to one embodiment. FIG. 9 is a graph showing the transfer characteristics of the first and second test transistors in a display device according to one embodiment. FIG. 10 is a circuit diagram showing a pixel of a display device according to another embodiment. FIG. 11 is a cross-sectional view showing a part of a display device according to another embodiment. Specific details for implementing the invention

[0030] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0031] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0032] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0033] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0034] Specific embodiments will be described below with reference to the attached drawings.

[0035] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0036] Referring to FIG. 1, the display device (10) can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra mobile PCs (UMPCs). For example, the display device (10) can be applied to a television, laptop, monitor, billboard, or display unit of the Internet of Things (IOT). As another example, the display device (10) can be applied to wearable devices such as smart watches, watch phones, glasses displays, and head-mounted displays (HMDs).

[0037] The display device (10) may be formed in a planar shape similar to a rectangle. For example, the display device (10) may have a planar shape similar to a rectangle having a short side in the X-axis direction and a long side in the Y-axis direction. The corners where the short side in the X-axis direction and the long side in the Y-axis direction meet may be formed rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display device (10) is not limited to a rectangle and may be formed similarly to other polygons, circles, or ellipses.

[0038] The display device (10) may include a display panel (100), a display driving unit (200), a circuit board (300), a touch driving unit (400), and a power supply unit (500).

[0039] The display panel (100) may include a main area (MA) and a sub-area (SBA).

[0040] The main area (MA) may include a display area (DA) having pixels that display an image, and a non-display area (NDA) disposed around the display area (DA). The display area (DA) may emit light from a plurality of light-emitting areas or a plurality of aperture areas. For example, the display panel (100) may include a pixel circuit including switching elements, a pixel defining film defining a light-emitting area or an aperture area, and a self-light-emitting element.

[0041] For example, the self-luminous device may include at least one of an organic light-emitting diode (OLED) including an organic light-emitting layer, a quantum dot light-emitting diode (QLED) including a quantum dot light-emitting layer, an inorganic light-emitting diode (Inorganic LED) including an inorganic semiconductor, and a micro light-emitting diode (Micro LED), but is not limited thereto.

[0042] The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may be defined as an edge area of ​​the main area (MA) of the display panel (100). The non-display area (NDA) may include a gate driver (not shown) that supplies gate signals to gate lines, and fan-out lines (not shown) connecting the display driver (200) and the display area (DA).

[0043] A sub-region (SBA) may extend from one side of a main region (MA). The sub-region (SBA) may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-region (SBA) is bent, the sub-region (SBA) may overlap with the main region (MA) in the thickness direction (Z-axis direction). The sub-region (SBA) may include a pad portion connected to a display driving unit (200) and a circuit board (300). Optionally, the sub-region (SBA) may be omitted, and the display driving unit (200) and the pad portion may be placed in a non-display area (NDA).

[0044] The display driver (200) can output signals and voltages for driving the display panel (100). The display driver (200) can supply data voltages to data lines. The display driver (200) can supply power voltage to power lines and supply gate control signals to the gate driver. The display driver (200) can be formed as an integrated circuit (IC) and mounted on the display panel (100) using a Chip on Glass (COG) method, a Chip on Plastic (COP) method, or an ultrasonic bonding method. For example, the display driver (200) can be placed in a sub-region (SBA) and can overlap with the main region (MA) in the thickness direction (Z-axis direction) by bending the sub-region (SBA). As another example, the display driver (200) can be mounted on a circuit board (300).

[0045] The circuit board (300) can be attached to the pad portion of the display panel (100) using an anisotropic conductive film (ACF). The lead lines of the circuit board (300) can be electrically connected to the pad portion of the display panel (100). The circuit board (300) may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip-on-film.

[0046] The touch driving unit (400) may be mounted on the circuit board (300). The touch driving unit (400) may be electrically connected to the touch sensing unit of the display panel (100). The touch driving unit (400) may supply a touch driving signal to a plurality of touch electrodes of the touch sensing unit and sense the amount of change in capacitance between the plurality of touch electrodes. For example, the touch driving signal may be a pulse signal having a predetermined frequency. The touch driving unit (400) may calculate whether an input has been made and the input coordinates based on the amount of change in capacitance between the plurality of touch electrodes. The touch driving unit (400) may be formed as an integrated circuit (IC).

[0047] The power supply unit (500) is positioned on the circuit board (300) and can supply power voltage to the display driving unit (200) and the display panel (100). The power supply unit (500) can generate a driving voltage and supply it to the driving voltage line, generate an initialization voltage and supply it to the initialization voltage line, and generate a common voltage and supply it to a common electrode common to the light-emitting elements of a plurality of pixels. For example, the driving voltage may be a high potential voltage for driving the light-emitting element, and the common voltage may be a low potential voltage for driving the light-emitting element.

[0048] FIG. 2 is a cross-sectional view showing a display device according to one embodiment.

[0049] Referring to FIG. 2, the display panel (100) may include a display unit (DU), a touch sensing unit (TSU), and a color filter layer (CFL). The display unit (DU) may include a substrate (SUB), a thin film transistor layer (TFTL), a light-emitting element layer (EML), and an encapsulation layer (TFEL).

[0050] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate (SUB) may include a glass material or a metal material.

[0051] A thin-film transistor layer (TFTL) may be disposed on a substrate (SUB). The thin-film transistor layer (TFTL) may include a plurality of thin-film transistors that constitute a pixel circuit of pixels. The thin-film transistor layer (TFTL) may further include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver (200) and the data lines, and lead lines connecting the display driver (200) and the pad portion. Each of the thin-film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, if the gate driver is formed on one side of the non-display area (NDA) of the display panel (100), the gate driver may include thin-film transistors.

[0052] The thin-film transistor layer (TFTL) can be placed in a display area (DA), a non-display area (NDA), and a sub-area (SBA). The thin-film transistors, gate lines, data lines, and power lines of each pixel of the thin-film transistor layer (TFTL) can be placed in the display area (DA). The gate control lines and fan-out lines of the thin-film transistor layer (TFTL) can be placed in the non-display area (NDA). The lead lines of the thin-film transistor layer (TFTL) can be placed in the sub-area (SBA).

[0053] A light-emitting element layer (EML) may be disposed on a thin-film transistor layer (TFTL). The light-emitting element layer (EML) may include a plurality of light-emitting elements that emit light by sequentially stacking a pixel electrode, a light-emitting layer, and a common electrode, and a pixel defining film that defines the pixels. The plurality of light-emitting elements of the light-emitting element layer (EML) may be disposed in a display area (DA).

[0054] For example, the light-emitting layer may be an organic light-emitting layer containing an organic material. The light-emitting layer may include a hole transporting layer, an organic light-emitting layer, and an electron transporting layer. When the pixel electrode receives a predetermined voltage through a thin-film transistor of a thin-film transistor layer (TFTL) and the common electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transporting layer and the electron transporting layer, respectively, and combine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode and the common electrode may be a cathode electrode, but is not limited thereto.

[0055] As another example, a plurality of light-emitting elements may include a quantum dot light-emitting diode comprising a quantum dot light-emitting layer, an inorganic light-emitting diode comprising an inorganic semiconductor, or a micro-light-emitting diode.

[0056] The encapsulation layer (TFEL) can cover the upper surface and side surface of the light-emitting element layer (EML) and can protect the light-emitting element layer (EML). The encapsulation layer (TFEL) may include at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer (EML).

[0057] A touch sensing unit (TSU) may be disposed on an encapsulation layer (TFEL). The touch sensing unit (TSU) may include a plurality of touch electrodes for detecting a user's touch in a capacitive manner, and touch lines connecting the plurality of touch electrodes to a touch driving unit (400). For example, the touch sensing unit (TSU) may sense a user's touch in a mutual capacitance manner or a self-capacitance manner.

[0058] As another example, the touch sensing unit (TSU) may be disposed on a separate substrate placed on the display unit (DU). In this case, the substrate supporting the touch sensing unit (TSU) may be a base member that encapsulates the display unit (DU).

[0059] Multiple touch electrodes of the touch sensing unit (TSU) may be placed in a touch sensor area that overlaps with the display area (DA). Touch lines of the touch sensing unit (TSU) may be placed in a touch peripheral area that overlaps with the non-display area (NDA).

[0060] A color filter layer (CFL) may be disposed on a touch sensing unit (TSU). The color filter layer (CFL) may include a plurality of color filters corresponding to each of a plurality of light-emitting regions. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer (CFL) may absorb a portion of the light entering from outside the display device (10) to reduce reflected light caused by external light. Therefore, the color filter layer (CFL) can prevent color distortion caused by external light reflection.

[0061] Since the color filter layer (CFL) is placed directly on the touch sensing unit (TSU), the display device (10) may not require a separate substrate for the color filter layer (CFL). Therefore, the thickness of the display device (10) can be relatively reduced.

[0062] A sub-region (SBA) of the display panel (100) may extend from one side of the main region (MA). The sub-region (SBA) may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-region (SBA) is bent, the sub-region (SBA) may overlap with the main region (MA) in the thickness direction (Z-axis direction). The sub-region (SBA) may include a pad portion electrically connected to the display driving unit (200) and the circuit board (300).

[0063] FIG. 3 is a plan view showing a display unit of a display device according to one embodiment, and FIG. 4 is a block diagram showing a display panel and a display driving unit according to one embodiment.

[0064] Referring to FIGS. 3 and FIGS. 4, the display panel (100) may include a display area (DA) and a non-display area (NDA).

[0065] The display area (DA) may include a plurality of pixels (SP), a plurality of driving voltage lines (VDDL) connected to the plurality of pixels (SP), a plurality of gate lines (GL), a plurality of light emission control lines (EML), and a plurality of data lines (DL).

[0066] Each of the plurality of pixels (SP) can be connected to a gate line (GL), a data line (DL), a light emission control line (EML), and a driving voltage line (VDDL). Each of the plurality of pixels (SP) may include at least one transistor, a light-emitting element, and a capacitor.

[0067] The gate lines (GL) can be extended in the X-axis direction and can be spaced apart from each other in the Y-axis direction intersecting the X-axis direction. The gate lines (GL) can sequentially supply gate signals to multiple pixels (SP).

[0068] The light emission control lines (EML) can be extended in the X-axis direction and spaced apart from each other in the Y-axis direction. The light emission control lines (EML) can sequentially supply light emission signals to a plurality of pixels (SP).

[0069] Data lines (DL) can be extended in the Y-axis direction and spaced apart from each other in the X-axis direction. Data lines (DL) can supply data voltage to multiple pixels (SP). The data voltage can determine the brightness of each of the multiple pixels (SP).

[0070] The driving voltage lines (VDDL) can be extended in the Y-axis direction and spaced apart from each other in the X-axis direction. The driving voltage lines (VDDL) can supply driving voltage to multiple pixels (SP). The driving voltage may be a high potential voltage for driving the light-emitting elements of the pixels (SP).

[0071] A non-display area (NDA) may surround a display area (DA). The non-display area (NDA) may include a gate driver (610), a light emission control driver (620), fan-out lines (FL), a first gate control line (GSL1), and a second gate control line (GSL2).

[0072] Fan-out lines (FL) can extend from the display driver (200) to the display area (DA). Fan-out lines (FL) can supply data voltage received from the display driver (200) to a plurality of data lines (DL).

[0073] The first gate control line (GSL1) may extend from the display driver (200) to the gate driver (610). The first gate control line (GSL1) may supply a gate control signal (GCS) received from the display driver (200) to the gate driver (610).

[0074] The second gate control line (GSL2) can be extended from the display driver (200) to the light emission control driver (620). The second gate control line (GSL2) can supply a light emission control signal (ECS) received from the display driver (200) to the light emission control driver (620).

[0075] A sub-region (SBA) may extend from one side of a non-display area (NDA). The sub-region (SBA) may include a display driver (200) and a pad portion (DP). The pad portion (DP) may be positioned adjacent to one edge of the sub-region (SBA) than the display driver (200). The pad portion (DP) may be electrically connected to a circuit board (300) through an anisotropic conductive film (ACF).

[0076] The display driving unit (200) may include a timing control unit (210) and a data driving unit (220).

[0077] The timing control unit (210) can receive digital video data (DATA) and timing signals from the circuit board (300). The timing control unit (210) can control the operation timing of the data driver (220) by generating a data control signal (DCS) based on the timing signals, control the operation timing of the gate driver (610) by generating a gate control signal (GCS), and control the operation timing of the light emission control driver (620) by generating a light emission control signal (ECS). The timing control unit (210) can supply the gate control signal (GCS) to the gate driver (610) through the first gate control line (GSL1). The timing control unit (210) can supply the light emission control signal (ECS) to the light emission control driver (620) through the second gate control line (GSL2). The timing control unit (210) can supply digital video data (DATA) and a data control signal (DCS) to the data driving unit (220).

[0078] The data driver (220) can convert digital video data (DATA) into analog data voltages and supply them to data lines (DL) through fan-out lines (FL). The gate signals of the gate driver (610) can select pixels (SP) to which data voltage is supplied, and the selected pixels (SP) can receive data voltage through data lines (DL).

[0079] The power supply unit (500) is positioned on the circuit board (300) and can supply power voltage to the display driving unit (200) and the display panel (100). The power supply unit (500) can generate a driving voltage and supply it to the driving voltage line (VDDL), generate an initialization voltage and supply it to the initialization voltage line, and generate a common voltage and supply it to a common electrode that is common to the light-emitting elements of a plurality of pixels.

[0080] The gate driver (610) may be positioned on one side outside the display area (DA) or on one side of the non-display area (NDA), and the light emission control driver (620) may be positioned on the other side outside the display area (DA) or on the other side of the non-display area (NDA), but is not limited thereto. As another example, the gate driver (610) and the light emission control driver (620) may be positioned on either one side or the other side of the non-display area (NDA).

[0081] The gate driver (610) may include a plurality of transistors that generate gate signals based on a gate control signal (GCS). The light emission control driver (620) may include a plurality of transistors that generate light emission signals based on a light emission control signal (ECS). For example, the transistors of the gate driver (610) and the transistors of the light emission control driver (620) may be formed on the same layer as the transistors of each pixel (SP). The gate driver (610) may supply gate signals to gate lines (GL), and the light emission control driver (620) may supply light emission signals to light emission control lines (EML).

[0082] FIG. 5 is a circuit diagram showing a pixel of a display device according to one embodiment, and FIG. 6 is a waveform diagram of signals supplied to the pixel shown in FIG. 5.

[0083] Referring to FIGS. 5 and 6, a display panel (100) may include a plurality of pixels (SP) arranged along p rows (p is a natural number) and q columns (q is a natural number). Each of the plurality of pixels (SP) may be connected to a first gate line (GWL), a second gate line (GCL), a third gate line (GIL), a fourth gate line (GBL), a light emission control line (EML), a data line (DL), a driving voltage line (VDDL), a first initialization voltage line (VIL1), a second initialization voltage line (VIL2), and a bias voltage line (VBL).

[0084] A pixel (SP) may include a pixel circuit and a light-emitting element (ED). The pixel circuit may include a first transistor (ST1), a second transistor (ST2), a third-1 transistor (ST3-1), a third-2 transistor (ST3-2), a fourth-1 transistor (ST4-1), a fourth-2 transistor (ST4-2), a fifth transistor (ST5), a sixth transistor (ST6), a seventh transistor (ST7), an eighth transistor (ST8), and a storage capacitor (CST).

[0085] The first transistor (ST1) may include a gate electrode, a source electrode, and a drain electrode. The first transistor (ST1) can control a source-drain current (Isd, hereinafter referred to as "driving current") according to a data voltage applied to the gate electrode. The driving current (Isd) flowing through the channel of the first transistor (ST1) may be proportional to the square of the difference between the voltage (Vsg) between the source electrode and the gate electrode of the first transistor (ST1) and the threshold voltage (Vth) (Isd = k × (Vsg - Vth) 2 Here, k represents the proportionality constant determined by the structure and physical characteristics of the first transistor (ST1), Vsg represents the source-gate voltage of the first transistor (ST1), and Vth represents the threshold voltage of the first transistor (ST1).

[0086] A light-emitting element (ED) can emit light by receiving a driving current (Isd). The amount of light emitted or the brightness of the light-emitting element (ED) can be proportional to the magnitude of the driving current (Isd).

[0087] The light-emitting element (ED) may be an organic light-emitting diode comprising a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode. As another example, the light-emitting element (ED) may be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. As yet another example, the light-emitting element (ED) may be a quantum dot light-emitting element comprising a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first electrode and the second electrode. As yet another example, the light-emitting element (ED) may be a micro light-emitting diode.

[0088] The first electrode of the light-emitting element (ED) can be electrically connected to the fourth node (N4). The first electrode of the light-emitting element (ED) can be connected to the drain electrode of the sixth transistor (ST6) and the source electrode of the seventh transistor (ST7) through the fourth node (N4). The second electrode of the light-emitting element (ED) can be connected to the low potential line (VSSL). The second electrode of the light-emitting element (ED) can receive a low potential voltage from the low potential line (VSSL).

[0089] The second transistor (ST2) can be turned on by the first gate signal (GW[n]) of the first gate line (GWL) to electrically connect the data line (DL) and the first node (N1), which is the source electrode of the first transistor (ST1). By turning on the second transistor (ST2) based on the first gate signal (GW[n]), it can supply a data voltage to the first node (N1). The gate electrode of the second transistor (ST2) can be electrically connected to the first gate line (GWL), the source electrode can be electrically connected to the data line (DL), and the drain electrode can be electrically connected to the first node (N1).

[0090] The third-1 transistor (ST3-1) and the third-2 transistor (ST3-2) can be turned on by the second gate signal (GC[n]) of the second gate line (GCL) to electrically connect the second node (N2), which is the drain electrode of the first transistor (ST1), and the third node (N3), which is the gate electrode of the first transistor (ST1). The third-1 transistor (ST3-1) and the third-2 transistor (ST3-2) can be connected in series between the second node (N2) and the third node (N3). The gate electrode of the third-1 transistor (ST3-1) can be electrically connected to the second gate line (GCL), the source electrode can be electrically connected to the third node (N3), and the drain electrode can be electrically connected to the source electrode of the third-2 transistor (ST3-2). The gate electrode of the third-2 transistor (ST3-2) is electrically connected to the second gate line (GCL), the source electrode is electrically connected to the drain electrode of the third-1 transistor (ST3-1), and the drain electrode can be electrically connected to the second node (N2). The gate electrode of the third-1 transistor (ST3-1) and the gate electrode of the third-2 transistor (ST3-2) can be formed as a single unit.

[0091] Each of the third-1 transistor (ST3-1) and the third-2 transistor (ST3-2) may include a bias electrode. The bias electrode of the third-1 transistor (ST3-1) may overlap with the semiconductor region of the third-1 transistor (ST3-1), and the bias electrode of the third-2 transistor (ST3-2) may overlap with the semiconductor region of the third-2 transistor (ST3-2). The bias electrodes of the third-1 transistor (ST3-1) and the third-2 transistor (ST3-2) may be electrically connected to a driving voltage line (VDDL) and may receive a driving voltage from the driving voltage line (VDDL). Accordingly, the bias electrodes of the third-1 transistor (ST3-1) and the third-2 transistor (ST3-2) may stabilize the electric field of the third-1 transistor (ST3-1) and the third-2 transistor (ST3-2) and improve output characteristics.

[0092] The 3-1 transistor (ST3-1) and the 3-2 transistor (ST3-2) may have excellent off-current characteristics. Therefore, the 3-1 transistor (ST3-1) and the 3-2 transistor (ST3-2) can prevent leakage current from flowing at the third node (N3), which is the gate electrode of the 1 transistor (ST1), and can stably maintain the voltage inside the pixel (SP). The leakage current characteristics of the 3-1 transistor (ST3-1) and the 3-2 transistor (ST3-2) are explained in detail in FIG. 7.

[0093] The 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) can be turned on by the third gate signal (GI[n]) of the third gate line (GIL) to electrically connect the third node (N3), which is the gate electrode of the 1 transistor (ST1), to the first initialization voltage line (VIL1). The 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) can be connected in series between the third node (N3) and the first initialization voltage line (VIL1). The gate electrode of the 4-1 transistor (ST4-1) can be electrically connected to the third gate line (GIL), the source electrode can be electrically connected to the third node (N3), and the drain electrode can be electrically connected to the source electrode of the 4-2 transistor (ST4-2). The gate electrode of the 4-2 transistor (ST4-2) is electrically connected to the 3rd gate line (GIL), the source electrode is electrically connected to the drain electrode of the 4-1 transistor (ST4-1), and the drain electrode can be electrically connected to the 1st initialization voltage line (VIL1). The gate electrode of the 4-1 transistor (ST4-1) and the gate electrode of the 4-2 transistor (ST4-2) can be formed as a single unit.

[0094] Each of the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) may include a bias electrode. The bias electrode of the 4-1 transistor (ST4-1) may overlap with the semiconductor region of the 4-1 transistor (ST4-1), and the bias electrode of the 4-2 transistor (ST4-2) may overlap with the semiconductor region of the 4-2 transistor (ST4-2). The bias electrodes of the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) may be electrically connected to a driving voltage line (VDDL) and may receive a driving voltage from the driving voltage line (VDDL). Accordingly, the bias electrodes of the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) may stabilize the electric field of the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) and improve output characteristics.

[0095] The 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) may have excellent off-current characteristics. Therefore, the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) can prevent leakage current from flowing at the third node (N3), which is the gate electrode of the 1 transistor (ST1), and can stably maintain the voltage inside the pixel (SP). The leakage current characteristics of the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) are explained in detail in FIG. 8.

[0096] The fifth transistor (ST5) can be turned on by the light emission signal (EM[n]) of the light emission control line (EML) to electrically connect the driving voltage line (VDDL) and the first node (N1), which is the source electrode of the first transistor (ST1). The gate electrode of the fifth transistor (ST5) can be electrically connected to the light emission control line (EML), the source electrode can be electrically connected to the driving voltage line (VDDL), and the drain electrode can be electrically connected to the first node (N1).

[0097] The sixth transistor (ST6) can be turned on by the light emission signal (EM[n]) of the light emission control line (EML) to electrically connect the second node (N2), which is the drain electrode of the first transistor (ST1), and the fourth node (N4), which is the first electrode of the light emission element (ED). The gate electrode of the sixth transistor (ST6) can be electrically connected to the light emission control line (EML), the source electrode can be electrically connected to the second node (N2), and the drain electrode can be electrically connected to the fourth node (N4).

[0098] When the fifth transistor (ST5), the first transistor (ST1), and the sixth transistor (ST6) are all turned on, the driving current can be supplied to the light-emitting element (ED).

[0099] The seventh transistor (ST7) can be turned on by the fourth gate signal (GB[n]) of the fourth gate line (GBL) to electrically connect the fourth node (N4), which is the first electrode of the light-emitting element (ED), and the second initialization voltage line (VIL2). By turning on the seventh transistor (ST7) based on the fourth gate signal (GB[n]), the first electrode of the light-emitting element (ED) can be discharged to the second initialization voltage. The gate electrode of the seventh transistor (ST7) can be electrically connected to the fourth gate line (GBL), the source electrode can be electrically connected to the fourth node (N4), and the drain electrode can be electrically connected to the second initialization voltage line (VIL2).

[0100] The eighth transistor (ST8) can be turned on by the fourth gate signal (GB[n]) of the fourth gate line (GBL) to electrically connect the bias voltage line (VBL) and the first node (N1), which is the source electrode of the first transistor (ST1). By turning on the eighth transistor (ST8) based on the fourth gate signal (GB[n]), it can supply a bias voltage to the first node (N1). By supplying a bias voltage to the source electrode of the first transistor (ST1), the eighth transistor (ST8) can improve the hysteresis of the first transistor (ST1). The gate electrode of the eighth transistor (ST8) can be electrically connected to the fourth gate line (GBL), the source electrode can be electrically connected to the bias voltage line (VBL), and the drain electrode can be electrically connected to the first node (N1).

[0101] Each of the first transistor (ST1), second transistor (ST2), third-1 transistor (ST3-1), third-2 transistor (ST3-2), fourth-1 transistor (ST4-1), fourth-2 transistor (ST4-2), fifth transistor (ST5), sixth transistor (ST6), seventh transistor (ST7), and eighth transistor (ST8) may include a silicon-based active layer. For example, each of the first transistor (ST1), second transistor (ST2), third-1 transistor (ST3-1), third-2 transistor (ST3-2), fourth-1 transistor (ST4-1), fourth-2 transistor (ST4-2), fifth transistor (ST5), sixth transistor (ST6), seventh transistor (ST7), and eighth transistor (ST8) may include an active layer made of low-temperature polycrystalline silicon (LTPS). An active layer made of low-temperature polycrystalline silicon may have high electron mobility and excellent turn-on characteristics. Accordingly, the display device (10) can stably and efficiently drive a plurality of pixels (SP) by including transistors with excellent turn-on characteristics.

[0102] Each of the first transistor (ST1), second transistor (ST2), third-1 transistor (ST3-1), third-2 transistor (ST3-2), fourth-1 transistor (ST4-1), fourth-2 transistor (ST4-2), fifth transistor (ST5), sixth transistor (ST6), seventh transistor (ST7), and eighth transistor (ST8) may correspond to a p-type transistor. For example, each of the first transistor (ST1), second transistor (ST2), third-1 transistor (ST3-1), third-2 transistor (ST3-2), fourth-1 transistor (ST4-1), fourth-2 transistor (ST4-2), fifth transistor (ST5), sixth transistor (ST6), seventh transistor (ST7), and eighth transistor (ST8) can output current flowing into the source electrode to the drain electrode based on the gate low voltage applied to the gate electrode.

[0103] As another example, at least one of the first transistor (ST1), second transistor (ST2), third-1 transistor (ST3-1), third-2 transistor (ST3-2), fourth-1 transistor (ST4-1), fourth-2 transistor (ST4-2), fifth transistor (ST5), sixth transistor (ST6), seventh transistor (ST7), and eighth transistor (ST8) may include an oxide-based active layer. A transistor including an oxide-based active layer may have a coplanar structure with a gate electrode disposed on top. A transistor including an oxide-based active layer may correspond to an n-type transistor and may output current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0104] The storage capacitor (CST) can be electrically connected between the third node (N3), which is the gate electrode of the first transistor (ST1), and the driving voltage line (VDDL). For example, the first capacitor electrode of the storage capacitor (CST) is electrically connected to the third node (N3), and the second capacitor electrode of the storage capacitor (CST) is electrically connected to the driving voltage line (VDDL), thereby maintaining a potential difference between the driving voltage line (VDDL) and the gate electrode of the first transistor (ST1).

[0105] When combining FIG. 6 with FIG. 5, when the display device (10) is driven at a predetermined driving frequency, one frame period may include at least one scanning period (SCP) and at least one blanking period (BLP). The scanning period (SCP) may include a first to fifth period (t1 to t5), and the blanking period (BLP) may include a sixth and seventh period (t6, t7).

[0106] The 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) can receive a low-level third gate signal (GI[n]) during a first period (t1). The 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) can be turned on based on the low-level third gate signal (GI[n]) and can discharge the third node (N3), which is the gate electrode of the 1 transistor (ST1), to a first initialization voltage. Thus, the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) can initialize the gate electrode of the 1 transistor (ST1) during the first period (t1).

[0107] The second transistor (ST2) can receive a low-level first gate signal (GW[n]) during the second period (t2). The second transistor (ST2) can be turned on based on the low-level first gate signal (GW[n]) and can supply a data voltage to the first node (N1), which is the source electrode of the first transistor (ST1).

[0108] The 3-1 transistor (ST3-1) and the 3-2 transistor (ST3-2) can receive a low-level second gate signal (GC[n]) during the third period (t3). The 3-1 transistor (ST3-1) and the 3-2 transistor (ST3-2) can be turned on based on the low-level second gate signal (GC[n]) and can electrically connect the second node (N2) and the third node (N3).

[0109] The seventh transistor (ST7) can receive a low-level fourth gate signal (GB[n]) during the fourth period (t4). The fourth gate signal (GB[n]) can be stepped down during the fourth period (t4). The seventh transistor (ST7) can be turned on based on the low-level fourth gate signal (GB[n]) and discharge the first electrode of the light-emitting element (ED) to a second initialization voltage. Thus, the seventh transistor (ST7) can initialize the first electrode of the light-emitting element (ED) during the fourth period (t4).

[0110] The eighth transistor (ST8) can receive a low-level fourth gate signal (GB[n]) during the fourth period (t4). The eighth transistor (ST8) can be turned on based on the low-level fourth gate signal (GB[n]) and can supply a bias voltage to the first node (N1), which is the source electrode of the first transistor (ST1). The eighth transistor (ST8) can set the operating point or operating condition of the first transistor (ST1) during the fourth period (t4). The eighth transistor (ST8) can prevent changes in the characteristics of the first transistor (ST1) due to bias stress and improve hysteresis.

[0111] When the source electrode of the first transistor (ST1) receives a data voltage (VDATA), the source-gate voltage (Vsg) of the first transistor (ST1) may correspond to the difference voltage (VDATA-VI1) between the data voltage (VDATA) and the first initialization voltage (VI1), and the first transistor (ST1) may be turned on when the source-gate voltage (Vsg) becomes greater than the threshold voltage (hereinafter referred to as "Vth") (VDATA-VI1 >= Vth). Accordingly, at the moment the second transistor (ST2) is turned on during the second period (t2), the source-drain current (Isd) of the first transistor (ST1) may be determined according to the data voltage (VDATA), the first initialization voltage (VI1), and the threshold voltage (Vth) of the first transistor (ST1) (Isd = k × (VDATA-VI1-Vth)^2). The first transistor (ST1) can supply a source-drain current (Isd) to the second node (N2) until the source-gate voltage (Vsg) reaches the threshold voltage (Vth) of the first transistor (ST1). Then, the third-1 transistor (ST3-1) and the third-2 transistor (ST3-2) can be turned on during a third period (t3) to supply the voltage of the second node (N2) to the third node (N3). In this way, while the first transistor (ST1) is turned on, the voltage of the third node (N3) and the source-drain current (Isd) of the first transistor (ST1) can be changed, and the voltage of the third node (N3) can eventually converge to the difference voltage (VDATA-Vth) between the data voltage (VDATA) and the threshold voltage (Vth) of the first transistor (ST1).

[0112] The light emission signal (EM[n]) may have a gate low voltage during the fifth period (t5). The light emission signal (EM[n]) may step down during the fifth period (t5). When the light emission signal (EM[n]) has a low level, the fifth and sixth transistors (ST5, ST6) may be turned on to supply driving current to the light-emitting element (ED).

[0113] The fourth gate signal (GB[n]) may have a gate low voltage during the sixth period (t6) of the blanking period (BLP). Thus, the seventh transistor (ST7) can initialize the fourth node (N4), which is the first electrode of the light-emitting element (ED), to the second initialization voltage even during the blanking period (BLP). The eighth transistor (ST8) can supply a bias voltage to the first node (N1), which is the source electrode of the first transistor (ST1), even during the blanking period (BLP), and can improve the hysteresis of the first transistor (ST1).

[0114] The light emission signal (EM[n]) may have a gate low voltage during the seventh period (t7) of the blanking interval (BLP). Thus, when the light emission signal (EM[n]) has a low level, the fifth and sixth transistors (ST5, ST6) can be turned on to supply a driving current to the first electrode of the initialized light emission element (ED).

[0115] FIG. 7 is a cross-sectional view showing a part of a display device according to one embodiment.

[0116] Referring to FIG. 7, a display panel (100) may include a substrate (SUB), a barrier layer (BR), a first metal layer (BML1), a first buffer layer (BF1), a second buffer layer (BF2), a hydrogen passivation layer (HPL), a first transistor (ST1), a third-first transistor (ST3-1), a third-second transistor (ST3-2), a capping layer (CPL), a first gate insulating film (GI1), a first bias electrode (BE1), a second bias electrode (BE2), a second gate insulating film (GI2), a capacitor electrode (CPE), an interlayer insulating film (ILD), a first connection electrode (CNE1), a second connection electrode (CNE2), a third connection electrode (CNE3), a first via layer (VIA1), an anode connection electrode (ANE), a second via layer (VIA2), a pixel defining film (PDL), a light-emitting element (ED), and an encapsulation layer (TFEL).

[0117] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a glass material or a metal material, but is not limited thereto. As another example, the substrate (SUB) may include a polymer resin such as polyimide (PI).

[0118] A barrier layer (BR) may be disposed on a substrate (SUB). The barrier layer (BR) may flatten the surface of the substrate (SUB) and protect the pixel circuit. The barrier layer (BR) may include an inorganic insulating material capable of preventing the penetration of air or moisture. The barrier layer (BR) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0119] The first metal layer (BML1) may be disposed on the barrier layer (BR). The first metal layer (BML1) may overlap with the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1) and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2). A portion of the first metal layer (BML1) may be the gate electrode (GE3-1) of the third-1 transistor (ST3-1), and another portion of the first metal layer (BML1) may be the gate electrode (GE3-2) of the third-2 transistor (ST3-2). The first metal layer (BML1) may be electrically connected to the second gate line (GCL) to receive the second gate signal (GC[n]). The first metal layer (BML1) may be formed as a single layer or a multilayer comprising at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0120] The first buffer layer (BF1) may be disposed on the first metal layer (BML1) and the barrier layer (BR). The first buffer layer (BF1) may include an inorganic insulating material capable of preventing the penetration of air or moisture. The first buffer layer (BF1) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0121] A second buffer layer (BF2) may be disposed on a first buffer layer (BF1). The second buffer layer (BF2) may include an inorganic insulating material capable of preventing the penetration of air or moisture. The second buffer layer (BF2) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto. For example, the first buffer layer (BF1) may include a silicon nitride layer, and the second buffer layer (BF2) may include a silicon oxide layer, but is not limited thereto.

[0122] A hydrogen passivation layer (HPL) may be disposed on a second buffer layer (BF2). The thickness of the hydrogen passivation layer (HPL) may be about 50 angstroms (Å) or less, but is not limited thereto. The hydrogen passivation layer (HPL) may be in direct contact with the lower surface of the semiconductor region (ACT1) of the first transistor (ST1), the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1), and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2). Since no protrusions are formed on the lower surface of the semiconductor region (ACT1) of the first transistor (ST1), the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1), and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2), the hydrogen passivation layer (HPL) may have a flat surface.

[0123] The hydrogen passivation layer (HPL) may have a high hydrogen content. The hydrogen passivation layer (HPL) may include silicon oxide having a high hydrogen content. For example, the ratio of nitrogen dioxide (N2O) to silane (SiH4) in the hydrogen passivation layer (HPL) (N2O / SiH4) may be 10 to 40, but is not limited thereto. As another example, the hydrogen passivation layer (HPL) can be formed through hydrogen implantation (H-Implantation) or hydrogen plasma treatment (H2 Plasma Treatment). The hydrogen in the hydrogen passivation layer (HPL) can reduce dangling coupling between the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1) and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2) by bonding with silicon on the surface of the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1) and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2). Thus, the hydrogen passivation layer (HPL) can eliminate interface defects between the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1) and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2) and improve leakage current characteristics and low-frequency characteristics. The display device (10) includes a hydrogen passivation layer (HPL) so that leakage current can be prevented from flowing through the third-1 transistor (ST3-1) and the third-2 transistor (ST3-2), and the voltage inside the pixel (SP) can be maintained stably.

[0124] The semiconductor region (ACT1), source electrode (SE1), and drain electrode (DE1) of the first transistor (ST1) may be placed on a hydrogen passivation layer (HPL). The semiconductor region (ACT1) of the first transistor (ST1) may overlap with the gate electrode (GE1) in the thickness direction and may be insulated from the gate electrode (GE1) by a capping layer (CPL) and a first gate insulating film (GI1). The source electrode (SE1) and the drain electrode (DE1) may be provided by making the material of the semiconductor region (ACT1) conductive. The drain electrode (DE1) of the first transistor (ST1) may be electrically connected to the drain electrode (DE3-2) of the third-second transistor (ST3-2) through the second node (N2) of FIG. 5.

[0125] The semiconductor region (ACT3-1), source electrode (SE3-1), and drain electrode (DE3-1) of the third-1 transistor (ST3-1) may be disposed on a hydrogen passivation layer (HPL). A portion of the first metal layer (BML1) may be the gate electrode (GE3-1) of the third-1 transistor (ST3-1). The semiconductor region (ACT3-1) of the third-1 transistor (ST3-1) may overlap with the gate electrode (GE3-1) in the thickness direction and may be insulated from the gate electrode (GE3-1) by a first buffer layer (BF1) and a second buffer layer (BF2). The source electrode (SE3-1) and the drain electrode (DE3-1) may be provided by making the material of the semiconductor region (ACT3-1) conductive. The drain electrode (DE3-1) of the third-1 transistor (ST3-1) may be formed integrally with the source electrode (SE3-2) of the third-2 transistor (ST3-2). The drain electrode (DE3-1) of the third-1 transistor (ST3-1) and the source electrode (SE3-2) of the third-2 transistor (ST3-2) may overlap with the first metal layer (BML1), but are not limited thereto.

[0126] The semiconductor region (ACT3-2), source electrode (SE3-2), and drain electrode (DE3-2) of the third-2 transistor (ST3-2) may be disposed on a hydrogen passivation layer (HPL). Another part of the first metal layer (BML1) may be the gate electrode (GE3-2) of the third-2 transistor (ST3-2). The semiconductor region (ACT3-2) of the third-2 transistor (ST3-2) may overlap with the gate electrode (GE3-2) in the thickness direction and may be insulated from the gate electrode (GE3-2) by a first buffer layer (BF1) and a second buffer layer (BF2). The source electrode (SE3-2) and drain electrode (DE3-2) may be provided by making the material of the semiconductor region (ACT3-2) conductive.

[0127] A capping layer (CPL) may be disposed on the semiconductor region (ACT1), source electrode (SE1), and drain electrode (DE1) of the first transistor (ST1), the semiconductor region (ACT3-1), source electrode (SE3-1), and drain electrode (DE3-1) of the third-first transistor (ST3-1), and the semiconductor region (ACT3-2), source electrode (SE3-2), and drain electrode (DE3-2) of the third-second transistor (ST3-2). The capping layer (CPL) may have the same pattern on a plane as the semiconductor region (ACT1), source electrode (SE1), and drain electrode (DE1) of the first transistor (ST1), the semiconductor region (ACT3-1), source electrode (SE3-1), and drain electrode (DE3-1) of the third-first transistor (ST3-1), and the semiconductor region (ACT3-2), source electrode (SE3-2), and drain electrode (DE3-2) of the third-second transistor (ST3-2). The capping layer (CPL) can cover protrusions formed on the semiconductor region (ACT1), source electrode (SE1), and drain electrode (DE1) of the first transistor (ST1). If the semiconductor region (ACT1) of the first transistor (ST1) includes low-temperature polycrystalline silicon (LTPS), the amorphous silicon layer provided on the substrate (SUB) can be melted and crystallized by a laser. In this case, as the amorphous silicon layer crystallizes, grains can grow, and protrusions can be formed at the grain boundaries between the grains. By covering the protrusions of the first transistor (ST1), the capping layer (CPL) can prevent the electric field from concentrating on the protrusions during the operation of the first transistor (ST1) and can improve the driving range of the first transistor (ST1). Accordingly, the display device (10) can precisely control the gradation of light emitted from the light-emitting element (ED) by including the capping layer (CPL).The capping layer (CPL) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0128] The first gate insulating film (GI1) may be disposed on the capping layer (CPL) and the hydrogen passivation layer (HPL). The first gate insulating film (GI1) may insulate the gate electrode (GE1) and the semiconductor region (ACT1) of the first transistor (ST1). The first gate insulating film (GI1) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto. The first gate insulating film (GI1) may include the same material as the capping layer (CPL), but is not limited thereto.

[0129] When the first gate insulating film (GI1) is formed through a deposition process, the thickness of the first gate insulating film (GI1) on the hydrogen passivation layer (HPL) and the thickness of the first gate insulating film (GI1) on the capping layer (CPL) may be substantially the same. The first thickness (T1) may be greater than the second thickness (T2). Here, the first thickness (T1) may be the sum of the thicknesses of the capping layer (CPL) and the first gate insulating film (GI1) that overlap each other, and the second thickness (T2) may be the thickness of the first gate insulating film (GI1) that does not overlap with the capping layer (CPL). The thickness of the capping layer (CPL) may be determined by the difference between the first thickness (T1) and the second thickness (T2). The thickness of the capping layer (CPL) may be about 20 to 200 Angstroms (Å), and preferably about 100 Angstroms (Å). Therefore, even if the first gate insulating film (GI1) and the capping layer (CPL) contain the same material, it can be seen that the capping layer (CPL) is placed on the first transistor (ST1), the third-1 transistor (ST3-1), and the third-2 transistor (ST3-2) to cover the protrusions of the first transistor (ST1), the third-1 transistor (ST3-1), and the third-2 transistor (ST3-2).

[0130] The first bias electrode (BE1), the second bias electrode (BE2), and the gate electrode (GE1) of the first transistor (ST1) may be disposed on the first gate insulating film (GI1). The first bias electrode (BE1), the second bias electrode (BE2), and the gate electrode (GE1) of the first transistor (ST1) may be formed of the same material in the same layer, but are not limited thereto.

[0131] The first bias electrode (BE1) may be the bias electrode of the third-1 transistor (ST3-1). The first bias electrode (BE1) may overlap with the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1). The first bias electrode (BE1) may be electrically connected to the driving voltage line (VDDL) and may receive a driving voltage from the driving voltage line (VDDL). Thus, the first bias electrode (BE1) can stabilize the electric field of the third-1 transistor (ST3-1) and improve output characteristics.

[0132] The second bias electrode (BE2) may be the bias electrode of the third-2 transistor (ST3-2). The second bias electrode (BE2) may overlap with the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2). The second bias electrode (BE2) may be electrically connected to the driving voltage line (VDDL) and may receive a driving voltage from the driving voltage line (VDDL). Thus, the second bias electrode (BE2) can stabilize the electric field of the third-2 transistor (ST3-2) and improve output characteristics.

[0133] The second gate insulating film (GI2) may be disposed on the first bias electrode (BE1), the second bias electrode (BE2), the gate electrode (GE1) of the first transistor (ST1), and the first gate insulating film (GI1). The second gate insulating film (GI2) may insulate the capacitor electrode (CPE) and the gate electrode (GE1) of the first transistor (ST1). The second gate insulating film (GI2) may include a contact hole through which the first and second connecting electrodes (CNE1, CNE2) pass. The second gate insulating film (GI2) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0134] A capacitor electrode (CPE) may be placed on a second gate insulating film (GI2) and overlap with the gate electrode (GE1) of the first transistor (ST1). The capacitor electrode (CPE) and the gate electrode (GE1) of the first transistor (ST1) may form a capacitance. For example, the storage capacitor (CST) of FIG. 5 may be formed between the gate electrode (GE1) of the first transistor (ST1) and the capacitor electrode (CPE). The gate electrode (GE1) of the first transistor (ST1) may be electrically connected to the third node (N3) as the first capacitor electrode of the storage capacitor (CST), and the capacitor electrode (CPE) may be electrically connected to the driving voltage line (VDDL) as the second capacitor electrode of the storage capacitor (CST).

[0135] An interlayer insulating film (ILD) may be disposed on a capacitor electrode (CPE) and a second gate insulating film (GI2). The interlayer insulating film (ILD) may include a contact hole through which the first and second connecting electrodes (CNE1, CNE2) pass. The contact hole of the interlayer insulating film (ILD) may be connected to the contact hole of the second gate insulating film (GI2).

[0136] The first connection electrode (CNE1) may be disposed on the interlayer insulating film (ILD). The first connection electrode (CNE1) may be inserted into a contact hole provided in the interlayer insulating film (ILD) and the second gate insulating film (GI2) to contact the first bias electrode (BE1). The first connection electrode (CNE1) may be electrically connected between the first bias electrode (BE1) and the driving voltage line (VDDL). Thus, the first connection electrode (CNE1) can supply a driving voltage received from the driving voltage line (VDDL) to the first bias electrode (BE1).

[0137] The second connecting electrode (CNE2) may be positioned on the interlayer insulating film (ILD) spaced apart from the first connecting electrode (CNE1). The second connecting electrode (CNE2) may be inserted into a contact hole provided in the interlayer insulating film (ILD) and the second gate insulating film (GI2) to contact the second bias electrode (BE2). The second connecting electrode (CNE2) may be electrically connected between the second bias electrode (BE2) and the driving voltage line (VDDL). Thus, the second connecting electrode (CNE2) can supply the driving voltage received from the driving voltage line (VDDL) to the second bias electrode (BE2).

[0138] The third connecting electrode (CNE3) may be spaced apart from the first and second connecting electrodes (CNE1, CNE2) on the interlayer insulating film (ILD). The third connecting electrode (CNE3) may electrically connect the pixel circuit of the pixel (SP) and the anode connecting electrode (ANE). For example, the third connecting electrode (CNE3) may be electrically connected to the fourth node (N4) of FIG. 5. Thus, the third connecting electrode (CNE3) may supply the driving current received from the pixel circuit of the pixel (SP) to the light-emitting element (ED).

[0139] The first via layer (VIA1) may be disposed on the first to third connecting electrodes (CNE1, CNE2, CNE3) and the interlayer insulating film (ILD). For example, the first via layer (VIA1) may include a contact hole through which the anode connecting electrode (ANE) passes. For example, the first via layer (VIA1) may include an organic insulating material such as polyimide (PI), but is not limited thereto.

[0140] An anode connection electrode (ANE) can be placed on a first via layer (VIA1). The anode connection electrode (ANE) can electrically connect the pixel electrode (PE) of the light-emitting element (ED) and the third connection electrode (CNE3). The anode connection electrode (ANE) can be inserted into a contact hole provided in the first via layer (VIA1) and contact the third connection electrode (CNE3). Accordingly, the anode connection electrode (ANE) can supply a driving current received from the pixel circuit of the pixel (SP) to the light-emitting element (ED).

[0141] The second via layer (VIA2) may be disposed on the anode connection electrode (ANE) and the second via layer (VIA2). For example, the second via layer (VIA2) may include a contact hole through which a pixel electrode (PE) passes. For example, the second via layer (VIA2) may include an organic insulating material such as polyimide (PI), but is not limited thereto.

[0142] A pixel defining film (PDL) may be disposed on a second via layer (VIA2). The pixel defining film (PDL) may define a plurality of light-emitting regions or a plurality of aperture regions. The pixel defining film (PDL) may separate and insulate the pixel electrode (PE) of each of the plurality of pixels (SP).

[0143] A light-emitting element (ED) may be disposed on a second via layer (VIA2). Each light-emitting element (ED) of a plurality of pixels (SP) may include a pixel electrode (PE), a light-emitting layer (EL), and a common electrode (CE). The pixel electrode (PE) may be disposed on the second via layer (VIA2). The pixel electrode (PE) may overlap with one of a plurality of light-emitting regions defined by a pixel defining film (PDL). The pixel electrode (PE) may receive a driving current from the pixel circuit of the pixel (SP) through an anode connecting electrode (ANE) and a third connecting electrode (CNE3).

[0144] The light-emitting layer (EL) may be placed on the pixel electrode (PE). For example, the light-emitting layer (EL) may be an organic light-emitting layer made of an organic material, but is not limited thereto. When the light-emitting layer (EL) corresponds to an organic light-emitting layer, the pixel circuit of the pixel (SP) applies a predetermined voltage to the pixel electrode (PE), and when the common electrode (CE) receives a common voltage or a cathode voltage, holes and electrons can move to the organic light-emitting layer (EL) through the hole transport layer and the electron transport layer, respectively, and the holes and electrons can combine with each other in the organic light-emitting layer (EL) to emit light.

[0145] A common electrode (CE) can be placed on an emitting layer (EL). For example, the common electrode (CE) can be implemented in the form of an electrode common to all pixels (SP) without being separated by multiple pixels (SP). The common electrode (CE) can be placed on the emitting layer (EL) in multiple emitting regions and can be placed on a pixel defining film (PDL) in regions excluding multiple emitting regions.

[0146] The encapsulation layer (TFEL) is disposed on a common electrode (CE) and can cover a plurality of light-emitting elements (ED). The encapsulation layer (TFEL) may include at least one inorganic film to prevent oxygen or moisture from penetrating into the plurality of light-emitting elements (ED). The encapsulation layer (TFEL) may include at least one organic film to protect the plurality of light-emitting elements (ED) from foreign substances such as dust.

[0147] FIG. 8 is a cross-sectional view showing another part of a display device according to one embodiment. Hereinafter, configurations identical to the above-described configuration will be briefly described or omitted.

[0148] Referring to FIG. 8, the display panel (100) may include a substrate (SUB), a barrier layer (BR), a second metal layer (BML2), a first buffer layer (BF1), a second buffer layer (BF2), a hydrogen passivation layer (HPL), a fourth-1 transistor (ST4-1), a fourth-2 transistor (ST4-2), a capping layer (CPL), a first gate insulating layer (GI1), a third bias electrode (BE3), a fourth bias electrode (BE4), a second gate insulating layer (GI2), an interlayer insulating layer (ILD), a fourth connection electrode (CNE4), a fifth connection electrode (CNE5), a third connection electrode (CNE3), a first via layer (VIA1), an anode connection electrode (ANE), a second via layer (VIA2), a pixel defining layer (PDL), a light-emitting element (ED), and an encapsulation layer (TFEL).

[0149] The second metal layer (BML2) may be disposed on the barrier layer (BR). The second metal layer (BML2) may overlap the semiconductor region (ACT4-1) of the 4-1 transistor (ST4-1) and the semiconductor region (ACT4-2) of the 4-2 transistor (ST4-2). A portion of the second metal layer (BML2) may be the gate electrode (GE4-1) of the 4-1 transistor (ST4-1), and another portion of the second metal layer (BML2) may be the gate electrode (GE4-2) of the 4-2 transistor (ST4-2). The second metal layer (BML2) may be electrically connected to the third gate line (GIL) to receive the third gate signal (GI[n]). The second metal layer (BML2) may be formed as a single layer or a multilayer comprising at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0150] A hydrogen passivation layer (HPL) may be disposed on the second buffer layer (BF2). The thickness of the hydrogen passivation layer (HPL) may be about 50 angstroms (Å) or less, but is not limited thereto. The hydrogen passivation layer (HPL) may be in direct contact with the lower surface of the semiconductor region (ACT4-1) of the 4-1 transistor (ST4-1) and the semiconductor region (ACT4-2) of the 4-2 transistor (ST4-2). Since no protrusions are formed on the lower surface of the semiconductor region (ACT4-1) of the 4-1 transistor (ST4-1) and the semiconductor region (ACT4-2) of the 4-2 transistor (ST4-2), the hydrogen passivation layer (HPL) may have a flat surface.

[0151] The hydrogen passivation layer (HPL) may have a high hydrogen content. The hydrogen passivation layer (HPL) may include silicon oxide having a high hydrogen content. For example, the ratio of nitrogen dioxide (N2O) to silane (SiH4) in the hydrogen passivation layer (HPL) (N2O / SiH4) may be 10 to 40, but is not limited thereto. As another example, the hydrogen passivation layer (HPL) may be formed through hydrogen implantation (H-Implantation) or hydrogen plasma treatment (H2 Plasma Treatment).

[0152] Hydrogen in the hydrogen passivation layer (HPL) can reduce dangling coupling in the semiconductor region (ACT4-1) of the 4-1 transistor (ST4-1) and the semiconductor region (ACT4-2) of the 4-2 transistor (ST4-2) by coupling with silicon on the surface of the semiconductor region (ACT4-1) of the 4-1 transistor (ST4-1) and the semiconductor region (ACT4-2) of the 4-2 transistor (ST4-2). Therefore, the hydrogen passivation layer (HPL) can eliminate interface defects in the semiconductor region (ACT4-1) of the 4-1 transistor (ST4-1) and the semiconductor region (ACT4-2) of the 4-2 transistor (ST4-2) and improve leakage current characteristics and low-frequency characteristics. The display device (10) includes a hydrogen passivation layer (HPL) so that leakage current can be prevented from flowing through the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2), and the voltage inside the pixel (SP) can be maintained stably.

[0153] The semiconductor region (ACT4-1), source electrode (SE4-1), and drain electrode (DE4-1) of the 4-1 transistor (ST4-1) may be disposed on a hydrogen passivation layer (HPL). A portion of the second metal layer (BML2) may be the gate electrode (GE4-1) of the 4-1 transistor (ST4-1). The semiconductor region (ACT4-1) of the 4-1 transistor (ST4-1) may overlap with the gate electrode (GE4-1) in the thickness direction and may be insulated from the gate electrode (GE4-1) by a first buffer layer (BF1) and a second buffer layer (BF2). The source electrode (SE4-1) and drain electrode (DE4-1) may be provided by making the material of the semiconductor region (ACT4-1) conductive. The drain electrode (DE4-1) of the 4-1 transistor (ST4-1) may be formed integrally with the source electrode (SE4-2) of the 4-2 transistor (ST4-2). The drain electrode (DE4-1) of the 4-1 transistor (ST4-1) and the source electrode (SE4-2) of the 4-2 transistor (ST4-2) may overlap with the second metal layer (BML2), but are not limited thereto.

[0154] The semiconductor region (ACT4-2), source electrode (SE4-2), and drain electrode (DE4-2) of the 4-2 transistor (ST4-2) may be disposed on a hydrogen passivation layer (HPL). Another part of the second metal layer (BML2) may be the gate electrode (GE4-2) of the 4-2 transistor (ST4-2). The semiconductor region (ACT4-2) of the 4-2 transistor (ST4-2) may overlap with the gate electrode (GE4-2) in the thickness direction and may be insulated from the gate electrode (GE4-2) by a first buffer layer (BF1) and a second buffer layer (BF2). The source electrode (SE4-2) and drain electrode (DE4-2) may be provided by making the material of the semiconductor region (ACT4-2) conductive.

[0155] A capping layer (CPL) may be disposed on the semiconductor region (ACT4-1), source electrode (SE4-1), and drain electrode (DE4-1) of the 4-1 transistor (ST4-1), and the semiconductor region (ACT4-2), source electrode (SE4-2), and drain electrode (DE4-2) of the 4-2 transistor (ST4-2). The capping layer (CPL) may have the same pattern as the semiconductor region (ACT4-1), source electrode (SE4-1), and drain electrode (DE4-1) of the 4-1 transistor (ST4-1), and the semiconductor region (ACT4-2), source electrode (SE4-2), and drain electrode (DE4-2) of the 4-2 transistor (ST4-2) on a planar surface. The capping layer (CPL) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0156] When the first gate insulating film (GI1) is formed through a deposition process, the thickness of the first gate insulating film (GI1) on the hydrogen passivation layer (HPL) and the thickness of the first gate insulating film (GI1) on the capping layer (CPL) may be substantially the same. The first thickness (T1) may be greater than the second thickness (T2). Here, the first thickness (T1) may be the sum of the thicknesses of the capping layer (CPL) and the first gate insulating film (GI1) that overlap each other, and the second thickness (T2) may be the thickness of the first gate insulating film (GI1) that does not overlap with the capping layer (CPL). The thickness of the capping layer (CPL) may be determined by the difference between the first thickness (T1) and the second thickness (T2). The thickness of the capping layer (CPL) may be about 20 to 200 Angstroms (Å), and preferably about 100 Angstroms (Å). Therefore, even if the first gate insulating film (GI1) and the capping layer (CPL) contain the same material, it can be seen that the capping layer (CPL) is placed on the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) to cover the protrusions of the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2).

[0157] The third bias electrode (BE3) and the fourth bias electrode (BE4) may be disposed on the first gate insulating film (GI1). The first to fourth bias electrodes (BE1, BE2, BE3, BE4) and the gate electrode (GE1) of the first transistor (ST1) may be formed of the same material in the same layer, but are not limited thereto.

[0158] The third bias electrode (BE3) may be the bias electrode of the fourth-1 transistor (ST4-1). The third bias electrode (BE3) may overlap with the semiconductor region (ACT4-1) of the fourth-1 transistor (ST4-1). The third bias electrode (BE3) may be electrically connected to the driving voltage line (VDDL) and may receive a driving voltage from the driving voltage line (VDDL). Thus, the third bias electrode (BE3) can stabilize the electric field of the fourth-1 transistor (ST4-1) and improve output characteristics.

[0159] The fourth bias electrode (BE4) may be the bias electrode of the fourth-2 transistor (ST4-2). The fourth bias electrode (BE4) may overlap with the semiconductor region (ACT4-2) of the fourth-2 transistor (ST4-2). The fourth bias electrode (BE4) may be electrically connected to the driving voltage line (VDDL) and may receive a driving voltage from the driving voltage line (VDDL). Thus, the fourth bias electrode (BE4) can stabilize the electric field of the fourth-2 transistor (ST4-2) and improve output characteristics.

[0160] The fourth connecting electrode (CNE4) may be disposed on the interlayer insulating film (ILD). The fourth connecting electrode (CNE4) may be inserted into a contact hole provided in the interlayer insulating film (ILD) and the second gate insulating film (GI2) to contact the third bias electrode (BE3). The fourth connecting electrode (CNE4) may be electrically connected between the third bias electrode (BE3) and the driving voltage line (VDDL). Thus, the fourth connecting electrode (CNE4) can supply the driving voltage received from the driving voltage line (VDDL) to the third bias electrode (BE3).

[0161] The fifth connecting electrode (CNE5) may be positioned on the interlayer insulating film (ILD) spaced apart from the fourth connecting electrode (CNE4). The fifth connecting electrode (CNE5) may be inserted into a contact hole provided in the interlayer insulating film (ILD) and the second gate insulating film (GI2) to contact the fourth bias electrode (BE4). The fifth connecting electrode (CNE5) may be electrically connected between the fourth bias electrode (BE4) and the driving voltage line (VDDL). Thus, the fifth connecting electrode (CNE5) can supply the driving voltage received from the driving voltage line (VDDL) to the fourth bias electrode (BE4).

[0162] FIG. 9 is a graph showing the transfer characteristics of the first and second test transistors in a display device according to one embodiment.

[0163] Referring to FIG. 9, the first test transistor (TR1) may be the third-1 transistor (ST3-1), third-2 transistor (ST3-2), fourth-1 transistor (ST4-1), or fourth-2 transistor (ST4-2) of the display device (10). The second test transistor (TR2) may be a transistor not adjacent to the hydrogen passivation layer.

[0164] The lower surface of the first test transistor (TR1) may come into contact with the hydrogen passivation layer (HPL). Since no protrusions are formed on the lower surface of the first test transistor (TR1), the hydrogen passivation layer (HPL) may have a flat surface. Hydrogen in the hydrogen passivation layer (HPL) can reduce dangling coupling of the first test transistor (TR1) by bonding with silicon on the surface of the semiconductor region of the first test transistor (TR1). Therefore, the hydrogen passivation layer (HPL) can remove interface defects in the semiconductor region of the first test transistor (TR1) and improve leakage current characteristics and low-frequency characteristics. For example, the first and second test transistors (TR1, TR2) may correspond to p-type transistors and can output current flowing into the source electrode to the drain electrode based on the gate low voltage applied to the gate electrode. In the region where the gate-source voltage (Vgs) of a p-type transistor has a positive value, the drain-source current (Ids) may correspond to leakage current.

[0165] In the region where the gate-source voltage (Vgs) has a positive value, the magnitude of the leakage current of the first test transistor (TR1) may be smaller than the magnitude of the leakage current of the second test transistor (TR2). Accordingly, the display device (10) can prevent leakage current from flowing through the third-1 transistor (ST3-1), the third-2 transistor (ST3-2), the fourth-1 transistor (ST4-1), and the fourth-2 transistor (ST4-2) by including a hydrogen passivation layer (HPL), and can maintain the voltage inside the pixel (SP) stably.

[0166] FIG. 10 is a circuit diagram showing a pixel of a display device according to another embodiment.

[0167] Referring to FIG. 10, the display panel (100) may include a plurality of pixels (SP) arranged along p rows (p is a natural number) and q columns (q is a natural number). Each of the plurality of pixels (SP) may be connected to a first gate line (GWL), a second gate line (GCL), a third gate line (GIL), a fourth gate line (GBL), a light emission control line (EML), a data line (DL), a driving voltage line (VDDL), a first initialization voltage line (VIL1), a second initialization voltage line (VIL2), and a bias voltage line (VBL).

[0168] A pixel (SP) may include a pixel circuit and a light-emitting element (ED). The pixel circuit may include a first transistor (ST1), a second transistor (ST2), a third-1 transistor (ST3-1), a third-2 transistor (ST3-2), a fourth-1 transistor (ST4-1), a fourth-2 transistor (ST4-2), a fifth transistor (ST5), a sixth transistor (ST6), a seventh transistor (ST7), an eighth transistor (ST8), and a storage capacitor (CST).

[0169] The first transistor (ST1) may include a gate electrode, a source electrode, and a drain electrode. The first transistor (ST1) can control a source-drain current (Isd, hereinafter referred to as "driving current") according to a data voltage applied to the gate electrode. The driving current (Isd) flowing through the channel of the first transistor (ST1) may be proportional to the square of the difference between the voltage (Vsg) between the source electrode and the gate electrode of the first transistor (ST1) and the threshold voltage (Vth) (Isd = k × (Vsg - Vth) 2 Here, k represents the proportionality constant determined by the structure and physical characteristics of the first transistor (ST1), Vsg represents the source-gate voltage of the first transistor (ST1), and Vth represents the threshold voltage of the first transistor (ST1).

[0170] The first transistor (ST1) may include a bias electrode. The bias electrode of the first transistor (ST1) may overlap with the semiconductor region of the first transistor (ST1). The bias electrode of the first transistor (ST1) may be electrically connected to a driving voltage line (VDDL) and may receive a driving voltage from the driving voltage line (VDDL). Accordingly, the bias electrode of the first transistor (ST1) can stabilize the electric field of the first transistor (ST1) and improve output characteristics.

[0171] A light-emitting element (ED) can emit light by receiving a driving current (Isd). The amount of light emitted or the brightness of the light-emitting element (ED) can be proportional to the magnitude of the driving current (Isd).

[0172] The light-emitting element (ED) may be an organic light-emitting diode comprising a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode. As another example, the light-emitting element (ED) may be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. As yet another example, the light-emitting element (ED) may be a quantum dot light-emitting element comprising a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first electrode and the second electrode. As yet another example, the light-emitting element (ED) may be a micro light-emitting diode.

[0173] The first electrode of the light-emitting element (ED) can be electrically connected to the fourth node (N4). The first electrode of the light-emitting element (ED) can be connected to the drain electrode of the sixth transistor (ST6) and the source electrode of the seventh transistor (ST7) through the fourth node (N4). The second electrode of the light-emitting element (ED) can be connected to the low potential line (VSSL). The second electrode of the light-emitting element (ED) can receive a low potential voltage from the low potential line (VSSL).

[0174] The second transistor (ST2) can be turned on by the first gate signal (GW[n]) of the first gate line (GWL) to electrically connect the data line (DL) and the first node (N1), which is the source electrode of the first transistor (ST1). By turning on the second transistor (ST2) based on the first gate signal (GW[n]), it can supply a data voltage to the first node (N1). The gate electrode of the second transistor (ST2) can be electrically connected to the first gate line (GWL), the source electrode can be electrically connected to the data line (DL), and the drain electrode can be electrically connected to the first node (N1).

[0175] The third-1 transistor (ST3-1) and the third-2 transistor (ST3-2) can be turned on by the second gate signal (GC[n]) of the second gate line (GCL) to electrically connect the second node (N2), which is the drain electrode of the first transistor (ST1), and the third node (N3), which is the gate electrode of the first transistor (ST1). The gate electrode of the third-1 transistor (ST3-1) can be electrically connected to the second gate line (GCL), the source electrode can be electrically connected to the third node (N3), and the drain electrode can be electrically connected to the source electrode of the third-2 transistor (ST3-2). The gate electrode of the third-2 transistor (ST3-2) can be electrically connected to the second gate line (GCL), the source electrode can be electrically connected to the drain electrode of the third-1 transistor (ST3-1), and the drain electrode can be electrically connected to the second node (N2). The gate electrode of the 3-1 transistor (ST3-1) and the gate electrode of the 3-2 transistor (ST3-2) can be formed as a single unit.

[0176] The third-1 transistor (ST3-1) may include a bias electrode. The bias electrode of the third-1 transistor (ST3-1) may overlap with the semiconductor region of the third-1 transistor (ST3-1). The bias electrode of the third-1 transistor (ST3-1) may be electrically connected to a driving voltage line (VDDL) and may receive a driving voltage from the driving voltage line (VDDL). The bias electrode of the third-1 transistor (ST3-1) may provide high potential characteristics to improve the output characteristics of the third-1 transistor (ST3-1). Thus, the bias electrode of the third-1 transistor (ST3-1) may stabilize the electric field of the third-1 transistor (ST3-1) and improve the output characteristics.

[0177] The third-2 transistor (ST3-2) may include a bias electrode. The bias electrode of the third-2 transistor (ST3-2) may overlap with the semiconductor region of the third-2 transistor (ST3-2). The bias electrode of the third-2 transistor (ST3-2) may be electrically connected to the gate electrode of the third-2 transistor (ST3-2) and may receive a second gate signal (GC[n]) from the second gate line (GCL). The bias electrode of the third-2 transistor (ST3-2) may increase the electric field due to the second gate signal (GC[n]) to improve the output characteristics of the third-2 transistor (ST3-2). Therefore, the bias electrode of the third-2 transistor (ST3-2) may stabilize the electric field of the third-2 transistor (ST3-2) and improve the output characteristics.

[0178] The 3-1 transistor (ST3-1) and the 3-2 transistor (ST3-2) may have excellent off-current characteristics. Therefore, the 3-1 transistor (ST3-1) and the 3-2 transistor (ST3-2) can prevent leakage current from flowing at the third node (N3), which is the gate electrode of the 1 transistor (ST1), and can stably maintain the voltage inside the pixel (SP). The leakage current characteristics of the 3-1 transistor (ST3-1) and the 3-2 transistor (ST3-2) are explained in detail in FIG. 11.

[0179] The 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) can be turned on by the third gate signal (GI[n]) of the third gate line (GIL) to electrically connect the third node (N3), which is the gate electrode of the 1 transistor (ST1), to the first initialization voltage line (VIL1). The gate electrode of the 4-1 transistor (ST4-1) can be electrically connected to the third gate line (GIL), the source electrode can be electrically connected to the third node (N3), and the drain electrode can be electrically connected to the source electrode of the 4-2 transistor (ST4-2). The gate electrode of the 4-2 transistor (ST4-2) can be electrically connected to the third gate line (GIL), the source electrode can be electrically connected to the drain electrode of the 4-1 transistor (ST4-1), and the drain electrode can be electrically connected to the first initialization voltage line (VIL1). The gate electrode of the 4-1 transistor (ST4-1) and the gate electrode of the 4-2 transistor (ST4-2) can be formed as a single unit.

[0180] Each of the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) may include a bias electrode. The bias electrode of the 4-1 transistor (ST4-1) may overlap with the semiconductor region of the 4-1 transistor (ST4-1), and the bias electrode of the 4-2 transistor (ST4-2) may overlap with the semiconductor region of the 4-2 transistor (ST4-2). The bias electrodes of the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) may be electrically connected to a driving voltage line (VDDL) and may receive a driving voltage from the driving voltage line (VDDL). Accordingly, the bias electrodes of the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) may stabilize the electric field of the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) and improve output characteristics.

[0181] The 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) may have excellent off-current characteristics. Therefore, the 4-1 transistor (ST4-1) and the 4-2 transistor (ST4-2) can prevent leakage current from flowing at the third node (N3), which is the gate electrode of the 1 transistor (ST1), and can stably maintain the voltage inside the pixel (SP).

[0182] The fifth transistor (ST5) can be turned on by the light emission signal (EM[n]) of the light emission control line (EML) to electrically connect the driving voltage line (VDDL) and the first node (N1), which is the source electrode of the first transistor (ST1). The gate electrode of the fifth transistor (ST5) can be electrically connected to the light emission control line (EML), the source electrode can be electrically connected to the driving voltage line (VDDL), and the drain electrode can be electrically connected to the first node (N1).

[0183] The sixth transistor (ST6) can be turned on by the light emission signal (EM[n]) of the light emission control line (EML) to electrically connect the second node (N2), which is the drain electrode of the first transistor (ST1), and the fourth node (N4), which is the first electrode of the light emission element (ED). The gate electrode of the sixth transistor (ST6) can be electrically connected to the light emission control line (EML), the source electrode can be electrically connected to the second node (N2), and the drain electrode can be electrically connected to the fourth node (N4).

[0184] When the fifth transistor (ST5), the first transistor (ST1), and the sixth transistor (ST6) are all turned on, the driving current can be supplied to the light-emitting element (ED).

[0185] The seventh transistor (ST7) can be turned on by the fourth gate signal (GB[n]) of the fourth gate line (GBL) to electrically connect the fourth node (N4), which is the first electrode of the light-emitting element (ED), and the second initialization voltage line (VIL2). By turning on the seventh transistor (ST7) based on the fourth gate signal (GB[n]), the first electrode of the light-emitting element (ED) can be discharged to the second initialization voltage. The gate electrode of the seventh transistor (ST7) can be electrically connected to the fourth gate line (GBL), the source electrode can be electrically connected to the fourth node (N4), and the drain electrode can be electrically connected to the second initialization voltage line (VIL2).

[0186] The eighth transistor (ST8) can be turned on by the fourth gate signal (GB[n]) of the fourth gate line (GBL) to electrically connect the bias voltage line (VBL) and the first node (N1), which is the source electrode of the first transistor (ST1). By turning on the eighth transistor (ST8) based on the fourth gate signal (GB[n]), it can supply a bias voltage to the first node (N1). By supplying a bias voltage to the source electrode of the first transistor (ST1), the eighth transistor (ST8) can improve the hysteresis of the first transistor (ST1). The gate electrode of the eighth transistor (ST8) can be electrically connected to the fourth gate line (GBL), the source electrode can be electrically connected to the bias voltage line (VBL), and the drain electrode can be electrically connected to the first node (N1).

[0187] Each of the first transistor (ST1), second transistor (ST2), third-1 transistor (ST3-1), third-2 transistor (ST3-2), fourth-1 transistor (ST4-1), fourth-2 transistor (ST4-2), fifth transistor (ST5), sixth transistor (ST6), seventh transistor (ST7), and eighth transistor (ST8) may include a silicon-based active layer. For example, each of the first transistor (ST1), second transistor (ST2), third-1 transistor (ST3-1), third-2 transistor (ST3-2), fourth-1 transistor (ST4-1), fourth-2 transistor (ST4-2), fifth transistor (ST5), sixth transistor (ST6), seventh transistor (ST7), and eighth transistor (ST8) may include an active layer made of low-temperature polycrystalline silicon (LTPS). An active layer made of low-temperature polycrystalline silicon may have high electron mobility and excellent turn-on characteristics. Accordingly, the display device (10) can stably and efficiently drive a plurality of pixels (SP) by including transistors with excellent turn-on characteristics.

[0188] Each of the first transistor (ST1), second transistor (ST2), third-1 transistor (ST3-1), third-2 transistor (ST3-2), fourth-1 transistor (ST4-1), fourth-2 transistor (ST4-2), fifth transistor (ST5), sixth transistor (ST6), seventh transistor (ST7), and eighth transistor (ST8) may correspond to a p-type transistor. For example, each of the first transistor (ST1), second transistor (ST2), third-1 transistor (ST3-1), third-2 transistor (ST3-2), fourth-1 transistor (ST4-1), fourth-2 transistor (ST4-2), fifth transistor (ST5), sixth transistor (ST6), seventh transistor (ST7), and eighth transistor (ST8) can output current flowing into the source electrode to the drain electrode based on the gate low voltage applied to the gate electrode.

[0189] As another example, at least one of the first transistor (ST1), second transistor (ST2), third-1 transistor (ST3-1), third-2 transistor (ST3-2), fourth-1 transistor (ST4-1), fourth-2 transistor (ST4-2), fifth transistor (ST5), sixth transistor (ST6), seventh transistor (ST7), and eighth transistor (ST8) may include an oxide-based active layer. A transistor including an oxide-based active layer may have a coplanar structure with a gate electrode disposed on top. A transistor including an oxide-based active layer may correspond to an n-type transistor and may output current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0190] The storage capacitor (CST) can be electrically connected between the third node (N3), which is the gate electrode of the first transistor (ST1), and the driving voltage line (VDDL). For example, the first capacitor electrode of the storage capacitor (CST) is electrically connected to the third node (N3), and the second capacitor electrode of the storage capacitor (CST) is electrically connected to the driving voltage line (VDDL), thereby maintaining a potential difference between the driving voltage line (VDDL) and the gate electrode of the first transistor (ST1).

[0191] FIG. 11 is a cross-sectional view showing a part of a display device according to another embodiment. Hereinafter, configurations identical to the above-described configuration will be briefly described or omitted.

[0192] Referring to FIG. 11, a display panel (100) may include a substrate (SUB), a barrier layer (BR), a first metal layer (BML1), a third metal layer (BML3), a first buffer layer (BF1), a second buffer layer (BF2), a hydrogen passivation layer (HPL), a first transistor (ST1), a third-first transistor (ST3-1), a third-second transistor (ST3-2), a capping layer (CPL), a first gate insulating film (GI1), a first bias electrode (BE1), a second bias electrode (BE2), a second gate insulating film (GI2), a capacitor electrode (CPE), an interlayer insulating film (ILD), a first connection electrode (CNE1), a third connection electrode (CNE3), a sixth connection electrode (CNE6), a first via layer (VIA1), an anode connection electrode (ANE), a second via layer (VIA2), a pixel defining film (PDL), a light-emitting element (ED), and an encapsulation layer (TFEL).

[0193] The first metal layer (BML1) may be disposed on the barrier layer (BR). The first metal layer (BML1) may overlap with the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1) and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2). A portion of the first metal layer (BML1) may be the gate electrode (GE3-1) of the third-1 transistor (ST3-1), and another portion of the first metal layer (BML1) may be the gate electrode (GE3-2) of the third-2 transistor (ST3-2). The first metal layer (BML1) may be electrically connected to the second gate line (GCL) to receive the second gate signal (GC[n]).

[0194] The third metal layer (BML3) may be spaced apart from the first metal layer (BML1) on the barrier layer (BR). The third metal layer (BML3) may overlap with the semiconductor region (ACT1) of the first transistor (ST1). The third metal layer (BML3) may be the bias electrode of the first transistor (ST1). The third metal layer (BML3) may be electrically connected to the driving voltage line (VDDL) through the sixth connection electrode (CNE6) and may receive a driving voltage from the driving voltage line (VDDL). Thus, the third metal layer (BML3) can stabilize the electric field of the first transistor (ST1) and improve output characteristics.

[0195] A hydrogen passivation layer (HPL) may be disposed on a second buffer layer (BF2). The thickness of the hydrogen passivation layer (HPL) may be about 50 angstroms (Å) or less, but is not limited thereto. The hydrogen passivation layer (HPL) may be in direct contact with the lower surface of the semiconductor region (ACT1) of the first transistor (ST1), the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1), and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2). Since no protrusions are formed on the lower surface of the semiconductor region (ACT1) of the first transistor (ST1), the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1), and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2), the hydrogen passivation layer (HPL) may have a flat surface.

[0196] The hydrogen passivation layer (HPL) may have a high hydrogen content. The hydrogen passivation layer (HPL) may include silicon oxide having a high hydrogen content. For example, the ratio of nitrogen dioxide (N2O) to silane (SiH4) in the hydrogen passivation layer (HPL) (N2O / SiH4) may be 10 to 40, but is not limited thereto. As another example, the hydrogen passivation layer (HPL) may be formed through hydrogen implantation (H-Implantation) or hydrogen plasma treatment (H2 Plasma Treatment).

[0197] Hydrogen in the hydrogen passivation layer (HPL) can reduce dangling coupling in the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1) and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2) by coupling with silicon on the surface of the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1) and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2). Therefore, the hydrogen passivation layer (HPL) can eliminate interface defects in the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1) and the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2) and improve leakage current characteristics and low-frequency characteristics. The display device (10) includes a hydrogen passivation layer (HPL) so that leakage current can be prevented from flowing through the third-1 transistor (ST3-1) and the third-2 transistor (ST3-2), and the voltage inside the pixel (SP) can be maintained stably.

[0198] The semiconductor region (ACT1), source electrode (SE1), and drain electrode (DE1) of the first transistor (ST1) may be placed on a hydrogen passivation layer (HPL). The semiconductor region (ACT1) of the first transistor (ST1) may overlap with the gate electrode (GE1) in the thickness direction and may be insulated from the gate electrode (GE1) by a capping layer (CPL) and a first gate insulating film (GI1). The source electrode (SE1) and the drain electrode (DE1) may be provided by making the material of the semiconductor region (ACT1) conductive. The drain electrode (DE1) of the first transistor (ST1) may be electrically connected to the drain electrode (DE3-2) of the third-second transistor (ST3-2) through the second node (N2) of FIG. 10.

[0199] The semiconductor region (ACT3-1), source electrode (SE3-1), and drain electrode (DE3-1) of the third-1 transistor (ST3-1) may be disposed on a hydrogen passivation layer (HPL). A portion of the first metal layer (BML1) may be the gate electrode (GE3-1) of the third-1 transistor (ST3-1). The semiconductor region (ACT3-1) of the third-1 transistor (ST3-1) may overlap with the gate electrode (GE3-1) in the thickness direction and may be insulated from the gate electrode (GE3-1) by a first buffer layer (BF1) and a second buffer layer (BF2). The source electrode (SE3-1) and the drain electrode (DE3-1) may be provided by making the material of the semiconductor region (ACT3-1) conductive. The drain electrode (DE3-1) of the third-1 transistor (ST3-1) may be formed integrally with the source electrode (SE3-2) of the third-2 transistor (ST3-2). The drain electrode (DE3-1) of the third-1 transistor (ST3-1) and the source electrode (SE3-2) of the third-2 transistor (ST3-2) may overlap with the first metal layer (BML1), but are not limited thereto.

[0200] The semiconductor region (ACT3-2), source electrode (SE3-2), and drain electrode (DE3-2) of the third-2 transistor (ST3-2) may be disposed on a hydrogen passivation layer (HPL). Another part of the first metal layer (BML1) may be the gate electrode (GE3-2) of the third-2 transistor (ST3-2). The semiconductor region (ACT3-2) of the third-2 transistor (ST3-2) may overlap with the gate electrode (GE3-2) in the thickness direction and may be insulated from the gate electrode (GE3-2) by a first buffer layer (BF1) and a second buffer layer (BF2). The source electrode (SE3-2) and drain electrode (DE3-2) may be provided by making the material of the semiconductor region (ACT3-2) conductive.

[0201] A capping layer (CPL) may be disposed on the semiconductor region (ACT1), source electrode (SE1), and drain electrode (DE1) of the first transistor (ST1), the semiconductor region (ACT3-1), source electrode (SE3-1), and drain electrode (DE3-1) of the third-first transistor (ST3-1), and the semiconductor region (ACT3-2), source electrode (SE3-2), and drain electrode (DE3-2) of the third-second transistor (ST3-2). The capping layer (CPL) may have the same pattern on a plane as the semiconductor region (ACT1), source electrode (SE1), and drain electrode (DE1) of the first transistor (ST1), the semiconductor region (ACT3-1), source electrode (SE3-1), and drain electrode (DE3-1) of the third-first transistor (ST3-1), and the semiconductor region (ACT3-2), source electrode (SE3-2), and drain electrode (DE3-2) of the third-second transistor (ST3-2). The capping layer (CPL) can cover protrusions formed on the semiconductor region (ACT1), source electrode (SE1), and drain electrode (DE1) of the first transistor (ST1). If the semiconductor region (ACT1) of the first transistor (ST1) includes low-temperature polycrystalline silicon (LTPS), the amorphous silicon layer provided on the substrate (SUB) can be melted and crystallized by a laser. In this case, as the amorphous silicon layer crystallizes, grains can grow, and protrusions can be formed at the grain boundaries between the grains. By covering the protrusions of the first transistor (ST1), the capping layer (CPL) can prevent the electric field from concentrating on the protrusions during the operation of the first transistor (ST1) and can improve the driving range of the first transistor (ST1). Accordingly, the display device (10) can precisely control the gradation of light emitted from the light-emitting element (ED) by including the capping layer (CPL).The capping layer (CPL) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0202] When the first gate insulating film (GI1) is formed through a deposition process, the thickness of the first gate insulating film (GI1) on the hydrogen passivation layer (HPL) and the thickness of the first gate insulating film (GI1) on the capping layer (CPL) may be substantially the same. The first thickness (T1) may be greater than the second thickness (T2). Here, the first thickness (T1) may be the sum of the thicknesses of the capping layer (CPL) and the first gate insulating film (GI1) that overlap each other, and the second thickness (T2) may be the thickness of the first gate insulating film (GI1) that does not overlap with the capping layer (CPL). The thickness of the capping layer (CPL) may be determined by the difference between the first thickness (T1) and the second thickness (T2). The thickness of the capping layer (CPL) may be about 20 to 200 Angstroms (Å), and preferably about 100 Angstroms (Å). Therefore, even if the first gate insulating film (GI1) and the capping layer (CPL) contain the same material, it can be seen that the capping layer (CPL) is placed on the first transistor (ST1), the third-1 transistor (ST3-1), and the third-2 transistor (ST3-2) to cover the protrusions of the first transistor (ST1), the third-1 transistor (ST3-1), and the third-2 transistor (ST3-2).

[0203] The first bias electrode (BE1), the second bias electrode (BE2), and the gate electrode (GE1) of the first transistor (ST1) may be disposed on the first gate insulating film (GI1). The first bias electrode (BE1), the second bias electrode (BE2), and the gate electrode (GE1) of the first transistor (ST1) may be formed of the same material in the same layer, but are not limited thereto.

[0204] The first bias electrode (BE1) may be the bias electrode of the third-1 transistor (ST3-1). The first bias electrode (BE1) may overlap with the semiconductor region (ACT3-1) of the third-1 transistor (ST3-1). The first bias electrode (BE1) may be electrically connected to the driving voltage line (VDDL) and may receive a driving voltage from the driving voltage line (VDDL). Thus, the first bias electrode (BE1) can stabilize the electric field of the third-1 transistor (ST3-1) and improve output characteristics.

[0205] The second bias electrode (BE2) may be the bias electrode of the third-2 transistor (ST3-2). The second bias electrode (BE2) may overlap with the semiconductor region (ACT3-2) of the third-2 transistor (ST3-2). The second bias electrode (BE2) may be inserted into the first gate insulating film (GI1), the hydrogen passivation layer (HPL), the second buffer layer (BF2), and the contact hole provided in the first buffer layer (BF1) and electrically connected to the first metal layer (BML1). The second bias electrode (BE2) may receive a second gate signal (GC[n]) from the second gate line (GCL). Thus, the second bias electrode (BE2) can increase the electric field due to the second gate signal (GC[n]) to improve the output characteristics of the third-2 transistor (ST3-2).

[0206] The first connection electrode (CNE1) may be disposed on the interlayer insulating film (ILD). The first connection electrode (CNE1) may be inserted into a contact hole provided in the interlayer insulating film (ILD) and the second gate insulating film (GI2) to contact the first bias electrode (BE1). The first connection electrode (CNE1) may be electrically connected between the first bias electrode (BE1) and the driving voltage line (VDDL). Thus, the first connection electrode (CNE1) can supply a driving voltage received from the driving voltage line (VDDL) to the first bias electrode (BE1).

[0207] The third connecting electrode (CNE3) may be spaced apart from the first connecting electrode (CNE1) on the interlayer insulating film (ILD). The third connecting electrode (CNE3) may electrically connect the pixel circuit of the pixel (SP) and the anode connecting electrode (ANE). For example, the third connecting electrode (CNE3) may be electrically connected to the fourth node (N4) of FIG. 10. Thus, the third connecting electrode (CNE3) may supply the driving current received from the pixel circuit of the pixel (SP) to the light-emitting element (ED).

[0208] The sixth connecting electrode (CNE6) may be spaced apart from the first and third connecting electrodes (CNE1, CNE3) on the interlayer insulating film (ILD). The sixth connecting electrode (CNE6) may be inserted into a contact hole provided in the interlayer insulating film (ILD), the second gate insulating film (GI2), the first gate insulating film (GI1), the hydrogen passivation layer (HPL), the second buffer layer (BF2), and the first buffer layer (BF1) to contact the third metal layer (BML3). The sixth connecting electrode (CNE6) may be electrically connected between the third metal layer (BML3) and the driving voltage line (VDDL). Thus, the sixth connecting electrode (CNE6) can supply the driving voltage received from the driving voltage line (VDDL) to the third metal layer (BML3).

[0209] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0210] 10: Display device SP: Pixel GWL, GCL, GIL, GBL: 1st to 4th gate lines VDDL: Driving voltage line VBL: Bias voltage line VIL1, VIL2: 1st and 2nd initialization voltage lines ST1, 1st transistor ST2: 2nd transistor ST3-1: Transistor 3-1 ST3-2: Transistor 3-2 ST4-1: Transistor 4-1 ST4-2: Transistor 4-2 ST5: 5th transistor ST6: 6th transistor ST7: 7th transistor ST8: 8th transistor BML1, BML2, BML3: First to third metal layers HPL: Hydrogen Passivation Layer CPL: Capping Layer BE1, BE2, BE3, BE4: 1st to 4th bias electrodes

Claims

Claim 1 A display device comprising: a light-emitting element disposed on a substrate; a first transistor controlling a driving current flowing through the light-emitting element; a second transistor supplying a data voltage to the source electrode of the first transistor; a third-1 transistor and a third-2 transistor connected in series between the gate electrode of the first transistor and the drain electrode of the first transistor; a first metal layer disposed on the substrate and including the gate electrode of the third-1 transistor and the gate electrode of the third-2 transistor; a hydrogen passivation layer disposed on the first metal layer; semiconductor regions of the first transistor, the third-1 transistor, and the third-2 transistor, respectively, disposed on the hydrogen passivation layer; a capping layer disposed on the semiconductor region of the first transistor; a gate electrode of the first transistor disposed on the capping layer; a first bias electrode disposed on the same layer as the gate electrode of the first transistor and overlapping with the semiconductor region of the third-1 transistor; and a second bias electrode disposed on the same layer as the first bias electrode and overlapping with the semiconductor region of the third-2 transistor. Claim 2 In claim 1, the hydrogen passivation layer is a display device that is in direct contact with the lower surface of the semiconductor region of each of the first transistor, the third-1 transistor, and the third-2 transistor. Claim 3 In claim 1, the first and second bias electrodes are electrically connected to a driving voltage line to receive a driving voltage. Claim 4 A display device according to claim 1, further comprising: a 4-1 transistor and a 4-2 transistor connected in series between the gate electrode of the 1 transistor and a 1 initialization voltage line; and a 2 metal layer disposed on the same layer as the 1 metal layer and including the gate electrode of the 4-1 transistor and the gate electrode of the 4-2 transistor. Claim 5 A display device according to claim 4, wherein the gate electrode of the second transistor receives a first gate signal from a first gate line, and the first metal layer receives a second gate signal different from the first gate signal from a second gate line. Claim 6 In claim 5, the second metal layer is a display device that receives a third gate signal different from the first and second gate signals from a third gate line. Claim 7 A display device according to claim 4, further comprising: a third bias electrode disposed on the same layer as the second bias electrode and overlapping with the semiconductor region of the 4-1 transistor; and a fourth bias electrode disposed on the same layer as the third bias electrode and overlapping with the semiconductor region of the 4-2 transistor. Claim 8 In claim 7, the third and fourth bias electrodes are electrically connected to a driving voltage line to receive a driving voltage. Claim 9 A display device according to claim 4, further comprising: a fifth transistor disposed between the source electrode of the first transistor and a driving voltage line; a sixth transistor disposed between the drain electrode of the first transistor and the light-emitting element; and a seventh transistor disposed between the first electrode of the light-emitting element and a second initialization voltage line. Claim 10 A display device according to claim 9, further comprising an eighth transistor disposed between the source electrode and the bias voltage line of the first transistor. Claim 11 In claim 1, the first transistor comprises a protrusion formed on a semiconductor region, a source electrode, and a drain electrode of the first transistor, and the capping layer covers the protrusion of the first transistor. Claim 12 A display device according to claim 11, further comprising a gate insulating film disposed between the capping layer and the gate electrode of the first transistor, wherein the capping layer comprises a silicon oxide layer or an amorphous silicon layer, and the gate insulating film comprises at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer. Claim 13 A light-emitting element disposed on a substrate; a first transistor controlling a driving current flowing through the light-emitting element; a second transistor supplying a data voltage to the source electrode of the first transistor; a third-1 transistor and a third-2 transistor connected in series between the gate electrode of the first transistor and the drain electrode of the first transistor; a first metal layer disposed on the substrate and including the gate electrode of the third-1 transistor and the gate electrode of the third-2 transistor; a hydrogen passivation layer disposed on the first metal layer; semiconductor regions of the first transistor, the third-1 transistor, and the third-2 transistor, respectively, disposed on the hydrogen passivation layer; a capping layer disposed on the semiconductor region of the first transistor; the gate electrode of the first transistor disposed on the capping layer; and a first bias electrode disposed on the same layer as the gate electrode of the first transistor and overlapping with the semiconductor region of the third-1 transistor. A display device comprising a second bias electrode disposed on the same layer as the first bias electrode, overlapping with the semiconductor region of the third-second transistor, and electrically connected to the first metal layer. Claim 14 In claim 13, the first bias electrode is electrically connected to a driving voltage line and is a display device that receives a driving voltage. Claim 15 A display device according to claim 13, wherein the gate electrode of the second transistor receives a first gate signal from a first gate line, and the first metal layer and the second bias electrode receive a second gate signal different from the first gate signal from a second gate line. Claim 16 A display device according to claim 13, further comprising a second metal layer disposed in the same layer as the first metal layer and overlapping with the semiconductor region of the first transistor. Claim 17 In claim 16, the second metal layer is electrically connected to a driving voltage line and is a display device that receives a driving voltage. Claim 18 A light-emitting element disposed on a substrate; a first transistor for controlling a driving current flowing through the light-emitting element; a second transistor for supplying a data voltage to the source electrode of the first transistor; a third-1 transistor and a third-2 transistor connected in series between the gate electrode of the first transistor and the drain electrode of the first transistor; a first metal layer disposed on the substrate and including the gate electrode of the third-1 transistor and the gate electrode of the third-2 transistor; a semiconductor region of each of the first transistor, the third-1 transistor, and the third-2 transistor disposed on the first metal layer; a gate electrode of the first transistor disposed on the semiconductor region of the first transistor; and a first bias electrode disposed on the same layer as the gate electrode of the first transistor, overlapping with the semiconductor region of the third-1 transistor, and electrically connected to a driving voltage line, wherein the gate electrode of the first transistor is electrically connected to the source electrode of the third-1 transistor disposed on the same layer as the semiconductor region of the third-1 transistor. Claim 19 A display device according to claim 18, further comprising: a 4-1 transistor and a 4-2 transistor connected in series between the gate electrode of the 1 transistor and a first initialization voltage line; and a second metal layer disposed on the same layer as the 1 metal layer and including the gate electrode of the 4-1 transistor and the gate electrode of the 4-2 transistor, wherein the gate electrode of the 1 transistor is electrically connected to the source electrode of the 4-1 transistor disposed on the same layer as the semiconductor region of the 4-1 transistor. Claim 20 A display device according to claim 18, further comprising a third metal layer disposed in the same layer as the first metal layer, overlapping with the semiconductor region of the first transistor, and electrically connected to a driving voltage line.

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