Display device

Abstract

A display device is provided. A display device according to one embodiment comprises a substrate, a plurality of fan-out wirings disposed on the substrate, a plurality of signal wirings disposed on the substrate and spaced apart from the fan-out wirings, and a plurality of connecting wirings connecting each fan-out wiring and each signal wiring, wherein the plurality of fan-out wirings includes a plurality of first fan-out wirings belonging to a first fan-out group and a plurality of second fan-out wirings belonging to a second fan-out group, and the first fan-out group and the second fan-out group are adjacent to each other, and the distance between the outermost first fan-out wiring located closest to the second fan-out group in the first fan-out group and the outermost second fan-out wiring located closest to the first fan-out group in the second fan-out group is greater than the distance between the signal wirings to which the outermost first fan-out wiring and the outermost second fan-out wiring are respectively connected.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] The importance of display devices is increasing alongside the development of multimedia. In response to this, various types of display devices, such as Organic Light Emitting Displays (OLEDs) and Liquid Crystal Displays (LCDs), are being utilized. The applications of these display devices are becoming increasingly diverse, centering on a wide range of mobile electronic devices, such as portable electronic devices like smartphones, smartwatches, and tablet PCs.

[0003] Electrostatic discharge (ESD) can occur during the manufacturing process of display devices. Charges generated by static electricity can damage TFT transistors and insulation layers, leading to the degradation of the display panels included in the display devices and affecting production yield. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device capable of minimizing electrostatic discharge phenomena occurring during the manufacturing process of a display device by securing a sufficient separation distance between adjacent fan-out wiring groups.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem comprises: a substrate; a plurality of fan-out wirings disposed on the substrate; a plurality of signal wirings disposed on the substrate and spaced apart from the fan-out wirings; and a plurality of connecting wirings connecting each of the fan-out wirings and each of the signal wirings, wherein the plurality of fan-out wirings includes a plurality of first fan-out wirings belonging to a first fan-out group and a plurality of second fan-out wirings belonging to a second fan-out group, and the first fan-out group and the second fan-out group are adjacent to each other, and the distance between the outermost first fan-out wiring located closest to the second fan-out group in the first fan-out group and the outermost second fan-out wiring located closest to the first fan-out group in the second fan-out group is greater than the distance between the signal wirings to which the outermost first fan-out wiring and the outermost second fan-out wiring are respectively connected.

[0007] The distance between the outermost first fan-out wiring and the outermost second fan-out wiring may be greater than the distance between the first fan-out wirings that are adjacent to each other in the first fan-out group.

[0008] The distance between the outermost first fan-out wiring and the outermost second fan-out wiring may be greater than or equal to the distance between the connecting wires to which the outermost first fan-out wiring and the outermost first fan-out wiring are respectively connected.

[0009] The distance between the first fan-out wires that are adjacent to each other and positioned at the outermost edge of the first fan-out group may be less than or equal to the distance between the first fan-out wires that are adjacent to each other in the first fan-out group.

[0010] The plurality of connecting wires may include a plurality of first connecting wires that electrically connect the plurality of first fan-out wires and the signal wires, and a plurality of second connecting wires that electrically connect the second fan-out wires and the signal wires.

[0011] The first connecting wire may include a first sub-connecting wire electrically connected to the first fan-out wiring, a second sub-connecting wire electrically connected to the signal wiring, and a third sub-connecting wire electrically connecting the first sub-connecting wire and the second sub-connecting wire.

[0012] The third sub-connecting wire extends in a first direction, and the first sub-connecting wire and the second sub-connecting wire may extend in a second direction different from the first direction.

[0013] The distance between the outermost first fan-out wiring and the outermost second fan-out wiring may be greater than the distance between the first connecting wiring and the second connecting wiring to which the outermost first fan-out wiring and the outermost second fan-out wiring are respectively connected.

[0014] At least two ends of the first fan-out wires adjacent to each other in the first fan-out group can be aligned along the extension direction of the signal wire.

[0015] A display device according to another embodiment for solving the above problem comprises: a substrate; a first conductive layer disposed on the substrate and comprising a first fan-out group including a plurality of first fan-out wires, a second fan-out group including a plurality of second fan-out wires disposed on one side of a first direction of the first fan-out group, a first signal group including a plurality of first signal wires disposed spaced apart from the first fan-out group in a second direction intersecting the first direction, and a second signal group including a plurality of second signal wires spaced apart from the second fan-out group in the second direction; and a second conductive layer disposed on the first conductive layer and comprising a plurality of first connecting wires electrically connecting the plurality of first fan-out wires and the plurality of first signal wires, and a plurality of second connecting wires electrically connecting the plurality of second fan-out wires and the plurality of second signal wires, wherein the distance between the first fan-out group and the second fan-out group is greater than the distance between the first connecting wires and the second connecting wires.

[0016] The distance between the first fan-out group and the second fan-out group may be greater than the distance between the first signal group and the second signal group.

[0017] The distance between the first fan-out group and the second fan-out group may be greater than the distance between the first fan-out wires adjacent to each other in the first fan-out group.

[0018] The distance between the first fan-out group and the second fan-out group may be greater than or equal to the distance between the first signal group and the first fan-out group.

[0019] The distance between two adjacent first fan-out wires placed at the outermost edge of the first fan-out group may be less than or equal to the distance between adjacent first fan-out wires in the first fan-out group.

[0020] The first connecting wire may further include a first sub-connecting wire electrically connected to the first fan-out wiring and a second sub-connecting wire electrically connected to the first signal wiring, and may further include a third conductive layer disposed between the first conductive layer and the second conductive layer and including a third connecting wire that mutually electrically connects the first sub-connecting wire and the second sub-connecting wire.

[0021] The first sub-connecting wire and the second sub-connecting wire extend in the second direction, and the third connecting wire may extend in the first direction.

[0022] At least two ends of the first fan-out wiring in the first fan-out group can be aligned along the second direction.

[0023] A display device according to another embodiment for solving the above problem comprises: a substrate; a plurality of fan-out wirings disposed on the substrate; and a plurality of signal wirings disposed on the substrate and spaced apart from the fan-out wirings.and a plurality of connecting wires connecting each of the above fan-out wires and each of the above signal wires, wherein the plurality of fan-out wires include a plurality of first fan-out wires belonging to a first fan-out group and a plurality of second fan-out wires belonging to a second fan-out group adjacent to the first fan-out group, the plurality of first fan-out wires include an outermost first fan-out wire located closest to the second fan-out group in the first fan-out group, and the plurality of second fan-out wires include an outermost second fan-out wire located closest to the first fan-out group in the second fan-out group, and the plurality of signal wires include an outermost first signal wire connected to the outermost first fan-out wire and an outermost second signal wire connected to the outermost second fan-out wire, and the plurality of connecting wires include an outermost first connecting wire connecting the outermost first fan-out wire and the outermost first signal wire, and an outermost second connecting wire connecting the outermost second fan-out wire and the outermost second signal wire. The outermost first connection wiring comprises a first sub-connection wiring connected to the outermost first fan-out wiring, a second sub-connection wiring connected to the outermost first signal wiring, and a third sub-connection wiring interconnecting the first sub-connection wiring and the second sub-connection wiring, and the outermost second connection wiring comprises a fourth sub-connection wiring connected to the outermost second fan-out wiring, a fifth sub-connection wiring connected to the outermost second signal wiring, and a sixth sub-connection wiring interconnecting the fourth sub-connection wiring and the fifth sub-connection wiring, wherein the distance between the first sub-connection wiring and the fourth sub-connection wiring is greater than the distance between the second sub-connection wiring and the fifth sub-connection wiring.

[0024] The third sub-connecting wire extends in a first direction, and the first sub-connecting wire and the second sub-connecting wire may extend in a second direction different from the first direction.

[0025] The first sub-connecting wiring and the second sub-connecting wiring are disposed in a first conductive layer, and the third sub-connecting wiring may be disposed in a second conductive layer different from the first conductive layer.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0027] A display device according to one embodiment includes a plurality of fan-out wiring groups, each comprising a plurality of fan-out wirings. By increasing the spacing between adjacent fan-out wiring groups, the electrostatic discharge phenomenon occurring during the manufacturing process of the display device can be reduced. Accordingly, noise generated in the display device can be reduced, thereby improving the reliability of the display device.

[0028] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0029] FIG. 1 is a perspective view of a display device according to one embodiment. Figure 2 is a layout diagram showing an example of the display panel of Figure 1. FIG. 3 is an equivalent circuit diagram of a pixel of a display device according to one embodiment. FIG. 4 is a cross-sectional view of a pixel of a display device according to one embodiment. Figure 5 is an enlarged view of the P region of Figure 2. Figure 6 is an enlarged view of the Q region of Figure 2. Figure 7 is an enlarged view of the R region of Figure 2. Figure 8 is a cross-sectional view taken along VIII-VIII' of Figure 7. Figure 9 is a cross-sectional view taken along IX-IX' of Figure 7. FIG. 10 is a flowchart illustrating a method for manufacturing a display device according to one embodiment. FIGS. 11 and FIGS. 12 are schematic diagrams illustrating a method for manufacturing a display device according to one embodiment. FIG. 13 is a partial layout diagram of a display device according to another embodiment. FIG. 14 is a partial layout diagram of a display device according to another embodiment. Figure 15 is a cross-sectional view taken along XV-XV' of Figure 14. FIG. 16 is a partial layout diagram of a display device according to another embodiment. FIG. 17 is a partial layout diagram of a display device according to another embodiment. FIG. 18 is a partial layout diagram of a display device according to another embodiment. FIG. 19 is a partial layout diagram of a display device according to another embodiment. FIG. 20 is a partial layout diagram of a display device according to another embodiment. Specific details for implementing the invention

[0030] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0031] When elements or layers are referred to as being on another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components.

[0032] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0033] Specific embodiments will be described below with reference to the attached drawings.

[0034] FIG. 1 is a perspective view of a display device according to one embodiment.

[0035] Referring to FIG. 1, a display device (1) according to one embodiment is a device for displaying video or still images, and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0036] A display device (1) according to one embodiment includes a display panel (10), a display driving circuit (30), and a circuit board (20).

[0037] The display panel (10) may be formed in a rectangular shape having a long side in the first direction (X) and a short side in the second direction (Y) that intersects the first direction (X). The corner where the long side in the first direction (X) and the short side in the second direction (Y) meet may be formed at a right angle, but is not limited thereto and may be formed rounded to have a predetermined curvature. The planar shape of the display panel (10) is not limited to a rectangle and may be formed in other polygons, circles, or ellipses.

[0038] The display panel (10) may include a display area (DA) for displaying an image and a non-display area (NDA) placed around the display area (DA). The display area (DA) may occupy most of the area of ​​the display panel (10). The display area (DA) may be placed in the center of the display panel (10). A plurality of pixels (see 'PX' in FIG. 2) may be placed in the display area (DA) to display an image.

[0039] The non-display area (NDA) may be placed adjacent to the display area (DA). The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may be placed to surround the display area (DA). The non-display area (NDA) may be located at the edge of the display area (DA).

[0040] A plurality of circuit boards (20) may be disposed in the non-display area (NDA). Specifically, a plurality of circuit boards (20) may be disposed on one side edge of the display panel (10). Although a display device (1) including four circuit boards (20) is illustrated in FIG. 1, the number of circuit boards (20) is not limited thereto.

[0041] The display panel (10) can receive data signals, power voltages, and scan control signals through the circuit board (20). The circuit board (20) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0042] The display driving circuit (30) can generate a data signal and a scan control signal. The display driving circuit (30) can supply the data signal and the scan control signal to the display panel (10) through the circuit board (20). Alternatively, the scan control signal may be generated by a separate timing driving circuit other than the display driving circuit (30) and supplied to the display panel (10) through the circuit board (20). The display driving circuit (30) may be formed as an integrated circuit (IC) and attached to the circuit board (20).

[0043] Figure 2 is a layout diagram showing an example of the display panel of Figure 1.

[0044] Referring to FIG. 2, the display panel (10) may include a plurality of pixels (PX), a plurality of scan drivers (SDC), a plurality of scan lines (SL), a plurality of data lines (DL), first and second power lines (ELVDL, ELVSL), a plurality of pads (PD), and a plurality of fan-out lines (see 'PL' in FIG. 5).

[0045] A plurality of pixels (PX), a plurality of scan lines (SL), a plurality of data lines (DL), and first and second power lines (ELVDL, ELVSL) may be arranged in the display area (DA) of the display panel (10).

[0046] A plurality of scan lines (SL) may be extended in a first direction (X) and arranged in a second direction (Y). The scan lines (SL) are connected to a scan drive unit (SDC), and a scan signal provided from the scan drive unit (SDC) may be applied to the scan lines (SL).

[0047] Each data line (DL) can be extended in a second direction (Y). Each of the multiple data lines (DL) can be arranged in a first direction (X). Each data line (DL) is connected to a display pad (DP), thereby allowing each data line (DL) to be electrically connected to a display driving circuit (30) of a circuit board (20) through the display pad (DP). A data signal provided from the display driving circuit (30) can be applied to the data lines (DL).

[0048] Multiple pixels (PX) can be arranged in a first direction (X) and a second direction (Y). That is, multiple pixels (PX) can be arranged in a matrix form. The specific structure of each pixel (PX) will be described later.

[0049] In the non-display area (NDA) of the display panel (10), a plurality of pads (PD) and a plurality of fan-out wirings (PL) extending from each of the plurality of pads (PD) may be arranged. The plurality of pads (PD) may include a plurality of display pads (DP), a plurality of scan pads (SP), a plurality of first power pads (VDP), and a plurality of second power pads (VSP). A description of the plurality of fan-out wirings (PL) will be provided later with reference to FIGS. 5 to 7.

[0050] The scan driver (SDC) can be connected to the scan pad (SP). As a result, the scan driver (SDC) can be electrically connected to the circuit board (20) through the scan pad (SP). A scan control signal provided from the circuit board (20) can be applied to the scan driver (SDC). The scan driver (SDC) can generate a scan signal according to the scan control signal and supply it to the scan wiring (SL).

[0051] In FIG. 2, the scan drive unit (SDC) is exemplified as being placed in the non-display area (NDA) on the left outer side and the right outer side of the display area (DA), but is not limited thereto. For example, the scan drive unit (SDC) may be placed in either the non-display area (NDA) on the left outer side or the non-display area (NDA) on the right outer side of the display area (DA).

[0052] Multiple pads (PD) may be placed in a pad area (PDA) located on the other side of the second direction (Y) of the display panel (10). The pad area (PDA) may be placed extending along the first direction (X) from a non-display area (NDA) located on the other side of the second direction (Y) of the display area (DA).

[0053] In a pad area (PDA), a plurality of pads (PDs) may be arranged along a first direction (X). In the pad area (PDA), a plurality of pads (PDs) may be arranged to form a pad group (PG). A pad group (PG) may be a set of a plurality of pads (PDs) such that the distance between adjacent pads (PDs) is generally the same. A detailed description of the pad group (PG) will be provided later.

[0054] Within the pad area (PDA), a plurality of display pads (DP), a first power pad (VDP) disposed on one side of the plurality of display pads (DP), and a second power pad (VSP) disposed on the other side of the plurality of display pads (DP) may be disposed.

[0055] Multiple display pads (DP) may be arranged in a row along a first direction (X). However, they are not limited thereto, and multiple display pads (DP) may be arranged in multiple columns. A fan-out wiring (PL) extending in a second direction (Y) may be connected to the display pads (DP).

[0056] In a pad area (PDA), a first power pad (VDP) may be disposed on the other side of the first direction (X) of a plurality of display pads (DP). A fan-out wiring (PL) extending in the second direction (Y) may be connected to the first power pad (VDP). The fan-out wiring (PL) connected to the first power pad (VDP) may be electrically connected to the first power wiring (ELVDL).

[0057] In a pad area (PDA), a second power pad (VSP) may be disposed on one side of the first direction (X) of a plurality of display pads (DP). A fan-out wiring (PL) extending in the second direction (Y) may be connected to the second power pad (VSP). The fan-out wiring (PL) connected to the second power pad (VSP) may be electrically connected to the second power wiring (ELVSL).

[0058] A first power line (ELVDL) extending from a first power pad (VDP) in a second direction (Y) can be branched into multiple lines in a first direction (X) and connected to the pixel electrodes of each pixel (PX) (see 'PXE' in FIG. 4). A second power line (ELVSL) extending from a second power pad (VSP) in a second direction (Y) can be electrically connected to a common electrode (see 'CME' in FIG. 4) described later.

[0059] FIG. 3 is an equivalent circuit diagram of a pixel of a display device according to one embodiment.

[0060] Referring to FIG. 3, each pixel (PX) of a display device (1) according to one embodiment includes, in addition to a light-emitting element (EMD), three transistors (DTR, STR1, STR2) and one storage capacitor (CST).

[0061] The light-emitting diode (EMD) emits light according to the current supplied through the driving transistor (DTR). The light-emitting diode (EMD) can be implemented as an organic light-emitting diode, a micro light-emitting diode, a nano light-emitting diode, etc.

[0062] The first electrode (i.e., anode electrode) of the light-emitting element (EMD) is connected to the source electrode of the driving transistor (DTR), and the second electrode (i.e., cathode electrode) can be connected to the second power line (ELVSL) to which a low potential voltage (second power voltage) lower than the high potential voltage (first power voltage) of the first power line (ELVDL) is supplied.

[0063] The driving transistor (DTR) adjusts the current flowing from the first power line (ELVDL), to which the first power supply voltage is supplied, to the light-emitting element (EMD) according to the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor (DTR) is connected to the first source / drain electrode of the first switching transistor (STR1), the source electrode is connected to the first electrode of the light-emitting element (EMD), and the drain electrode can be connected to the first power line (ELVDL), to which the first power supply voltage is applied.

[0064] The first switching transistor (STR1) is turned on by a scan signal of the scan line (SL) to connect the data line (DL) to the gate electrode of the driving transistor (DTR). The gate electrode of the first switching transistor (STR1) is connected to the scan line (SL), the first source / drain electrode is connected to the gate electrode of the driving transistor (DTR1), and the second source / drain electrode can be connected to the data line (DL).

[0065] The second switching transistor (STR2) is turned on by the sensing signal of the sensing signal line (SSL) to connect the reference voltage line (RVL) to the source electrode of the driving transistor (DTR). The gate electrode of the second switching transistor (STR2) is connected to the sensing signal line (SSL), the first source / drain electrode is connected to the reference voltage line (RVL), and the second source / drain electrode can be connected to the source electrode of the driving transistor (DTR).

[0066] In one embodiment, the first source / drain electrode of each of the first and second switching transistors (STR1, STR2) may be a source electrode and the second source / drain electrode may be a drain electrode, but is not limited thereto and may be the opposite case.

[0067] A storage capacitor (CST) is formed between the gate electrode and the source electrode of a driving transistor (DTR). The storage capacitor (CST) can store the voltage difference between the gate voltage and the source voltage of the driving transistor (DTR).

[0068] The driving transistor (DTR) and the first and second switching transistors (STR1, STR2) may be formed as thin film transistors. The driving transistor (DTR) and the first and second switching transistors (STR1, STR2) may be formed as N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), but are not limited thereto, and may be formed as P-type MOSFETs, or some may be formed as N-type MOSFETs and others as P-type MOSFETs.

[0069] FIG. 4 is a cross-sectional view of a pixel of a display device according to one embodiment.

[0070] Referring to FIG. 4, FIG. 4 illustrates a front-emitting type display device in which light (L) is emitted in the opposite direction (toward the second base substrate (210)) rather than in the direction of the first base substrate (110) on which the light-emitting layer (EML) is formed, but is not limited thereto, and the display device (1) may be a back-emitting type or a double-sided light-emitting type display device.

[0071] The display device (1) may include a first display substrate (100), a second display substrate (200) facing the same, and a filling layer (300) that combines them.

[0072] The first display substrate (100) may sequentially have a base substrate (110), a barrier layer (111), a buffer layer (112), a semiconductor layer (130), a gate insulating layer (113), a second conductive layer (140), an interlayer insulating layer (161), a third conductive layer (150), a via layer (162), a pixel electrode (PXE), a pixel defining layer (PDL), an emitting layer (EML), a common electrode (CME), and a thin film encapsulation layer (170). Each of the above-described layers may be made of a single film, but may also be made of a stacked film comprising a plurality of films. Other layers may be further disposed between each layer.

[0073] The base substrate (110) supports each layer placed thereon. The base substrate (110) may be made of an insulating material, for example, a polymer resin. Not limited thereto, the base substrate (110) may also include a metal material.

[0074] When the organic light-emitting display device is of the back or double-sided emission type, a transparent substrate may be used. When the organic light-emitting display device is of the front emission type, not only a transparent substrate but also a translucent or opaque substrate may be applied.

[0075] A barrier layer (111) may be disposed on a base substrate (110). The barrier layer (111) can prevent the diffusion of impurity ions, prevent the penetration of moisture or external air, and perform a surface flattening function. The barrier layer (111) may include silicon nitride, silicon oxide, or silicon oxynitride, etc. The barrier layer (111) may be omitted depending on the type of base substrate (110) or process conditions.

[0076] A first conductive layer (120) may be disposed on the barrier layer (111). The first conductive layer (120) may include a light-blocking pattern (121). The light-blocking pattern (121) can prevent photocurrent from flowing in the channel region (131c) by blocking external light from being irradiated onto the channel region (131c) of the semiconductor pattern (131a, 131b, 131c) described later.

[0077] A buffer layer (112) may be disposed on the first conductive layer (120). The buffer layer (112) may be formed by including at least one of silicon nitride, silicon oxide, or silicon oxynitride. The buffer layer (112) may be omitted depending on the type of base substrate (110) or process conditions.

[0078] A semiconductor layer (130) may be disposed on the buffer layer (112). The semiconductor layer (130) may include semiconductor patterns (131a, 131b, 131c).

[0079] The semiconductor pattern (131a, 131b, 131c) may include a channel region (131c) that overlaps with the upper gate electrode (141) in the thickness direction, and a first source / drain region (131a) and a second source / drain region (131b) respectively disposed on one side and the other side of the channel region (131c). The first and second source / drain regions (131a, 131b) contain a plurality of carrier ions, so that the conductivity is higher and the electrical resistance is lower compared to the channel region (131c). The semiconductor layer (130) may be made of polycrystalline silicon, single-crystal silicon, or amorphous silicon, etc.

[0080] A gate insulating layer (113) may be disposed on the semiconductor layer (130). The gate insulating layer (113) may generally be disposed over the entire front surface of the base substrate (110). The gate insulating layer (113) may include silicon compounds, metal oxides, etc. For example, the gate insulating layer (113) may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These may be used alone or in combination with each other.

[0081] A second conductive layer (140) may be disposed on the gate insulating layer (113). The second conductive layer (140) may include a gate electrode (141) as a gate conductive layer. The second conductive layer (140) may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0082] An interlayer insulating layer (161) may be disposed on the second conductive layer (140). The interlayer insulating layer (161) may include silicon compounds, metal oxides, etc. For example, the interlayer insulating layer (161) may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These may be used alone or in combination with each other.

[0083] A third conductive layer (150) may be disposed on the interlayer insulating layer (161). The third conductive layer (150) is a data conductive layer and may include a data wiring (DL) that applies a data signal. The third conductive layer (150) may include a first source / drain electrode (151) and a second source / drain electrode (152) of a driving transistor (DTR).

[0084] The first source / drain electrode (151) can be electrically connected to the first source / drain region (131a) of the semiconductor pattern (131a, 131b, 131c) through a contact hole penetrating the interlayer insulating layer (161) and the gate insulating layer (113).

[0085] The second source / drain electrode (152) can be electrically connected to the second source / drain region (131b) of the semiconductor pattern (131a, 131b, 131c) through a contact hole penetrating the interlayer insulating layer (161) and the gate insulating layer (113).

[0086] The third conductive layer (150) may include one or more metals selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0087] A via layer (162) may be disposed on the third conductive layer (150). The via layer (162) may be disposed on the upper portion of the third conductive layer (150) to completely cover the upper surface of the interlayer insulating layer (161). If the via layer (162) is made of an organic film, the upper surface may be partially flat despite the step difference at the bottom.

[0088] The via layer (162) may include an organic insulating material such as an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ethers resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0089] A pixel electrode (PXE) may be disposed on the via layer (162). The pixel electrode (PXE) may be an anode electrode. The pixel electrode (PXE) may be disposed separately for each pixel (PX). The pixel electrode (PXE) may be electrically connected to a second source / drain electrode (152) through a contact hole penetrating the via layer (162).

[0090] For example, the pixel electrode (PXE) may have a stacked structure in which a high work function material layer such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), and indium oxide (In2O3) is stacked with a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof is stacked. The high work function layer may be positioned above the reflective material layer and positioned close to the light-emitting layer (EML).

[0091] A pixel defining film (PDL) may be disposed on the pixel electrode (PXE). The pixel defining film (PDL) may include an opening that partially exposes the pixel electrode (PXE). The pixel defining film (PDL) may partially cover the pixel electrode (PXE) and the via layer (162).

[0092] The pixel defining layer (PDL) may be composed of an organic insulating material or an inorganic insulating material. For example, the pixel defining layer (PDL) may be composed of at least one of a polyimide resin, an acrylic resin, a silicone compound, a polyacrylic resin, etc.

[0093] An emissive layer (EML) may be disposed on the pixel electrode (PXE) exposed by the pixel defining film (PDL). At least a portion of the emissive layer (EML) may be disposed within the opening of the pixel defining film (PDL). The emissive layer (EML) may partially cover the upper surface of the pixel defining film (PDL) and the side of the pixel defining film (PDL) forming the opening.

[0094] The emitting layer (EML) may include an organic material layer. The organic material layer includes an organic emitting layer and may further include a hole injection / transport layer and an electron injection / transport layer.

[0095] A common electrode (CME) may be disposed on the light-emitting layer (EML). The common electrode (CME) may be disposed across the entire surface without distinction between pixels (PX). The common electrode (CME) may be a cathode electrode.

[0096] The common electrode (CME) may include a layer of material with a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg). The common electrode (CME) may further include a transparent metal oxide layer disposed on the layer of material with a low work function.

[0097] The pixel electrode (PXE), the light-emitting layer (EML), and the common electrode (CME) can constitute a light-emitting element (EMD). The light-emitting element (EMD) may be, for example, an organic light-emitting element. In one embodiment, the wavelength of light emitted by the light-emitting element (EMD) may be constant for each pixel (PX). For example, the light-emitting layer (EML) of each color pixel (PX) emits blue light or ultraviolet light, and the second display substrate (200) described later includes a wavelength conversion layer (WCL), thereby allowing different colors to be displayed for each pixel (PX).

[0098] In another embodiment, the wavelength of light emitted by each light-emitting layer (EML) may differ for each color pixel (PX), so the color of the emitted light may differ. For example, the light-emitting layer (EML) of the first color pixel (PX) may emit a first color, the light-emitting layer (EML) of the second color pixel (PX) may emit a second color, and the light-emitting layer (EML) of the third color pixel (PX) may emit a third color.

[0099] A thin film encapsulation layer (170) may be disposed on the upper portion of the common electrode (CME). The thin film encapsulation layer (170) may include a first inorganic film (171), a first organic film (172) disposed on the first inorganic film (171), and a second inorganic film (173) disposed on the first organic film (172). Although not illustrated, at the ends of the thin film encapsulation layer (170), the first inorganic film (171) and the second inorganic film (173) may be in contact with each other, so that the first organic film (172) may be sealed by the first inorganic film (171) and the second inorganic film (173).

[0100] The first inorganic film (171) and the second inorganic film (173) may each include silicon nitride, silicon oxide, or silicon oxynitride, etc. The first organic film (172) may include an organic insulating material.

[0101] The second display substrate (200) can be positioned opposite the first display substrate (100) on top of the thin film encapsulation layer (170).

[0102] The second base substrate (210) of the second display substrate (200) may include a transparent insulating material such as glass. The second base substrate (210) may be a rigid substrate.

[0103] A light-blocking member (BML) may be disposed along the boundary of a pixel (PX) on one side of a second base substrate (210) facing a first base substrate (110). The light-blocking member (BML) may overlap with the pixel defining film (PDL) of the first display substrate (100). The light-blocking member (BML) is formed in a grid shape in a planar view and may include an opening that exposes one side of the second base substrate (210).

[0104] A color filter layer (CFL) may be disposed on one side of the second base substrate (210) on which a light-blocking member (BML) is disposed. The color filter layer (CFL) may be disposed on one side of the second base substrate (210) that is exposed through an opening of the light-blocking member (BML).

[0105] The color filter layer (CFL) may include a colorant, such as a dye or pigment, that absorbs wavelengths other than the corresponding color wavelength. The color filter layer (CFL) may include a colorant of a different color for each pixel (PX). For example, the color filter layer (CFL) may include a red colorant, a green colorant, and a blue colorant.

[0106] A first capping layer (220) that prevents the penetration of impurities such as moisture or air may be disposed on the color filter layer (CFL).

[0107] A partition (PTL) may be disposed on the first capping layer (220). The partition (PTL) may be disposed to overlap with the light-blocking member (BML). The partition (PTL) may include an opening that exposes an area where a color filter layer (CFL) is disposed.

[0108] A wavelength conversion layer (WCL) may be disposed within the space exposed by the opening of the partition wall (PTL). The wavelength conversion layer (WCL) may be formed by an inkjet process using the partition wall (PTL) as a bank, but is not limited thereto.

[0109] The wavelength conversion layer (WCL) can convert the wavelength of light incident from the light-emitting layer (EML). The wavelength conversion layer (WCL) may include a base resin (BRS), a scatterer (SCPC) disposed within the base resin (BRS), and a wavelength conversion material (WCP). The base resin (BRS) may include a transparent organic material. The wavelength conversion material (WCP) may be a quantum dot, a quantum rod, a phosphor, etc. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or a combination thereof.

[0110] A second capping layer (230) may be disposed on the wavelength conversion layer (WCL) and the partition (PTL). That is, the second capping layer (230) may be disposed over the entire surface of the second display substrate (200).

[0111] A filling layer (300) may be disposed between the first display substrate (100) and the second display substrate (200). The filling layer (300) fills the space between the first display substrate (100) and the second display substrate (200) and may serve to bond them together. The filling layer (300) may be disposed between the thin film encapsulation layer (170) of the first display substrate (100) and the second capping layer (230) of the second display substrate (200). The filling layer (300) may be composed of Si-based organic materials, epoxy-based organic materials, etc., but is not limited thereto.

[0112] Figure 5 is an enlarged view of the P region of Figure 2.

[0113] Referring to FIG. 5 in conjunction with FIG. 2, a display panel (10) included in a display device (1) according to one embodiment as described above may include a pad area (PDA) in which a plurality of pads (PDs) are arranged. The pad area (PDA) is arranged on the other side of the second direction (Y) of the display panel (10) and may have a shape extending along the first direction (X). In the pad area (PDA), a plurality of pads (PDs) may be arranged along the first direction (X). A plurality of pads (PDs) arranged in the pad area (PDA) may form a plurality of pad groups (PG). A pad group (PG) may be defined as a set of a plurality of pads (PDs) that overlap with a single circuit board (20). Pads (PDs) that overlap with different circuit boards (20) may belong to different pad groups (PG).

[0114] In a display panel (10) included in a display device (1) according to one embodiment, a pad group (PG) may include a first pad group (PG1) and a second pad group (PG2) disposed on one side of the first direction (X) of the first pad group (PG1).

[0115] The spacing (a1) between adjacent pads (PDs) within a pad group (PG) may generally be the same. That is, in one embodiment, among a plurality of pads (PDs), pads (PDs) with spacing between adjacent pads (PDs) generally being the same may be included in the same pad group (PG). Here, the meaning of "same" includes not only being completely identical, but also falling within an error range of about 10% from the average value of the spacing (a1) between adjacent pads (PDs) within a pad group (PG). However, it is not limited thereto, and the spacing (a1) between adjacent pads (PDs) included within a pad group (PG) may be different.

[0116] The gap (a2) between the first pad group (PG1) and the second pad group (PG2) may refer to the gap between the closest pads (PDs) in the first pad group (PG1) and the second pad group (PG2). That is, the gap (a2) between the first pad group (PG1) and the second pad group (PG2) may refer to the gap between the pad (PD) positioned on the first side of the first direction (X) in the first pad group (PG1) and the pad (PD) positioned on the other side of the first direction (X) in the second pad group (PG2). In other words, the gap (a2) between the first pad group (PG1) and the second pad group (PG2) may refer to the gap between the outermost pad (PD) located closest to the second pad group (PG2) in the first pad group (PG1) and the outermost pad (PD) located closest to the first pad group (PG1) in the second pad group (PG2).

[0117] The spacing (a2) between the first pad group (PG1) and the second pad group (PG2) may be larger than the spacing (a1) between adjacent pads (PD) within the pad group (PG1, PG2). Here, "larger" may mean that the spacing (a2) between the first pad group (PG1) and the second pad group (PG2) is 2 times, 5 times, or 10 times or more larger than the spacing (a1) between adjacent pads (PD) within the pad group (PG1, PG2).

[0118] A pad group (PG) may include approximately 100 pads (PDs), but is not limited thereto, and the number of pads (PDs) included in a pad group (PG) may vary.

[0119] In one embodiment, a pad (PD) positioned at the outermost edge of the other side of the first direction (X) in a pad group (PG) may be a first power pad (VDP) to which a first power voltage is applied, and a pad (PD) positioned at the outermost edge of the first side of the first direction (X) may be a second power pad (VSP) to which a second power voltage is applied. A plurality of pads (PDs) positioned between the first power pad (VDP) and the second power pad (VSP) may be display pads (DP) to which a data voltage is applied.

[0120] However, in the case of a pad group (PG) disposed at the outermost edge of one side of the first direction (X) in the display panel (10), the pad (PD) disposed at the outermost edge of one side of the first direction (X) may be a scan pad (SP) connected to a scan drive unit (SDC). Additionally, in the case of a pad group (PG) disposed at the outermost edge of the other side of the first direction (X) in the display panel (10), the pad (PD) disposed at the outermost edge of the other side of the first direction (X) may be a scan pad (SP) connected to a scan drive unit (SDC).

[0121] A fan-out wiring group (PLG) may be extended from each pad group (PG) toward one side of the second direction (Y). The fan-out wiring group (PLG) may include a plurality of fan-out wirings (PL). A detailed description of the fan-out wiring group (PLG) will be provided later with reference to FIG. 6.

[0122] FIG. 6 is an enlarged view of region Q of FIG. 2. FIG. 7 is an enlarged view of region R of FIG. 2. FIG. 8 is a cross-sectional view taken along VIII-VIII' of FIG. 7. FIG. 9 is a cross-sectional view taken along IX-IX' of FIG. 7.

[0123] Referring to FIGS. 2 and FIGS. 6 through 9, a fan-out wiring group (PLG) may include a plurality of fan-out wirings (PL). The plurality of fan-out wirings (PL) may be arranged in a first direction (X).

[0124] For each pad (PD) included in the pad group (PG), one fan-out wire (PL) may be extended. That is, the number of pads (PD) included in the pad group (PG) and the number of fan-out wires (PL) included in the fan-out wire group (PLG) extending from the pad group (PG) may be the same.

[0125] However, not limited thereto, if a pad group (PG) includes some pads (PD) to which the fan-out wiring (PL) is not extended, the number of pads (PD) included in the pad group (PG) may be less than the number of fan-out wiring (PL) included in the fan-out wiring group (PLG) extending from the pad group (PG).

[0126] Hereinafter, an example is given in which n fan-out wirings (PL) are included in a single fan-out wiring group (PLG). The fan-out wiring group (PLG) illustrated in FIG. 6 may include the first to nth fan-out wirings (PL1 to PL(n)).

[0127] In a fan-out wiring group (PLG), as one side of the second direction (Y) moves toward the outermost edge of one side of the first direction (X), the distance between the nth fan-out wiring (PL(n)) and the first fan-out wiring (PL1) placed at the outermost edge of the other side of the first direction (X) may increase. A plurality of fan-out wirings (PL) included in the fan-out wiring group (PLG) may have a shape that extends toward the second direction (Y) and moves away from an imaginary line bisecting the fan-out wiring group (PLG) as one side of the second direction (Y) moves toward the second direction (Y).

[0128] For example, in a fan-out wiring group (PLG), the fan-out wiring (PL) placed on the other side of the first direction (X) based on a virtual line that extends in the second direction (Y) and bisects the fan-out wiring group (PLG) may have a shape that extends in the direction between the other side of the first direction (X) and the one side of the second direction (Y).

[0129] In addition, in the fan-out wiring group (PLG), the fan-out wiring (PL) arranged on one side of the first direction (X) based on a virtual line that extends in the second direction (Y) and bisects the fan-out wiring group (PLG) may have a shape that extends in the direction between one side of the first direction (X) and one side of the second direction (Y).

[0130] However, not limited thereto, some fan-out wiring (PL) that is positioned adjacent to a virtual line extending in the second direction (Y) and bisecting the fan-out wiring group (PLG) in the fan-out wiring group (PLG) may have a shape that extends in the second direction (Y). Additionally, the degree of inclination of each fan-out wiring (PL) from the virtual line extending in the second direction (Y) in the fan-out wiring group (PLG) may increase as it moves outward from the fan-out wiring group (PLG).

[0131] In a display panel (10) according to one embodiment, a first fan-out wiring (PL1) extends from a first power pad (VDP), and an n-th fan-out wiring (PL(n)) may extend from a second power pad (VSP). The second to (n-1) fan-out wirings (PL(n-1)) may extend from a display pad (DP).

[0132] The spacing between fan-out wiring (PL) can be defined as the spacing between one end of the second direction (Y) of the fan-out wiring (PL). The spacing (b1) between adjacent fan-out wiring (PL) in a fan-out wiring group (PLG) may generally be constant. However, the spacing (b3) between two adjacent fan-out wiring (PL) placed at the outermost edge of one side of the first direction (X) and the outermost edge of the other side of the first direction (X) in a fan-out wiring group (PLG) may be smaller than or equal to the spacing (b1) between two adjacent fan-out wiring (PL) placed in different areas. Details regarding this will be described later.

[0133] A signal wiring group (DLG) may be spaced apart from one side of the second direction (Y) of the fan-out wiring group (PLG). The signal wiring group (DLG) may include a first power wiring (ELVDL), a second power wiring (ELVSL), and a plurality of data wirings (DL) extending in the second direction (Y). Hereinafter, the description of the wiring included in the signal wiring group (DLG) will be based on the data wiring (DL), but the same description may be applied to the first power wiring (ELVDL) and the second power wiring (ELVSL).

[0134] In a signal wiring group (DLG), the spacing (d1) between adjacent data wirings (DL) can generally be constant. In addition, the spacing (d2) between adjacent signal wiring groups (DLG) can also generally be constant. Furthermore, the spacing (d1) between adjacent data wirings (DL) in a signal wiring group (DLG) can be the same as the spacing (d2) between adjacent signal wiring groups (DLG).

[0135] The spacing (d2) between adjacent signal wiring groups (DLG) may be smaller than the spacing (a2) between the first pad group (PG1) and the second pad group (PG2) described above.

[0136] The spacing (d2) between adjacent signal wiring groups (DLG) may refer to the spacing between a data wiring (DL) placed at the outermost edge of one side of the first direction (X) in one signal wiring group (DLG) and a data wiring (DL) placed at the outermost edge of the other side of the first direction (X) in another signal wiring group (DLG) placed at the outermost edge of the other side of the first direction (X) in one side of the first signal wiring group (DLG).

[0137] The number of data wires (DL) included in a signal wiring group (DLG) may be the same as the number of fan-out wires (PL) included in a fan-out wiring group (PLG) positioned on the other side of the second direction (Y) of the signal wiring group (DLG). However, not limited thereto, the number of data wires (DL) included in a signal wiring group (DLG) may be different from the number of fan-out wires (PL) included in a fan-out wiring group (PLG) positioned on the other side of the second direction (Y) of the signal wiring group (DLG).

[0138] Data wiring (DL) included in a signal wiring group (DLG) may be aligned along the second direction (Y) with fan-out wiring (PL) included in a fan-out wiring group (PLG) positioned on the other side of the second direction (Y) of the signal wiring group (DLG). However, data wiring (DL) positioned at the outermost edge of one side of the first direction (X) and the outermost edge of the other side of the first direction (X) in a signal wiring group (DLG), and fan-out wiring (PL) positioned at the outermost edge of one side of the first direction (X) and the outermost edge of the other side of the first direction (X) in a fan-out wiring group (PLG) positioned on the other side of the second direction (Y) of the signal wiring group (DLG) may not be aligned along the second direction (Y). Specifically, the spacing between the data lines (DL) placed at the outermost edge of one side of the first direction (X) and the outermost edge of the other side of the first direction (X) in the signal wiring group (DLG) may be greater than the spacing between the fan-out lines (PL) placed at the outermost edge of one side of the first direction (X) and the outermost edge of the other side of the first direction (X) in the fan-out wiring group (PLG).

[0139] A signal wiring group (DLG) and a fan-out wiring group (PLG) positioned on the other side of the second direction (Y) of the signal wiring group (DLG) may be positioned spaced apart from each other in the second direction (Y). The end of the data wiring (DL) included in the signal wiring group (DLG) and the end of the fan-out wiring (PL) included in the fan-out wiring group (PLG) positioned on the other side of the second direction (Y) of the signal wiring group (DLG) may face each other. Accordingly, during the manufacturing process of the display device (1), an electrostatic discharge phenomenon may occur between the data wiring (DL) and the fan-out wiring (PL) depending on the circumstances. Since the electrostatic discharge phenomenon can cause damage to various insulating layers and conductive layers included in the display device (1), it may be desirable to minimize it. As a method to minimize the electrostatic discharge phenomenon, a sufficient distance can be secured between the signal wiring group (DLG) and the fan-out wiring group (PLG). The distance (c1) between the signal wiring group (DLG) and the fan-out wiring group (PLG) can be defined as the minimum distance in the second direction (Y) between the other end of the data wiring (DL) included in the signal wiring group (DLG) in the second direction (Y) and the one end of the fan-out wiring (PL) included in the fan-out wiring group (PLG) in the second direction (Y).

[0140] The distance (c1) between the signal wiring group (DLG) and the fan-out wiring group (PLG) may be approximately 280 µm or more. For example, the separation distance (c1) between one data wiring (DL) included in the signal wiring group (DLG) and one data wiring (DL) in the fan-out wiring group (PLG) placed on the other side of the second direction (Y) of the signal wiring group (DLG) may be approximately 280 µm or more.

[0141] The signal wiring group (DLG) and the fan-out wiring group (PLG) may be electrically connected to each other by a connecting electrode group (CEG). The connecting electrode group (CEG) may include a plurality of connecting wires (CE). The plurality of connecting wires (CE) may be arranged along a first direction (X). The plurality of connecting wires (CE) may include first to nth connecting wires (CE1 to CE(n)). Within the connecting electrode group (CEG), the second to (n-1) connecting wires (CE2 to CE(n-1)) may have a shape extending in the second direction (Y). On the other hand, the first connecting wire (CE1) and the nth connecting wire (CE(n)) positioned at the outermost edge of one side of the first direction (X) and the outermost edge of the other side of the first direction (X) within the connecting electrode group (CEG) may have a partially bent structure.

[0142] Specifically, the first connecting wire (CE1) can be connected to the first fan-out wire (PL1) at one end and to the first power wire (ELVDL) at the other end through the first contact hole (CNT1). The first connecting wire (CE1) can be extended to one side of the second direction (Y) from one end that overlaps with the first fan-out wire (PL1), then bent to the other side of the first direction (X), and then extended again to one side of the second direction (Y). Through this, the other end of the first connecting wire (CE1) can overlap with the first power wire (ELVDL).

[0143] Additionally, the nth connection wiring (CE(n)) can be connected to the nth fan-out wiring (PL(n)) at one end and to the second power wiring (ELVSL) at the other end through the nth contact hole (CNT(n)). The nth connection wiring (CE(n)) can be extended to one side of the second direction (Y) from one end that overlaps with the nth fan-out wiring (PL(n)), then bent to one side of the first direction (X), and then extended again to one side of the second direction (Y). Through this, the other end of the nth connection wiring (CE(n)) can overlap with the second power wiring (ELVSL).

[0144] In one embodiment, the first and nth fan-out wirings (PL1, PL(n)) connected to the first power pad (VDP) and the second power pad (VSP), respectively, may be electrically connected to a dummy electrode (DE) through a plurality of contact holes (CNT1a, CNT1b). The dummy electrode (DE) may reduce the resistance of the first and nth fan-out wirings (PL1, PL(n)) to which the first power voltage and the second power voltage are applied. The dummy electrode (DE) may be arranged to overlap with the fan-out wiring group (PLG), but is not limited thereto.

[0145] The dummy electrode (DE) may include a first dummy electrode (DE1) that overlaps with the first fan-out wiring group (PLG1) and a second dummy electrode (DE2) that overlaps with the second fan-out wiring group (PLG2). The first dummy electrode (DE1) may include a first dummy electrode (DE1a) located on the other side of the first direction (X) with respect to a virtual line that bisects the first fan-out wiring group (PLG1) and a first dummy electrode (DE1b) located on one side of the first direction (X), extending in the second direction (Y). The first dummy electrode (DE1) may include a second dummy electrode (DE2a) located on the other side of the first direction (X) with respect to a virtual line that bisects the second fan-out wiring group (PLG2) and a second dummy electrode (DE2b) located on one side of the first direction (X), extending in the second direction (Y).

[0146] A first dummy electrode (DE1a) can be electrically connected to the first fan-out wiring (PL1) of the first fan-out wiring group (PLG1) through a plurality of first contact holes (CNT1a). The first contact holes (CNT1a) can be placed on one side and the other side, respectively, in the area where the first dummy electrode (DE1a) and the first fan-out wiring (PL1) of the first fan-out wiring group (PLG1) overlap. A first dummy electrode (DE1b) can be electrically connected to the nth fan-out wiring (PL(n)) of the first fan-out wiring group (PLG1) through a plurality of first contact holes (CNT1b). The first contact holes (CNT1b) can be placed on one side and the other side, respectively, in the area where the first dummy electrode (DE1b) and the nth fan-out wiring (PL(n)) of the first fan-out wiring group (PLG1) overlap.

[0147] The 2a dummy electrode (DE2a) can be electrically connected to the first fan-out wiring (PL1) of the second fan-out wiring group (PLG2) through a plurality of 2a contact holes (CNT2a). The 2a contact holes (CNT2a) can be placed on one side and the other, respectively, in the area where the 2a dummy electrode (DE2a) and the first fan-out wiring (PL1) of the second fan-out wiring group (PLG2) overlap. The 2b dummy electrode (DE2b) can be electrically connected to the nth fan-out wiring (PL(n)) of the second fan-out wiring group (PLG2) through a plurality of 2b contact holes (CNT2b). The 2b contact holes (CNT2b) can be placed on one side and the other, respectively, in the area where the 2b dummy electrode (DE2b) and the nth fan-out wiring (PL(n)) of the second fan-out wiring group (PLG2) overlap.

[0148] A display panel (10) according to one embodiment may include a first pad group (PG1), a first fan-out wiring group (PLG1) extending from the first pad group (PG1), a first signal wiring group (DLG1) spaced apart from the first fan-out wiring group (PLG1) in one side of the second direction (Y), and a first connection wiring group (CEG1) electrically connecting the first fan-out wiring group (PLG1) and the first signal wiring group (DLG1). Additionally, a display panel (10) according to one embodiment may include a second fan-out wiring group (PLG2) spaced apart from the first pad group (PG1) in one side of the first direction (X), a second signal wiring group (DLG2) spaced apart from the second fan-out wiring group (PLG2) in one side of the second direction (Y), and a second connection wiring group (CEG2) electrically connecting the second fan-out wiring group (PLG2) and the second signal wiring group (DLG2).

[0149] The first and second pad groups (PG1, PG2), the first and second fan-out wiring groups (PLG1, PLG2), and the first and second signal wiring groups (DLG1, DLG2) may be made of the same conductive layer. For example, the first and second pad groups (PG1, PG2), the first and second fan-out wiring groups (PLG1, PLG2), and the first and second signal wiring groups (DLG1, DLG2) may be made of the first conductive layer (120). That is, the first and second pad groups (PG1, PG2), the first and second fan-out wiring groups (PLG1, PLG2), and the first and second signal wiring groups (DLG1, DLG2) may be made of the same layer as the light-blocking pattern (121).

[0150] The first and second connecting wiring groups (CEG1, CEG2) and the first and second dummy electrodes (DE1, DE2) may be made of the same conductive layer. For example, the first and second connecting wiring groups (CEG1, CEG2) and the first and second dummy electrodes (DE1, DE2) may be made of the third conductive layer (150). That is, the first and second connecting wiring groups (CEG1, CEG2) and the first and second dummy electrodes (DE1, DE2) may be made of the same layer as the first source / drain electrode (151) and the second source / drain electrode (152).

[0151] In the first and second connecting wire groups (CEG1, CEG2), the spacing (e1) between the connecting wires (CE) may generally be constant. However, the spacing (e3) between the first connecting wire (CE1) and the second connecting wire (CE2), or the spacing (e3) between the (n-1) connecting wire (CE(n-1)) and the nth connecting wire (CE(n)), may differ from the spacing (e1) between other connecting wires (CE). Specifically, the spacing (e3) between the first connecting wire (CE1) and the second connecting wire (CE2), or the spacing (e3) between the (n-1) connecting wire (CE(n-1)) and the nth connecting wire (CE(n)), may differ from the spacing (e1) between other connecting wires (CE) due to the shape of the first connecting wire (CE1) and the nth connecting wire (CE(n)).

[0152] The minimum distance (e2) between the first connection wiring group (CEG1) and the second connection wiring group (CEG2) can be defined as the minimum distance between the nth connection wiring (CE(n)) of the first connection wiring group (CEG1) and the first connection wiring (CE1) of the second connection wiring group (CEG2).

[0153] The spacing (b2) between adjacent first fan-out wiring group (PLG1) and second fan-out wiring group (PLG2) can be defined as the distance between the second direction (Y) end of the nth fan-out wiring (PL(n)) positioned on one side of the first direction (X) within one fan-out wiring group (PLG) and the second direction (Y) end of the first fan-out wiring (PL1) positioned on the other side of the first direction (X) within the fan-out wiring group (PLG) adjacent to one side of the first direction (X).

[0154] In a display panel (10) according to one embodiment, if the spacing (b2) between adjacent first fan-out wiring group (PLG1) and second fan-out wiring group (PLG2) is sufficient, the electrostatic discharge phenomenon occurring between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) during the manufacturing process of the display device (1) can be minimized. Through this, damage to various conductive layers or insulating layers within the display panel (10) can be minimized, thereby improving the reliability of the display device (1).

[0155] The gap (b2) between adjacent first fan-out wiring group (PLG1) and second fan-out wiring group (PLG2) may be larger than the gap (d2) between adjacent first signal wiring group (DLG1) and second signal wiring group (DLG2).

[0156] The distance (b2) between adjacent first fan-out wiring group (PLG1) and second fan-out wiring group (PLG2) may be greater than or equal to the distance (c1) between the first signal wiring group (DLG1) and the first fan-out wiring (PLG1). For example, the distance (b2) between adjacent first fan-out wiring group (PLG1) and second fan-out wiring group (PLG2) may be about 280 µm or more.

[0157] The spacing (b2) between adjacent first fan-out wiring group (PLG1) and second fan-out wiring group (PLG2) may be greater than or equal to the minimum distance (e2) between first connection wiring group (CEG1) and second connection wiring group (CEG2).

[0158] According to a display device (1) according to one embodiment, a sufficient separation distance is secured between a first fan-out wiring group (PLG1) and a second fan-out wiring group (PLG2) to minimize the electrostatic discharge phenomenon occurring between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) during the manufacturing process of the display device (1). Through this, damage that may occur to various conductive layers and insulating layers of the display device (1) can be minimized, thereby improving the reliability of the display device (1).

[0159] FIG. 10 is a flowchart illustrating a method for manufacturing a display device according to one embodiment. FIG. 11 and FIG. 12 are schematic diagrams illustrating a method for manufacturing a display device according to one embodiment.

[0160] Referring to FIG. 10, a method for manufacturing a display device according to one embodiment may include the step (S11) of patterning a first conductive layer on a substrate, the first conductive layer including a fan-out wiring group including a plurality of fan-out wirings and a signal wiring group including a plurality of signal wirings spaced apart from the fan-out wiring group, and the step (S21) of patterning a second conductive layer on the first conductive layer, the second conductive layer including a connection wiring group including a plurality of connection wirings that electrically connect each fan-out wiring and each signal wiring.

[0161] Referring to FIG. 11 in conjunction with FIG. 10, first, a step (S11) of patterning a first conductive layer on a substrate may be performed, the first conductive layer comprising a fan-out wiring group including a plurality of fan-out wirings and a signal wiring group including a plurality of signal wirings spaced apart from the fan-out wiring group. Here, the substrate may include a first base substrate (110) described above with reference to FIG. 4 and a barrier layer (111) disposed on the first base substrate (110).

[0162] A fan-out wiring group (PLG) may include a plurality of fan-out wirings (PL). For example, a fan-out wiring group (PLG) may include a first fan-out wiring group (PLG1) and a second fan-out wiring group (PLG2) positioned on one side of the first direction (X) of the first fan-out wiring group (PLG1).

[0163] A signal wiring group (DLG) may include a first power wiring (ELVDL), a second power wiring (ELVSL), and a plurality of data wirings (DL). A signal wiring group (DLG) may include a first signal wiring group (DLG1) positioned on one side of the second direction (Y) of a first fan-out wiring group (PLG1), and a second signal wiring group (DLG2) positioned on one side of the second direction (Y) of a second fan-out wiring group (PLG2).

[0164] The spacing (b2) between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) may be greater than the distance between adjacent fan-out wirings (PL) in the first fan-out wiring group (PLG1).

[0165] The description of the fan-out wiring group (PLG) and the signal wiring group (DLG) has been described in detail with reference to FIGS. 2 and FIGS. 5 to 7, so further description will be omitted.

[0166] Referring to FIG. 12 in conjunction with FIG. 10, after the step (S11) of patterning a first conductive layer on a substrate, comprising a fan-out wiring group including a plurality of fan-out wirings and a signal wiring group including a plurality of signal wirings spaced apart from the fan-out wiring group, a step (S21) of patterning a second conductive layer on the first conductive layer, comprising a connection wiring group including a plurality of connection wirings that electrically connect each fan-out wiring and each signal wiring, may be performed.

[0167] The step (S21) of patterning a second conductive layer including a group of connecting wires including a plurality of connecting wires that electrically connect each fan-out wire and each signal wire on the first conductive layer may include the step of patterning a first connecting wire group (CEG1) that electrically connects a first fan-out wire group (PLG1) and a first signal wire group (DLG1) and a second connecting wire group (CEG2) that electrically connects a second fan-out wire (PLG2) and the second signal wire group (DLG2) on the first conductive layer (see '120' in FIG. 4).

[0168] The gap (b2) between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) may be greater than the minimum distance (e2) between the first connection wiring group (CEG1) and the second connection wiring group (CEG2).

[0169] The description of the connecting wiring group (CEG) has been described above with reference to FIGS. 2 and FIGS. 5 to 7, so further description will be omitted.

[0170] According to a method for manufacturing a display device (1) according to one embodiment, a sufficient separation distance is secured between a first fan-out wiring group (PLG1) and a second fan-out wiring group (PLG2) so that the electrostatic discharge phenomenon occurring between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) during the manufacturing process of the display device (1) can be minimized. Through this, damage that may occur to various conductive layers and insulating layers of the display device (1) can be minimized, thereby improving the reliability of the display device (1).

[0171] Hereinafter, another embodiment of the display device (1) will be described. The description of the display device (1) according to the other embodiment described below will omit descriptions that overlap with the display device (1) according to the first embodiment and will focus on the differences.

[0172] FIG. 13 is a partial layout diagram of a display device according to another embodiment.

[0173] Referring to FIG. 13, the display device (1_1) according to the present embodiment differs from the display device (1) according to the first embodiment in that the nth connecting wire (CE(n)_1) of the first connecting wire group (CEG1_1) and the first connecting wire (CE1_1) of the second connecting wire group (CEG2_2) have a shape that extends in one direction.

[0174] In this embodiment, the nth connecting wire (CE(n)_1) of the first connecting wire group (CEG1_1) and the first connecting wire (CE1_1) of the second connecting wire group (CEG2_2) may be arranged to be inclined toward each other. Specifically, the nth connecting wire (CE(n)_1) of the first connecting wire group (CEG1_1) may extend in a direction between one side of the first direction (X) and one side of the second direction (Y). Additionally, the first connecting wire (CE1_1) of the second connecting wire group (CEG2_2) may extend in a direction between the other side of the first direction (X) and one side of the second direction (Y).

[0175] In this embodiment, other connecting wires (CE), excluding the nth connecting wire (CE(n)_1) of the first connecting wire group (CEG1_1) and the first connecting wire (CE1_1) of the second connecting wire group (CEG2_2), may be extended toward the second direction (Y).

[0176] According to the display device (1_1) of the present embodiment, a sufficient separation distance is secured between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) to minimize the electrostatic discharge phenomenon occurring between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) during the manufacturing process of the display device (1). Through this, damage that may occur to various conductive layers and insulating layers of the display device (1) can be minimized, thereby improving the reliability of the display device (1).

[0177] In addition, the display device (1_1) according to the present embodiment includes the nth connecting wire (CE(n)_1) of the first connecting wire group (CEG1_1) having a structure extending in one direction and the first connecting wire (CE1_1) of the second connecting wire group (CEG2_2), so that the connecting wire (CE) can be formed more easily when forming the connecting wire (CE).

[0178] FIG. 14 is a partial layout diagram of a display device according to another embodiment. FIG. 15 is a cross-sectional view taken along XV-XV' of FIG. 14.

[0179] Referring to FIG. 14, the display device (1_2) according to the present embodiment differs from the display device (1) according to the first embodiment in that the nth connecting wire (CE(n)_2) of the first connecting wire group (CEG1_2) and the first connecting wire (CE1_2) of the second connecting wire group (CEG2_2) each include a sub-connecting wire (SCE) extended in one direction, and further include a bridge wire (BE) that electrically connects the sub-connecting wire (SCE).

[0180] In this embodiment, the nth connecting wire (CE(n)_2) of the first connecting wire group (CEG1_2) may include a first sub-connecting wire (SCE1a) and a second sub-connecting wire (SCE1b) that extend in the second direction (Y) and are spaced apart from each other and arranged in an alternating manner. The first sub-connecting wire (SCE1a) and the second sub-connecting wire (SCE1b) may not overlap each other and may be arranged in the first direction (X).

[0181] The first connecting wire (CE1_2) of the second connecting wire group (CEG2_2) may include a third sub-connecting wire (SCE2a) and a fourth sub-connecting wire (SCE2b) that extend in the second direction (Y) and are spaced apart from each other and arranged in an alternating manner. The third sub-connecting wire (SCE2a) and the fourth sub-connecting wire (SCE2b) may be non-interlocked with each other and arranged in the first direction (X).

[0182] The bridge wiring (BE) may include a first bridge wiring (BE1) placed in a first connection wiring group (CEG1_2) and a second bridge wiring (BE2) placed in a second connection wiring group (CEG2_2).

[0183] The other end of the first sub-connecting wire (SCE1a) is electrically connected to the first power wire (ELVSL), and one end may be electrically connected to the first bridge wire (BE1). One end of the second sub-connecting wire (SCE1b) is electrically connected to the nth fan-out wire (PL(n)) of the first fan-out wire group (PLG1), and the other end may be electrically connected to the first bridge wire (BE1). CE1_2)

[0184] The bridge wiring (BE) may have a structure that extends in the first direction (X). The bridge wiring (BE) may be composed of a different conductive layer than the connection wiring group (CEG). For example, the bridge wiring (BE) may be composed of the second conductive layer (140) described above with reference to FIG. 4. That is, the bridge wiring (BE) may be composed of the same conductive layer as the gate electrode (see '141' in FIG. 4). By changing the cross-sectional area or material of the bridge wiring (BE), the resistance of the nth connection wiring (CE(n)_2) of the first connection wiring group (CEG1_2) and the first connection wiring (CE1_2) of the second connection wiring group (CEG2_2) can be varied.

[0185] According to the display device (1_2) of the present embodiment, a sufficient separation distance is secured between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) to minimize the electrostatic discharge phenomenon occurring between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) during the manufacturing process of the display device (1). Through this, damage that may occur to various conductive layers and insulating layers of the display device (1) can be minimized, thereby improving the reliability of the display device (1).

[0186] In addition, the display device (1_2) according to the present embodiment includes a plurality of sub-connecting wires (SCE) in which the nth connecting wire (CE(n)_2) of the first connecting wire group (CEG1_2) and the first connecting wire (CE1_2) of the second connecting wire group (CEG2_2) are each extended in one direction, and each sub-connecting wire (SCE) can adjust the resistance of the nth connecting wire (CE(n)_2) of the first connecting wire group (CEG1_2) and the first connecting wire (CE1_2) of the second connecting wire group (CEG2_2) through a structure in which each sub-connecting wire (SCE) is electrically connected by a bridge wire (BE).

[0187] FIG. 16 is a partial layout diagram of a display device according to another embodiment.

[0188] Referring to FIG. 16, the display device (1_3) according to the present embodiment differs from the display device (1_2) according to FIG. 15 in that the bridge wiring (BE_3) is arranged at an angle. Specifically, in the present embodiment, the bridge wiring (BE_3) of the first connection wiring group (CEG1_3) can be extended in a direction between one side of the first direction (X) and one side of the second direction (Y). Additionally, the bridge wiring (BE_3) of the second connection wiring group (CEG2_3) can be extended in a direction between the other side of the first direction (X) and one side of the second direction (Y).

[0189] According to the display device (1_3) of the present embodiment, a sufficient separation distance is secured between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) to minimize the electrostatic discharge phenomenon occurring between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) during the manufacturing process of the display device (1). Through this, damage that may occur to various conductive layers and insulating layers of the display device (1) can be minimized, thereby improving the reliability of the display device (1).

[0190] In addition, the display device (1_3) according to the present embodiment includes a plurality of sub-connecting wires (SCE) in which the nth connecting wire (CE(n)_3) of the first connecting wire group (CEG1_3) and the first connecting wire (CE1_3) of the second connecting wire group (CEG2_3) are each extended in one direction, and each sub-connecting wire (SCE) can adjust the resistance of the nth connecting wire (CE(n)_3) of the first connecting wire group (CEG1_3) and the first connecting wire (CE1_3) of the second connecting wire group (CEG2_3) through a structure in which each sub-connecting wire (SCE) is electrically connected by a bridge wire (BE).

[0191] FIG. 17 is a partial layout diagram of a display device according to another embodiment.

[0192] Referring to FIG. 17, the display device (1_4) according to the present embodiment differs from the display device (1) according to the first embodiment in that it secures a gap between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) through a connecting wire (CE) with a bent shape.

[0193] In the display device (1_4) according to the present embodiment, the ends of the (n-2) to nth fan-out wirings (PL(n-2), PL(n-1), PL(n)) arranged at the outermost edge of one side of the first direction (X) of the first fan-out wiring group (PLG1) can be aligned in the second direction (Y). The (n-2) to nth fan-out wirings (PL(n-2), PL(n-1), PL(n)) of the first fan-out wiring group (PLG1) can each be electrically connected to one end of the (n-2) to nth connecting wirings (CE(n-2)_4, CE(n-1)_4, CE(n)_4) of the first connecting wiring group (CEG1_4).

[0194] The (n-2) to nth connecting wires (CE(n-2)_4, CE(n-1)_4, CE(n)_4) of the first connecting wire group (CEG1_4) may each have a shape that extends in the direction between one side of the first direction (X) and one side of the second direction (Y), then is bent and extends in the second direction (Y). The spacing between the (n-2) to nth connecting wires (CE(n-2)_4, CE(n-1)_4, CE(n)_4) of the first connecting wire group (CEG1_4) may be constant for each area.

[0195] The other end of the (n-2) to the nth connection wiring (CE(n-2)_4, CE(n-1)_4, CE(n)_4) of the first connection wiring group (CEG1_4) can be electrically connected to the (n-3) and (n-2) data wiring (DL(n-3), DL(n-2)) of the first signal wiring group (DLG1) and the second power wiring (ELVSL), respectively.

[0196] Additionally, the ends of the first to third fan-out wirings (PL1, PL2, PL3) positioned at the outermost edge of the other side of the first direction (X) of the second fan-out wiring group (PLG2) may be aligned in the second direction (Y). The first to third fan-out wirings (PL1, PL2, PL3) of the second fan-out wiring group (PLG2) may each be electrically connected to one end of the first to third connecting wirings (CE1_4, CE2_4, CE3_4) of the second connecting wiring group (CEG2_4).

[0197] The first to third connecting wires (CE1_4, CE2_4, CE3_4) of the second connecting wire group (CEG2_4) may each have a shape that extends in the direction between the other side of the first direction (X) and the one side of the second direction (Y), and then is bent to extend in the second direction (Y). The spacing between the first to third connecting wires (CE1_4, CE2_4, CE3_4) of the second connecting wire group (CEG2_4) may be constant for each area.

[0198] The other ends of the first to third connection wires (CE1_4, CE2_4, CE3_4) of the second connection wire group (CEG2_4) can be electrically connected to the first power wire (ELVDL) and the first and second data wires (DL1, DL2) of the second signal wire group (DLG2), respectively.

[0199] In this embodiment, the 1b dummy electrode (DE1b_4) and the 2a dummy electrode (DE2a_4) may have a shape that exposes the connecting wiring (CE). For example, the 1b dummy electrode (DE1b_4) may have an 'L' shape that overlaps with the first fan-out wiring group (PLG1). The 2a dummy electrode (DE2a_4) may have a symmetrical structure with respect to the 1b dummy electrode (DE1b_4) to overlap with the second fan-out wiring group (PLG2).

[0200] According to the display device (1_4) of the present embodiment, a sufficient separation distance is secured between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) to minimize the electrostatic discharge phenomenon occurring between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) during the manufacturing process of the display device (1_4). Through this, damage that may occur to various conductive layers and insulating layers of the display device (1_4) can be minimized, thereby improving the reliability of the display device (1_4).

[0201] In addition, according to the display device (1_4) of the present embodiment, the length of the fan-out wiring (PL) is reduced and the length of the connecting wiring (CE) is increased, thereby further increasing the distance between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2), which can drastically reduce the electrostatic discharge phenomenon that occurs during the manufacturing process of the display device (1_4).

[0202] FIG. 18 is a partial layout diagram of a display device according to another embodiment.

[0203] Referring to FIG. 18, the display device (1_5) according to the present embodiment differs from the display device (1_4) according to FIG. 17 in that the ends of the (n-2) to nth fan-out wirings (PL(n-2), PL(n-1), PL(n)) arranged at the outermost edge of the first direction (X) of the first fan-out wiring group (PLG1) are aligned in the first direction (X). The (n-2) to nth fan-out wirings (PL(n-2), PL(n-1), PL(n)) of the first fan-out wiring group (PLG1) can each be electrically connected to one end of the (n-2) to nth connecting wirings (CE(n-2)_5, CE(n-1)_5, CE(n)_5) of the first connecting wiring group (CEG1_5).

[0204] Additionally, the ends of the first to third fan-out wirings (PL1, PL2, PL3) positioned at the outermost edge of the other side of the first direction (X) of the second fan-out wiring group (PLG2) may be aligned in the first direction (X). The first to third fan-out wirings (PL1, PL2, PL3) of the second fan-out wiring group (PLG2) may each be electrically connected to one end of the first to third connecting wirings (CE1_5, CE2_5, CE3_5) of the second connecting wiring group (CEG2_5).

[0205] According to the display device (1_5) of the present embodiment, a sufficient separation distance is secured between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) to minimize the electrostatic discharge phenomenon occurring between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) during the manufacturing process of the display device (1_5). Through this, damage that may occur to various conductive layers and insulating layers of the display device (1_5) can be minimized, thereby improving the reliability of the display device (1_5).

[0206] In addition, according to the display device (1_5) of the present embodiment, the length of the fan-out wiring (PL) is reduced and the length of the connecting wiring (CE) is increased, thereby further increasing the distance between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2), which can drastically reduce the electrostatic discharge phenomenon that occurs during the manufacturing process of the display device (1_5).

[0207] FIG. 19 is a partial layout diagram of a display device according to another embodiment.

[0208] Referring to FIG. 19, the display device (1_6) in this embodiment differs from the display device (1_4) according to the embodiment described above with reference to FIG. 17 in that the (n-2) to nth fan-out wiring (PL(n-2), PL(n-1), PL(n)) of the first connection wiring group (CEG1_6), which electrically connects the (n-3) and (n-2) data wiring (DL(n-3), DL(n-2)) of the first signal wiring group (DLG1) and the second power wiring (ELVSL), respectively, each includes a plurality of sub-connection wirings (SCE1a_6, SCE1b_6).

[0209] The sub-connection wiring (SCE1a_6, SCE1b_6) included in the (n-2) to nth connection wirings (CE(n-2)_6, CE(n-1)_6, CE(n)_6) of the first connection wiring group (CEG1_6) may include a first sub-connection wiring (SCE1a_6) connected to the first signal wiring group (DLG1) and a second sub-connection wiring (SCE1b_6) connected to the first fan-out wiring group (PLG1).

[0210] The first sub-connecting wire (SCE1a_6) and the second sub-connecting wire (SCE1b_6) included in the first connecting wire group (CEG1_6) may be made of different conductive layers. For example, the first sub-connecting wire (SCE1a_6) may be made of the second conductive layer (140) described above with reference to FIG. 4, and the second sub-connecting wire (SCE1b_6) may be made of the third conductive layer (150) described above with reference to FIG. 4. Furthermore, conversely, the first sub-connecting wire (SCE1a_6) may be made of the third conductive layer (150), and the second sub-connecting wire (SCE1b_6) may be made of the second conductive layer (140). However, not limited thereto, the first sub-connecting wire (SCE1a_6) and the second sub-connecting wire (SCE1b_6) may be made of different conductive layers within the display device (1_6).

[0211] The firsta sub-connection wiring (SCE1a_6) and the seconda sub-connection wiring (SCE1b_6) included in the first connection wiring group (CEG1_6) can be electrically connected to each other by the first sub-contact hole (CNTa_6).

[0212] In addition, the first to third connecting wires (CE1_6, CE2_6, CE3_6) of the second connecting wire group (CEG2_6), which electrically connect the first to third fan-out wires (PL1, PL2, PL3) positioned at the outermost edge of the first direction (X) of the second fan-out wire group (PLG2) and whose ends are aligned in the second direction (Y), and the first to third data wires (DL1, DL2, DL3) of the second signal wire group (DLG2), are different from the display device (1_4) according to the embodiment described above with reference to FIG. 17 in that they include a plurality of sub-connecting wires (SCE2a_6, SCE2b_6).

[0213] The sub-connection wiring (SCE2a_6, SCE2b_6) included in the first to third connection wirings (CE1_6, CE2_6, CE3_6) of the second connection wiring group (CEG2_6) may include a third sub-connection wiring (SCE2a_6) connected to the second signal wiring group (DLG2) and a fourth sub-connection wiring (SCE2b_6) connected to the first fan-out wiring group (PLG1).

[0214] The third sub-connecting wire (SCE2a_6) and the fourth sub-connecting wire (SCE2b_6) included in the first connecting wire group (CEG2_6) may be made of different conductive layers. For example, the third sub-connecting wire (SCE2a_6) may be made of the second conductive layer (140) described above with reference to FIG. 4, and the fourth sub-connecting wire (SCE2b_6) may be made of the third conductive layer (150) described above with reference to FIG. 4. Furthermore, conversely, the third sub-connecting wire (SCE2a_6) may be made of the third conductive layer (150), and the fourth sub-connecting wire (SCE2b_6) may be made of the second conductive layer (140). However, not limited thereto, the third sub-connecting wire (SCE2a_6) and the fourth sub-connecting wire (SCE2b_6) may be made of different conductive layers within the display device (1_6).

[0215] The third sub-connecting wire (SCE2a_6) and the fourth sub-connecting wire (SCE2b_6) included in the first connecting wire group (CEG2_6) can be electrically connected to each other by the second sub-contact hole (CNTb_6).

[0216] The display device (1_6) according to the present embodiment can vary the resistance of the (n-2) to nth connection wires (CE(n-2)_6, CE(n-1)_6, CE(n)_6) of the first connection wire group (CEG1_6) and the first to third connection wires (CE1_6, CE2_6, CE3_6) of the second connection wire group (CEG2_6) by changing the cross-sectional area or material of the first to fourth sub-connection wires (SCE1a_6, SCE1b_6, SCE2a_6, SCE2b_6).

[0217] According to the display device (1_6) of the present embodiment, a sufficient separation distance is secured between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) to minimize the electrostatic discharge phenomenon occurring between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) during the manufacturing process of the display device (1_6). Through this, damage that may occur to various conductive layers and insulating layers of the display device (1_6) can be minimized, thereby improving the reliability of the display device (1_6).

[0218] In addition, the display device (1_6) according to the present embodiment is composed of different conductive layers and can adjust the resistance of the (n-2) to nth connection wires (CE(n-2)_6, CE(n-1)_6, CE(n)_6) of the first connection wire group (CEG1_6) and the first to third connection wires (CE1_6, CE2_6, CE3_6) of the second connection wire group (CEG2_6) in various ways through the first and second sub-connection wires (SCE1a_6, SCE1b_6) and the third and fourth sub-connection wires (SCE2a_6, SCE2b_6) that are electrically connected through the first and second sub-contact holes (CNTa_6, CNTb_6), respectively.

[0219] FIG. 20 is a partial layout diagram of a display device according to another embodiment.

[0220] Referring to FIG. 20, the display device (1_7) in this embodiment differs from the display device (1_4) according to the embodiment described above with reference to FIG. 17 in that the (n-2) to nth fan-out wiring (PL(n-2), PL(n-1), PL(n)), which is positioned at the outermost edge of one side of the first direction (X) of the first fan-out wiring group (PLG1) and whose ends are aligned in the first direction (X), and the (n-2) to nth connection wiring (CE(n-2)_7, CE(n-1)_7, CE(n)_7) of the first connection wiring group (CEG1_7), which electrically connects the (n-3) and (n-2) data wiring (DL(n-3), DL(n-2)) of the first signal wiring group (DLG1) and the second power wiring (ELVSL), each include a plurality of sub-connection wirings (SCE1a_7, SCE1b_7).

[0221] The sub-connection wiring (SCE1a_7, SCE1b_7) included in the (n-2) to nth connection wirings (CE(n-2)_7, CE(n-1)_7, CE(n)_7) of the first connection wiring group (CEG1_7) may include a first sub-connection wiring (SCE1a_7) connected to the first signal wiring group (DLG1) and a second sub-connection wiring (SCE1b_7) connected to the first fan-out wiring group (PLG1).

[0222] The first sub-connecting wire (SCE1a_7) and the second sub-connecting wire (SCE1b_7) included in the first connecting wire group (CEG1_7) may be made of different conductive layers. For example, the first sub-connecting wire (SCE1a_7) may be made of the second conductive layer (140) described above with reference to FIG. 4, and the second sub-connecting wire (SCE1b_7) may be made of the third conductive layer (150) described above with reference to FIG. 4. Furthermore, conversely, the first sub-connecting wire (SCE1a_7) may be made of the third conductive layer (150), and the second sub-connecting wire (SCE1b_7) may be made of the second conductive layer (140). However, not limited thereto, the first sub-connecting wire (SCE1a_7) and the second sub-connecting wire (SCE1b_7) may be made of different conductive layers within the display device (1_7).

[0223] The firsta sub-connection wiring (SCE1a_7) and the seconda sub-connection wiring (SCE1b_7) included in the first connection wiring group (CEG1_7) can be electrically connected to each other by the first sub-contact hole (CNTa_7).

[0224] In addition, the first to third connecting wires (CE1_7, CE2_7, CE3_7) of the second connecting wire group (CEG2_7), which electrically connect the first to third fan-out wires (PL1, PL2, PL3) positioned at the outermost edge of the other side of the first direction (X) of the second fan-out wire group (PLG2) and whose ends are aligned in the first direction (X), and the first to third data wires (DL1, DL2, DL3) of the second signal wire group (DLG2), are different from the display device (1_4) according to the embodiment described above with reference to FIG. 17 in that they include a plurality of sub-connecting wires (SCE2a_7, SCE2b_7).

[0225] The sub-connection wiring (SCE2a_7, SCE2b_7) included in the first to third connection wirings (CE1_7, CE2_7, CE3_7) of the second connection wiring group (CEG2_7) may include a third sub-connection wiring (SCE2a_7) connected to the second signal wiring group (DLG2) and a fourth sub-connection wiring (SCE2b_7) connected to the first fan-out wiring group (PLG1).

[0226] The third sub-connecting wire (SCE2a_7) and the fourth sub-connecting wire (SCE2b_7) included in the first connecting wire group (CEG2_7) may be made of different conductive layers. For example, the third sub-connecting wire (SCE2a_7) may be made of the second conductive layer (140) described above with reference to FIG. 4, and the fourth sub-connecting wire (SCE2b_7) may be made of the third conductive layer (150) described above with reference to FIG. 4. Furthermore, conversely, the third sub-connecting wire (SCE2a_7) may be made of the third conductive layer (150), and the fourth sub-connecting wire (SCE2b_7) may be made of the second conductive layer (140). However, not limited thereto, the third sub-connecting wire (SCE2a_7) and the fourth sub-connecting wire (SCE2b_7) may be made of different conductive layers within the display device (1_7).

[0227] The third sub-connecting wire (SCE2a_7) and the fourth sub-connecting wire (SCE2b_7) included in the first connecting wire group (CEG2_7) can be electrically connected to each other by the second sub-contact hole (CNTb_7).

[0228] The display device (1_7) according to the present embodiment can vary the resistance of the (n-2) to nth connection wires (CE(n-2)_7, CE(n-1)_7, CE(n)_7) of the first connection wire group (CEG1_7) and the first to third connection wires (CE1_7, CE2_7, CE3_7) of the second connection wire group (CEG2_7) by changing the cross-sectional area or material of the first to fourth sub-connection wires (SCE1a_7, SCE1b_7, SCE2a_7, SCE2b_7).

[0229] According to the display device (1_7) of the present embodiment, a sufficient separation distance is secured between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) to minimize the electrostatic discharge phenomenon occurring between the first fan-out wiring group (PLG1) and the second fan-out wiring group (PLG2) during the manufacturing process of the display device (1_7). Through this, damage that may occur to various conductive layers and insulating layers of the display device (1_7) can be minimized, thereby improving the reliability of the display device (1_7).

[0230] In addition, the display device (1_7) according to the present embodiment is composed of different conductive layers and can adjust the resistance of the (n-2) to nth connection wires (CE(n-2)_7, CE(n-1)_7, CE(n)_7) of the first connection wire group (CEG1_7) and the first to third connection wires (CE1_7, CE2_7, CE3_7) of the second connection wire group (CEG2_7) in various ways through the first and second sub-connection wires (SCE1a_7, SCE1b_7) and the third and fourth sub-connection wires (SCE2a_7, SCE2b_7) that are electrically connected through the first and second sub-contact holes (CNTa_7, CNTb_7), respectively.

[0231] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0232] 1: Display device 10: Display panel PD: Pad PLG: Fan-out wiring group CEG: Connection Wiring Group DLG: Signal Wiring Group

Claims

Claim 1 A substrate; a plurality of fan-out wirings disposed on the substrate; a plurality of signal wirings disposed on the substrate and spaced apart from the fan-out wirings; and includes a plurality of connecting wires connecting each of the above fan-out wires and each of the above signal wires, wherein the plurality of connecting wires are located on a different layer from the plurality of fan-out wires and the plurality of signal wires, and the plurality of fan-out wires include a plurality of first fan-out wires belonging to a first fan-out group and a plurality of second fan-out wires belonging to a second fan-out group, and the first fan-out group and the second fan-out group are adjacent to each other, and the distance between the outermost first fan-out wire located closest to the second fan-out group in the first fan-out group and the outermost second fan-out wire located closest to the first fan-out group in the second fan-out group is greater than the distance between the signal wires to which the outermost first fan-out wire and the outermost second fan-out wire are respectively connected, and the first fan-out group further includes an outermost first-1 fan-out wire located farthest from the second fan-out group, and the plurality of connecting wires include an outermost first connecting wire connecting the outermost first fan-out wire and the signal wire and the outermost first-1 fan-out wire and A display device comprising an outermost first-1 connecting wire connecting the signal wires, wherein the outermost first connecting wire and the outermost first-1 connecting wire each include a bent portion, and among the plurality of connecting wires, at least one of the plurality of connecting wires located between the outermost first connecting wire and the outermost first-1 connecting wire has a straight shape extending along a first direction. Claim 2 A display device according to claim 1, wherein the distance between the outermost first fan-out wiring and the outermost second fan-out wiring is greater than the distance between the first fan-out wirings adjacent to each other in the first fan-out group. Claim 3 A display device according to claim 1, wherein the distance between the outermost first fan-out wiring and the outermost second fan-out wiring is greater than or equal to the distance between the connecting wirings to which the outermost first fan-out wiring and the outermost first fan-out wiring are respectively connected. Claim 4 A display device according to claim 1, wherein the distance between the first fan-out wires that are adjacent to each other and positioned at the outermost edge of the first fan-out group is less than or equal to the distance between the first fan-out wires that are adjacent to each other in the first fan-out group. Claim 5 A display device according to claim 1, wherein the plurality of connecting wires includes a plurality of first connecting wires that electrically connect the plurality of first fan-out wires and the signal wires, and a plurality of second connecting wires that electrically connect the second fan-out wires and the signal wires. Claim 6 A display device according to claim 5, wherein the first connecting wiring comprises a first sub-connecting wiring electrically connected to the first fan-out wiring, a second sub-connecting wiring electrically connected to the signal wiring, and a third sub-connecting wiring electrically connecting the first sub-connecting wiring and the second sub-connecting wiring to each other. Claim 7 In claim 6, the third sub-connecting wire extends in a first direction, and the first sub-connecting wire and the second sub-connecting wire extend in a second direction different from the first direction, a display device. Claim 8 A display device according to claim 5, wherein the distance between the outermost first fan-out wiring and the outermost second fan-out wiring is greater than the distance between the first connecting wiring and the second connecting wiring to which the outermost first fan-out wiring and the outermost second fan-out wiring are respectively connected. Claim 9 In claim 5, the ends of at least two adjacent first fan-out wires in the first fan-out group are aligned along the extension direction of the signal wires. Claim 10 A substrate; a first conductive layer disposed on the substrate and comprising: a first fan-out group including a plurality of first fan-out wirings; a second fan-out group including a plurality of second fan-out wirings disposed on one side of a first direction of the first fan-out group; a first signal group including a plurality of first signal wirings disposed separated and spaced apart from the first fan-out group in a second direction intersecting the first direction; and a second signal group including a plurality of second signal wirings separated and spaced apart from the second fan-out group in the second direction. and a second conductive layer disposed on the first conductive layer, comprising a plurality of first connecting wires electrically connecting the plurality of first fan-out wires and the plurality of first signal wires, and a plurality of second connecting wires electrically connecting the plurality of second fan-out wires and the plurality of second signal wires, wherein the first conductive layer and the second conductive layer are located on different layers, and the distance between the first fan-out group and the second fan-out group is greater than the distance between the first connecting wire and the second connecting wire, and the plurality of first connecting wires include an outermost first connecting wire located closest to any one of the plurality of second connecting wires and an outermost first-1 connecting wire located farthest from any one of the plurality of second connecting wires, wherein the outermost first connecting wire and the outermost first-1 connecting wire each include a bent portion, and among the plurality of first connecting wires, at least one of the plurality of first connecting wires located between the outermost first connecting wire and the outermost first-1 connecting wire has a straight shape extending along the second direction. A display device having. Claim 11 A display device according to claim 10, wherein the distance between the first fan-out group and the second fan-out group is greater than the distance between the first signal group and the second signal group. Claim 12 A display device according to claim 10, wherein the distance between the first fan-out group and the second fan-out group is greater than the distance between the first fan-out wires adjacent to each other in the first fan-out group. Claim 13 In claim 10, a display device in which the distance between the first fan-out group and the second fan-out group is greater than or equal to the distance between the first signal group and the first fan-out group. Claim 14 A display device according to claim 10, wherein the distance between two adjacent first fan-out wires positioned at the outermost edge of the first fan-out group is less than or equal to the distance between adjacent first fan-out wires in the first fan-out group. Claim 15 A display device according to claim 10, wherein the first connecting wire comprises a first sub-connecting wire electrically connected to the first fan-out wire and a second sub-connecting wire electrically connected to the first signal wire, and further comprises a third conductive layer disposed between the first conductive layer and the second conductive layer and comprising a third connecting wire that mutually electrically connects the first sub-connecting wire and the second sub-connecting wire. Claim 16 In claim 15, the first sub-connecting wiring and the second sub-connecting wiring extend in the second direction, and the third connecting wiring extends in the first direction, forming a display device. Claim 17 In claim 10, at least two ends of the first fan-out wiring in the first fan-out group are aligned along the second direction in the display device. Claim 18 A substrate; a plurality of fan-out wirings disposed on the substrate; a plurality of signal wirings disposed on the substrate and spaced apart from the fan-out wirings; and includes a plurality of connecting wires connecting each of the above fan-out wires and each of the above signal wires, wherein the plurality of connecting wires are located on a different layer from the plurality of fan-out wires and the plurality of signal wires, and the plurality of fan-out wires include a plurality of first fan-out wires belonging to a first fan-out group and a plurality of second fan-out wires belonging to a second fan-out group adjacent to the first fan-out group, the plurality of first fan-out wires include an outermost first fan-out wire located closest to the second fan-out group in the first fan-out group, and the plurality of second fan-out wires include an outermost second fan-out wire located closest to the first fan-out group in the second fan-out group, and the plurality of signal wires include an outermost first signal wire electrically connected to the outermost first fan-out wire and an outermost second signal wire electrically connected to the outermost second fan-out wire, and the plurality of connecting wires include an outermost first connecting wire connecting the outermost first fan-out wire and the outermost first signal wire, and the outermost second It includes an outermost second connection wiring that connects the fan-out wiring and the outermost second signal wiring, wherein the outermost first connection wiring includes a first sub-connection wiring connected to the outermost first fan-out wiring, a second sub-connection wiring connected to the outermost first signal wiring, and a third sub-connection wiring that interconnects the first sub-connection wiring and the second sub-connection wiring, and the outermost second connection wiring includes a fourth sub-connection wiring connected to the outermost second fan-out wiring, a fifth sub-connection wiring connected to the outermost second signal wiring, and a sixth sub-connection wiring that interconnects the fourth sub-connection wiring and the fifth sub-connection wiring.A display device wherein the distance between the first sub-connecting wire and the fourth sub-connecting wire is greater than the distance between the second sub-connecting wire and the fifth sub-connecting wire, and the plurality of first fan-out wires further include an outermost first-1 fan-out wire located furthest from the second fan-out group in the first fan-out group, the plurality of signal wires further include an outermost first-1 signal wire electrically connected to the outermost first-1 fan-out wire, and the plurality of connecting wires further include an outermost first-1 connecting wire connecting the outermost first-1 fan-out wire and the outermost first-1 signal wire, wherein, among the plurality of connecting wires, at least one of the plurality of connecting wires located between the outermost first connecting wire and the outermost first-1 connecting wire has a straight shape extending along a first direction. Claim 19 In claim 18, the third sub-connecting wire extends in a second direction different from the first direction, and the first sub-connecting wire and the second sub-connecting wire extend in the first direction. Claim 20 A display device according to claim 18, wherein the first sub-connecting wiring and the second sub-connecting wiring are disposed in a first conductive layer, and the third sub-connecting wiring is disposed in a second conductive layer different from the first conductive layer.

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