IC die and heat spreaders with solderable thermal interface structures for multi-chip assemblies including solder array thermal interconnects

Abstract

Thermal diffusers and / or IC dies having solderable thermal structures can be assembled together with solder array thermal interconnects. The thermal diffuser may include one or more metallized surfaces suitable for bonding to a non-metallic material and a solder alloy used as a thermal interface material between the thermal diffuser and the IC die. The IC die may include a metallized back surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. The metallization on the IC die and / or thermal diffuser may include a plurality of solderable structures. A multi-chip package may include a plurality of IC dies having different die thicknesses accommodated by z-height thickness variations in the thermal interconnects and / or solderable structures of the IC die or thermal diffuser.

Description

Technology Field

[0001] Related applications

[0002] This application relates to the U.S. patent application filed on March 26, 2020, with attorney case number 01.AC3750-US and titled “IC DIE AND HEAT SPREADERS WITH SOLDERABLE THERMAL INTERFACE STRUCTURES FOR ASSEMBLIES INCLUDING SOLDER ARRAY THERMAL INTERCONNECTS”. This application also relates to the U.S. patent application filed on March 26, 2020, with attorney case number 01.AC7952-US and titled "IC DIE WITH SOLDERABLE THERMAL INTERFACE STRUCTURES FOR ASSEMBLIES INCLUDING SOLDER ARRAY THERMAL INTERCONNECTS". Background Technology

[0003] Addressing warping is one of the major challenges in the manufacturing of thin integrated circuit (IC) device packages. Differences in the coefficient of thermal expansion (CTE) between device and package materials can lead to warping issues. Thin form-factor packages without an integrated heat spreader (IHS) may experience progressive pump-out of the thermal interface material (TIM) between the IC die, IHS, and / or system-level heat sink or heat pipe. This pump-out can be attributed to changes in die surface curvature as the die cycles between a cold phase and a hot phase during compute system operation. As the TIM pumps out, the thermal performance of the IC device deteriorates, limiting the performance and / or lifespan of the computing system.

[0004] The thermal performance of IC devices also decreases as the TIM thickness increases. Variations in die thickness, as well as variations in the height of first-level interconnects (e.g., solder), can cause changes in step height between adjacent dies in a multi-chip package (MCP). Often, these step height changes are accommodated by the TIM, and consequently, the TIM may be configured to be thicker on thinner IC dies than on thicker IC dies.

[0005] Therefore, IC die and thermal diffuser structures capable of solving one or more of these problems will be commercially advantageous. Brief explanation of the drawing

[0006] The materials described herein are illustrated in the accompanying drawings by example rather than by limitation. For the sake of clarity, the elements depicted in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Additionally, where deemed appropriate, reference labels have been repeated between the drawings to indicate corresponding or similar elements. In the drawings: FIG. 1 is a flowchart illustrating methods for fabricating thermal interconnect structures on an IC die surface and / or a thermal diffuser and assembling them into a solder array TIM according to some embodiments. FIGS. 2A, 2B, 2C, 2D, 2E, and 2F illustrate exploded isometric views of system-level IC device assemblies according to some embodiments. FIG. 3a is a flowchart illustrating methods for manufacturing thermal interconnect interface structures on the surface of an IC die according to some embodiments. FIG. 3b is a flowchart illustrating methods for applying solder TIM to thermal interconnect interface structures on the surface of an IC die according to some embodiments. FIG. 4a illustrates cross-sectional views of thermal interconnect interface structures developed during the implementation of the methods of FIG. 3a and FIG. 3b according to some embodiments. FIG. 4b illustrates a plan view of thermal interconnect interface structures on the surface of an IC die according to some embodiments. FIG. 5a illustrates cross-sectional views of thermal interconnect interface structures developed during the implementation of the methods of FIG. 3a and FIG. 3b according to some embodiments. FIG. 5b illustrates a top view of thermal interconnect interface structures on the surface of an IC die according to some alternative embodiments. FIG. 6 is a flowchart illustrating methods for manufacturing thermal interconnect interface structures on an IC die according to some alternative embodiments. FIG. 7 illustrates cross-sectional views of thermal interconnect interface structures developed during the implementation of the methods of FIG. 6 according to some alternative embodiments. FIG. 8a is a flowchart illustrating methods for manufacturing thermal interconnect interface structures on a thermal diffuser sheet according to some embodiments. FIG. 8b is a flowchart illustrating methods for applying a solder array TIM to thermal interconnect interface structures on a thermal diffuser according to some embodiments. FIG. 9a illustrates cross-sectional views of thermal interconnect interface structures that develop during the implementation of the methods of FIG. 8a and FIG. 8b according to some embodiments. FIG. 9b illustrates a plan view of thermal interconnect interface structures on a thermal diffuser according to some embodiments. FIG. 10a illustrates cross-sectional views of thermal interconnect interface structures developed during the implementation of the methods of FIG. 8a and FIG. 8b according to some alternative embodiments. FIG. 10b illustrates a plan view of thermal interconnect interface structures on a thermal diffuser according to some alternative embodiments. FIG. 11 is a flowchart illustrating methods for manufacturing thermal interconnect interface structures on a thermal diffuser according to some alternative embodiments. FIG. 12a illustrates cross-sectional views of thermal interconnect interface structures developed during the implementation of the methods of FIG. 11 according to some embodiments. FIG. 12b illustrates cross-sectional views of thermal interconnect interface structures developed during the implementation of the methods of FIG. 11 according to some alternative embodiments. FIG. 13 is a flowchart illustrating methods for assembling a thermal diffuser and an IC die with a solder array TIM according to some alternative embodiments. FIG. 14a is a plan view of thermal interconnect interface structures on the surface of an IC die assembly according to some embodiments. FIG. 14b illustrates cross-sectional views of thermal interconnect interface structures joined by a solder array TIM during the implementation of the methods of FIG. 13 according to some embodiments. FIG. 14c is a plan view of thermal interconnects on thermal interconnect interface structures of an IC die assembly according to some alternative embodiments. FIG. 14d illustrates cross-sectional views of thermal interconnect interface structures joined by solder thermal interconnects during the implementation of the methods of FIG. 13 according to some alternative embodiments. FIGS. 15a, 15b, 15c and 15d illustrate cross-sectional views of IC die assemblies according to some embodiments. FIG. 16 illustrates a cross-sectional view of a system-level IC device assembly according to some embodiments. FIG. 17 illustrates a mobile computing platform and a data server machine utilizing an integrated circuit package including thermal interconnect interface structures and a solder array TIM according to some embodiments. FIG. 18 is a functional block diagram of an electronic computing device according to some embodiments. Specific details for implementing the invention

[0007] One or more embodiments are described with reference to the accompanying drawings. Specific configurations and arrangements are illustrated and discussed in detail, but it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of this description. It will be apparent to those skilled in the art that the technologies and / or arrangements described herein may be used in various other systems and applications other than those described in detail herein.

[0008] In the following detailed description, reference is made to the accompanying drawings, which form part of the description and illustrate exemplary embodiments. It should also be understood that other embodiments may be used and structural and / or logical modifications may be made without departing from the scope of the claimed subject matter. Additionally, it should be noted that directions and references, e.g., up, down, upper, lower, etc., may be used merely to facilitate the description of features in the drawings. Accordingly, the following detailed description should not be construed as limiting, and the scope of the claimed subject matter is defined only by the appended claims and their equivalents.

[0009] In the following description, numerous details are provided. However, it will be apparent to those skilled in the art that the present invention can be practiced without these specific details. In some instances, to avoid obscuring the present invention, known methods and devices are depicted in block diagram form rather than in detail. References to "examples" or "one embodiment" throughout this specification mean that specific features, structures, functions, or characteristics described in relation to such embodiments are included in at least one embodiment of the present invention. Accordingly, appearances of phrases such as "in examples" or "in some embodiments" throughout this specification do not necessarily refer to the same embodiment of the present invention. Furthermore, specific features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, two embodiments may be combined if the specific features, structures, functions, or characteristics associated with the first and second embodiments are not mutually exclusive.

[0010] As used in the description of the invention and in the appended claims, singular forms (“a,” “an,” and “the”) are intended to include plural forms unless the context clearly indicates otherwise. It will also be understood that the term “and / or,” as used herein, refers to and includes any and all possible combinations of one or more of the associated enumerated items.

[0011] The terms “coupled” and “connected,” along with their derivatives, may be used in this specification to describe functional or structural relationships between components. It should be understood that these terms are not intended to be synonyms for one another. Rather, in certain embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intervening elements between them) and / or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship).

[0012] The terms “over,” “under,” “between,” and “on,” as used herein, refer to the relative positions of one component or material with respect to other components or materials where such physical relationships are notable. For example, in the context of materials, another material placed on or under one material may be in direct contact or may have one or more interposed materials. Furthermore, one material placed between two materials may be in direct contact with two layers or may have one or more interposed layers. In contrast, a first material or material “on” a second material or material is in direct contact with the second material / material. Similar distinctions should be made in the context of component assemblies.

[0013] As used throughout this description and in the claims, a list of items linked by the terms “at least one of” or “one or more of” may mean any combination of the listed items. For example, the phrase “at least one of A, B or C” may mean A; B; C; A and B, A and C; B and C; or A, B and C.

[0014] According to some embodiments of this specification, a plurality of solderable thermal interface structures are fabricated on a thermal diffuser and / or on the back surface of an IC die. Subsequently, the thermal diffuser and the IC die can be assembled together with a plurality of thermal interconnects comprising solder. Such solder thermal interface materials (TIMs) can be distributed over the area of ​​the thermal diffuser and / or the IC die by patterning the thermal interconnect interface structures. The integrated thermal diffuser may comprise a non-metallic material such as a graphite sheet or other carbon-based preform. One or more surfaces of the non-metallic material may be metallized, and thermal interconnect interface structures may be formed on one or more surfaces. The IC die may comprise a metallized back surface suitable for bonding with thermal interconnects comprising solder alloys. The thickness of the thermal interconnects and / or the thickness of the solderable thermal interconnect interface structures may vary across the area of ​​the thermal diffuser to accommodate a plurality of IC die thicknesses associated with various IC dies of a multi-chip package.

[0015] As further described below, solderable thermal interconnect interface structures can be manufactured by patterning a metal layer of a thermal diffuser. Solderable thermal interconnect interface structures can also be manufactured by patterning a metal layer on the back surface of an IC die. In other embodiments, solderable thermal interconnect interface structures can be manufactured by additionally depositing mask material and / or metal on optional areas on the back surface of an IC die or a thermal diffuser.

[0016] By applying one or more of the techniques described below, the thickness (i.e., z-height) of the thermal diffuser and / or the thickness of the thermal interconnects between the thermal diffuser and the IC die can be reduced to less than 100 µm each. These low thicknesses are suitable for thin IC device assembly applications, and the thermal resistance is also significantly reduced below the thermal resistance of assemblies with significantly greater thickness.

[0017] FIG. 1 is a flowchart illustrating methods (101) for manufacturing solderable thermal interconnect interface structures on an IC die surface and / or a thermal diffuser sheet according to some embodiments and assembling them into a plurality of thermal interconnects including a solder TIM.

[0018] In methods (101), a heat diffuser preform is received as a first input (110). The preform may be any material having sufficient mechanical strength (e.g., elastic modulus) and sufficient thermal conductivity (K). As further described below, the heat diffuser preform may comprise a metal sheet or a non-metal sheet. The non-metal sheet may be a composite containing a filler material within a matrix material, or a sheet of substantially homogeneous carbon-based material. In some exemplary embodiments, the homogeneous carbon-based material is graphite, which may advantageously be a pyrolytic graphite sheet (PGS) having high thermal in-plane conductivity (e.g., >1700 W / mK).

[0019] Methods (101) are continued in block 120, where a plurality of solderable metal features are fabricated on a thermal diffuser. These features must be spaced apart over areas of the thermal diffuser so that each provides discrete interfaces to a plurality of thermal interconnects containing a solder TIM. These features may interface the solder TIM to a preform of a non-metallic composition (e.g., PGS) or any other composition having relatively poor solder wettability. These features may also be fabricated to have multiple z-heights across different areas of the thermal diffuser so that a thermal diffuser preform of substantially uniform thickness can span across multiple IC dies of different z-heights. As further described below, cut-and-add techniques may be applied to fabricate these solderable metal features.

[0020] Methods (101) continue in block 130, where a plurality of solder TIM thermal interconnects are applied to the surface of a prepared thermal diffuser. In block 130, any solder TIM composition known to be suitable as a thermal interconnect between an IC die and a thermal diffuser may be applied. When an array of solder TIM thermal interconnects is applied, the resulting thermal diffuser may be staged for subsequent assembly with one or more IC dies. In some embodiments, an underfill / overfill material may be applied prior to assembly with the IC die to at least partially surround the plurality of solder TIM thermal interconnects. This material may have any composition known to be suitable as a solder feature underfill. Noting that some materials may degrade over time, unless the pre-applied material can be reliably B-staged, the underfill may instead be applied during assembly with the IC die and the thermal diffuser in block 180.

[0021] In methods (101), an IC die is received as a second input (140). The received IC die may be any IC die having a first side (front) comprising an integrated circuit comprising transistors coupled to one or more metallization levels terminated at a plurality of interfaces suitable for connecting to a host component (e.g., a package substrate) through any first-level electrical interconnects, such as solder features (e.g., microbumps, etc.). The IC die received at the input (140) may be in a wafer format or a panelized format, and thus subsequent operations may be performed at the wafer level or the panel level. Alternatively, a package assembly may be received as a third input (150). The package assembly received at the input (140) may include one or more IC dies. The front sides of the IC die are electrically interconnected to the package substrate, and the back side of the IC die is exposed and prepared to perform additional processing at the package level.

[0022] Continuing from input (140 or 150), in block 160, a plurality of solderable metal features are fabricated on the second side (back side) of the IC die. These features must be spaced apart over an area of ​​the IC die so that each provides discrete interfaces to a plurality of thermal interconnects containing a solder TIM. These features can interface the solder TIM to a crystalline substrate of the IC die (e.g., crystalline silicon, germanium, Group IV alloy, III-V alloy, III-N alloy, etc.). These features can be fabricated to have any z-height. As further described below, these solderable metal features can be fabricated by applying reduction and addition techniques while the die is in a wafer / panel format or during the packaging of the die.

[0023] Methods (101) continue in block 170, where a plurality of solder TIM thermal interconnects are applied to the surface of a prepared IC die. In block 170, any solder TIM composition known to be suitable as a thermal interconnect between the IC die and a thermal diffuser may be applied. When an array of solder TIM thermal interconnects is applied, the resulting IC die may be staged for subsequent assembly with a thermal diffuser and / or a package substrate. In some embodiments, an underfill / overfill material may be pre-applied to at least partially surround the plurality of solder TIM thermal interconnects. This material may have any composition known to be suitable as a solder feature underfill. Noting that some materials may degrade over time, unless the pre-applied material can be reliably B-staged, the underfill may instead be applied during the assembly of the IC die and the thermal diffuser in block 180.

[0024] Methods (101) continue in block 180, where a heat diffuser is assembled to the back surface of an IC die. In some embodiments, both the heat diffuser and the IC die are output from blocks 130 and 170, respectively. In other embodiments, at least one of the IC heat diffuser and the IC die is prepared through blocks 130 and 170, respectively. For example, a heat diffuser prepared according to blocks 120 and 130 can be assembled with an IC die having any surface preparation in block 180. In other examples, an IC die back surface prepared according to blocks 160 and 170 can be assembled with any IC die heat diffuser in block 180. In yet other examples, a heat diffuser prepared according to blocks 120 and 130 is assembled with an IC die having a back surface prepared according to blocks 160 and 170.

[0025] Subsequently, the methods (101) end at an output (190) in which the IC die-heat diffuser assembly is integrated into any suitable upper-level assembly. In some embodiments, the IC die of the assembly is coupled to a package substrate via any first-level electrical interconnects known to be suitable. In some other embodiments, the package substrate is coupled to a host component, such as a printed circuit board, via any second-level electrical interconnects known to be suitable, for example. In some additional embodiments, the heat diffuser is coupled to a heat exchanger, such as a finned heat sink, heat pipe, vapor chamber, etc.

[0026] FIGS. 2a through 2f illustrate exploded isometric views of some exemplary system-level IC device assemblies that can be manufactured through the implementation of methods (101). While the system-level assemblies illustrated in FIGS. 2a through 2f serve to further illustrate various structural features associated with one or more advantageous embodiments, such assemblies may be manufactured according to methods other than those illustrated in FIGS. 2a through 2f. Similarly, methods (101) may also be implemented to obtain assemblies other than those illustrated in FIGS. 2a through 2f. As further described below, the assemblies illustrated in FIGS. 2a-2f can advantageously facilitate spatial distribution of multiple solder TIM thermal interconnects between an IC die and a thermal spreader, allowing such thermal interconnects to have a minimum z-height (thickness) and / or enabling a substantially flat sheet material of high in-plane thermal conductivity to thermally bond to multiple IC dies of different die thicknesses.

[0027] FIGS. 2a-2b illustrate some exemplary assemblies in which a thermal diffuser is integrated with a plurality of IC dies having surfaces prepared by the methods (101). First, referring to FIG. 2a, an IC device assembly (201) comprises a package substrate (220) which may be any package substrate (or "package") suitable for interfacing a host component (299) to one or more IC dies. The device assembly (201) comprises a multi-chip package including both an IC die (205) and an IC die (210) laterally adjacent to the IC die (205). The active surface of each IC die (205, 210) comprises an integrated circuit having die interfaces attached to the package substrate (220) via a plurality of first-level electrical interconnects (208). The first-level interconnects (208) may be, for example, microbumps suitable for a flip-chip assembly or any other solder-based or solder-free interconnects.

[0028] Each of the IC dies (205, 210) may have been prepared and electrically tested, for example, according to any suitable manufacturing, die preparation, and e-test processes. For example, the IC die (205) may be the first of any of a wireless radio circuit, a microprocessor or graphics processor circuit, an electronic memory circuit, a floating-point gate array (FPGA), a power management and / or power supply circuit, or a MEMS device. As an additional example, the IC die (210) may be the second of any of a wireless radio circuit, a microprocessor or graphics processor circuit, an electronic memory circuit, an FPGA, a power management and / or power supply circuit, or a MEMS device. In some specific examples, the IC die (205) is a microprocessor and the IC die (210) is an electronic memory. One or more of the IC dies (205, 210) may include an IC die stack. For example, the electronic memory may include a stack of IC dies. For the sake of discussion, two IC dies are shown, but any number of IC dies may be interfaced to the package substrate (220). In some embodiments, the IC dies attached to the package substrate (220) have different die thicknesses (e.g., z-dimensions). In the case of the examples illustrated by FIG. 2a, the IC die (210) is significantly thicker than the IC die (205) (e.g., greater than 50 µm and may be 250-500 µm thicker).

[0029] The package substrate (220) may comprise any type of substrate suitable for providing electrical communication between the IC die (205) or IC die (210) and to a next-level host component (299) to which the package substrate (220) can be coupled (e.g., via second-level electrical interconnects). The host component (299) may be, for example, a circuit board or another package level. The package substrate (220) may also provide structural support for the IC die (205, 210). As further described below, the package substrate may be a multilayer structure comprising levels of package metallization and layers of package dielectric material continuously accumulated around a core. The package core may be, for example, a dielectric material and may further comprise conductive through-via structures. In other embodiments, the package substrate (220) may comprise a coreless multilayer structure, in which case through-via structures may or may not be present.

[0030] As further illustrated in FIG. 2a, a structural member (225) is attached to a package substrate (220). The package substrate (220) may have a relatively low elastic modulus and thus may deform extensively when subjected to stress such as that given through thermal expansion. The structural member (225) may be any material and may have any dimensions suitable for improving package strength and / or controlling package warping in other ways. Thus, the structural member (225) may be any material having a greater elastic modulus (greater strength) than the package substrate (220). The structural member (225) may include bulk metal (e.g., steel, stainless steel, aluminum, etc.) and may also have a surface finish (e.g., nickel, etc.).

[0031] In the illustrated embodiments, a plurality of thermal interconnect interface structures (230) are spaced apart over an area on the back surface of the IC die (205). The back surface of the IC die (210) similarly includes a plurality of thermal interconnect interface structures (240) spaced apart over an area on the IC die (210). In exemplary embodiments, each of the thermal interconnect interface structures (230, 240) comprises one or more metals having a surface finish of the thermal interconnect interface structures (230, 240) having a solderable composition. Accordingly, the thermal interconnect interface structures (230, 240) may be referred to herein as "thermal interconnect lands," and because at least the surface finish is metal, the thermal interconnect interface structures (230, 240) may also be referred to herein as "metal lands." The thermal interconnect interface structures (230, 240) may have any dimensions and / or feature pitch. In some embodiments, the thermal interconnect interface structures (230, 240) have a feature pitch substantially equal to the feature pitch of the features on the front surface of the IC die (205, 210) coupled to the first level electrical interconnect (208). In other embodiments, the thermal interconnect interface structures (230, 240) may have a feature pitch significantly larger than the feature pitch of the features on the front surface of the IC die (205, 210). As further described below, the thickness (e.g., z-dimension) of the thermal interconnect interface structures (230, 240) may vary significantly.

[0032] As further illustrated in FIG. 2a, individual thermal interconnect interfaces among the thermal interconnect interfaces (230) are joined or bonded to corresponding thermal interconnects among the plurality of thermal interconnects (250). Similarly, individual thermal interconnect interfaces among the thermal interconnect interfaces (240) are joined or bonded to corresponding thermal interconnects among the plurality of thermal interconnects (260). Both of the thermal interconnects (250, 260) are solder TIMs comprising a metal alloy composition having a sufficiently low melting temperature to form an intermetallic compound with the interconnect interfaces (230, 240) to form, for example, a good thermal joint. Since the application of solder TIM can be difficult due to the strict process controls required to form good thermal joints, the presence of discrete thermal interconnect interface structures (230, 240) can have advantages over a continuous metal layer spanning the entire area of ​​the IC dies (205, 210).

[0033] In the illustrated example, the thermal interconnects (250, 260) may have substantially the same solder alloy composition, but their dimensions (e.g., radius and / or diameter, pitch and / or z-height) may differ. In some embodiments, individual thermal interconnects among the thermal interconnects (250) have larger lateral and / or vertical dimensions than individual thermal interconnects among the thermal interconnects (260). The target vertical dimension of the thermal interconnects (250) may be larger than the target dimension of the thermal interconnects (260) by an amount that fully accommodates the amount of the die thickness of the IC die (205) being smaller than the die thickness of the IC die (210). Thus, the feature pitch of the thermal interconnect interfaces (230) may be larger than the feature pitch of the thermal interconnect interfaces (240).

[0034] Although not illustrated for clarity, the IC device assembly (201) may further include an underfill material between individual thermal interconnects among the thermal interconnects (250, 260). Such underfill material may have any suitable composition (e.g., a polymer dielectric containing an epoxy resin having a filler such as fumigated silica). The epoxy resin and filler may be selected to achieve a good coefficient of thermal expansion (CTE) match with the thermal interconnects (250, 260) and / or the IC die (205, 210).

[0035] The IC device assembly (201) further comprises an integrated thermal diffuser (275). The thermal diffuser (275) may be made of one or more materials having sufficient thermal conductivity and may have any thickness suitable for providing sufficient strength and / or protection to the lower IC die (205, 210). Any thermal diffuser (275) architecture compatible with thermal interconnects (250, 260) may be used, but in the illustrated embodiments, the thermal diffuser (275) has a stacked architecture comprising a sheet material (271) and a solderable metal (272) between the sheet material (271) and a plurality of thermal interconnects (250, 260). The solderable metal (272) may be any metal having suitable solder TIM wettability. In some embodiments, the solderable metal (272) may comprise at least one of Cu, W, Ti, Ru, or Co and may further comprise a surface finish such as, but not limited to, Ni and / or Au. The thickness of the solderable metal (272) can vary significantly. In some embodiments, the solderable metal (272) has a thickness of less than 100 µm and may be less than 25 µm (e.g., 15-25 µm). This limited thickness is advantageous for reducing the thermal resistance of the thermal diffuser (275). In the embodiments illustrated in FIG. 2a, the solderable metal (272) is a continuous layer covering at least most of the sheet material (271), possibly substantially the entire area. One or more of the underfill material or thermal interconnect interfaces (230, 240) may serve to contain / retain any desired spatial arrangement of the thermal interconnects (250, 260). By this inclusion, the total z-height of individual thermal interconnects among the thermal interconnects (250, 260) can be minimized to a bond line thickness (BLT) of less than 100 μm even if the interconnects are bonded to a continuous sheet of solderable metal (272).This BLT is significantly smaller than the 200-300 µm BLT that can occur when the solder TIM is simply allowed to form a continuous pool on individual IC dies (205, 210).

[0036] As illustrated in FIG. 2a, the sheet material (271) may be substantially flat. In the presence of a solderable metal (272), the sheet material (271) may have a wide range of compositions, such as other metals or non-metal materials (e.g., having worse solder wettability than the metal (272)). In some exemplary embodiments, the sheet material (271) is a flat sheet of a material that is primarily carbon. This carbon-based material may, for example, contain carbon nanotubes or graphite particles within the matrix material. In some other carbon-based embodiments, the sheet material (271) is a graphite sheet. The graphite sheet may be, for example, pyrolytic or crystalline graphite. Such graphite sheets provide significant mechanical strength at thicknesses well below 100 µm and also provide very high thermal conductivity values, particularly in the plane of the sheet material (271). In some exemplary embodiments, the sheet material (271) has a thickness of 25 µm or less (e.g., 15-25 µm). Not only graphite sheets, but also certain other carbon-based materials exhibit an advantageously small coefficient of linear thermal expansion (CTE), which can help the thermal diffuser (275) match the CTE associated with the IC die (205, 210) better than bulk metal alone.

[0037] The heat diffuser (275) may have any area, and in some advantageous embodiments, has an area sufficient to completely cover any lower IC die. In the illustrated example, the sheet material (271) has an area sufficient to extend beyond the edges of both the IC die (205) and the IC die (210) and to come into contact with a structural member (reinforcement) (225). As further described elsewhere in this specification, in the absence of a structural member (225), the heat diffuser (275) may similarly extend beyond the edge of at least one IC die and be supported by one or more solder features (e.g., solder balls) or be a cantilevered overhang. In other embodiments, the heat diffuser (275) may be dimensioned to have an area substantially equal to the area of ​​one or more lower IC dies.

[0038] The IC device assembly (201) further comprises an IC die package thermal solution (290) that may be in direct contact with a thermal diffuser (275) (e.g., sheet material (271)) or coupled thereto via a second level TIM (not shown). The thermal solution may be any heat exchanger known to be suitable for IC dies and / or multi-chip packages. Although the heat exchanger architecture may vary, the heat exchanger generally includes a surface that is in direct contact with or positioned in close proximity to the thermal diffuser (275). The heat exchanger may be, for example, a finned heat sink, a cold plate, or a heat pipe (vapor chamber).

[0039] Next, referring to FIG. 2b, the IC device assembly (202) is another example comprising a package substrate (220), wherein the active surfaces of the IC die (205) and the IC die (210), respectively, are attached to the package substrate (220) via a plurality of first-level electrical interconnects (208). References introduced in FIG. 2a are also used in FIG. 2b, and one or more of the attributes described in the context of FIG. 2a are applicable to the embodiments illustrated by FIG. 2b. In the IC device assembly (202), the IC die (210) is again significantly thicker than the IC die (205) (e.g., exceeding 50 μm, being 250-500 μm thicker, or greater).

[0040] As illustrated in FIG. 2b, the thermal interconnect interface structures (230) are again spaced apart over the area of ​​the back surface of the IC die (205), while the back surface of the IC die (210) similarly includes a plurality of thermal interconnect interface structures (240). Each of the thermal interconnect interface structures (230, 240) comprises one or more metals having a surface finish of the thermal interconnect interface structures (230, 240) having a solderable composition. As illustrated, the thermal interconnect interface structures (230) have a greater z-height or thickness out of the plane of the IC die (205) than the interface structures (240). Thus, compared to the interface structures (240), the interface structures (230) can be considered as pillars having a z-dimensional height greater than a predetermined minimum z-thickness of the interface structures (240).

[0041] Although their z-heights differ, each of the thermal interconnect interface structures (230 and 240) may have any lateral dimensions and / or feature pitch suitable for bonding with solder TIM thermal interconnects (250, 260). In some embodiments, one or both of the thermal interconnect interface structures (230, 240) may have a feature pitch substantially the same as the features on the front of the IC die (205, 210) that is coupled to the first level electrical interconnects (208). In other embodiments, one or both of the thermal interconnect interface structures (230, 240) may have a feature pitch significantly larger than the features on the front of the IC die (205, 210).

[0042] Individual thermal interconnect interfaces among the thermal interconnect interfaces (230, 240) are joined or bonded to corresponding ones among the plurality of solder TIM thermal interconnects (250, 260). In the illustrated example, the thermal interconnects (250) have substantially the same solder alloy composition and target dimensions (e.g., sphere radius and / or diameter, and / or z-height) as the solder TIM thermal interconnects (260). The target dimensions of the thermal interconnects (250, 260) may be the same if the z-height of the thermal interconnect features (230) is sufficiently larger than the z-height of the thermal interconnect features (240) to fully accommodate an amount that is smaller than the die thickness of the IC die (205) than the die thickness of the IC die (210). Although not illustrated for clarity, the IC device assembly (202) may also have underfill material between individual thermal interconnects among the thermal interconnects (250, 260).

[0043] The IC device assembly (202) further includes an integrated thermal diffuser (276). In exemplary embodiments illustrated in FIG. 2b, the thermal diffuser (276) comprises a sheet material (271), the sheet material (271) has a metal (272) on a surface facing the IC die (205, 210) and a metal (281) on a surface opposite the sheet material (271). In some embodiments, the metal (281) is also a solderable metal and may have substantially the same composition as the metal (272) and / or may have the same thickness as the solderable metal (272). In some embodiments, the metal (281) may include at least one of Cu, W, Ti, Ru, or Co, and may further include a surface finish such as, but not limited to, Ni and / or Au. The thickness of the metal (281) may vary, but in some embodiments, the metal (281) has substantially the same thickness as the metal (272), which can help maintain the flatness of the heat diffuser (276) during thermal cycles (e.g., by balancing the CTE differences of the component materials within the stacked heat diffuser). In some specific examples, both the metal (281) and the metal (272) have a thickness of less than 100 µm, and both may be less than 25 µm (e.g., 15 to 25 µm). Such limited thickness is advantageous for reducing the thermal resistance of the heat diffuser (275). In the embodiments illustrated in FIG. 2b, both the metal (272) and the metal (281) are each a continuous layer covering at least most of the sheet material (271), possibly substantially the entire area.

[0044] The heat diffuser (276) may also have any area, and in some advantageous embodiments, has an area sufficient to cover any lower IC die. In the illustrated example, the sheet material (271) has an area sufficient to extend beyond the edges of both the IC die (205) and the IC die (210) so that the solderable metal (272) overlaps with the structural member (reinforcement) (225). As further described elsewhere in this specification, where the structural member (225) is absent, the heat diffuser (276) may similarly extend beyond the edge of at least one IC die and may be supported by one or more solder features (e.g., solder balls) or be a cantilever overhang. In other embodiments, the heat diffuser (276) may be dimensioned to have an area substantially equal to the area of ​​one or more lower IC dies. The IC device assembly (202) also includes an IC die package thermal solution (290) that can be in direct contact with a thermal diffuser (276) (e.g., in contact with a metal (281)) or coupled thereto through a second level TIM (not shown).

[0045] FIGS. 2c-2d illustrate some exemplary assemblies in which a thermal diffuser having thermal interconnect lands is integrated with a plurality of IC dies. Reference numbers introduced in FIG. 2a or 2b are also used in FIGS. 2c and 2d, and one or more of the attributes described in the context of FIGS. 2a-2b are applicable to the embodiments illustrated in FIGS. 2c-2d.

[0046] Referring first to FIG. 2c, the IC device assembly (203) includes a package substrate (220), and the active surfaces of the IC die (205) and the IC die (210), respectively, are attached to the package substrate (220) through a plurality of first-level electrical interconnects. In these embodiments, the IC die (210) is again significantly thicker than the IC die (205) (e.g., greater than 50 μm, 250-500 μm thicker, or greater).

[0047] A metal layer (231) is on the back surface of the IC die (205), and a metal layer (241) is on the back surface of the IC die (210). The back surface metal layers (231, 241) may each have a solderable composition. The back surface metal layers (231, 241) may have different thicknesses to accommodate, for example, at least partially, the difference in die thickness between the IC die (205) and the IC die (210), but in some embodiments, the back surface metal layers (231, 241) have substantially the same thickness. As an example, the back surface metal layers (231, 241) have a thickness of less than 100 μm. The back surface metal layers (231, 241) may each function as an interface to solder TIM thermal interconnects (250, 260). However, since the back metal layers (231, 241) are continuous, unpatterned sheets that extend over most of the IC die area, for example, they maintain the desired spatial distribution of the thermal interconnects (250, 260) by relying on other structures within the assembly (203).

[0048] The back metal layer (231) is joined or bonded to individual solder TIM thermal interconnects among a plurality of solder TIM thermal interconnects (250). Similarly, the back metal layer (241) is joined or bonded to corresponding thermal interconnects among a plurality of thermal interconnects (260). Both thermal interconnects (250, 260) are solder TIMs. In the illustrated example, the thermal interconnects (250, 260) have different dimensions (e.g., spherical radius and / or diameter, and / or z-height). As illustrated, individual thermal interconnects among the thermal interconnects (250) have larger dimensions than individual thermal interconnects among the thermal interconnects (260). The target dimensions of the thermal interconnects (250) may be larger than the target dimensions of the thermal interconnects (260) by an amount that substantially accommodates a die thickness of the IC die (205) that is smaller than the die thickness of the IC die (210). Although not illustrated for clarity, the IC device assembly (203) may further include underfill material between individual thermal interconnects among the thermal interconnects (250, 260).

[0049] The IC device assembly (203) further includes an integrated thermal diffuser (277). In this exemplary embodiment, the thermal diffuser (277) includes a plurality of discrete thermal interconnect interface structures (or lands) (273, 274) on a surface of a sheet material (271) facing the IC die (205, 210). The interface structures (273, 274) can advantageously define and / or maintain a desired spatial distribution of thermal interconnects (250, 260) in a manner similar to the thermal interconnect interfaces (230, 240) of the assembly (201) (Fig. 2a).

[0050] In the embodiments illustrated in FIG. 2c, the thermal interconnect interface structures (273) are spaced apart over a first region of the thermal diffuser (277) placed over the back surface of the IC die (205). The thermal interconnect interface structures (274) are similarly spaced apart over a second region of the thermal diffuser (277) placed over the back surface of the IC die (210). In exemplary embodiments, each of the thermal interconnect interface structures (273, 274) comprises one or more metals having a surface finish having a solderable composition. The thermal interface structures (273, 274) may have the same composition. The thermal interconnect interface structures (273, 274) may have any lateral dimensions and / or feature pitch. In some embodiments, the thermal interconnect interface structures (273, 274) may have a feature pitch substantially equal to the feature pitch of the features on the front surface of the IC die (205, 210) coupled to the first level electrical interconnect (208). In other embodiments, the thermal interconnect interface structures (273, 274) may have a feature pitch significantly larger than the feature pitch of the features on the front surface of the IC die (205, 210). In the examples illustrated in FIG. 2c where the solder TIM thermal interconnects (250, 260) have different dimensions, the feature pitch of the thermal interconnect interface structures (273) may differ from (e.g., be larger than) the feature pitch of the thermal interconnect interface structures (274). As further described below, the thermal interconnect interface structures (230, 240) may have any thickness (e.g., z-dimension). In some specific examples, both thermal interconnect interface structures (273, 274) may have a thickness of 100 µm or less, and both may be 25 µm or less (e.g., 15-25 µm). Individual thermal interconnect interfaces among the thermal interconnect interfaces (273) are joined or bonded to corresponding thermal interconnects among the plurality of thermal interconnects (250).Similarly, individual column interconnect interfaces among the column interconnect interfaces (274) are joined or bonded to corresponding column interconnects among the plurality of column interconnects (260).

[0051] The heat diffuser (277) may also have any area, and in some advantageous embodiments, has an area sufficient to cover any lower IC die. In the illustrated example, the sheet material (271) has an area sufficient to extend beyond the edges of both the IC die (205) and the IC die (210) so that the sheet material (271) overlaps with the structural member (reinforcement) (225). As further described elsewhere in this specification, where the structural member (225) is absent, the heat diffuser (277) may similarly extend beyond the edge of at least one IC die and may be supported by one or more solder features (e.g., solder balls) or be a cantilever overhang. In other embodiments, the heat diffuser (277) may be dimensioned to have an area substantially equal to the area of ​​one or more lower IC dies.

[0052] The sheet material (271) may have any of the compositions described above (e.g., pyrolytic graphite sheet, synthetic material sheet, metal sheet, etc.). In some embodiments, the thermal interconnect interface structures (273, 274) are in direct contact with the sheet material (271), but one or more interposed materials may be present. In this example, one side of the sheet material (271) is in direct contact with the IC die package thermal solution (290). However, the IC die package thermal solution (290) may be in direct contact with and / or may be in direct contact with other materials of the thermal diffuser (277), such as a metallization layer (not shown), or may be coupled to the thermal diffuser (277) through a second level TIM (not shown).

[0053] Next, referring to FIG. 2d, the IC device assembly (204) is another example comprising a package substrate (220), wherein the active surfaces of the IC die (205) and the IC die (210), respectively, are attached to the package substrate (220) via a plurality of first-level electrical interconnects. In the assembly (204), the IC die (210) is again significantly thicker than the IC die (205) (e.g., greater than 50 μm, 250-500 μm thicker, or greater). In the assembly (204), the difference in die thickness is at least partially accommodated by a thermal diffuser (278) comprising thermal interconnect interface structures (273) having a greater z-height than the thermal interconnect interface structures (274). Accordingly, in such embodiments, the thermal interconnect interface structures (273, 274) allow the sheet material (271) to be thermally bonded to IC dies of different thicknesses and also facilitate minimum thermal interconnect z-heights by maintaining a predetermined spatial distribution of solder TIM features having some minimum target dimensions (e.g., 50-100 μm).

[0054] Similar to assembly (203) (Fig. 2c), back metal layers (231, 241) are on the IC die (205, 210) (e.g., in direct contact with a crystalline substrate material or a dielectric material such as SiN on it). Although the back metal layers (231, 241) may again have different thicknesses, in some embodiments, the back metal layers (231, 241) have substantially the same thickness (e.g., 15-25 μm). The back metal layers (231, 241) each interface with solder TIM thermal interconnects (250, 260). In assembly (204), the thermal interconnects (250, 260) have substantially the same dimensions. For example, the thermal interconnects (250, 260) may be solder features of a single target diameter or may have the same lateral (xy) and vertical (z) dimensions.

[0055] As illustrated in FIG. 2d, thermal interconnect interface structures (273, 274) are spaced above an area of ​​thermal diffuser sheet material (271). In the illustrated embodiments, the thermal interconnect interface structures (273) have a greater z-height or thickness out of the plane of the IC die (205) than the interface structures (274). Thus, the thermal interconnect interface structures (273) can be considered as pillars similar to the die-side interface structures (230) of the assembly (202) (Fig. 2b). In contrast, the thermal interconnect interface structures (274) may have a certain minimum z-thickness sufficient to function as discrete lands for solder TIM thermal interconnects (260) while maintaining spatial distribution and a minimum thermal interconnect z-height (e.g., 50-100 μm). Although their z heights differ, each of the interface structures (273, 274) may have any lateral dimensions and / or feature pitch. In some embodiments, both of the thermal interconnect interface structures (273, 274) have substantially the same feature pitch, which may be substantially the same as or significantly larger than the pitch of features on the front surface of the IC die (205, 210) coupled to the first level electrical interconnect (208).

[0056] Although not illustrated for clarity, the IC device assembly (202) may also have underfill material between individual thermal interconnects among the thermal interconnects (250, 260) and / or between individual thermal interconnect interface structures among the thermal interconnect interface structures (273, 274). The IC device assembly (204) further includes an integrated thermal diffuser (278). In this exemplary embodiment, the thermal diffuser (278) includes a sheet material (271) and a metal (281) on the surface of the sheet material (271) facing the IC die (205, 210). The metal (281) is again a continuous layer covering at least most of the sheet material (271), possibly substantially the entire area.

[0057] The thermal diffuser (278) may have any area and, in some advantageous embodiments, has an area sufficient to cover any lower IC die. In the illustrated example, the sheet material (271) has an area sufficient to extend beyond the edges of both the IC die (205) and the IC die (210) so that the sheet material (271) overlaps with the structural member (reinforcement) (225). Thermal interconnect interface structures (273 and / or 274) may also overlap with the structural member (225). As further described elsewhere in this specification, where the structural member (225) is absent, the thermal diffuser (278) may similarly extend beyond the edge of at least one IC die and be supported by one or more solder features (e.g., solder balls) or be a cantilever overhang. In other embodiments, the thermal diffuser (278) may be dimensioned to have an area substantially equal to the area of ​​one or more lower IC dies. The IC die package thermal solution (290) may be in direct contact with the thermal diffuser (278) (e.g., in contact with metal (281)) or may be coupled to the thermal diffuser (278) through a second level TIM (not shown).

[0058] FIGS. 2e and 2f illustrate two or more ID die assemblies (206, 207) that combine certain IC die-side thermal interconnect interface features of assembly (203) with certain thermal diffuser-size thermal interconnect interface features of assemblies (201 and 202). Thus, assemblies (206, 207) illustrate examples of how various features introduced in the context of FIGS. 2a through 2d can be combined together. Reference numbers introduced in FIGS. 2a-2d are retained in FIGS. 2e-2f, and one or more of the aforementioned attributes are applicable to the embodiments illustrated in FIGS. 2e-2f.

[0059] In assemblies (206, 207), the IC die (210) is significantly thicker than the IC die (205). In assembly (206), the difference in IC die thickness is at least partially accommodated by the solder TIM thermal interconnects (250, 260), for example, substantially as described above. In assembly (207), the difference in IC die thickness is instead at least partially accommodated by the z-height of the thermal interface structures (230) on the back of the IC die (205).

[0060] As illustrated in FIG. 2e, the assembly (206) includes a thermal diffuser (277) which may substantially be as described for assembly (203) (Fig. 2c). In assembly (206), thermal interface structures (273, 274) are spatially distributed to position solder TIM thermal interconnects (250, 260), respectively. Rather than a continuous metallization layer, the back surface of the IC die (205, 210) further includes thermal interconnect interface structures (230 and 240) which may substantially be as described for assembly (201) (Fig. 2a). Thus, discrete solder TIM lands exist on the IC die (205, 210) and also on the thermal diffuser (277). The spatial array of interface structures (230) is aligned with the spatial array of interface structures (273), and the spatial array of interface structures (240) is aligned with the spatial array of interface structures (274). Thus, the thermal interconnects (250, 260) can be accurately positioned over the area of ​​the junction between the thermal diffuser (277) and the IC die (205, 210). The accurate positioning can be maintained over time (e.g., undergoing minimal pump-out in terms of IC die warping, etc.).

[0061] In FIG. 2f, the assembly (207) includes a thermal diffuser (279) whose architecture is similar to that of the thermal diffuser (277), but substantially further includes metal (281) as described in the context of the assemblies (202 (Fig. 2b), 204 (Fig. 2d)). The assembly (207) illustrates an exemplary architecture in which a plurality of solder TIM thermal interconnects (250, 260) have substantially the same dimensions (e.g., z-height). Differences in die thickness are at least partially accommodated by thermal interconnect interface structures (230) which may be significantly thicker than the metal (241) on the back surface of the IC die (210). Thus, IC dies having different back surface structures can be coupled within a multi-chip package, and each IC die can nevertheless be thermally coupled to a thermal diffuser with a plurality of solder TIM interconnects.

[0062] Although many structural features of exemplary assemblies are illustrated in FIGS. 2a through 2f, many other variations are possible. For example, an assembly having only a single IC die or multiple IC dies of substantially the same thickness can simplify solder TIM thermal interconnects so that the interconnect interfaces of the thermal diffuser need to have only a single z-height or thickness and / or the thermal interconnects need to have only a single diameter. In particular, the assemblies illustrated in FIGS. 2a-2f may rely on IC dies having specific thermal interconnect interface features and / or stacked structures. Alternatively or additionally, the assemblies illustrated in FIGS. 2a-2f may rely on thermal diffusers having specific thermal interconnect interface features.

[0063] FIG. 3a is a flowchart illustrating methods (301) for manufacturing thermal interconnect interface structures on the surface of an IC die according to some embodiments. Methods (301) may be performed to manufacture an IC die suitable for integration into a package assembly including a thermal diffuser, such as, for example, any of the assemblies shown in FIG. 2a through 2f. In particular, methods (301) may be performed on an IC die that is in a wafer / panel format or assembled into a package. Methods (301) begin with receiving an IC die at an input (140). In exemplary embodiments, the IC die has a thickness of 50 µm to 500 µm. In block 362, metal is deposited on the back surface of the IC die. The metal may be deposited directly onto a crystalline substrate material of the IC die (e.g., single-crystal silicon) or directly onto a dielectric material (e.g., <500 nm thickness) on the crystalline substrate material, which can improve adhesion to the crystalline substrate material (e.g., SiN). The metal may be deposited by any technique suitable for the composition and thickness of the desired metal. In some exemplary embodiments, the metal is deposited by sputter deposition (PVD). In some embodiments, the metal is deposited by electroless or electrolytic deposition. More than one deposition technique may be used in Block 362, for example, a seed layer may be deposited by PVD, and the seed layer may be used to deposit additional metal by electroplating. In an example further illustrated in FIG. 4a, the metal (231) is deposited on the back surface of the IC die (205) facing the front surface (415). The front surface (415) may be supported by a carrier or attached to a package substrate via first-level electrical interconnects. As previously mentioned, the metal (231) is solderable. In some embodiments, the metal (231) is copper. In other embodiments, the metal (231) is one of W, Co, or Ru.The metal (231) may have multiple layers having, for example, a solderable surface finish (e.g., Ni or Au). The metal (231) is deposited with a thickness (T1) that is smaller than 100 μm in some embodiments and advantageously thin to about 15-25 μm.

[0064] Referring again to FIG. 3a, methods (301) continue defining a metal pattern in block 364. The metal pattern can be defined subtractively by removing a portion of the metal deposited in block 362, or additively by depositing additional material on top of the metal deposited in block 362. In an example further illustrated in FIG. 4a, the metal (231) is removed to form discrete thermal interconnect interface structures (230). In some embodiments, the thermal interconnect interface structures (230) are defined subtractively by removing a portion of the metal (231) with a laser.

[0065] FIG. 4b illustrates a top view of thermal interconnect interface structures on the surface of an IC die according to some embodiments. For reference, the line AA' of the cross-sectional view of FIG. 4a is shown in FIG. 4b. As illustrated in FIG. 4a and 4b, a continuous groove or a plurality of intersecting grooves may be formed by laser removal of the metal (231) to expose the back surface material of the IC die (205). An example CO2 or Nd:YAG laser may be used as a laser source. As illustrated in FIG. 4a, laser grooving of predetermined regions of the metal (231) may provide structures (230) having positively inclined sidewalls (445), and the lower part of the groove has a smaller lateral dimension than the upper part of the groove. Laser grooving can also recess the back surface material of the IC die (205) to form a recess in crystalline silicon of depth D1, for example, below the interface (473) between the adjacent interface structure (230) and the IC die (205). Depth D1 may vary depending on the laser parameters but is significantly larger than the minimum (e.g., nanometer) recess depths associated with more selective (chemical) etching processes. In some embodiments, depth D1 is greater than 5-10 µm. As illustrated in FIG. 4b, laser removal of cross grooves with a width of 25-100 µm is approximately 25-100 µm, which has the longest removal time (e.g., twice the removal time outside the intersection (446)). 2 A groove intersection (446) having an area can be formed. These removal path overlapping areas may have a larger recess depth D1. FIG. 4b illustrates an exemplary spatial arrangement of interface structures (230) belonging to a fixed-pitch 2D grid (e.g., including 25-100 µm spaces and 200-1000 µm lands). However, any spatial arrangement is possible.

[0066] Laser grooving can be particularly advantageous as it is a high-throughput, low-cost process that does not require masking, but other reduction patterning techniques may also be used. For example, if an etchant is available for the metal (231), a lithographically defined mask may be formed on the metal (231), and then the metal (231) may be etched according to the mask pattern to reach interface structures (230) (e.g., having an isotropically curved sidewall profile and / or reduced recess depth D1).

[0067] Referring again to FIG. 3a, at this point in methods (301), the IC die can be substantially prepared for assembly with a thermal diffuser. During such assembly, solder TIM thermal interconnects can be applied to the interface structures (230). As further described below, the solder TIM thermal interconnects can be provided as pre-applied subcomponents of the thermal diffuser subassembly. Alternatively, methods (301) can be completed at output (170) with additional application of solder TIM thermal interconnects to further prepare the IC die for assembly with the thermal diffuser. In FIG. 3a, output (170) is indicated by a dashed line to emphasize that solder TIM does not need to be applied in all embodiments of methods (301). In some embodiments, methods (302) (Fig. 3b) can be performed to apply solder TIM thermal interconnects to the surface of the prepared IC die. Methods (302) begin, for example, with receiving an IC die having a surface prepared according to methods (301). In block 374, individual solder features are deposited on individual interface structures among the interface structures. Optionally, methods (302) may further include the deposition of dielectric material as an underfill / overfill that at least partially fills the spaces between adjacent solder features.

[0068] In the example illustrated in FIG. 4a, solder features (e.g., microbumps) are formed on each interface structure (230) as solder TIM thermal interconnects (250). The dimensions of the solder features may be predetermined to reach a desired z-height Z1 from the back surface of the IC die (205). In some embodiments, when the solder TIM thermal interconnects (250) are 50-100 μm, the z-height Z1 may be, for example, 75-125 μm. The solder features may be formed according to any technique known to be suitable for front IC die electrical interconnects. With the solder TIM thermal interconnects (250) distributed or arranged over an area of ​​the IC die (205), an underfill material (455) may be applied between individual solder TIM thermal interconnects among the solder TIM thermal interconnects (250). The underfill material (455) may have any composition (e.g., polymer dielectrics) known to be suitable for solder feature underfill applications.

[0069] FIG. 5a illustrates cross-sectional views of thermal interconnect interface structures developing during the execution of the methods in 301 and 302 according to some exemplary additional embodiments. As illustrated in FIG. 5a, a mask material (560) is applied over the metal deposited in block 362 (Fig. 3a), and the mask material (560) defines a negative pattern between the discrete thermal interconnect interface structures (230). The mask material (560) may be, for example, a solder resist and / or may be printed as ink. FIG. 5b illustrates a top view of thermal interconnect interface structures on the surface of an IC die according to some embodiments. For reference, the line AA' of the cross-sectional view in FIG. 5a is indicated in FIG. 5b. Although FIG. 5b illustrates an exemplary spatial arrangement of the interface structures (230) belonging to a fixed-pitch 2D grid, any spatial arrangement is possible.

[0070] In the example illustrated in FIG. 5a, solder features (e.g., microbumps) are formed on each interface structure (230) as individual solder TIM thermal interconnects (250). The dimensions of the solder features may be predetermined to reach a z-height Z1, which may be, for example, 75-125 μm or less. Optionally, an underfill material (455) may be applied between the individual solder TIM thermal interconnects of the solder TIM thermal interconnects (250).

[0071] FIG. 6 is a flowchart illustrating methods (601) for manufacturing thermal interconnect interface structures on an IC die according to some alternative additional embodiments. Methods (601) begin again at an input (140) where the IC die is received. In block 362, a metal (e.g., Cu) is deposited on the back surface of the IC die. Then, in block 622, a plating mask material is applied over the metal, and then in block 626, additional metal (e.g., Cu) is plated through plating mask openings where the underlying metal is exposed. In block 627, the plating mask is removed, and if desired, a solder TIM is applied to the plated interface structures at the output (130).

[0072] FIG. 7 illustrates cross-sectional views of thermal interconnect interface structures that develop during the execution of methods (601) according to some embodiments. In this example, a metal (231) is deposited on the back surface of an IC die (205) so as to be in direct contact with, for example, a crystalline substrate material. As previously described, the metal (231) is deposited to any suitable thickness (T1). In some exemplary embodiments, the metal (231) is sputter-deposited as a seed layer and may comprise, for example, copper. A patterned plating mask (660) is formed over the metal (231), and the metal is electroplated to a thickness T3 within the unmasked areas of the metal (231). Subsequently, the plating mask (660) may be removed (however, in alternative embodiments, it may be retained permanently), and a flash etch of the metal (231) may be performed to define the discrete thermal interconnect interface features (lands) (230). In the example illustrated in FIG. 7, solder features (e.g., microbumps) are formed on each interface structure (230) as individual solder TIM thermal interconnects (250). The dimensions of the solder features may again be predetermined to reach a z-height Z1, which may be, for example, 75-125 μm or less. Optionally, an underfill material (455) may be applied between the individual solder TIM thermal interconnects of the solder TIM thermal interconnects (250).

[0073] FIG. 8a is a flowchart illustrating methods (801) for manufacturing thermal interconnect interface structures on a thermal diffuser sheet according to some embodiments. Methods (801) begin with receiving a thermal diffuser sheet preform at an input (110). The sheet preform may be very thin, for example, in the range of 15-25 μm, and may be temporarily attached to any carrier suitable for providing mechanical support during processing. The sheet preform may be any of the high thermal conductivity sheet materials introduced above, such as, but not limited to, pyrolytic graphite sheets or copper sheets. The sheet preform may be of any size sufficient to diffuse heat over at least an IC die, advantageously over an area of ​​a plurality of IC dies, and preferably over one or more edges of one or more IC dies.

[0074] In Block 818, a solderable metal is deposited on one or more surfaces of a sheet preform. The metal may be deposited directly onto the sheet material (e.g., pyrolytic graphite). The metal may be deposited by any technique suitable for the composition and thickness of the desired metal. In some exemplary embodiments, the metal is deposited by PVD. In some embodiments, the metal is deposited by electroless or electrolytic deposition. More than one deposition technique may be used in Block 818; for example, a seed layer may be deposited by PVD, and the seed layer may be used to deposit additional metal by electroplating. Following the deposition of the metal in Block 818, the thermal diffuser has a laminated structure comprising a sheet material preform and at least one metal layer on one or both sides of the sheet material.

[0075] Methods (801) continue in block 825, where a pattern comprising a plurality of solderable surfaces or structures is defined on at least one side of a synthetic thermal diffuser sheet. Similar to the aforementioned techniques for preparing the back side of an IC die, the metal pattern can be defined subtractively by removing a portion of the metal deposited in block 818, or additively by depositing additional material on top of the metal deposited in block 818. Once patterned, the thermal diffuser can be substantially prepared for assembly with the IC die. During such assembly, solder TIM thermal interconnects can be applied to the interface structures defined in block 825. As previously described, the solder TIM thermal interconnects can be provided as subcomponents of the IC die subassembly. Alternatively, methods (801) can be completed in output (130) by applying solder TIM thermal interconnects to further prepare the thermal diffuser for assembly with one or more IC dies. In FIG. 8a, the output (130) is indicated by a dashed line to emphasize that solder TIM does not need to be applied in all embodiments of methods (801). In some embodiments, methods (802) (Fig. 8b) are performed to apply solder TIM thermal interconnects to a prepared thermal diffuser surface. Methods (802) begin at an input (870) where a thermal diffuser having a prepared surface (e.g., according to methods (801)) is received. In block 872, individual solder features are deposited on individual thermal diffuser interface structures. The solder features may be dimensioned to a predetermined minimum size (e.g., 50-100 µm) for optimal thermal performance. In embodiments where a thermal diffuser is thermally coupled with a plurality of IC dies and the difference in z-height between IC dies is at least partially accommodated by solder features, in block 874, additional solder features of different sizes may be additionally deposited on a subset of the thermal diffuser interface structures.As another option, the methods (802) may further include the deposition of dielectric material as an underfill / overfill that at least partially fills the spaces between the solder features.

[0076] FIG. 9a illustrates cross-sectional views of thermal interconnect interface structures developing during the execution of methods (801, 802) according to some embodiments. As illustrated, a sheet material (271) is supported by a temporary carrier (950). In this example, metal (272) is deposited on the exposed surface of the sheet material (271). In other embodiments, carrier transfer may be performed or a core plating process may be performed to deposit metal on both sides of the sheet material (271). As further illustrated in FIG. 9a, the metal (272) is optionally removed to form a discrete thermal interconnect interface structure (273). In some embodiments, the thermal interconnect interface structure (273) is defined by reduction by laser-removing a portion of the metal (272). Alternatively, any etching process suitable for the metal (272) may be used to define the interface structures (273).

[0077] FIG. 9b illustrates a top view of a thermal interconnect interface structure on a thermal diffuser surface according to some embodiments. For reference, the line AA' of the cross-sectional view of FIG. 9a is shown in FIG. 9b. As illustrated in FIG. 9a and FIG. 9b, a continuous groove or a plurality of intersecting grooves may be formed by laser removal of the metal (272) to expose the sheet material (271) below the grooves. As illustrated in FIG. 9a, laser grooving of predetermined areas of the metal (272) may cause the structures (273) to have positively inclined sidewalls (445), for example, the lower part of the groove has a smaller lateral dimension than the upper part of the groove. Laser grooving may also recess the sheet material (271) to form a recess of depth D1, for example, below the interface (973) between adjacent interface structures (273) and the sheet material (271). As shown in FIG. 9b, laser removal of intersecting grooves with a width of 25-100 µm involves approximately 25-100 µm, where the removal time is longest (e.g., twice the removal time outside the intersection). 2 Groove intersections having an area can be formed. These removal path overlapping areas may have a larger recess depth D1. FIG. 9b illustrates an exemplary spatial arrangement of interface structures (273) belonging to a fixed-pitch 2D grid (e.g., including 25-100 µm spaces and 200-1000 µm lands). However, any spatial arrangement is possible. While laser grooving may be particularly advantageous, other reduction patterning techniques may also be used. For example, if an etchant is available for the metal (272), a lithographically defined mask may be formed on the metal (272), and then the metal (272) may be etched according to the mask pattern to reach interface structures (273) (e.g., having an isotropically curved sidewall profile and / or a minimum recess depth D1).

[0078] In an example further illustrated in FIG. 9a, solder features (e.g., microbumps) are formed on each interface structure (273) as solder TIM thermal interconnects (250). The dimensions of the solder features may be predetermined to reach a desired z-height Z1 from the surface of the sheet material (271). In some embodiments, when the solder TIM thermal interconnects (250) are 50-100 μm, the z-height Z1 may be, for example, 75-125 μm. With the solder TIM thermal interconnects (250) distributed or arranged over an area of ​​the thermal diffuser (275), any suitable underfill material (not shown) may be applied between individual solder TIM thermal interconnects among the solder TIM thermal interconnects (250). Considering that underfill materials (e.g., polymer dielectrics) can lose their advantageous properties over time, the underfill material does not need to be applied as part of the thermal diffuser solder TIM assembly, but instead is applied during the assembly of the thermal diffuser and the IC device package.

[0079] FIG. 10a illustrates cross-sectional views of thermal interconnect interface structures developing during the execution of methods (801, 802) according to some additional patterning embodiments. As illustrated in FIG. 10a, a mask material (560) is applied over a metal (272), and the mask material (560) defines a negative pattern between the discrete thermal interconnect interface structures (273). The mask material (560) may be, for example, a solder resist and / or may be printed as ink. FIG. 10b illustrates a top view of thermal interconnect interface structures on an IC die surface according to some embodiments. For reference, the AA' line of the cross-sectional view in FIG. 10a is indicated in FIG. 10b. FIG. 10b illustrates an exemplary spatial arrangement of interface structures (273) belonging to a fixed-pitch 2D grid, but any spatial arrangement is possible. As further illustrated in FIG. 10, according to some embodiments, solder features may be deposited on corresponding interface structures among the interface structures (273) to integrate the thermal interconnects (250) into the thermal diffuser assembly.

[0080] FIG. 11 is a flowchart illustrating methods (1101) for manufacturing thermal interconnect interface structures on a thermal diffuser according to some alternative additional embodiments. The methods (1101) begin again at an input (110) where a sheet material preform is received. In block 818, a metal (e.g., Cu) is deposited on the surface of the sheet material. Then, in block 1122, a plating mask material is applied over the metal, and in block 1126, additional metal (e.g., Cu) is plated through plating mask openings where the underlying metal is exposed. In block 1127, the plating mask can be removed, and if desired, a solder TIM is applied to the plated interface structures.

[0081] FIG. 12a illustrates cross-sectional views of thermal interconnect interface structures that develop during the execution of methods (1101) according to some embodiments. In this example, a metal (272) is deposited on a sheet material (271) (e.g., in direct contact with a graphite sheet). As previously described, the metal (272) is deposited to any suitable thickness (T1). In some exemplary embodiments, the metal (272) is sputter-deposited as a seed layer and may comprise, for example, copper. A patterned plating mask (660) is formed over the metal (272), and the metal is electroplated to a thickness T3 within the unmasked areas of the metal (272). Subsequently, the plating mask (660) may be removed (however, the plating mask (660) may be permanently retained in alternative embodiments), and a flash etch of the metal (272) may be performed to define the discrete thermal interconnect interface features (lands) (273). In the example illustrated in FIG. 12a, features of solder (e.g., microbumps) are formed as individual solder TIM thermal interconnects (250) on each interface structure (273). The dimensions of the solder features may again be predetermined to reach a z-height Z1, which may be, for example, 75-125 μm. Optionally, an underfill material (not shown) may be applied between the individual solder TIM thermal interconnects among the solder TIM thermal interconnects (250).

[0082] FIG. 12b illustrates cross-sectional views of thermal interconnect interface structures developing during the implementation of methods (1100) according to some alternative embodiments, wherein the thickness of the interface structures varies between regions (703) and regions (704) of the thermal diffuser. The variation in the thickness of the interface structures between regions (703, 704) can accommodate, for example, IC dies of different die thicknesses. As illustrated in FIG. 12b, a plating mask (660) is applied over the metal (272). The plating mask pattern within region (704) includes openings where the metal (272) is exposed. The plating mask pattern within region (703) substantially does not include openings where the metal (272) is exposed. Additional metal may be plated within the mask openings to increase the thickness of the interface structures (274) within region (704) to thickness T3. When the plating mask is removed, the metal (272) of thickness T1 remains in the regions where the metal is not plated. If desired, other mask materials (e.g., solder resist or dielectric ink, etc.) may be applied over the metal (272) to define multiple other interface structures (not shown). The difference between thicknesses T1 and T3 may be, for example, about 500 µm, which can fully accommodate the difference in IC die thicknesses. Alternatively, the difference between thicknesses T1 and T3 may be somewhat smaller than the difference in IC die thicknesses and can only partially accommodate the difference in IC die thicknesses. In such embodiments, the remainder of the difference in IC die thicknesses may be accommodated by differences in TIM solder feature dimensions and / or differences in thickness in thermal interconnect interface structures on different IC dies.

[0083] In some embodiments, the assembly of a solder-ready IC die and a solder-ready thermal diffuser surface proceeds according to methods (1301) as illustrated in FIG. 13. In methods (1301), a solderable or "solder-ready" thermal diffuser is received at the input (1305). The solderable thermal diffuser may have any of the aforementioned features and / or may have been prepared according to any of the aforementioned methods. Alternatively, another thermal diffuser having a surface suitable for thermal coupling to the IC die by a plurality of solder TIM interconnects may be received. In block 1310, one or more solderable or "solder-ready" IC dies are received at the input (1310). The solderable IC die may have any of the aforementioned features and / or may have been prepared according to any of the aforementioned methods. Alternatively, another IC die having a surface suitable for thermal coupling to the thermal diffuser by a plurality of solder TIM interconnects may be received.

[0084] Methods (1301) continue in block 1374, where the solderable surface of a thermal diffuser is soldered to the solderable surface of an IC die. Any technique(s) may be performed in block 1374. In some embodiments, the thermal diffuser is pick-and-placed onto the target IC die, and a thermo-compression process is performed to melt the solder interconnects and bond them to both solderable surfaces. According to advantageous embodiments, at least one of the solderable surfaces includes a plurality of interface structures or lands, such as those described above, that maintain a desired spatial distribution of a plurality of thermal interconnects. Methods (1301) are completed at an output (190) where any higher-level assembly may be performed. For example, at the output (190), a package bonded to the side of the IC die facing the thermal diffuser may be electrically bonded to a host component. Alternatively or additionally, a system-level thermal solution may be bonded to the side of the thermal diffuser facing the IC die.

[0085] FIG. 14a is a plan view of thermal interconnect interface structures on the surface of an IC die assembly (1401) according to some embodiments. The IC die assembly (1401) includes flip chips of IC dies (205, 210) bonded to the surface of a package substrate (220). The package substrate (220) further includes an embedded IC (1418), indicated by a dotted line, which is located below the plane of the IC dies (205, 210). Thermal interconnect surface interface structures (273) are distributed on the back surface of the IC die (205). Thermal interconnect surface interface structures (274) are distributed on the back surface of the IC die (210). The IC die assembly (1401) is a multi-chip package that may be received, for example, from a chip manufacturer. The IC die assembly (1401) may have been received substantially as illustrated, or a system assembler may have formed in-situ interface structures (273, 274) on the IC die assembly (1401) (e.g., by laser scribing the back metal provided on each of the IC dies (205, 210).

[0086] FIG. 14b illustrates cross-sectional views of thermal interconnect interface structures joined by a plurality of solder TIM thermal interconnects during the execution of methods (1301) (Fig. 13) according to some embodiments, wherein the solder TIM thermal interconnects are provided as components of a thermal diffuser subassembly. The cross-sectional view illustrated in FIG. 14b follows the BB' line indicated in FIG. 14a.

[0087] As illustrated in FIG. 14b, the package substrate (220) comprises layers of package metallization between dielectric materials (1420a, 1420b). The package substrate metallization layers may comprise copper, other suitable metals, or other conductive materials that are electroplated directly onto the dielectric material or formed in a different manner, for example, after a given iteration of the stacking process. There may be any number of package metallization levels within the package substrate (220). The highest metallization level is on the first (e.g., top) surface of the package substrate (220) or the Nth metallization level (M) closest thereto. N ) may be. The Nth metallization level is located on metal zero (M0), which is the base metallization level furthest from the first surface of the package substrate (220) and in direct contact with the core (1405) in the illustrated example. Any number of intermediate package metallization levels (e.g., M1) are metallization levels (M N and may be between M0). As shown in FIG. 14b, the package substrate (220) is substantially symmetric with respect to the core (1405), and the metallization levels (M0-M N ) is also present on the second (e.g., bottom) surface of the package substrate (220). A metallization level (e.g., copper) may be sputtered, plated, or a foil may be laminated as a metallization level. Each metallization level (M0-M N) may have a thickness of, for example, 5 to 50 micrometers and may be patterned to route electrical communications vertically through the package substrate thickness (e.g., through dielectric materials (1420a), through the core (1405), and through dielectric materials (1420B). In embodiments where metallization levels are plated, the metallization features of each level may be formed by semi-additive processing (SAP) in which a plating mask may be used, or by a modified SAP (mSAP) in which a foil is applied and a masked etching process (e.g., wet chemical) is used.

[0088] As additionally illustrated in FIG. 14b, the package substrate (220) is coupled to second-level interconnects (1408), which may be, for example, solder balls or other solder features. Thus, package metallization level routing can electrically couple the second-level interconnects (1408) to the first-level interconnects (208). Some of the first-level interconnects (208) couple IC dies (205, 210) to ICs (1418) embedded within the package substrate (220). The IC (1418) may include IC-scale metallization that interconnects the IC die (205) to the IC die (210) as a communication bridge between the IC die (205) and the IC die (210). An underfill material (1455) surrounds each of the IC dies (205, 210). In the illustrated example, the IC die (210) is actually a die-level integrated circuit comprising a plurality of IC dies (210A). Accordingly, the z-height of the IC die (210) is significantly larger than the z-height of the IC die (205).

[0089] A thermal diffuser (275) handled via a carrier (450) includes thermal interconnects (250) attached to interface structures (273) and thermal interconnects (260) attached to interface structures (274). A thermal diffuser region (704) is aligned over an IC die (205), and a thermal diffuser region (703) is aligned over an IC die (210), so that thermal interconnects (260) having a smaller z-height Z1 are bonded to thermal interconnect interface structures (240), and thermal interconnects (250) having a larger z-height Z2 are bonded to thermal interconnect interface structures (230). Subsequently, the thermal diffuser carrier (450) can be removed, for example, via a UV-assisted release process. In the illustrated example, the thermal diffuser subassembly includes an underfill material (455) between the thermal interconnects (250, 260).

[0090] In particular, the heat diffuser (275) may primarily have a thermal conductive function, but is not excluded from serving certain auxiliary electrical functions, such as a ground plane and / or an EMI shield, for example. Embodiments in which the heat diffuser (275) includes a conductive layer are possible. The heat diffuser (275) may have sufficient conductivity, for example, if the sheet material (271) is PGS and / or includes one or more metal layers. The heat diffuser (275) may be electrically coupled to the voltage potential of the IC die assembly (1401), for example, through solder balls (1460) located at the peripheral edge of the heat diffuser (275). The solder balls (1460) may be distributed around the periphery to completely surround the IC die (205, 210). The heat diffuser (275) and solder balls (1460) together can form an EMI shield or cage on and around the IC die (205, 210).

[0091] FIG. 14c is a top view of thermal interconnect interface structures on the surface of an IC die assembly (1402) according to some alternative embodiments, wherein solder TIM thermal interconnects (250, 260) are provided as components of the IC die assembly (1402). FIG. 14d illustrates cross-sectional views of thermal interconnect interface structures joined by a plurality of solder TIM interconnects during the execution of methods (1301) according to some alternative embodiments. The cross-sectional view illustrated in FIG. 14d follows the DD' line indicated in FIG. 14c.

[0092] As illustrated in FIGS. 14c and 14d, solder interconnects (250, 260) are attached to an IC die assembly (1402). Solder balls (1460) are also attached to a package substrate (220). The IC die assembly (1402) is otherwise substantially identical to the IC die assembly (1401) ( FIGS. 14a and 14b). A thermal diffuser (275) comprising only a lamination of sheet material (271) and metal (272) can be bonded to the solder interconnects (250, 260) and solder balls (1460) using any thermal compression suitable for forming good solder interconnect joints, for example.

[0093] FIGS. 15a through 15d illustrate cross-sectional views of IC die assemblies according to some alternative embodiments. Each of the assemblies illustrated in FIGS. 15a through 15d can be assembled according to methods (1301) (Fig. 13), for example, substantially as described in FIGS. 14a and 14b or FIGS. 14c through 14d. The assemblies illustrated in FIGS. 15a through 15d can be provided to a computing system assembler that integrates the assembly (1501) into a higher-level system, such as a laptop computer or a mobile communication handset, for example.

[0094] FIG. 15a illustrates an IC device and an integrated thermal diffuser assembly (1501) according to some embodiments. The assembly (1501) illustrates an example in which solder interconnects (250) join a plurality of thermal interconnect structures (230) on the IC die side to a plurality of thermal interconnect structures (273) on the thermal diffuser side.

[0095] FIG. 15b illustrates an IC device and an integrated thermal diffuser assembly (1502) according to some alternative embodiments, wherein an underfill material (455) is applied after the thermal compression bonding of the thermal diffuser subassembly and the IC die assembly. In some embodiments, the underfill material (455) may be distributed as a liquid into the through holes in the thermal diffuser (275) located over the IC die (205) and into the through holes in the thermal diffuser (275) located over the IC die (210), so that the underfill material (455) is confined to the regions (704, 703) over the thermal diffuser (275) (i.e., only surrounding the thermal interconnects (250, 260)). The assembly (1502) also illustrates an embodiment in which the thermal diffuser (275) includes a cantilever overhang beyond the edges of the IC die (205, 210).

[0096] FIG. 15c illustrates an IC device and an integrated thermal diffuser assembly (1503) according to some alternative embodiments, wherein differences in the die thicknesses of the IC dies (205, 210) are fully accommodated by differences in the z-heights of the thermal interconnect interface structures (273, 274) on the thermal diffuser side. Thus, the thermal interconnects (250) may have substantially the same lateral and vertical dimensions as the thermal interconnects (260).

[0097] FIG. 15d illustrates an IC device and an integrated thermal diffuser assembly (1504) according to some alternative embodiments, wherein differences in the die thicknesses of the IC dies (205, 210) are fully accommodated by differences in the z-heights of the thermal interconnect interface structures (230 and 240) on the IC die side. Thus, the thermal interconnects (250) may have substantially the same lateral and vertical dimensions as the thermal interconnects (260). The assembly (1504) further illustrates an embodiment comprising a sheet material (271) (e.g., a graphite sheet) having a continuous layer of metal (272) (e.g., Cu) in which the thermal diffuser (275) contacts a plurality of thermal interconnects (250, 260). As a laminate, the thermal diffuser (275) further comprises a metal (281) (e.g., Cu) on a surface of a sheet material (271) facing the metal (272). This Cu / G / Cu thermal diffuser architecture can provide particularly good thermal performance, such as potentially less than 100 µm, have good strength and CTE match for low package warping, and also enable electrical grounding of the thermal diffuser.

[0098] FIG. 16 illustrates a cross-sectional view of a system-level IC device assembly (202) according to some embodiments. As introduced in FIG. 2a, the assembly (202) is a system-level integrated circuit comprising an integrated IC die-thermal diffuser assembly (1504), a host component (299) (e.g., a PCB), and an IC die package thermal solution (290) (e.g., a fin-type heat sink, a cooling plate, a vapor chamber, a heat pipe, etc.).

[0099] FIG. 17 illustrates a system in which a mobile computing platform (1705) and / or a data server machine (1706) further comprises an IC package assembly (1750) comprising a plurality of solder thermal interconnects and thermal interfaces, for example according to some embodiments described elsewhere in this specification, and further comprises a package integrated thermal diffuser (IHS). The server machine (1706) may be any commercial server comprising any number of high-performance computing platforms placed on a shelf and networked together for electronic data processing, for example, comprising an IC package assembly (1701) in an exemplary embodiment. The mobile computing platform (1705) may be any portable device configured for electronic data display, electronic data processing, wireless electronic data transmission, etc. For example, the mobile computing platform (1705) may be any of a tablet, a smartphone, a laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a package-level integrated system (1710), and a battery (1715).

[0100] Whether placed within the integrated system (1710) shown in the enlarged view (1750) or as a standalone packaged chip within the server machine (1706), the IC package assembly (1701) may include memory circuits (e.g., RAM) within the IC die (210) and logic circuits (e.g., microprocessor, graphics processor, etc.) within the IC die (205). The IC package assembly (1701) may also be coupled to a host board, an interposer, or a component (not shown). In the illustrated example, the IC package assembly (1701) may include an interconnect bridge IC coupled to both of them communically to facilitate interconnection between, for example, the memory IC die (210) and the processor IC die (205).

[0101] The integrated system (1710) further includes a power management IC (PMIC) (1730) and a radio frequency IC (RFIC) (1725) having an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols designated as 3G, 4G, 5G or higher.

[0102] FIG. 18 is a functional block diagram of an electronic computing device (1800) according to some embodiments. The device (1800) further comprises a motherboard (1801) hosting a plurality of components, such as, but not limited to, a package substrate (220) to which a processor (1804) (e.g., an application processor) is coupled. The processor (1804) may be physically and / or electrically coupled to the package substrate (220). In some examples, the processor (1804) is part of an IC package assembly comprising solder thermal interconnects coupled to a thermal diffuser through a plurality of thermal interconnect interface structures, as described elsewhere in this specification, for example. Generally, the terms “processor” or “microprocessor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts said electronic data into other electronic data that may be further stored in registers and / or memory.

[0103] In various examples, one or more communication chips (1806) may also be physically and / or electrically coupled to the motherboard (1801). In additional implementations, the communication chips (1806) may be part of the processor (1804). The computing device (1800) may include other components that may or may not be physically and electrically coupled to the package substrate (220), depending on its application. These other components include, but are not limited to, volatile memory (e.g., DRAM (1832)), non-volatile memory (e.g., ROM (1835)), flash memory (e.g., NAND or NOR), magnetic memory (MRAM (1830)), graphics processor (1822), digital signal processor, cryptographic processor, chipset (1812), antenna (1825), touchscreen display (1815), touchscreen controller (1865), battery (1816), audio codec, video codec, power amplifier (1821), GPS (global positioning system) device (1840), compass (1845), accelerometer, gyroscope, speaker (1820), camera (1841), and mass storage devices (such as a hard disk drive, SSD (solid-state drive), CD (compact disk), DVD (digital versatile disk), etc.). Any of these components may be assembled into a package including an integral structural member according to one or more embodiments described elsewhere in this specification, for example.

[0104] Communication chips (1806) can enable wireless communication for the transmission of data to and from the computing device (1800). The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., capable of communicating data through the use of modulated electromagnetic radiation over a non-solid medium. This term does not imply that the devices involved do not include any wires, although this may be the case in some embodiments. Communication chips (706) may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere in this specification. As discussed, the computing device (1800) may include a plurality of communication chips (1806). For example, the first communication chip may be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0105] While certain features set forth in this specification have been described in relation to various implementations, such description is not intended to be interpreted in a limiting sense. Accordingly, various modifications of the implementations described in this specification that are obvious to those skilled in the art to which this disclosure pertains, as well as other implementations, are deemed to be within the spirit and scope of this disclosure.

[0106] It will be recognized that the present invention is not limited to the embodiments described above but may be practiced with modifications and changes without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features as further provided below.

[0107] In the first examples, the integrated circuit (IC) device assembly comprises a package substrate, an IC die having a first surface electrically coupled to the package substrate through a plurality of first-level electrical interconnects, a plurality of thermal interconnects comprising a solder alloy—the thermal interconnects are coupled to a second surface of the IC die opposite to the first surface—and a thermal diffuser coupled to the IC die through a plurality of thermal interconnects, wherein the thermal diffuser comprises a graphite sheet and one or more first metals between the graphite sheet and the thermal interconnects.

[0108] In the second examples, for any one of the first examples, the graphite sheet is a crystalline or pyrolytic graphite sheet.

[0109] In the third example, for either the first or second example, the graphite sheet has a layer thickness of 25 μm or less.

[0110] In the fourth example, for any one of the first to third examples, the first metals include copper in direct contact with the graphite sheet.

[0111] In the fifth example, for any one of the first to fourth examples, the first metals further include a surface finish between copper and the solder alloy.

[0112] In the 6th example, for any one of the 5th examples, the surface finish material comprises at least one of Ni or Au.

[0113] In the seventh example, for any one of the first to sixth examples, one or more first metals are in contact with a first surface of the graphite sheet between the graphite sheet and the thermal interconnects, and the thermal diffuser further comprises one or more first metals in contact with a second surface of the graphite sheet opposite the first surface.

[0114] In the eighth example, for any one of the seventh examples, one or more first metals on each of the first and second surfaces of the graphite sheet have a thickness of 25 μm or less.

[0115] In the ninth example, for any one of the first to eighth examples, the assembly further comprises a polymer underfill material between individual thermal interconnects among a plurality of thermal interconnects.

[0116] In the 10th example, for any one of the 1st to 9th examples, the second surface of the IC die includes a second metal between the individual thermal interconnects among the plurality of thermal interconnects and the crystalline semiconductor material of the IC die.

[0117] In the 11th example, for any one of the 10 examples, the IC die comprises individual discrete metal features among a plurality of discrete metal features distributed on a second surface of the IC die, and the metal features comprise a second metal.

[0118] In the 12th example, for any one of the 10th to 11th examples, a plurality of thermal interconnect lands comprises at least one of the first metals or the second metals, and individual lands among the lands correspond to individual thermal interconnects of the thermal interconnects.

[0119] In the 13th example, for any one of the 1st to 12th examples, individual thermal interconnects among the plurality of thermal interconnects have a thickness between the thermal spreader and the IC die of 100 μm or less.

[0120] In the 14th example, for any one of the 13 examples, the IC die is a first IC die, and the assembly further comprises a second IC die laterally adjacent to the first IC die and coupled to a package substrate, the first IC die has a first thickness, the second IC die has a second thickness smaller than the first thickness, and among the thermal interconnects between the thermal spreader and the first IC die, the first thermal interconnect has a thickness smaller than the second thermal interconnect among the thermal interconnects between the thermal spreader and the second IC die.

[0121] In the 15th example, the integrated circuit (IC) die thermal spreader comprises a graphite sheet and a plurality of thermal interconnect lands on a first surface of the graphite sheet, and the thermal interconnect lands comprise one or more first metals.

[0122] In the 16th example, for any one of the 15 examples, the graphite sheet is a crystalline or pyrolytic graphite sheet having a layer thickness of 25 μm or less, and one or more first metals have a thickness of 25 μm or less.

[0123] In the 17th example, for any one of the 15th to 16th examples, one or more first metals are in contact with a first surface of a graphite sheet, and the heat diffuser further comprises a metal in contact with a second surface of a graphite sheet opposite to the first surface.

[0124] In the 18th example, for any one of the 15 to 17 examples, a plurality of lands include a plurality of discrete metal features spaced apart on a first surface of a graphite sheet.

[0125] In the 19th example, for any one of the 15 to 18 examples, individual solder lands among the plurality of solder lands include regions of a continuous layer separated from adjacent regions of a continuous layer of the first metal by a masking material.

[0126] In the 20th example, the thermal diffuser further comprises a plurality of thermal interconnects comprising a solder alloy, and individual thermal interconnects among the thermal interconnects contact corresponding lands among the lands.

[0127] In the 21st example, the computing system includes a processor IC, and a first side of the processor IC is coupled to a first side of a package substrate through a plurality of first electrical interconnects. The system includes a thermal diffuser, and a first side of the thermal diffuser is coupled to a second side of the processor IC through a plurality of thermal interconnects comprising a solder alloy, and the thermal diffuser includes a graphite sheet and one or more first metals between the graphite sheet and the thermal interconnects. The system includes a heat exchanger coupled to the second side of the thermal diffuser. The system includes a host board coupled to the second side of the package substrate through a plurality of second electrical interconnects.

[0128] In the 22nd example, for any one of the 21st examples, the heat exchanger includes a finned heat sink, a cold plate, or a heat pipe.

[0129] In the 23rd example, for any one of the 21st to 22nd examples, the system further includes a memory IC adjacent to the processor IC, the first side of the memory IC is coupled to the first side of the package substrate by a second plurality of first electrical interconnects, and the first side of the thermal diffuser is further coupled to the second side of the memory IC through a second plurality of thermal interconnects.

[0130] In the 24th example, for any one of the 21st to 23rd examples, the peripheral portion of the thermal diffuser beyond the edge of the processor IC is bonded to the peripheral portion of the package substrate through one or more solder balls or through package reinforcement.

[0131] In Example 25, for any one of Examples 21 to 24, the thermal diffuser is electrically coupled to the voltage potential of the package substrate through solder balls.

[0132] In the 26th example, the integrated circuit (IC) device assembly comprises a package substrate, an IC die having a first surface electrically coupled to the package substrate through a plurality of first-level electrical interconnects and a second surface comprising a plurality of metal lands. The assembly comprises a thermal diffuser coupled to the second surface of the IC die through a plurality of thermal interconnects comprising a solder alloy, and individual thermal interconnects among the plurality of thermal interconnects contact corresponding metal lands among the metal lands.

[0133] In the 27th example, for any one of the 26 examples, the first metal of the lands is in direct contact with the crystalline substrate material of the IC die.

[0134] In the 28th example, for any one of the 26th to 27th examples, individual thermal interconnects among a plurality of thermal interconnects have a first thickness, individual lands among a plurality of lands have a second thickness, and at least one of the first and second thicknesses is 100 μm or less.

[0135] In the 29th example, for any one of the 28 examples, a plurality of lands include a plurality of spaced discrete metal features on a second face of the IC die, and a first portion of the crystalline substrate material of the IC die is between adjacent metal features among the metal features.

[0136] In the 30th example, for any one of the 29 examples, the surface of the first portion of the crystalline substrate material is recessed below the plane of the interface between the adjacent metal feature among the metal features and the second portion of the crystalline substrate material.

[0137] In the 31st example, for any one of the 30 examples, the recess has a depth of at least 10 μm.

[0138] In the 32nd example, for any one of the 30th to 31st examples, the metal features are arranged in a two-dimensional (2D) grid of fixed intervals, and each of the metal features has substantially the same area.

[0139] In the 33rd example, for any one of the 32 examples, the depth of the recess is greater at the intersections than outside the intersections of the 2D grid.

[0140] In the 34th example, for any one of the 29 examples, at least one of the first and second thicknesses varies by at least 20 μm.

[0141] In the 35th example, for any one of the 26th to 34th examples, the IC die is a first IC die, and the assembly further includes a second IC die laterally adjacent to the first IC die. The first IC die has a first die thickness, and the second IC die has a second die thickness greater than the first die thickness. A first land among the lands is on the first IC die, and a second land among the lands is on the second IC die. A first column interconnect among the column interconnects is coupled to a first land among the lands, and a second column interconnect among the column interconnects is coupled to a second land among the lands. A first z-height equal to the thickness of the first solder land among the solder lands, which is summed with the thickness of the first column interconnect among the column interconnects, is greater than a second z-height equal to the thickness of the second land among the lands, which is summed with the thickness of the second column interconnect among the column interconnects.

[0142] In the 36th example, for any one of the 35 examples, there is a difference of at least 250 μm between the first die thickness and the second die thickness. The difference between the first and second z heights is substantially the same as the difference between the first and second die thicknesses.

[0143] In the 37th example, for any one of the 36 examples, the thickness of the first land among the lands is substantially the same as the thickness of the second land among the lands.

[0144] In the 38th example, for any one of the 36 examples, the thickness of the first column interconnect among the column interconnects is substantially the same as the thickness of the second column interconnect among the column interconnects.

[0145] In the 39th example, for any one of the 29 examples, individual lands among the plurality of lands include regions of a metal layer separated from adjacent regions of a continuous metal layer by a masking material.

[0146] In the 40th example, for any one of the 39 examples, the masking material includes solder resist.

[0147] In the 41st example, for any one of the 26th to 40th examples, the thermal diffuser comprises a graphite sheet having a layer thickness of 25 μm or less, and a metal in contact with the graphite sheet and between the graphite sheet and the thermal interconnects.

[0148] In the 42nd example, the integrated circuit (IC) die thermal diffuser comprises a sheet of a first material and a plurality of thermal interconnect lands in contact with a first surface of the sheet. The plurality of lands comprises one or more metal layers. The thermal diffuser comprises a plurality of thermal interconnects comprising a solder alloy, and individual thermal interconnects among the thermal interconnects contact corresponding lands among the lands.

[0149] In the 43rd example, for any one of the 42 examples, the first material is crystalline graphite or pyrolytic graphite, and the sheet has a thickness of 25 μm or less.

[0150] In the 44th example, for any one of the 42nd to 43rd examples, the heat diffuser further comprises a metal in contact with the second surface of the sheet facing the first surface.

[0151] In the 45th example, for any one of the 42nd to 44th examples, a plurality of lands include a plurality of discrete metal features spaced apart on the first surface of the sheet.

[0152] In the 46th example, for any one of the 42 to 45 examples, individual lands among the plurality of lands include regions of a metal layer separated from adjacent regions of a continuous metal layer by a masking material.

[0153] In the 47th example, the computing system includes a processor IC having a first surface coupled to a first surface of a package substrate by a plurality of first electrical interconnects. The system includes a thermal diffuser having a first surface coupled to a second surface of the processor IC through a plurality of thermal interconnects. The thermal interconnects comprise a solder alloy, and individual thermal interconnects of the thermal interconnects contact corresponding thermal interconnect lands among a plurality of thermal interconnect lands distributed over the second surface of the processor IC. The system includes a heat exchanger coupled to the second surface of the thermal diffuser. The system includes a host board coupled to the second surface of the package substrate by a plurality of second electrical interconnects.

[0154] In the 48th example, for any one of the 47 examples, the heat exchanger includes a finned heat sink, a cold plate, or a heat pipe.

[0155] In the 49th example, for any one of the 47th to 48th examples, the system further includes a memory IC adjacent to the processor IC. A first side of the memory IC is coupled to a first side of the package substrate by a second plurality of first electrical interconnects. A first side of the thermal diffuser is further coupled to a second side of the memory IC through a second plurality of thermal interconnects.

[0156] In the 50th example, for any one of the 47 to 49 examples, the peripheral portion of the thermal diffuser beyond the edge of the processor IC is bonded to the peripheral portion of the package substrate through one or more solder balls or through package reinforcement.

[0157] In the 51st example, for any one of the 47th to 50th examples, the thermal diffuser comprises a conductive material and is electrically coupled to the voltage potential of the package substrate through solder balls.

[0158] In the 52nd example, the integrated circuit (IC) device assembly comprises a package substrate, an IC die having a first surface electrically coupled to the package substrate through a plurality of first-level electrical interconnects, and a thermal diffuser coupled to a second surface of the IC die through a plurality of thermal interconnects comprising a solder alloy, wherein at least one of the thermal diffuser and the second surface of the IC die comprises a plurality of thermal interconnect lands, and individual lands among the lands contact corresponding thermal interconnects among the thermal interconnects.

[0159] In the 53rd example, the IC die is a first IC die, and the assembly further includes a second IC die laterally adjacent to the first IC die. The first IC die has a first die thickness, and the second IC die has a second die thickness greater than the first die thickness. A first land among the lands is located between the first IC die and the thermal diffuser, and a second land among the lands is located between the second IC die and the thermal diffuser. A first thermal interconnect among the thermal interconnects is coupled to a first land among the lands, and a second thermal interconnect among the thermal interconnects is coupled to a second land among the lands. A first z-height equal to the thickness of the first solder land among the solder lands, which is summed with the thickness of the first thermal interconnect among the thermal interconnects, is greater than a second z-height equal to the thickness of the second land among the lands, which is summed with the thickness of the second thermal interconnect among the thermal interconnects.

[0160] In the 54th example, for any one of the 53 examples, there is a difference of at least 250 μm between the first die thickness and the second die thickness, and the difference between the first and second z-heights is substantially the same as the difference between the first and second die thicknesses.

[0161] In the 55th example, for any one of the 54 examples, the thickness of the first land among the lands is substantially the same as the thickness of the second land among the lands.

[0162] In the 56th example, for any one of the 55 examples, individual lands among the plurality of lands have a thickness of 100 μm or less.

[0163] In the 57th example, for any one of the 54 examples, the thickness of the first column interconnect among the column interconnects is substantially the same as the thickness of the second column interconnect among the column interconnects.

[0164] In the 58th example, for any one of the 57 examples, individual thermal interconnects among the plurality of thermal interconnects have a thickness of 100 μm or less.

[0165] In the 59th example, for any one of the 53 examples, individual lands among the plurality of lands include regions of a continuous metal layer separated from adjacent regions of a continuous metal layer by a masking material.

[0166] In the 60th example, for any one of the 59 examples, the masking material includes solder resist.

[0167] In the 61st example, for any one of the 53 examples, a plurality of lands include a plurality of discrete metal features spaced apart over the surface of an IC die or a thermal diffuser, and a first part of the IC die or a thermal diffuser is between adjacent metal features among the metal features.

[0168] In the 62nd example, for any one of the 53rd to 61st examples, the first metal of the lands is in direct contact with the non-metallic material of the thermal diffuser or IC die.

[0169] In the 63rd example, for any one of the 62nd examples, the first metal of the lands is in direct contact with the non-metallic material of the heat diffuser.

[0170] In the 64th example, for any one of the 63 examples, the non-metallic material comprises a graphite sheet having a thickness of 25 μm or less.

[0171] In the 65th example, for any one of the 62 examples, the first metal of the lands is in direct contact with the crystalline substrate material of the IC die.

[0172] In the 66th example, for any one of the 65 examples, a plurality of lands include a plurality of spaced discrete metal features on a second face of the IC die, and a first portion of the crystalline substrate material of the IC die is between adjacent metal features among the metal features.

[0173] In the 67th example, for any one of the 66 examples, the surface of the first portion of the crystalline substrate material is resized below the plane of the interface between the adjacent metal feature among the metal features and the second portion of the crystalline substrate material.

[0174] In the 68th example, the integrated circuit (IC) die thermal diffuser comprises a plurality of thermal interconnect lands on a first surface of the thermal diffuser, and the plurality of lands comprises one or more metal layers. The thermal diffuser comprises a plurality of thermal interconnects comprising a solder alloy, and individual thermal interconnects among the thermal interconnects contact corresponding lands among the lands. The thickness of at least one of the lands or thermal interconnects varies between a first region of the thermal diffuser coupled to a first IC die of a first die thickness and a second region of the thermal diffuser coupled to a second IC die of a second die thickness different from the first die thickness.

[0175] In the 69th example, for any one of the 68 examples, the heat diffuser further comprises a graphite sheet in contact with the lands, and the sheet has a thickness of 25 μm or less.

[0176] In the 70th example, for any one of the 68th to 69th examples, the heat diffuser further comprises a metal in contact with a second surface of a sheet facing a first surface.

[0177] In the 71st example, for any one of the 68 examples, a plurality of lands include a plurality of discrete metal features spaced apart on the first surface of the sheet.

[0178] In the 72nd example, for any one of the 68 examples, individual lands among the plurality of lands include regions of a metal layer separated from adjacent regions of a continuous metal layer by a masking material.

[0179] In the 73rd example, for any one of the 68 examples, there is a difference of at least 250 μm between the first die thickness and the second die thickness, and the thickness of at least one of the lands or thermal interconnects varies between the first region and the second region of the thermal diffuser by an amount substantially equal to the difference between the first and second die thicknesses.

[0180] In the 74th example, for any one of the 73rd examples, the thickness of the first land among the lands is substantially the same as the thickness of the second land among the lands.

[0181] In the 75th example, for any one of the 73 examples, the thickness of the first column interconnect among the column interconnects is substantially the same as the thickness of the second column interconnect among the column interconnects.

[0182] In the 76th example, the computing system comprises a package substrate, a processor IC die having a first surface electrically coupled to the package substrate via a first plurality of first-level electrical interconnects, a memory IC die having a first surface electrically coupled to the package substrate via a second plurality of first-level electrical interconnects, and a thermal diffuser coupled to a second surface of both the processor IC die and the memory IC die via a plurality of thermal interconnects comprising a solder alloy. At least one of the second surfaces of the processor IC die and the memory IC die comprises a plurality of thermal interconnect lands, and individual lands among the lands contact corresponding thermal interconnects among the thermal interconnects. The system comprises a heat exchanger coupled to the thermal diffuser, and a host board coupled to the second surface of the package substrate by a plurality of second electrical interconnects.

[0183] In the 77th example, for any one of the 76 examples, the peripheral portion of the thermal diffuser beyond the edge of the processor IC is bonded to the peripheral portion of the package substrate through one or more solder balls or through package reinforcement.

[0184] However, the above embodiments are not limited in this regard, and in various implementations, the above embodiments may include taking only a subset of such features, taking a different order of such features, taking a different combination of such features, and / or taking additional features other than those explicitly listed. Accordingly, the scope of the invention should be determined by referring together to the entire scope of the appended claims and the equivalents given to such claims.

Claims

Claim 1 An integrated circuit (IC) device assembly comprising: a package substrate; an IC die having a first surface electrically coupled to the package substrate through a plurality of first interconnects; and a thermal diffuser coupled to a second surface of the IC die through a plurality of second interconnects comprising a solder alloy, wherein the thermal diffuser comprises a plurality of metal lands, and individual lands among the plurality of metal lands contact corresponding second interconnects among the plurality of second interconnects. Claim 2 In claim 1, the IC die is a first IC die, and the assembly further comprises a second IC die laterally adjacent to the first IC die; the first IC die has a first die thickness, and the second IC die has a second die thickness greater than the first die thickness; among the plurality of metal lands, the first land is located between the first IC die and the thermal diffuser, and among the plurality of metal lands, the second land is located between the second IC die and the thermal diffuser; An IC device assembly in which a first interconnect among a plurality of second interconnects is coupled to a first land among a plurality of metal lands, and a second interconnect among a plurality of second interconnects is coupled to a second land among a plurality of metal lands; and a first z-height equal to the thickness of the first land among the plurality of metal lands, which is added to the thickness of the first interconnect among the plurality of second interconnects, is greater than a second z-height equal to the thickness of the second land among the plurality of metal lands, which is added to the thickness of the second interconnect among the plurality of second interconnects. Claim 3 An IC device assembly according to claim 2, wherein there is a difference of at least 250 μm between the first die thickness and the second die thickness; and the difference between the first and second z-heights is substantially the same as the difference between the first and second die thicknesses. Claim 4 An IC device assembly according to paragraph 3, wherein the thickness of the first land among the plurality of metal lands is substantially the same as the thickness of the second land among the plurality of metal lands. Claim 5 An IC device assembly according to claim 4, wherein individual lands among the plurality of metal lands have a thickness of 100 μm or less. Claim 6 An IC device assembly according to paragraph 3, wherein the thickness of the first interconnect among the plurality of second interconnects is substantially the same as the thickness of the second interconnect among the plurality of second interconnects. Claim 7 In claim 6, the IC device assembly wherein individual interconnects among the plurality of second interconnects have a thickness of 100 μm or less. Claim 8 An IC device assembly according to claim 1, wherein individual lands among the plurality of metal lands include regions of a continuous metal layer that are laterally spaced from adjacent regions of a continuous metal layer by a masking material. Claim 9 In claim 8, the above masking material comprises a solder resist, an IC device assembly. Claim 10 An IC device assembly according to claim 1, wherein the plurality of metal lands comprises a plurality of spaced discrete metal features on the surface of the heat diffuser, and the first portion of the heat diffuser is located between adjacent metal features among the metal features. Claim 11 An IC device assembly according to claim 1, wherein the plurality of metal lands comprises a metal that is in direct contact with a non-metallic material of the thermal diffuser or the IC die. Claim 12 In claim 11, the above metal is in direct contact with the non-metallic material of the heat diffuser, in an IC device assembly. Claim 13 In claim 12, the IC device assembly comprises a graphite sheet having a thickness of 25 μm or less, wherein the non-metallic material comprises the graphite sheet. Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 An integrated circuit (IC) die heat diffuser comprising: a plurality of interconnect lands on a first surface of the heat diffuser, wherein individual lands among the plurality of interconnect lands comprise one or more metal layers; and a plurality of interconnects comprising a solder alloy, wherein individual interconnects among the plurality of interconnects are in contact with corresponding lands among the plurality of interconnect lands, and the thickness of at least one of the plurality of interconnect lands or the plurality of interconnects varies between a first region of the heat diffuser and a second region of the heat diffuser. Claim 18 In claim 17, the thermal diffuser further comprises a graphite sheet in contact with the plurality of interconnect lands, and the graphite sheet has a thickness of 25 μm or less, an IC die thermal diffuser. Claim 19 In claim 18, the IC die heat diffuser further comprises a metal in contact with a second surface of the graphite sheet facing the first surface. Claim 20 An IC die thermal diffuser according to claim 18, wherein the plurality of interconnect lands comprises a plurality of discrete metal features spaced apart on the first surface of the graphite sheet. Claim 21 An IC die thermal diffuser according to claim 17, wherein individual lands among the plurality of interconnect lands comprise regions of a continuous metal layer that are laterally spaced from adjacent regions of a continuous metal layer by a masking material. Claim 22 An IC die thermal diffuser according to claim 17, wherein the thickness varies by at least 250 μm between the first region of the thermal diffuser and the second region of the thermal diffuser. Claim 23 An IC die thermal diffuser according to claim 22, wherein the thickness of the first land among the plurality of interconnect lands is substantially the same as the thickness of the second land among the plurality of interconnect lands. Claim 24 An IC die thermal diffuser according to claim 22, wherein the thickness of the first interconnect among the plurality of interconnects is substantially the same as the thickness of the second interconnect among the plurality of interconnects. Claim 25 A computing system comprising: a package substrate; a processor IC die having a first surface electrically coupled to the package substrate through a plurality of first interconnects; a memory IC die having a first surface electrically coupled to the package substrate through a plurality of first interconnects; a heat diffuser coupled to a second surface of both the processor IC die and the memory IC die through a plurality of second interconnects comprising a solder alloy, wherein the heat diffuser comprises a plurality of interconnect lands, and individual lands among the plurality of interconnect lands contact corresponding second interconnects among the plurality of second interconnects; a heat exchanger coupled to the heat diffuser; and a host board coupled to a second surface of the package substrate by a plurality of third interconnects.

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