Semiconductor memory device and operating method thereof

Abstract

A semiconductor memory device includes a memory cell array, peripheral circuitry, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuitry is configured to perform program operations and read operations for the memory cell array. The control logic is configured to control the operation of the peripheral circuitry. The control logic controls the peripheral circuitry to perform an SLC program operation for memory cells included in a selected page among the plurality of memory cells, compares a first number of fail bits counted by performing a general sensing operation on the selected page with a second number of fail bits counted by performing a multi-sensing operation on the selected page, and corrects at least one evaluation time to be used for a read operation based on the comparison result.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a semiconductor memory device and a method of operating the same. Background Technology

[0002] A semiconductor memory device may be formed as a two-dimensional structure in which strings are arranged horizontally on a semiconductor substrate, or as a three-dimensional structure in which strings are stacked vertically on a semiconductor substrate. A three-dimensional semiconductor memory device is a memory device designed to overcome the integration density limitations of a two-dimensional semiconductor memory device and may include a plurality of memory cells stacked vertically on a semiconductor substrate. Prior art literature

[65535] Published Patent Application No. 10-2014-0063146 (May 27, 2014) The problem to be solved

[0003] An embodiment of the present invention provides a semiconductor memory device capable of improving read performance and a method of operating the same. means of solving the problem

[0004] A semiconductor memory device according to one embodiment of the present invention includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a program operation and a read operation for the memory cell array. The control logic is configured to control the operation of the peripheral circuit. The control logic controls the peripheral circuit to perform an SLC program operation for memory cells included in a selected page among the plurality of memory cells, compares a first number of fail bits counted by performing a general sensing operation for the selected page with a second number of fail bits counted by performing a multi-sensing operation for the selected page, and corrects at least one evaluation time to be used for a read operation based on the comparison result.

[0005] A method of operating a semiconductor memory device comprising a plurality of memory cells according to another embodiment of the present invention comprises: performing an SLC program operation for selected memory cells among the plurality of memory cells; performing a general sensing operation based on a first voltage for the selected memory cells; counting a first number of fail bits based on the general sensing operation; performing a multi-sensing operation based on the first voltage and an auxiliary voltage smaller than the first voltage for the selected memory cells; counting a second number of fail bits based on the multi-sensing operation; and determining a correction method for an evaluation time used in a read operation based on the first number of fail bits and the second number of fail bits. Effects of the invention

[0006] The present technology can provide a semiconductor memory device capable of improving read performance and a method of operating the same. Brief explanation of the drawing

[0007] FIG. 1 is a block diagram showing a memory system including a controller and a semiconductor memory device. FIG. 2 is a block diagram showing an exemplary embodiment of the semiconductor memory device of FIG. 1. FIG. 3 is a block diagram showing one embodiment of the memory cell array (110) of FIG. 2. FIG. 4 is a circuit diagram showing one of the memory blocks (BLKa) among the memory blocks (BLK1~BLKz) of FIG. 3. FIG. 5 is a circuit diagram showing another embodiment of a memory block (BLKb) among the memory blocks (BLK1~BLKz) of FIG. 3. FIG. 6 is a circuit diagram showing an example of one memory block (BLKc) among a plurality of memory blocks (BLK1~BLKz) included in the memory cell array (110) of FIG. 2. Figures 7a and 7b are diagrams illustrating the verification operation of the entire bit line sensing method and the voltage compensation in the subsequent read operation. Figures 8a and 8b are diagrams illustrating the evaluation time correction method when the effect of the reference current downsizing is dominant and when the effect of the source line noise is dominant during verification using the full bit line sensing method. Figures 9a and 9b are diagrams illustrating the verification operation of the select bit line sensing method and the voltage compensation in the subsequent read operation. FIGS. 10a and FIGS. 10b are diagrams illustrating the evaluation time correction method when the effect of the reference current down is dominant and when the effect of the source line noise is dominant during verification using the selected bit line sensing method. FIG. 11 is a flowchart illustrating a method of operation of a semiconductor memory device according to one embodiment of the present invention. FIG. 12a is a diagram illustrating the difference in the number of fail bits between normal sensing operation and multi-sensing operation when the effect of reference current downsizing is dominant in the full bit line sensing method. FIG. 12b is a diagram illustrating the difference in the number of fail bits between normal sensing operation and multi-sensing operation when the effect of source line noise is dominant in the full bit line sensing method. FIG. 13 is a flowchart illustrating an exemplary embodiment of step (S160) of FIG. 11. FIGS. 14a and FIGS. 14b are flowcharts illustrating exemplary embodiments of steps (S250) and (S270) of FIG. 13, respectively. FIG. 15 is a flowchart illustrating another exemplary embodiment of step (S160) of FIG. 11. FIGS. 16a and FIGS. 16b are flowcharts illustrating exemplary embodiments of steps (S350) and (S370) of FIG. 15, respectively. FIGS. 17a and FIGS. 17b are drawings for explaining the multi-sensing operation and general sensing operation described in FIG. 11. FIGS. 18a and FIGS. 18b are flowcharts for explaining multi-sensing operation and general sensing operation, respectively. FIG. 19 is a block diagram showing a memory system (1000) including the semiconductor memory device (100) of FIG. 2. Figure 20 is a block diagram showing an application example of the memory system of Figure 19. FIG. 21 is a block diagram showing a computing system including a memory system described with reference to FIG. 20. Specific details for implementing the invention

[0008] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0010] FIG. 1 is a block diagram showing a memory system including a controller and a semiconductor memory device.

[0011] Referring to FIG. 1, the memory system (1000) includes a semiconductor memory device (100) and a controller (200). The memory system (1000) also communicates with a host (300). Additionally, the controller (200) controls the general operation of the semiconductor memory device (100) by transmitting commands (CMDs) based on requests received from the host (300). Additionally, the controller (200) transmits data (DATA) corresponding to each command (CMD) to the semiconductor memory device (100) or receives it from the semiconductor memory device (100). For example, when a program request and program data are received from the host (300), the controller (200) transmits the corresponding program command and program data to the semiconductor memory device (100). In another example, when a read request is received from the host (300), the controller (200) transmits the corresponding read command to the semiconductor memory device (100). Afterwards, the semiconductor memory device (100) transmits read data corresponding to the read command to the controller (200).

[0012] When the memory system (1000) transitions from a turn-off state to a turn-on state, a boot operation of the memory system (1000) may be performed. The boot operation of the memory system (1000) may include scanning the current state of a plurality of memory blocks included in the semiconductor memory device (100) and storing the state of each scanned memory block in memory within the controller (200). For example, the plurality of memory blocks included in the semiconductor memory device (100) may be in any one of an erased state, a programmed state, or an open state. If data is not stored in any of the physical pages included in the memory block, and all cells included in the memory block are in an erased state, the memory block is in an erased state. If data is stored in all of the physical pages included in the memory block, the memory block is in a programmed state. If data is stored in some of the physical pages included in the memory block and data is not stored in some of the physical pages included in the memory block, the memory block is in an open state. The state of a memory block can be determined by sequentially reading the data of the pages included in the memory block. To this end, the controller (200) can generate a plurality of read commands for reading the data of the pages included in the memory block and transmit them to the semiconductor memory device (100). The semiconductor memory device (100) can perform a read operation corresponding to the received read command and transmit the read data as a result of the read operation to the controller (200).

[0014] FIG. 2 is a block diagram showing an exemplary embodiment of the semiconductor memory device of FIG. 1.

[0015] Referring to FIG. 2, the semiconductor memory device (100) includes a memory cell array (110), an address decoder (120), a read and write circuit (130), control logic (140), and a voltage generation unit (150).

[0016] A memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) are connected to an address decoder (120) via word lines (WL). The plurality of memory blocks (BLK1 to BLKz) are connected to a read and write circuit (130) via bit lines (BL1 to BLm). Each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of memory cells. As an example, the plurality of memory cells are non-volatile memory cells and may be composed of non-volatile memory cells having a vertical channel structure. The memory cell array (110) may be composed of a memory cell array with a two-dimensional structure. According to an example, the memory cell array (110) may be composed of a memory cell array with a three-dimensional structure. Meanwhile, each of the plurality of memory cells included in the memory cell array may store at least 1 bit of data. In one embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a single-level cell (SLC) that stores 1 bit of data. In another embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a multi-level cell (MLC) that stores 2 bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a triple-level cell (TLC) that stores 3 bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a quad-level cell (QLC) that stores 4 bits of data. According to an embodiment, the memory cell array (110) may include a plurality of memory cells that each store 5 bits or more of data.

[0017] The address decoder (120), the read and write circuit (130), and the voltage generation unit (150) operate as peripheral circuits that drive the memory cell array (110). At this time, the peripheral circuits operate under the control of the control logic (140). The address decoder (120) is connected to the memory cell array (110) through word lines (WL). The address decoder (120) is configured to operate in response to the control of the control logic (140). The address decoder (120) receives an address through an input / output buffer (not shown) inside the semiconductor memory device (100).

[0018] The address decoder (120) is configured to decode a block address among the received addresses. The address decoder (120) selects at least one memory block according to the decoded block address. Additionally, during a read operation, when a read voltage is applied, the address decoder (120) applies a read voltage (Vread) generated by the voltage generator (150) to the selected word line among the selected memory blocks, and applies a pass voltage (Vpass) to the remaining unselected word lines. Additionally, during a program verification operation, when a verification voltage generated by the voltage generator (150) is applied to the selected word line among the selected memory blocks, and applies a pass voltage (Vpass) to the remaining unselected word lines.

[0019] The address decoder (120) is configured to decode the column address among the received addresses. The address decoder (120) transmits the decoded column address to the read and write circuit (130).

[0020] The read operation and program operation of the semiconductor memory device (100) are performed in page units. The address received when the read operation and program operation request is made includes a block address, a row address, and a column address. The address decoder (120) selects one memory block and one word line according to the block address and the row address. The column address is decoded by the address decoder (120) and provided to the read and write circuit (130). Multiple memory cells connected to one word line can form one physical page. If each of the multiple memory cells included in the semiconductor memory device is a single-level cell (SLC) that stores one bit, one logical page data can be stored in one physical page. In the case where each of the multiple memory cells included in a semiconductor memory device is a multi-level cell (MLC) that stores two bits, two logical page data, for example, MSB (Most Significant Bit) page data and LSB (Least Significant Bit) page data, can be stored in a single physical page. In the case where each of the multiple memory cells included in a semiconductor memory device is a triple-level cell (TLC) that stores three bits, three logical page data, for example, MSB page data, CSB (Central Significant Bit) page data, and LSB page data, can be stored in a single physical page.In the case where each of the multiple memory cells included in a semiconductor memory device is a quad-level cell (QLC) that stores four bits, one physical page may store four logical page data, for example, MSB page data, HCSB (High Central Significant Bit) page data, LCSB (Low Central Significant Bit) page data, and LSB page data.

[0021] The address decoder (120) may include a block decoder, a row decoder, a column decoder, and an address buffer, etc.

[0022] The read and write circuit (130) includes a plurality of page buffers (PB1 to PBm). The read and write circuit (130) can operate as a “read circuit” during a read operation of the memory cell array (110) and as a “write circuit” during a write operation. The plurality of page buffers (PB1 to PBm) are connected to the memory cell array (110) through bit lines (BL1 to BLm). The plurality of page buffers (PB1 to PBm) continuously supply sensing current to the bit lines connected to the memory cells to sense the threshold voltage of the memory cells during a read operation and a program verification operation, and latches the sensing data by detecting through a sensing node that the amount of current flowing changes according to the program state of the corresponding memory cell. The read and write circuit (130) operates in response to page buffer control signals output from the control logic (140).

[0023] The read and write circuit (130) senses data in a memory cell during a read operation, temporarily stores the read data, and then outputs the data (DATA) to an input / output buffer (not shown) of a semiconductor memory device (100). As an exemplary embodiment, the read and write circuit (130) may include a column selection circuit, etc., in addition to page buffers (or page registers).

[0024] The control logic (140) is connected to an address decoder (120), a read and write circuit (130), and a voltage generator (150). The control logic (140) receives a command (CMD) and a control signal (CTRL) through an input / output buffer (not shown) of the semiconductor memory device (100). The control logic (140) is configured to control the general operation of the semiconductor memory device (100) in response to the control signal (CTRL). Additionally, the control logic (140) outputs a control signal to adjust the sensing node precharge potential level of a plurality of page buffers (PB1~PBm). The control logic (140) can control the read and write circuit (130) to perform a read operation of the memory cell array (110). The control logic controls the voltage generator (150) to generate various voltages used during the program operation of the memory cell array (110). Additionally, the control logic (140) controls the address decoder (120) to transmit voltages generated from the voltage generation unit (150) to the local lines of the memory block to be operated through the global lines. Meanwhile, the control logic (140) controls the read and write circuit (130) to read data from the selected page of the memory block through the bit lines (BL1~BLm) during a read operation and store it in the page buffer (PB1~PBm). Additionally, the control logic (140) controls the read and write circuit (130) to program the data stored in the page buffer (PB1~PBm) to the selected page during a program operation.

[0025] The voltage generation unit (150) generates a read voltage (Vread) and a pass voltage (Vpass) during a read operation in response to a control signal output from the control logic (140). To generate multiple voltages having various voltage levels, the voltage generation unit (150) includes multiple pumping capacitors that receive an internal power supply voltage, and will generate multiple voltages by selectively activating the multiple pumping capacitors in response to the control of the control logic (140).

[0026] The address decoder (120), the read and write circuit (130), and the voltage generation unit (150) can function as "peripheral circuits" that perform read, write, and erase operations on the memory cell array (110). The peripheral circuits perform read, write, and erase operations on the memory cell array (110) based on the control of the control logic (140).

[0028] FIG. 3 is a block diagram showing one embodiment of the memory cell array (110) of FIG. 2.

[0029] Referring to FIG. 3, the memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). Each memory block has a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. These plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. The structure of each memory block is described in more detail with reference to FIG. 4 and FIG. 5.

[0031] FIG. 4 is a circuit diagram showing one of the memory blocks (BLKa) among the memory blocks (BLK1~BLKz) of FIG. 3.

[0032] Referring to FIG. 4, the memory block (BLKa) includes a plurality of cell strings (CS11–CS1m, CS21–CS2m). As an example, each of the plurality of cell strings (CS11–CS1m, CS21–CS2m) may be formed in a 'U' shape. Within the memory block (BLKa), m cell strings are arranged in the row direction (i.e., +X direction). In FIG. 3, two cell strings are shown arranged in the column direction (i.e., +Y direction). However, this is for convenience of explanation, and it will be understood that three or more cell strings may be arranged in the column direction.

[0033] Each of the plurality of cell strings (CS11~CS1m, CS21~CS2m) includes at least one source select transistor (SST), first to n memory cells (MC1~MCn), a pipe transistor (PT), and at least one drain select transistor (DST).

[0034] Each of the select transistors (SST, DST) and memory cells (MC1~MCn) may have a similar structure. As an example, each of the select transistors (SST, DST) and memory cells (MC1~MCn) may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an example, a pillar for providing a channel layer may be provided in each cell string. As an example, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

[0035] The source select transistor (SST) of each cell string is connected between the common source line (CSL) and the memory cells (MC1~MCp).

[0036] As an example, source select transistors of cell strings arranged in the same row are connected to a source select line extending in the row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. In FIG. 4, source select transistors of cell strings (CS11–CS1m) of the first row are connected to a first source select line (SSL1). Source select transistors of cell strings (CS21–CS2m) of the second row are connected to a second source select line (SSL2).

[0037] As another embodiment, the source selection transistors of the cell strings (CS11~CS1m, CS21~CS2m) can be commonly connected to a single source selection line.

[0038] The first to nth memory cells (MC1 to MCn) of each cell string are connected between a source select transistor (SST) and a drain select transistor (DST).

[0039] The first to nth memory cells (MC1~MCn) can be divided into the first to pth memory cells (MC1~MCp) and the p+1~nth memory cells (MCp+1~MCn). The first to pth memory cells (MC1~MCp) are arranged sequentially in the +Z direction and in the reverse direction and are connected in series between a source select transistor (SST) and a pipe transistor (PT). The p+1~nth memory cells (MCp+1~MCn) are arranged sequentially in the +Z direction and are connected in series between a pipe transistor (PT) and a drain select transistor (DST). The first to pth memory cells (MC1~MCp) and the p+1~nth memory cells (MCp+1~MCn) are connected through a pipe transistor (PT). The gates of the first to nth memory cells (MC1~MCn) of each cell string are each connected to the first to nth word lines (WL1~WLn).

[0040] The gate of the pipe transistor (PT) of each cell string is connected to the pipeline (PL).

[0041] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and the memory cells (MCp+1 to MCn). The cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings of the first row (CS11 to CS1m) are connected to the first drain select line (DSL1). The drain select transistors of the cell strings of the second row (CS21 to CS2m) are connected to the second drain select line (DSL2).

[0042] Cell strings arranged in a column direction are connected to a bit line extending in a column direction. In FIG. 5, the cell strings of the first column (CS11, CS21) are connected to the first bit line (BL1). The cell strings of the m-th column (CS1m, CS2m) are connected to the m-th bit line (BLm).

[0043] Memory cells connected to the same word line within cell strings arranged in a row direction constitute one page. For example, among the cell strings (CS11–CS1m) of the first row, memory cells connected to the first word line (WL1) constitute one page. Among the cell strings (CS21–CS2m) of the second row, memory cells connected to the first word line (WL1) constitute another page. By selecting either of the drain selection lines (DSL1, DSL2), cell strings arranged in a row direction will be selected. By selecting any of the word lines (WL1–WLn), one page among the selected cell strings will be selected.

[0044] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m bit lines (BL1 to BLm). And among the cell strings arranged in the row direction (CS11 to CS1m or CS21 to CS2m), the even-numbered cell strings may be connected to the even bit lines, and among the cell strings arranged in the row direction (CS11 to CS1m or CS21 to CS2m), the odd-numbered cell strings may be connected to the odd bit lines.

[0045] As an example, at least one of the first to nth memory cells (MC1 to MCn) may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor (SST) and the memory cells (MC1 to MCp). Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor (DST) and the memory cells (MCp+1 to MCn). As more dummy memory cells are provided, the reliability of operation for the memory block (BLKa) is improved, while the size of the memory block (BLKa) increases. As fewer memory cells are provided, the size of the memory block (BLKa) decreases, while the reliability of operation for the memory block (BLKa) may decrease.

[0046] To efficiently control at least one dummy memory cell, each dummy memory cell may have a required threshold voltage. Program operations may be performed on all or some of the dummy memory cells before or after an erase operation on the memory block (BLKa). If an erase operation is performed after a program operation, the dummy memory cells may have a required threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0048] FIG. 5 is a circuit diagram showing another embodiment of a memory block (BLKb) among the memory blocks (BLK1~BLKz) of FIG. 3.

[0049] Referring to FIG. 5, the memory block (BLKb) includes a plurality of cell strings (CS11'~CS1m', CS21'~CS2m'). Each of the plurality of cell strings (CS11'~CS1m', CS21'~CS2m') is extended along the +Z direction. Each of the plurality of cell strings (CS11'~CS1m', CS21'~CS2m') includes at least one source select transistor (SST), first to nth memory cells (MC1~MCn), and at least one drain select transistor (DST), which are stacked on a substrate (not shown) below the memory block (BLK1').

[0050] The source select transistor (SST) of each cell string is connected between the common source line (CSL) and the memory cells (MC1 to MCn). The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings (CS11' to CS1m') arranged in the first row are connected to the first source select line (SSL1). The source select transistors of cell strings (CS21' to CS2m') arranged in the second row are connected to the second source select line (SSL2). In another embodiment, the source select transistors of cell strings (CS11' to CS1m', CS21' to CS2m') may be commonly connected to a single source select line.

[0051] The first to nth memory cells (MC1 to MCn) of each cell string are connected in series between a source select transistor (SST) and a drain select transistor (DST). The gates of the first to nth memory cells (MC1 to MCn) are each connected to the first to nth word lines (WL1 to WLn).

[0052] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and the memory cells (MC1 to MCn). The drain select transistors of the cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings of the first row (CS11' to CS1m') are connected to the first drain select line (DSL1). The drain select transistors of the cell strings of the second row (CS21' to CS2m') are connected to the second drain select line (DSL2).

[0053] Consequently, the memory block (BLKb) of FIG. 5 has an equivalent circuit similar to the memory block (BLKa) of FIG. 4, except that the pipe transistor (PT) is excluded from each cell string.

[0054] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m bit lines (BL1 to BLm). And among the cell strings arranged in the row direction (CS11' to CS1m' or CS21' to CS2m'), the even-numbered cell strings may be connected to the even bit lines, and among the cell strings arranged in the row direction (CS11' to CS1m' or CS21' to CS2m'), the odd-numbered cell strings may be connected to the odd bit lines.

[0055] As an example, at least one of the first to nth memory cells (MC1 to MCn) may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor (SST) and the memory cells (MC1 to MCn). Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor (DST) and the memory cells (MC1 to MCn). As more dummy memory cells are provided, the reliability of operation for the memory block (BLKb) is improved, while the size of the memory block (BLKb) increases. As fewer memory cells are provided, the size of the memory block (BLKb) decreases, while the reliability of operation for the memory block (BLKb) may decrease.

[0056] To efficiently control at least one dummy memory cell, each dummy memory cell may have a required threshold voltage. Program operations may be performed on all or some of the dummy memory cells before or after an erase operation on the memory block (BLKb). If an erase operation is performed after a program operation, the dummy memory cells may have a required threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0058] FIG. 6 is a circuit diagram showing an example of one memory block (BLKc) among a plurality of memory blocks (BLK1~BLKz) included in the memory cell array (110) of FIG. 2.

[0059] Referring to FIG. 6, a memory block (BKLc) includes a plurality of cell strings (CS1 to CSm). The plurality of cell strings (CS1 to CSm) can each be connected to a plurality of bit lines (BL1 to BLm). Each of the plurality of cell strings (CS1 to CSm) includes at least one source select transistor (SST), first to nth memory cells (MC1 to MCn), and at least one drain select transistor (DST).

[0060] Each of the select transistors (SST, DST) and memory cells (MC1~MCn) may have a similar structure. As an example, each of the select transistors (SST, DST) and memory cells (MC1~MCn) may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an example, a pillar for providing a channel layer may be provided in each cell string. As an example, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

[0061] The source select transistor (SST) of each cell string is connected between the common source line (CSL) and the memory cells (MC1~MCn).

[0062] The first to nth memory cells (MC1 to MCn) of each cell string are connected between a source select transistor (SST) and a drain select transistor (DST).

[0063] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and the memory cells (MC1~MCn).

[0064] Memory cells connected to the same word line constitute one page. Cell strings (CS1–CSm) will be selected by selecting the drain selection line (DSL). One page of the selected cell strings will be selected by selecting any one of the word lines (WL1–WLn).

[0065] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines (BL1 to BLm). Among the cell strings (CS1 to CSm), the even-numbered cell strings may be connected to the even-bit lines, and the odd-numbered cell strings may be connected to the odd-bit lines.

[0066] As illustrated in FIGS. 3 to 5, the memory cell array (110) of the semiconductor memory device (100) may be configured as a memory cell array with a three-dimensional structure. Additionally, as illustrated in FIG. 6, the memory cell array (110) of the semiconductor memory device (100) may be configured as a memory cell array with a two-dimensional structure.

[0068] Figures 7a and 7b are diagrams illustrating the verification operation of the entire bit line sensing method and the voltage compensation in the subsequent read operation.

[0069] Referring to FIG. 7a, the threshold voltage distribution of memory cells during a program operation is illustrated. In FIG. 7a, the memory cells are TLCs capable of storing three bits each. Therefore, when the program operation is completed, the threshold voltage of each memory cell will have either an erase state (E) or one of the first to seventh program states (PV1 to PV7). FIG. 7a illustrates a situation in which, during the program operation, the programming for the first and second program states (PV1, PV2) is completed, but the programming for the third to seventh program states (PV3 to PV7) is not completed, and a verification operation for the third program state (PV3) is performed. To perform the verification operation for the third program state (PV3), a third verification voltage (VFY3) will be applied to a selected word line.

[0070] In FIG. 7a, all bit lines are precharged during the verification operation. That is, in the process of verifying whether the memory cells to be programmed into the third program state (PV3) are fully programmed, all bit lines connected to the memory cells to be programmed into the third program state (PV3) as well as the remaining memory cells are precharged together.

[0071] Meanwhile, referring to FIG. 7b, a situation is illustrated in which a third read voltage (V3) is applied for a read operation after the program operation is completed. As the third read voltage is applied, memory cells having a threshold voltage lower than the third read voltage and memory cells having a threshold voltage higher than the third read voltage are distinguished. That is, due to the application of the third read voltage, memory cells belonging to either the erase state (E) or the first and second program states (PV1, PV2) and memory cells belonging to the third to seventh program states (PV3~PV7) are distinguished.

[0072] Comparing FIG. 7a and FIG. 7b, the threshold voltage distribution of memory cells during the verification operation differs from the threshold voltage distribution of memory cells after the program is completed. That is, since the threshold voltage state of memory cells during the verification operation differs from the threshold voltage state of memory cells during the read operation, a difference in the reference current used in the sensing operation may occur. For example, during the verification operation for the first program state (PV1), most memory cells are in a relatively low threshold voltage state, so there is a significant difference from the threshold voltage distribution of memory cells in the state where the program is completed. On the other hand, during the verification operation for the seventh program state (PV7), the memory cells in the erase state (E) and the first to sixth program states (PV1~PV6) have completed their distribution formation, so there is a small difference from the threshold voltage distribution of memory cells in the state where the program is completed. Accordingly, it is necessary to individually compensate for the evaluation time in the sensing operation corresponding to each program state during the read operation.

[0074] Figures 8a and 8b are diagrams illustrating the evaluation time correction method when the effect of the reference current downsizing is dominant and when the effect of the source line noise is dominant during verification using the full bit line sensing method.

[0075] Referring to FIG. 8a, an evaluation time correction method is illustrated when the effect of the reference current downsizing is more dominant than the effect of the source line noise when using a full bit line sensing method. When the effect of the reference current downsizing is more dominant than the effect of the source line noise, it is necessary to increase the evaluation time in the overall read operation compared to the evaluation time used during the verification operation. In this case, since the threshold voltage distribution state of the memory cells during the verification of the first program state (PV1) differs most significantly from the threshold voltage distribution state after programming, the increase in the evaluation time during the sensing operation using the first read voltage is set to be the largest, and conversely, the increase in the evaluation time during the sensing operation using the seventh read voltage is set to be the smallest. That is, the evaluation time (tEV - R1) corresponding to the first read voltage becomes a value increased by the first time width (Δt1) compared to the evaluation time (tEV - VFY1~VFY7) used during the verification operation. Meanwhile, the evaluation time (tEV - R7) corresponding to the 7th lead voltage is a value increased by the second time width (Δt2) compared to the evaluation time (tEV - VFY1~VFY7) used during the verification operation. Here, the first time width (Δt1) is a value greater than the second time width (Δt2).

[0076] In FIG. 8a, for convenience, only the evaluation time of the sensing operation using the first lead voltage and the evaluation time of the sensing operation using the seventh lead voltage are shown, but it will be seen that the evaluation time corresponding to the second to sixth lead voltages can be applied with a size that decreases sequentially between the evaluation time corresponding to the first and seventh lead voltages.

[0077] Referring to FIG. 8b, an evaluation time correction method is illustrated when the effect of source line noise is more dominant than the effect of reference current downsizing when using a full bit line sensing method. When the effect of source line noise is more dominant than the effect of reference current downsizing, it is necessary to reduce the evaluation time in the overall read operation compared to the evaluation time used during the verification operation. In this case, the reduction range of the evaluation time during the sensing operation using the first read voltage is set to the largest, and conversely, the reduction range of the evaluation time during the sensing operation using the seventh read voltage is set to the smallest. That is, the evaluation time (tEV - R1) corresponding to the first read voltage becomes a value reduced by the third time width (Δt3) compared to the evaluation time (tEV - VFY1~VFY7) used during the verification operation. Meanwhile, the evaluation time (tEV - R7) corresponding to the 7th lead voltage is a value reduced by the 4th time width (Δt4) compared to the evaluation time (tEV - VFY1~VFY7) used during the verification operation. Here, the 3rd time width (Δt3) is a value greater than the 4th time width (Δt4).

[0079] Figures 9a and 9b are diagrams illustrating the verification operation of the select bit line sensing method and the voltage compensation in the subsequent read operation.

[0080] Referring to FIG. 9a, the threshold voltage distribution of memory cells during a program operation is illustrated. In FIG. 9a, the memory cells are TLCs capable of storing three bits each. Therefore, when the program operation is completed, the threshold voltage of each memory cell will have either an erase state (E) or one of the first to seventh program states (PV1 to PV7). FIG. 9a illustrates a situation in which, during the program operation, the programming for the first and second program states (PV1, PV2) is completed, but the programming for the third to seventh program states (PV3 to PV7) is not completed, and a verification operation for the third program state (PV3) is performed. To perform the verification operation for the third program state (PV3), a third verification voltage (VFY3) will be applied to a selected word line.

[0081] In FIG. 9a, only the selected bit lines are precharged during the verification operation. That is, during the process of verifying whether the memory cells to be programmed into the third program state (PV3) are fully programmed, all bit lines connected to the cells that are not yet fully programmed among the memory cells to be programmed into the third program state (PV3) are precharged together. The shaded area in FIG. 9a represents the number of cells that are not yet fully programmed among the memory cells to be programmed into the third program state (PV3), i.e., the number of fail bit cells (N). FBC It represents ).

[0082] Meanwhile, referring to FIG. 9b, a situation is illustrated in which a third read voltage (V3) is applied for a read operation after the program operation is completed, similar to FIG. 7b. As the third read voltage is applied, memory cells having a threshold voltage lower than the third read voltage and memory cells having a threshold voltage higher than the third read voltage are distinguished. That is, due to the application of the third read voltage, memory cells belonging to either the erase state (E) or the first and second program states (PV1, PV2) and memory cells belonging to the third to seventh program states (PV3~PV7) are distinguished.

[0083] Comparing Fig. 9a and Fig. 9b, the threshold voltage distribution of memory cells during the verification operation differs from the threshold voltage distribution of memory cells after the program is completed. That is, since the threshold voltage state of memory cells during the verification operation differs from the threshold voltage state of memory cells during the read operation, a difference in the reference current used in the sensing operation may occur. Accordingly, it is necessary to individually compensate for the evaluation time in the sensing operation corresponding to each program state during the read operation.

[0085] FIGS. 10a and FIGS. 10b are diagrams illustrating the evaluation time correction method when the effect of the reference current down is dominant and when the effect of the source line noise is dominant during verification using the selected bit line sensing method.

[0086] Referring to FIG. 10a, an evaluation time correction method is illustrated when using a select bit line sensing method, in which the effect of the reference current downward is more dominant than the effect of the source line noise. When the effect of the reference current downward is more dominant than the effect of the source line noise, it is necessary to reduce the evaluation time in the overall read operation compared to the evaluation time used during the verification operation. In this case, the reduction range of the evaluation time during the sensing operation using the first read voltage is set to the smallest, and conversely, the reduction range of the evaluation time during the sensing operation using the seventh read voltage is set to the largest. That is, the evaluation time (tEV - R1) corresponding to the first read voltage becomes a value reduced by the fifth time width (Δt5) compared to the evaluation time (tEV - VFY1~VFY7) used during the verification operation. Meanwhile, the evaluation time (tEV - R7) corresponding to the 7th lead voltage is a value reduced by the 6th time width (Δt6) compared to the evaluation time (tEV - VFY1~VFY7) used during the verification operation. Here, the 5th time width (Δt5) is a value smaller than the 6th time width (Δt6).

[0087] delete

[0088] Referring to FIG. 10b, an evaluation time correction method is illustrated when using a select bit line sensing method, in which the effect of source line noise is more dominant than the effect of reference current downsizing. When the effect of source line noise is more dominant than the effect of reference current downsizing, it is necessary to increase the evaluation time in the overall lead operation compared to the evaluation time used during the verification operation. In this case, the increase range of the evaluation time during the sensing operation using the first lead voltage is set to the smallest, and conversely, the increase range of the evaluation time during the sensing operation using the seventh lead voltage is set to the largest. That is, the evaluation time (tEV - R1) corresponding to the first lead voltage becomes a value increased by the seventh time width (Δt7) compared to the evaluation time (tEV - VFY1~VFY7) used during the verification operation. Meanwhile, the evaluation time (tEV - R7) corresponding to the 7th lead voltage is a value increased by the 8th time width (Δt8) compared to the evaluation time (tEV - VFY1~VFY7) used during the verification operation. Here, the 7th time width (Δt7) is a smaller value than the 8th time width (Δt8).

[0090] FIG. 11 is a flowchart illustrating a method of operation of a semiconductor memory device according to one embodiment of the present invention.

[0091] Referring to FIG. 11, a method of operation of a semiconductor memory device according to an embodiment of the present invention comprises: a step of performing an SLC program operation for a selected page (S110); a step of performing a general sensing operation for a selected page based on a first voltage (S120); and a first fail bit number (N FB1 A step of counting ) (S130), a step of performing a multi-sensing operation for a selected page based on a first voltage and a first auxiliary voltage (S140), and a second fail bit number (N FB2The method includes a step of counting ) (S150), a step of determining an evaluation time (tEV) correction method to be used during a read operation based on the number of first and second fail bits (S160), and a step of correcting a set of evaluation times (tEV) for a read operation based on the determined correction method (S170).

[0092] In step (S110), an SLC program operation is performed on the selected page. This is a program operation to test whether the effect of the reference current downsizing or the effect of the source line noise is more dominant during the read operation for the corresponding page.

[0093] In step (S120), a general sensing operation is performed on the selected page where an SLC program operation is performed based on the first voltage. The general sensing operation may be an operation of sensing the threshold voltage of each memory cell once while the first voltage is applied to the word line connected to the selected page.

[0094] In step (S130), the number of first fail bits (N) resulting from a general sensing operation based on the first voltage FB1 Counts ). Number of first fail bits (N FB1 ) may mean the number of memory cells among the selected pages whose threshold voltage is lower than the first voltage as a result of general sensing operation.

[0095] In step (S140), a multi-sensing operation is performed on a selected page based on a first voltage and a first auxiliary voltage. The multi-sensing operation may be an operation in which, after first sensing the threshold voltage of each memory cell while applying a first auxiliary voltage smaller than the first voltage to the word line connected to the selected page, the first voltage is applied once again to the word line connected to the selected page to secondarily sense the threshold voltage of the memory cells. At this time, in the second sensing operation using the first voltage, the sensing operation is not performed for memory cells determined to be on-cell in the first sensing operation. Accordingly, erase cell noise can be suppressed as much as possible during the second sensing operation. The multi-sensing operation will be explained in more detail with reference to FIGS. 17a to 18b.

[0096] In step (S150), the number of second fail bits (N) of the multi-sensing operation result based on the first voltage and the first auxiliary voltage FB2 Counts ) the number of second fail bits (N FB2 ) may mean the number of memory cells among the memory cells included in the selected page whose threshold voltage is lower than the first voltage as a result of multi-sensing operation.

[0097] In step (S160), the first fail bit number (N FB1 ) and the number of second fail bits (N FB2 A method for correcting the evaluation time (tEV) is determined based on ). A detailed embodiment of step (S160) will be described later with reference to FIG. 13.

[0098] In step (S170), a set of evaluation times (tEV) for a read operation is corrected based on a determined correction method. In the case of TLC, since there are a total of 7 read voltages, the evaluation times (tEV) for the read operation can be determined individually for the 7 read voltages (R1 to R7). That is, the set of evaluation times (tEV) can include 7 evaluation times. Subsequently, in the read operation, a sensing operation is performed based on the set of evaluation times (tEV) corrected by step (S170).

[0099] In FIG. 11, steps (S120, S130) for counting the number of failure bits resulting therefrom and a general sensing operation are performed first, followed by steps (S140, S150) for counting the number of failure bits resulting therefrom and a multi-sensing operation are performed thereafter, but the present invention is not limited thereto. For example, after the execution of step (S110), steps (S140, S150) for counting the number of failure bits resulting therefrom and a multi-sensing operation may be performed first, followed by steps (S120, S130) for counting the number of failure bits resulting therefrom and a general sensing operation.

[0100] FIG. 12a is a diagram illustrating the difference in the number of fail bits between normal sensing operation and multi-sensing operation when the effect of reference current downsizing is dominant in the full bit line sensing method. FIG. 12b is a diagram illustrating the difference in the number of fail bits between normal sensing operation and multi-sensing operation when the effect of source line noise is dominant in the full bit line sensing method.

[0101] Referring to FIG. 12a, the threshold voltage distribution resulting from performing a general sensing operation with a first voltage (V1) on an SLC programmed page is shown as a solid line. Meanwhile, the threshold voltage distribution resulting from performing a multi-sensing operation with a first voltage (V1) on an SLC programmed page is shown as a dotted line.

[0102] That is, the number of fail bits counted during normal sensing operation with the first voltage (V1), i.e., the first number of fail bits (N FB1 ) is the number of fail bits counted during multi-sensing operation with the first voltage (V1), i.e., the number of second fail bits (N FB2 It is smaller than ). This means that the threshold voltage distribution observed during multi-sensing operation with the first voltage (V1) is shifted to the left compared to the threshold voltage distribution observed during general sensing operation with the first voltage (V1). Therefore, the read voltage used during multi-sensing operation is a first compensation voltage (V1) lower than the first voltage (V1). CP It will need to be moved to ). In this case, it means that the time to evaluation (tEV) must be increased.

[0103] Meanwhile, referring to FIG. 12b, the number of fail bits counted during normal sensing operation with the first voltage (V1), i.e., the first number of fail bits (N FB1 ) is the number of fail bits counted during multi-sensing operation with the first voltage (V1), i.e., the number of second fail bits (N FB2 It is greater than ). This means that the threshold voltage distribution observed during multi-sensing operation with the first voltage (V1) is shifted to the right compared to the threshold voltage distribution observed during general sensing operation with the first voltage (V1). Therefore, the read voltage used during multi-sensing operation is a first compensation voltage (V1) that is higher than the first voltage (V1). CP It will need to be moved to ). In this case, it means that the time to evaluation (tEV) must be reduced.

[0105] FIG. 13 is a flowchart illustrating an exemplary embodiment of step (S160) of FIG. 11. FIG. 13 is an embodiment for determining a correction method for the evaluation time (tEV) when performing a verification operation through a full bit line sensing method.

[0106] Referring to FIG. 13, step (S160) of FIG. 11 is the first fail bit number (N FB1 ) is the second fail bit number (N FB2 A step of comparing with ) (S210), the first fail bit number (N FB1 ) is the number of second fail bits (N FB2 If it is smaller than ) (S230: Yes), a step (S250) of increasing the evaluation time (tEV) used during the read operation or the first fail bit number (N FB1 ) is the number of second fail bits (N FB2 If it is not less than ) (S230: No), it includes a step (S270) of reducing the evaluation time (tEV) used during the read operation. As described above with reference to FIGS. 12a and 12b, the first fail bit number (N FB1 ) is the number of second fail bits (N FB2 If it is smaller than ), this means that the threshold voltage distribution observed during read using the multi-sensing method has shifted to the left. Therefore, the evaluation time is increased to compensate for the read voltage. Meanwhile, the first fail bit number (N FB1 ) is the number of second fail bits (N FB2 If it is greater than ), this means that the threshold voltage distribution observed during read using the multi-sensing method has shifted to the right. Therefore, the evaluation time is reduced to compensate for the read voltage.

[0107] FIGS. 14a and FIGS. 14b are flowcharts illustrating exemplary embodiments of steps (S250) and (S270) of FIG. 13, respectively.

[0108] Referring to FIG. 14a, the step (250) of increasing the evaluation time (tEV) used during a read operation in the entire bit line sensing method includes a step (S251) of setting the increase in the evaluation time corresponding to a low read voltage relatively larger than the increase in the evaluation time corresponding to a high read voltage. The fact that the threshold voltage distribution observed during reading in a multi-sensing method has shifted to the left means that the effect of the reference current downward is more dominant than the effect of the source line noise. Therefore, as described above with reference to FIG. 8a, since the threshold voltage distribution state of the memory cells differs most significantly from the threshold voltage distribution state after programming when verifying the first program state (PV1), the increase in the evaluation time during the sensing operation using the first read voltage is set to the largest, and conversely, the increase in the evaluation time during the sensing operation using the seventh read voltage is set to the smallest.

[0109] Meanwhile, referring to FIG. 14b, the step (270) of reducing the evaluation time (tEV) used during a read operation in the entire bit line sensing method includes a step (S271) of setting the reduction range of the evaluation time corresponding to a low read voltage relatively larger than the reduction range of the evaluation time corresponding to a high read voltage. The fact that the threshold voltage distribution observed during reading in a multi-sensing method has shifted to the right means that the effect of source line noise is more dominant than the effect of the reference current downward. Therefore, as described above with reference to FIG. 8b, since the threshold voltage distribution state of the memory cells differs most significantly from the threshold voltage distribution state after programming when verifying the first program state (PV1), the reduction range of the evaluation time during the sensing operation using the first read voltage is set to the largest, and conversely, the reduction range of the evaluation time during the sensing operation using the seventh read voltage is set to the smallest.

[0111] FIG. 15 is a flowchart illustrating another exemplary embodiment of step (S160) of FIG. 11. FIG. 15 is an embodiment for determining a correction method for the evaluation time (tEV) when performing a verification operation through a selected bit line sensing method.

[0112] Referring to FIG. 15, step (S160) of FIG. 11 is the first fail bit number (N FB1 ) is the second fail bit number (N FB2 Step of comparing with ) (S310), first fail bit number (N FB1 ) is the number of second fail bits (N FB2 If it is smaller than ) (S330: Yes), a step (S350) to reduce the evaluation time (tEV) used during the read operation or the first fail bit number (N FB1 ) is the number of second fail bits (N FB2 If it is not less than (S330: No), the method includes a step (S370) of increasing the evaluation time (tEV) used during the read operation. Unlike the above description with reference to FIGS. 12a and 12b, the method of correcting the evaluation time (tEV) when performing a verification operation through a selected bit line sensing method may be performed in the opposite direction to the method of correcting the evaluation time (tEV) when performing a verification operation through a full bit line sensing method.

[0114] FIGS. 16a and FIGS. 16b are flowcharts illustrating exemplary embodiments of steps (S350) and (S370) of FIG. 15, respectively.

[0115] Referring to FIG. 16a, the step (350) of reducing the evaluation time (tEV) used during a read operation in a select bit line sensing method includes a step (S351) of setting the reduction range of the evaluation time corresponding to a high read voltage relatively larger than the reduction range of the evaluation time corresponding to a low read voltage. That is, as described above with reference to FIG. 10a, the reduction range of the evaluation time during a sensing operation using the 7th read voltage is set to be the largest, and conversely, the reduction range of the evaluation time during a sensing operation using the 1st read voltage is set to be the smallest.

[0116] Meanwhile, referring to FIG. 16b, the step (370) of increasing the evaluation time (tEV) used during a read operation in a select bit line sensing method includes a step (S371) of setting the increase in the evaluation time corresponding to a high read voltage relatively larger than the increase in the evaluation time corresponding to a low read voltage. That is, as described above with reference to FIG. 10b, the increase in the evaluation time during a sensing operation using the 7th read voltage is set to be the largest, and conversely, the increase in the evaluation time during a sensing operation using the 1st read voltage is set to be the smallest.

[0117] FIGS. 17a and FIGS. 17b are drawings for explaining the multi-sensing operation and general sensing operation described in FIG. 11.

[0118] Referring to FIG. 17a, a graph is shown to illustrate a multi-sensing operation using a first lead voltage (R1) and an associated auxiliary voltage (R1'). In FIG. 17a, for convenience of explanation, only the threshold voltage distributions of the erase state (E) and the first program state (PV1) are shown.

[0119] In a multi-sensing operation according to one embodiment of the present invention, first, the threshold voltage of memory cells is sensed using an auxiliary voltage (R1') that is smaller than the first read voltage. More specifically, memory cells included in a selected page can be divided into memory cells having a threshold voltage smaller than the auxiliary voltage (R1') and memory cells having a threshold voltage larger than the auxiliary voltage (R1').

[0120] As illustrated in FIG. 17a, when the threshold voltages of the memory cells are primarily sensed using an auxiliary voltage (R1'), the first memory cells (MCs1) are determined to be on-cell, and the second memory cells (MCs2) and third memory cells (MCs3) are determined to be off-cell. The determination results can be stored in latches within the page buffers (PB1~PNm).

[0121] Subsequently, the threshold voltage of the memory cells is secondarily sensed using the first read voltage (R1). At this time, the sensing operation is not performed for the first memory cells (MCs1) that have already been identified as on-cell. This is because the first read voltage (R1) is greater than the auxiliary voltage (R1'), so the sensing result for the first memory cells (MCs1) will not change. Accordingly, the second sensing operation using the first read voltage (R1) is performed only for the second memory cells (MCs2) and the third memory cells (MCs3) that were identified as off-cell in the first sensing result. As a result of the second sensing, the second memory cells (MCs2) will be identified as on-cell, and the third memory cells (MCs3) will be identified as off-cell.

[0122] During the second sensing operation for the second memory cells (MCs2) and the third memory cells (MCs3), the sensing operation is not performed for the first memory cells (MCs1). For example, during the bit line precharge process for the second sensing operation, the bit lines connected to the first memory cells (MCs1) may not be precharged. In this case, only the bit lines connected to the second memory cells (MCs2) and the third memory cells (MCs3) may be precharged.

[0123] As another example, during the second sensing operation, the page buffers connected to the first memory cells (MCs1) may not operate. In this case, only the page buffers connected to the second memory cells (MCs2) and the third memory cells (MCs3) may operate.

[0124] During the second sensing operation, the page buffers connected to the first memory cells (MCs1) do not operate, so cell current will not flow through the bit lines connected to the first memory cells (MCs1). Accordingly, the problem of source round bouncing or the problem of a temporary drop in power supply voltage caused by the cell current associated with the first memory cells (MCs1) can be mitigated. Additionally, the problem of bit line coupling can also be mitigated. Consequently, by not operating the page buffers connected to the first memory cells (MCs1) during the second sensing operation, noise that could affect the threshold voltage sensing of the second memory cells (MCs2) and the third memory cells (MCs3) can be minimized. As a result, sensing accuracy can be improved.

[0125] Referring to FIG. 17b, a graph is shown to explain a general sensing operation using a first read voltage (R1). As shown in FIG. 17b, in a general sensing operation, the threshold voltage of the memory cells is sensed once using the first read voltage (R1).

[0126] FIGS. 18a and FIGS. 18b are flowcharts for explaining multi-sensing operation and general sensing operation, respectively. Referring to FIG. 18a, a flowchart illustrating an exemplary embodiment of step (S140) of FIG. 11 is shown. Below, the multi-sensing operation will be explained with reference to FIG. 17a and FIG. 18a.

[0127] To perform a multi-sensing operation for a selected page, the bit lines connected to all memory cells included in the selected page are first precharged (S410). In step (S410), the bit lines connected to the first memory cells (MCs1), second memory cells (MCs2), and third memory cells (MCs3), respectively, as illustrated in FIG. 17a, will be precharged.

[0128] Subsequently, based on a first auxiliary voltage smaller than the first voltage, a first threshold voltage sensing operation is performed for all memory cells included in the selected page (S420). The first voltage described in step (S420) may correspond to the first read voltage (R1) shown in FIG. 17a, and the first auxiliary voltage described in step (S420) may correspond to the auxiliary voltage (R1') shown in FIG. 17a.

[0129] Subsequently, memory cells having a threshold voltage lower than the first auxiliary voltage are determined as the first cell group, and memory cells having a threshold voltage higher than the first auxiliary voltage are determined as the second cell group (S430). That is, the first memory cells (MCs1) determined to be on-cells by the first threshold voltage sensing result are determined as the first cell group, and the second and third memory cells (MCs2, MCs3) determined to be off-cells are determined as the second cell group.

[0130] Subsequently, among the memory cells included in the selected page, the bit lines connected to the memory cells included in the second cell group are precharged (S440). As described above with reference to FIG. 17a, in step (S440), only the bit lines connected to the second and third memory cells (MCs2, MCs3) can be precharged.

[0131] Subsequently, based on the first voltage, a second threshold voltage sensing operation is performed on the memory cells included in the second cell group (S450). In step (S450), the second threshold voltage sensing operation is not performed for the first memory cells (MCs1), and the threshold voltage sensing operation is performed only for the second and third memory cells (MCs2, MCs3). As a result of the second threshold voltage sensing, the determination of the second memory cells (MCs2) will change from off-cell to on-cell. Meanwhile, as a result of the second threshold voltage sensing, the determination of the third memory cells (MCs3) will remain off-cell. Additionally, regardless of the second threshold voltage sensing, the determination of the first memory cells (MCs1) will remain on-cell.

[0132] Referring to FIG. 18b, a flowchart illustrating an exemplary embodiment of step (S120) of FIG. 11 is shown. Hereinafter, multi-sensing operations will be described with reference to FIG. 17b and FIG. 18b.

[0133] To perform a general sensing operation for a selected page, first, all memory cells included in the selected page and the connected bit lines are precharged (S510). Then, based on a first voltage, a threshold voltage sensing operation is performed for all memory cells included in the selected page (S520). The first voltage described in step (S520) may correspond to the first read voltage (R1) shown in FIG. 17b. As shown in FIG. 18b, the general sensing operation performs a single sensing operation using only the first voltage, i.e., the first read voltage, without the use of an auxiliary voltage.

[0134] Referring to FIGS. 17a and 17b, an example of performing multi-sensing operations and general sensing operations using a first lead voltage (R1) and an auxiliary voltage (R1') of a smaller magnitude has been described. However, this is exemplary, and multi-sensing operations can also be performed by setting appropriate auxiliary voltages for each of the second lead voltages (R2) to the seventh lead voltages (R7).

[0136] FIG. 19 is a block diagram showing a memory system (1000) including the semiconductor memory device (100) of FIG. 2.

[0137] Referring to FIG. 19, the memory system (1000) includes a semiconductor memory device (100) and a controller (1100). The semiconductor memory device (100) may be the semiconductor memory device described with reference to FIG. 2. Redundant descriptions below are omitted.

[0138] The controller (1100) is connected to the host and the semiconductor memory device (100). The controller (1100) is configured to access the semiconductor memory device (100) in response to a request from the host. For example, the controller (1100) is configured to control read, write, erase, and background operations of the semiconductor memory device (100). The controller (1100) is configured to provide an interface between the semiconductor memory device (100) and the host. The controller (1100) is configured to run firmware for controlling the semiconductor memory device (100).

[0139] The controller (1100) includes RAM (1110, Random Access Memory), a processing unit (1120, processing unit), a host interface (1130, host interface), a memory interface (1140, memory interface), and an error correction block (1150). The RAM (1110) is used as at least one of the operating memory of the processing unit (1120), a cache memory between the semiconductor memory device (100) and the host, and a buffer memory between the semiconductor memory device (100) and the host. The processing unit (1120) controls the overall operation of the controller (1100). Additionally, the controller (1100) can temporarily store program data provided from the host during a write operation.

[0140] The host interface (1130) includes a protocol for performing data exchange between the host and the controller (1100). As an exemplary embodiment, the controller (1100) is configured to communicate with the host through at least one of various interface protocols, such as the USB (Universal Serial Bus) protocol, the MMC (multimedia card) protocol, the PCI (peripheral component interconnection) protocol, the PCI-E (PCI-express) protocol, the ATA (Advanced Technology Attachment) protocol, the Serial-ATA protocol, the Parallel-ATA protocol, the SCSI (small computer system interface) protocol, the ESDI (enhanced small disk interface) protocol, and the IDE (Integrated Drive Electronics) protocol, the private protocol, etc.

[0141] The memory interface (1140) interfaces with the semiconductor memory device (100). For example, the memory interface includes a NAND interface or a NOR interface.

[0142] The error correction block (1150) is configured to detect and correct errors in data received from the semiconductor memory device (100) using an error correction code (ECC). As an exemplary embodiment, the error correction block may be provided as a component of the controller (1100).

[0143] The controller (1100) and the semiconductor memory device (100) can be integrated into a single semiconductor device. As an exemplary embodiment, the controller (1100) and the semiconductor memory device (100) can be integrated into a single semiconductor device to form a memory card. For example, the controller (1100) and the semiconductor memory device (100) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash Card (CF), Smart Media Card (SM, SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro), SD Card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0144] The controller (1100) and the semiconductor memory device (100) can be integrated into a single semiconductor device to form a solid-state drive (SSD). The solid-state drive (SSD) includes a storage device configured to store data in semiconductor memory. When the memory system (1000) is used as a solid-state drive (SSD), the operating speed of the host connected to the memory system (2000) is dramatically improved.

[0145] As another example, the memory system (1000) is one of a computer, UMPC (Ultra Mobile PC), workstation, netbook, PDA (Personal Digital Assistants), portable computer, web tablet, wireless phone, mobile phone, smartphone, e-book, PMP (portable multimedia player), portable game console, navigation device, black box, digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network It is provided as one of the various components of an electronic device, such as an RFID device or one of the various components constituting a computing system.

[0146] As an exemplary embodiment, the semiconductor memory device (100) or memory system (1000) may be mounted in various types of packages. For example, the semiconductor memory device (100) or memory system (1000) may be mounted in a manner such as a Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip on Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi-Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-level Processed Stack Package (WSP), etc.

[0148] Figure 20 is a block diagram showing an application example of the memory system of Figure 19.

[0149] Referring to FIG. 20, the memory system (2000) includes a semiconductor memory device (2100) and a controller (2200). The semiconductor memory device (2100) includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0150] In FIG. 20, a plurality of groups are each shown communicating with the controller (2200) through the first to k channels (CH1~CHk). Each semiconductor memory chip will be configured and operated in the same way as the semiconductor memory device (100) described with reference to FIG. 2.

[0151] Each group is configured to communicate with the controller (2200) through a common channel. The controller (2200) is configured in the same way as the controller (1100) described with reference to FIG. 19 and is configured to control multiple memory chips of the semiconductor memory device (2100) through multiple channels (CH1~CHk).

[0153] FIG. 21 is a block diagram showing a computing system including a memory system described with reference to FIG. 20.

[0154] The computing system (3000) includes a central processing unit (3100), RAM (3200, RAM, Random Access Memory), a user interface (3300), a power supply (3400), a system bus (3500), and a memory system (2000).

[0155] The memory system (2000) is electrically connected to the central processing unit (3100), RAM (3200), user interface (3300), and power supply (3400) via the system bus (3500). Data provided through the user interface (3300) or processed by the central processing unit (3100) is stored in the memory system (2000).

[0156] In FIG. 21, the semiconductor memory device (2100) is shown as being connected to the system bus (3500) via a controller (2200). However, the semiconductor memory device (2100) may be configured to be directly connected to the system bus (3500). In this case, the function of the controller (2200) will be performed by the central processing unit (3100) and the RAM (3200).

[0157] In FIG. 21, a memory system (2000) described with reference to FIG. 20 is shown to be provided. However, the memory system (2000) may be replaced with the memory system (1000) described with reference to FIG. 19. As an exemplary embodiment, a computing system (3000) may be configured to include all of the memory systems (1000, 2000) described with reference to FIG. 19 and FIG. 20. Explanation of the symbols

[0158] 100: Semiconductor memory device 110: Memory cell array 120: Address decoder 130: Read and write circuit 140: Control logic 150: Voltage generation unit 200: Controller

Claims

Claim 1 A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program operation and a read operation for the memory cell array; and a control logic configured to control the operation of the peripheral circuit, wherein the control logic controls the peripheral circuit to perform an SLC program operation for memory cells included in a selected page among the plurality of memory cells; compares a first number of fail bits counted by performing a general sensing operation for the selected page with a second number of fail bits counted by performing a multi-sensing operation for the selected page, corrects at least one evaluation time to be used for a read operation based on the comparison result, wherein in the general sensing operation, one voltage is applied to a word line connected to the selected page, and in the multi-sensing operation, a plurality of voltages are applied to a word line connected to the selected page. Claim 2 A semiconductor memory device according to claim 1, wherein the control logic controls the peripheral circuit to use a full bit line sensing method during a verification operation, and increases the evaluation time used during the read operation when the number of the first fail bit is smaller than the number of the second fail bit. Claim 3 A semiconductor memory device according to claim 2, wherein the control logic determines the increase range of the evaluation time corresponding to the first read voltage to be relatively larger than the increase range of the evaluation time corresponding to the second read voltage which is higher than the first read voltage. Claim 4 A semiconductor memory device according to claim 1, wherein the control logic controls the peripheral circuit to use a full bit line sensing method during a verification operation, and reduces the evaluation time used during a read operation when the number of the first fail bit is greater than the number of the second fail bit. Claim 5 A semiconductor memory device according to claim 4, wherein the control logic determines the reduction range of the evaluation time corresponding to the first read voltage to be relatively larger than the reduction range of the evaluation time corresponding to the second read voltage which is higher than the first read voltage. Claim 6 A semiconductor memory device according to claim 1, wherein the control logic controls the peripheral circuit to use a select bit line sensing method during a verification operation, and reduces the evaluation time used during a read operation when the number of the first fail bit is smaller than the number of the second fail bit. Claim 7 A semiconductor memory device according to claim 6, wherein the control logic determines the reduction range of the evaluation time corresponding to the first read voltage to be relatively larger than the reduction range of the evaluation time corresponding to the second read voltage which is lower than the first read voltage. Claim 8 A semiconductor memory device according to claim 1, wherein the control logic controls the peripheral circuit to use a select bit line sensing method during a verification operation, and increases the evaluation time used during a read operation when the number of the first fail bit is greater than the number of the second fail bit. Claim 9 A semiconductor memory device according to claim 1, wherein the multi-sensing operation is performed by first sensing the threshold voltage of memory cells included in the selected page while applying a predetermined auxiliary voltage to a word line connected to the selected page, and secondarily sensing the threshold voltage of the remaining memory cells excluding the memory cells determined to be on-cell as a result of the first sensing by applying a main voltage greater than the auxiliary voltage to the word line connected to the selected page. Claim 10 A semiconductor memory device according to claim 8, wherein the control logic determines that the increase in the evaluation time corresponding to the first read voltage is relatively larger than the increase in the evaluation time corresponding to the second read voltage which is lower than the first read voltage. Claim 11 A method of operating a semiconductor memory device comprising a plurality of memory cells, the method comprising: performing an SLC program operation for selected memory cells among the plurality of memory cells; performing a general sensing operation based on a first voltage for the selected memory cells; counting a first number of fail bits according to the general sensing operation; performing a multi-sensing operation based on the first voltage and an auxiliary voltage smaller than the first voltage for the selected memory cells; counting a second number of fail bits according to the multi-sensing operation; and determining a correction method for an evaluation time used in a read operation based on the first number of fail bits and the second number of fail bits. Claim 12 A method of operating a semiconductor memory device according to claim 11, wherein the step of determining a correction method for an evaluation time used in a read operation based on the first number of fail bits and the second number of fail bits comprises: a step of comparing the first number of fail bits and the second number of fail bits; and a step of determining to increase at least one evaluation time used in a read operation in response to a determination that the first number of fail bits is smaller than the second number of fail bits when a verification operation is performed using a whole bit line sensing method. Claim 13 A method of operating a semiconductor memory device according to claim 12, wherein the step of determining to increase at least one evaluation time used during a read operation in response to a determination that the first fail bit number is smaller than the second fail bit number includes the step of determining the increase in the evaluation time corresponding to the first read voltage to be relatively larger than the increase in the evaluation time corresponding to the second read voltage which is higher than the first read voltage. Claim 14 A method of operating a semiconductor memory device according to claim 11, wherein the step of determining a correction method for an evaluation time used in a read operation based on the first number of fail bits and the second number of fail bits comprises: a step of comparing the first number of fail bits and the second number of fail bits; and a step of determining to reduce at least one evaluation time used in a read operation in response to a determination that the first number of fail bits is greater than the second number of fail bits when a verification operation is performed using a whole bit line sensing method. Claim 15 A method of operating a semiconductor memory device according to claim 14, wherein the step of determining to reduce at least one evaluation time used during a read operation in response to a determination that the first fail bit number is greater than the second fail bit number comprises the step of determining the reduction range of the evaluation time corresponding to the first read voltage to be relatively larger than the reduction range of the evaluation time corresponding to the second read voltage which is higher than the first read voltage. Claim 16 A method for operating a semiconductor memory device according to claim 11, wherein the step of determining a correction method for an evaluation time used in a read operation based on the first number of fail bits and the second number of fail bits comprises: a step of comparing the first number of fail bits and the second number of fail bits; and a step of determining to reduce at least one evaluation time used in a read operation in response to a determination that the first number of fail bits is smaller than the second number of fail bits when performing a verification operation using a select bit line sensing method. Claim 17 A method of operating a semiconductor memory device according to claim 16, wherein the step of determining to reduce at least one evaluation time used during a read operation in response to a determination that the first number of fail bits is smaller than the second number of fail bits includes the step of determining the reduction range of the evaluation time corresponding to the first read voltage to be relatively larger than the reduction range of the evaluation time corresponding to the second read voltage which is lower than the first read voltage. Claim 18 A method of operating a semiconductor memory device according to claim 11, wherein the step of determining a correction method for an evaluation time used in a read operation based on the first number of fail bits and the second number of fail bits comprises: a step of comparing the first number of fail bits and the second number of fail bits; and a step of determining to increase at least one evaluation time used in a read operation in response to a determination that the first number of fail bits is greater than the second number of fail bits when performing a verification operation using a select bit line sensing method. Claim 19 A method of operating a semiconductor memory device according to claim 18, wherein the step of determining to increase at least one evaluation time used during a read operation in response to a determination that the first fail bit number is greater than the second fail bit number includes the step of determining the increase in the evaluation time corresponding to the first read voltage to be relatively larger than the increase in the evaluation time corresponding to the second read voltage which is lower than the first read voltage. Claim 20 A method of operating a semiconductor memory device according to claim 11, further comprising the step of correcting at least one evaluation time used in the read operation based on the determined correction method. Claim 21 A method of operation of a semiconductor memory device according to claim 11, wherein the step of performing a multi-sensing operation based on the first voltage and the auxiliary voltage for the selected memory cells comprises: a step of pre-charging bit lines connected to the selected memory cells; a step of sensing the threshold voltage of the selected memory cells based on the auxiliary voltage; a step of pre-charging the first memory cells among the selected memory cells that are determined to be off-cells by the sensing result; and a step of re-sensing the threshold voltage of the first memory cells based on the first voltage.

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