Vertical charge transfer pixel sensor and method of manufacturing the same

Abstract

The present invention relates to a vertical charge transfer pixel sensor and a method for manufacturing the same. In the vertical charge transfer pixel sensor, shallow trench isolation and deep trench isolation are formed on one side of a semiconductor substrate. The deep trench isolation includes a deep trench penetrating the semiconductor substrate, a trench electrode filled within the deep trench, and a first isolation dielectric. The deep trench isolation defines a plurality of substrate units in a pixel area. Each substrate unit includes a photosensitive area and a charge reading area separated by shallow trench isolation. A substrate electrode is formed on the other side of the semiconductor substrate. The substrate electrode contacts each substrate unit and is isolated from the trench electrode. The deep trench isolation forms physical isolation between each pixel, thereby ensuring photoelectric conversion efficiency, effectively preventing crosstalk between pixels, and being advantageous for pixel scaling. Furthermore, the trench electrode provides a single operable electrode terminal to the vertical charge transfer pixel sensor, enabling the implementation of diversified operating modes.

Description

Technology Field

[0001] The present invention relates to the field of photosensitive technology, and more specifically, to a vertical charge transfer pixel sensor and a method for manufacturing a vertical charge transfer pixel sensor. Background Technology

[0002] Vertically charge transferring pixel sensors (VPS) are image sensors that implement imaging using a semiconductor substrate and a floating gate transistor structure. Referring to FIGS. 1 and 2, each pixel in the vertically charge transferring pixel sensor comprises a semiconductor substrate (10). The semiconductor substrate (10) comprises a photosensitive region (11) and a charge reading region (12) separated by shallow trench isolation (STI). On the front of the semiconductor substrate (10), a gate dielectric layer (13), a floating gate (FG), an inter-gate dielectric layer (14), and a control gate (CG) are formed, extending from the photosensitive region (11) to the charge reading region (12). A source region (S) and a drain region (D) are formed in the charge reading region (12) on both sides of the control gate (CG). Thus, each pixel comprises a MOS capacitor formed in the photosensitive region (11) and a read transistor formed in the charge reading region (12), which are connected to each other. When the above vertical charge transfer pixel sensor is in operation, light is incident from the back surface of the semiconductor substrate (10) to generate photoelectrons. Under the action of an appropriate bias voltage, the photoelectrons move to one side of the control gate (CG) and accumulate on the lower surface of the gate dielectric layer (13) of the photosensitive region (11) or cross the potential barrier and enter the floating gate (FG). Furthermore, the drain current and / or threshold voltage of the read transistor change, and by detecting this change, photoelectric detection and imaging can be implemented.

[0003] Vertical charge transfer pixel sensors can achieve a higher full well charge at the same pixel size compared to conventional photodiode-based semiconductor sensor devices (e.g., CMOS image sensors). Therefore, they have a higher signal-to-noise ratio and offer relatively distinct advantages in terms of pixel scaling.

[0004] For VPS sensors, the main challenge currently faced is how to prevent crosstalk between pixels while ensuring photoelectric conversion efficiency during pixel scaling.

[0005] In order to secure photoelectric conversion efficiency of a vertical charge transfer pixel sensor while preventing crosstalk between pixels, the present invention provides a vertical charge transfer pixel sensor and a method for manufacturing the same.

[0006] In one aspect, the present invention provides a vertical charge transfer pixel sensor. The vertical charge transfer pixel sensor comprises a semiconductor substrate, shallow trench isolation and deep trench isolation, a gate dielectric layer, a floating gate, a gate-to-gate dielectric layer and a control gate, and a substrate electrode.

[0007] The semiconductor substrate has a first doping type. The semiconductor substrate includes a pixel area and a peripheral area.

[0008] The above semiconductor substrate includes a pixel area.

[0009] The shallow trench isolation and deep trench isolation are formed on a first side of the semiconductor substrate. The deep trench isolation includes a deep trench penetrating the semiconductor substrate, a trench electrode filled within the deep trench, and a first isolation dielectric. The first isolation dielectric isolates the trench electrode from the semiconductor substrate. The deep trench isolation defines a plurality of substrate units in the pixel area. Each of the substrate units includes a photosensitive area and a charge reading area separated by the shallow trench isolation.

[0010] The gate dielectric layer, floating gate, inter-gate dielectric layer, and control gate are formed on the surface of each of the substrate units and extend from the photosensitive region to the charge reading region. In the charge reading region, a source region and a drain region are formed, respectively, located on both sides of the corresponding control gate.

[0011] The substrate electrode is formed on the second side of the semiconductor substrate. The substrate electrode is in contact with each of the substrate units and is isolated from the trench electrode.

[0012] Optionally, the semiconductor substrate includes a trench electrode extraction region located at the outer periphery of the pixel region. The trench electrode extends along the deep trench from the pixel region to the trench electrode extraction region. Additionally, it extends from the bottom to the top of the deep trench in the trench electrode extraction region.

[0013] Optionally, the vertical charge transfer pixel sensor further includes a trench electrode connection block. The trench electrode connection block is formed in the trench electrode extraction region and covers the trench electrode.

[0014] Optionally, in the pixel region, the first isolation dielectric filled within the deep trench comprises a linear oxide layer and a deep trench filling layer. The linear oxide layer is interposed between the trench electrode and the semiconductor substrate. The deep trench filling layer covers the trench electrode and is located at the top of the deep trench.

[0015] Optionally, the substrate electrode is installed on a second side of the semiconductor substrate corresponding to the deep trench of the pixel area. A second isolation dielectric is provided between the substrate electrode and the trench electrode.

[0016] Optionally, the second isolation dielectric comprises a high dielectric constant material.

[0017] Optionally, the control gate formed on each of the substrate units is connected by a plurality of word lines. Each of the word lines crosses the plurality of substrate units.

[0018] In one aspect, the present invention provides a method for manufacturing a vertical charge transfer pixel sensor, comprising the following steps.

[0019] A semiconductor substrate including a pixel area is provided.

[0020] A shallow trench isolation and a deep trench isolation are formed on a first side of the semiconductor substrate. The deep trench isolation includes a deep trench penetrating a portion of the semiconductor substrate, a trench electrode filled within the deep trench, and a first isolation dielectric. The first isolation dielectric insulates the trench electrode from the semiconductor substrate. The deep trench isolation defines a plurality of substrate units in the pixel area. Each of the substrate units includes a photosensitive area and a charge reading area separated by the shallow trench isolation.

[0021] A gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate are formed on the surface of each of the above-mentioned substrate units. The gate dielectric layer, the floating gate, the inter-gate dielectric layer, and the control gate extend from the photosensitive region to the charge reading region. Additionally, a source region and a drain region are formed, respectively, located on both sides of the control gate corresponding to the charge reading region.

[0022] The semiconductor substrate is thinned from the second side to expose the deep trench isolation. Additionally, a substrate electrode is formed on the second side. The substrate electrode contacts each of the substrate units and is isolated from the trench electrode.

[0023] Optionally, the step of forming the shallow trench isolation and the deep trench isolation on the first side of the semiconductor substrate comprises the following steps.

[0024] A pad oxide layer and a first hard mask layer are formed on the surface of the semiconductor substrate, and a shallow trench isolation is formed. The shallow trench isolation is installed through the first hard mask layer, the pad oxide layer, and a portion of the semiconductor substrate.

[0025] A second hard mask layer is formed. The second hard mask layer covers the first hard mask layer and the shallow trench isolation.

[0026] The deep trench is formed. The deep trench penetrates the second hard mask layer, the first hard mask layer, the pad oxide layer, and a portion of the semiconductor substrate.

[0027] A linear oxide layer and a trench conductive layer are formed within the deep trench. The linear oxide layer covers the semiconductor substrate exposed by the deep trench. The trench conductive layer covers the linear oxide layer and fills the deep trench. The top surface of the trench conductive layer is higher than the surface of the semiconductor substrate.

[0028] The trench conductive layer of the pixel region is etched back down to below the surface of the semiconductor substrate. An etched-back space is formed at the top of the deep trench of the pixel region. The remaining trench conductive layer is a trench electrode.

[0029] A deep trench filling layer is formed within the above etching back space. The linear oxide layer and the deep trench filling layer are the first isolation dielectric.

[0030] Optionally, the semiconductor substrate includes a trench electrode extraction region located at the outer periphery of the pixel region. The trench electrode extends along the deep trench from the pixel region to the trench electrode extraction region. Additionally, it extends from the bottom to the top of the deep trench in the trench electrode extraction region.

[0031] Optionally, the step of forming the substrate electrode comprises the following steps.

[0032] A first concave groove is formed in the deep trench isolation exposed from the second side of the semiconductor substrate. The first concave groove exposes the trench electrode and the substrate unit around the trench electrode.

[0033] A second isolation dielectric is formed on the second side. The second isolation dielectric fills the first concave groove and covers the surface of the substrate unit.

[0034] A second concave groove is formed. The bottom portion of the second concave groove is located above the first concave groove. The side surface of the second concave groove exposes the substrate unit surrounding the deep trench isolation. The trench electrode is covered by the second isolation dielectric.

[0035] The substrate electrode is formed by filling the second concave groove with a conductive material.

[0036] The vertical charge transfer pixel sensor and the method for manufacturing the vertical charge transfer pixel sensor provided in the present invention have the following technical effects:

[0037] First, the deep trench isolation penetrates the semiconductor substrate to define a plurality of substrate units in the pixel region. Each of the substrate units corresponds to a pixel of a vertical charge transfer pixel sensor. That is, by forming physical isolation between each pixel, the photoelectric conversion efficiency of the vertical charge transfer pixel sensor is secured, crosstalk between pixels is effectively prevented, and pixel scaling is advantageous;

[0038] Second, the substrate electrode is formed on the second side of the semiconductor substrate (i.e., the side far from the control gate). Since the substrate electrode does not need to occupy the area of ​​the side of the control gate, it is advantageous for pixel scaling.

[0039] Third, the deep trench isolation comprises a deep trench penetrating the semiconductor substrate, a trench electrode filled within the deep trench, and a first isolation dielectric. The first isolation dielectric isolates the trench electrode from the semiconductor substrate. The trench electrode provides a single operable electrode terminal to the vertical charge transfer pixel sensor. This can implement a diversified mode of operation together with other electrode terminals of the sensor;

[0040] Fourth, the trench electrode can be used in combination with a substrate electrode. By applying a positive bias voltage between the substrate electrode and the trench electrode during the photosensitive process, the potential barrier at the interface of the substrate unit and the deep trench isolation can be increased, thereby reducing the probability of photoelectrons being trapped at that interface. Therefore, this helps improve photoelectric conversion efficiency and address dark current and white pixel issues. Furthermore, the positive bias voltage is flexibly adjustable, and since a low dielectric constant material can be used for the isolation dielectric between the trench electrode and the substrate unit, the cost is relatively low;

[0041] Fifth, after one photosensitive and charge reading operation is completed, a reset can be performed by applying a negative bias voltage between the substrate electrode and the trench electrode. This helps to release the charge trapped in the deep trench isolation boundary region, thereby improving background noise during the next photosensitive and charge reading operation. Brief explanation of the drawing

[0042] Figure 1 is a plan view of a pixel within a vertical charge transfer pixel sensor. Figure 2 is a cross-sectional view along the XX' line of Figure 1. FIG. 3 is a plan view of a vertical charge transfer pixel sensor according to one embodiment of the present invention. Figure 4 is a schematic cross-sectional view of the region along line AA' in Figure 3. FIG. 5 is a flowchart of a method for manufacturing a vertical charge transfer pixel sensor according to one embodiment of the present invention. FIGS. 6a to 6v are cross-sectional views during the manufacturing process of a method for manufacturing a vertical charge transfer pixel sensor according to one embodiment of the present invention. Specific details for implementing the invention

[0043] The vertical charge transfer pixel sensor of the present invention and the method for manufacturing the same will be described in more detail with reference to the attached drawings and specific embodiments. The advantages and features of the present invention will become clearer through the following description. It should be noted that all attached drawings adopt highly simplified forms and use imprecise proportions. This is merely an auxiliary means to conveniently and clearly explain the embodiments of the present invention. The embodiments of the present invention are not limited to specific shapes of the areas depicted in the drawings, but may include shapes actually obtained, such as variations due to manufacturing. For clarity, in all attached drawings used to describe the embodiments of the present invention, the same reference numerals are used for identical parts, and redundant descriptions have been omitted.

[0044] Referring to FIGS. 3 and 4, an embodiment of the present invention includes a vertical charge transfer pixel sensor (or VPS sensor). The vertical charge transfer pixel sensor includes a semiconductor substrate (100), shallow trench isolation (STI) and deep trench isolation (DTI), a gate dielectric layer (108), a floating gate (FG), a gate-to-gate dielectric layer (111) and a control gate (CG), and a substrate electrode (E2).

[0045] The semiconductor substrate (100) includes a pixel area (A1).

[0046] Shallow trench isolation (STI) and deep trench isolation (DTI) are formed on one side of the semiconductor substrate (100). The deep trench isolation (DTI) includes a deep trench (DT) penetrating the semiconductor substrate (100), a trench electrode (E1) filled within the deep trench (DT), and a first isolation dielectric (specifically, for example, a linear oxide layer (105) and a deep trench filling layer (107)). The first isolation dielectric insulates the trench electrode (E1) from the semiconductor substrate (100). The deep trench isolation (DTI) defines a plurality of substrate units (110) in the pixel area (A1). Each of the substrate units (110) includes a photosensitive area (110a) and a charge reading area (110b) separated by the shallow trench isolation (STI).

[0047] A gate dielectric layer (108), a floating gate (FG), an inter-gate dielectric layer (111), and a control gate (CG) are formed on the surface of each of the substrate units (110) and extend from the photosensitive region (110a) to the charge reading region (110b). In the charge reading region (110b), a source region (S) and a drain region (D) are formed, respectively, located on both sides of the corresponding control gate (CG).

[0048] A substrate electrode (E2) is formed on the other side of the semiconductor substrate (100). The substrate electrode (E2) is in contact with each of the substrate units (110) and is isolated from the trench electrode (E1).

[0049] The semiconductor substrate (100) above may use various suitable semiconductor substrates in the field of the art. The material thereof may include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide. The semiconductor substrate (100) has, for example, ion doping. Specifically, for example, it is a silicon substrate doped with boron or boron difluoride. The doped boron ion density is, for example, 1×10⁻⁶ 12 / cm 2 ~2×10 12 / cm 2 It is between (P-). A P-type body region (PW, not shown) is formed in the charge reading region (110b) of the semiconductor substrate (100). The source region (S) and drain region (D) have, for example, N-type doping and are formed at the top of the P-type body region. It should be noted that the present invention primarily describes the case where the floating gate transistor in the pixel of the vertical charge transfer pixel sensor is an N-type device. It can be understood that when the floating gate transistor is a P-type device, an N-type body region is formed in the charge reading region (110b) and the source region (S) and drain region (D) have P-type doping.

[0050] Optionally, a plurality of substrate units (110) of the pixel area (A1) are arranged in an array. Each substrate unit (110) corresponds to a single pixel. The pixel includes a MOS capacitor formed in a photosensitive area (110a) of the corresponding substrate unit (110) and a read transistor formed in a charge read area (110b).

[0051] As illustrated in FIG. 3, in this embodiment, the semiconductor substrate (100) further includes a peripheral region located at the outer edge of the pixel area (A1). The peripheral region may be used to form some circuits of a vertical charge transfer pixel sensor. The invention is not limited thereto. In some embodiments, the peripheral region may be installed on another substrate. The other substrate may be stacked with the semiconductor substrate (100) and connected to each other.

[0052] In this embodiment, a portion of the surrounding area is a trench electrode picking-up area (A2) (picking-up area) that forms a connection of the trench electrode (E1). The deep trench (DT) and the trench electrode (E1) inside it extend from the pixel area (A1) to the trench electrode picking-up area (A2). In the pixel area (A1), the trench electrode (E1) is lower than the lower surface of the gate dielectric layer (108) and is covered by the deep trench filling layer (107). In the trench electrode picking-up area (A2), the trench electrode (E1) may extend from the bottom to the top of the deep trench (DT) and protrude from the surface of the semiconductor substrate (100) (see FIG. 6q-2). Optionally, the vertical charge transfer pixel sensor further includes a trench electrode connection block (E1-T). The trench electrode connection block (E1-T) is formed in the trench electrode extraction area (A2) and covers the trench electrode (E1). Thus, the trench electrode connection block (E1-T) is electrically connected to the trench electrode (E1).

[0053] In some embodiments, the substrate electrode (E2) is installed on the other side of the semiconductor substrate (100) corresponding to a deep trench (DT) of the pixel area (A1). A second isolation dielectric (113) is provided between the substrate electrode (E2) and the trench electrode (E1).

[0054] In some embodiments, the second isolation dielectric (113) comprises a high dielectric constant material (dielectric constant greater than 3.9). Optionally, the second isolation dielectric (113) covers the cross-section of the other side of the semiconductor substrate (100).

[0055] In some embodiments, the control gate (CG) formed in each of the substrate units (110) is connected to a plurality of word lines (WL). Each of the word lines (WL) crosses the plurality of substrate units (110).

[0056] In the vertical charge transfer pixel sensor described above, each pixel comprises a substrate unit (110), a gate dielectric layer (108) formed on the substrate unit (110), a floating gate (FG), a gate-to-gate dielectric layer (111) and a control gate (CG), and a source region (S) and a drain region (D) formed on both sides of the control gate (CG) in the charge reading region (110b). The photosensitive region (110a) and the gate dielectric layer (108), floating gate (FG), gate-to-gate dielectric layer (111), and control gate (CG) above it constitute a MOS capacitor for implementing photosensitive. The source region (S) and drain region (D) in the charge reading region (110b) and the gate dielectric layer (108), floating gate (FG), gate-to-gate dielectric layer (111), and control gate (CG) on the charge reading region (110b) constitute a read transistor for implementing charge reading.

[0057] As an example, the above vertical charge transfer pixel sensor can implement light detection and reading through the following process:

[0058] First, a photosensitive operation is performed to apply a negative bias voltage (e.g., -3V) to the semiconductor substrate (100). A positive bias voltage is applied to the control gate (CG) to form a continuous depletion region in the semiconductor substrate (100). When a photon enters the depletion region from one side far from the control gate (CG) of the semiconductor substrate (100), it is excited to form a photoelectron. The photoelectron is driven by an electric field and either accumulates on the lower surface of the gate dielectric layer (108) of the photosensitive region (110a) or flows over the potential barrier into the floating gate (FG). Since the floating gate (FG) of the photosensitive region (110a) and the charge reading region (110b) are connected to each other, the floating gate (FG) of the charge reading region (110b) changes. Furthermore, the drain current and / or threshold voltage of the reading transistor changes.

[0059] Next, a charge reading operation is performed to ground the source region (S) and the semiconductor substrate (100) to 0V, and a positive bias electrode (e.g. greater than 0 and less than 3V) is connected to the drain region (D). Additionally, the drain terminal current of the reading transistor is detected, or a change in the threshold voltage of the reading transistor is detected.

[0060] Next, a reset is performed to connect a negative bias voltage to the control gate (CG) and a positive bias voltage (e.g., greater than 0 and less than 3V) to the semiconductor substrate (100) and the source region (S). This causes photoelectrons to be emitted from the surface of the gate dielectric layer (108) or stored in the floating gate (FG).

[0061] In an embodiment of the present invention, the trench electrode (E1) provides one operable electrode terminal to the vertical charge transfer pixel sensor and can implement a diversified mode of operation together with other electrode terminals of the sensor (e.g., electrode terminals connected to the control gate, source region, and drain region, respectively, and substrate electrode). In some embodiments, the trench electrode (E1) can be used as a coupling terminal of the substrate electrode (E2). By applying a positive bias voltage between the substrate electrode (E2) and the trench electrode (E1), the potential barrier at the interface between the deep trench isolation (DTI) and the substrate unit (110) can be increased, thereby reducing the probability that photoelectrons will be trapped at the interface. This helps improve photoelectric conversion efficiency and improve dark current and white pixel issues. Additionally, after the photosensitive and charge reading operations are completed, a reset can be performed by applying a negative bias voltage between the substrate electrode and the trench electrode, thereby releasing the charge trapped in the deep trench isolation boundary region. This helps improve background noise during subsequent photosensitive and charge reading operations.

[0062] Embodiments of the present invention further include a method for manufacturing a vertical charge transfer pixel sensor. This can be used to manufacture the vertical charge transfer pixel sensor described in the above embodiments. The method for manufacturing the vertical charge transfer pixel sensor will be described below with reference to FIGS. 5 and FIGS. 6a to 6v.

[0063] FIG. 6a is a cross-sectional view of a semiconductor substrate after forming a pad oxide layer and a first hard mask layer. The cross-section shown in FIG. 6a is cut at the position of line AA' of the plan view shown in FIG. 3, for example. Referring to FIG. 3, FIG. 5 (specifically step S1) and FIG. 6a, a semiconductor substrate (100) having a first doping type is provided. The semiconductor substrate (100) includes a pixel region (A1). The semiconductor substrate (100) is, for example, a silicon substrate having P-type doping (P-). The pixel region (A1) is used to form a photosensitive pixel. The semiconductor substrate (100) may include a trench electrode extraction region (A2) located at the outer periphery of the pixel region (A1).

[0064] Referring to step S2 of FIG. 5, a shallow trench isolation (STI) and a deep trench isolation (DTI) are subsequently formed on one side of the semiconductor substrate (100). Specifically, the process may include the following steps.

[0065] As illustrated in FIG. 6a, a pad oxide layer (101) and a first hard mask layer (102) are formed on the surface of a semiconductor substrate (100). The pad oxide layer (101) comprises, for example, silicon oxide of a certain thickness. The first hard mask layer (102) comprises, for example, silicon nitride of a certain thickness.

[0066] FIG. 6b is a cross-sectional view after forming a shallow trench in a semiconductor substrate. As shown in FIG. 6b, a shallow trench isolation (STI) is defined using a photolithography process, and a shallow trench (ST) is formed penetrating the first hard mask layer (102), the pad oxide layer (101), and a portion of the semiconductor substrate (100) through etching one or more times. The depth (D1) of the shallow trench (ST) is about 100 nm to 400 nm, for example, about 200 nm.

[0067] FIG. 6c is a cross-sectional view after forming a shallow trench filling layer. As shown in FIG. 6c, after forming an oxide layer (not shown) along the inner surface of the shallow trench (ST), a shallow trench filling layer (103) is deposited. The shallow trench filling layer (103) fills the shallow trench (ST) and forms a certain thickness on the first hard mask layer (102). The shallow trench filling layer (103) may include silicon oxide or other insulating dielectrics. Optionally, before forming the oxide layer along the inner surface of the shallow trench (ST), the portion located on the first hard mask layer (102) and the pad oxide layer (101) of the shallow trench (ST) may be extended. This can subsequently reduce the risk of electrical leakage in the active region of the semiconductor substrate (100) defined by the shallow trench (ST) after removing the first hard mask layer (102) and the pad oxide layer (101).

[0068] FIG. 6d is a cross-sectional view after performing a planarization treatment on the shallow trench filling layer. As shown in FIG. 6d, a planarization treatment (e.g., CMP) is performed on the shallow trench filling layer (103) to expose the top surface of the first hard mask layer (102). The remaining shallow trench filling layer (103) is filled into the shallow trench (ST) to form a shallow trench isolation (STI).

[0069] FIG. 6e is a cross-sectional view after forming a second hard mask layer. As shown in FIG. 6e, the second hard mask layer (104) (e.g., silicon nitride adopted) is formed. The second hard mask layer (104) covers the shallow trench isolation (STI) and the first hard mask layer (102). The total thickness of the first hard mask layer (102) and the second hard mask layer (104) is approximately 2000 Å. Subsequently, the location of the deep trench isolation (DTI) is defined using a photolithography process. Additionally, a deep trench (DT) penetrating the second hard mask layer (104), the first hard mask layer (102), the pad oxide layer (101), and a portion of the semiconductor substrate (100) is formed through one or more etching steps. The depth (D2) of the deep trench (DT) is greater than the depth (D1) of the aforementioned shallow trench (ST). The depth (D2) of the deep trench (DT) is, for example, in the range of 1.5 μm to 2.5 μm. Furthermore, it may exceed 1.8 μm, for example, about 2 μm. The opening width (D3) of the deep trench (DT) is, for example, about 80 nm.

[0070] The cross-section shown in FIG. 6e is taken, for example, at the position of line AA' in the plan view shown in FIG. 3. Referring to FIG. 3 and FIG. 6e, some of the deep trenches (DT) are formed in the pixel area (A1) of the semiconductor substrate (100) to divide the pixel area (A1) and form a plurality of substrate units (110). Some shallow trench isolation (STI) is formed within each substrate unit (110). Each substrate unit (110) includes a photosensitive area (110a) and a charge reading area (110b) separated by the shallow trench isolation (STI). The deep trenches (DT) extend from the pixel area (A1) to the trench electrode extraction area (A2). As shown in FIG. 3, the width of the deep trenches (DT) located in the trench electrode extraction area (A2) is, for example, greater than the width of the deep trenches (DT) located in the pixel area (A1). The above trench electrode extraction area (A2) can be installed on one side or multiple sides of the pixel area (A1).

[0071] FIG. 6f is a cross-sectional view after forming a linear oxide layer. As shown in FIG. 6f, a linear oxide layer (105) is formed on the inner surface of the deep trench (DT). The linear oxide layer (105) covers the semiconductor substrate (100) exposed by the deep trench (DT). Prior to this, the portion within the second hard mask layer (104), the first hard mask layer (102), and the pad oxide layer (101) of the deep trench (DT) can be extended. Subsequently, annealing can be performed to repair lattice defects created in the semiconductor substrate (100) during the process of forming the deep trench (DT). The annealing temperature is, for example, about 1100°C.

[0072] FIG. 6g is a cross-sectional view after forming a trench conductive layer. As shown in FIG. 6g, a trench conductive layer (106) is formed by depositing a conductive material inside a deep trench (DT) and on a second hard mask layer (104). The trench conductive layer (106) fills the deep trench (DT) and forms a certain thickness on the second hard mask layer (104). The trench conductive layer (106) may adopt a conductive material with excellent light-blocking performance. Optionally, the trench conductive layer (106) comprises one or more combinations of tungsten, tungsten silicide, titanium, titanium nitride, and doped polycrystalline silicon. In this embodiment, the trench conductive layer (106) is, for example, doped polycrystalline silicon, and after deposition is completed, annealing is performed to recrystallize the doped polycrystalline silicon to obtain an appropriate grain size.

[0073] FIG. 6h is a cross-sectional view after performing a planarization treatment on the trench conductive layer. As shown in FIG. 6h, a planarization treatment (e.g., CMP) is performed on the trench conductive layer (106) to expose the top surface of the second hard mask layer (104). The remaining trench conductive layer (106) is filled into the deep trench (DT).

[0074] Next, the trench conductive layer (106) of the pixel region (A1) is etched back to below the surface of the semiconductor substrate (100) to form an etched-back space at the top of the deep trench (DT) of the pixel region (A1). FIGS. 6i-1 and FIGS. 6i-2 are cross-sectional views of the pixel region and the trench electrode extraction region, respectively, after the trench conductive layer has been etched back. Specifically, FIG. 6i-1 is cut at the position of line AA' of the plan view shown in FIG. 3, for example. FIG. 6i-2 is cut at the position of line BB' of the plan view shown in FIG. 3, for example. As shown in FIG. 6i-1, the trench conductive layer (106) of the pixel region (A1) is etched back to reduce the thickness of the trench conductive layer (106) of the pixel region (A1). Therefore, a portion of the depth of the deep trench (DT) in the pixel area (A1) is not filled, forming an etching back space. Through the etching back, the top surface of the trench conductive layer (106) in the pixel area (A1) is lower than the top surface of the semiconductor substrate (100). As shown in FIG. 6i-2, in the trench electrode extraction area (A2), the trench conductive layer (106) still extends to the opening point of the deep trench (DT). The remaining trench conductive layer (106) is the trench electrode (E1).

[0075] FIGS. 6j-1 and FIGS. 6j-2 are cross-sectional views of the pixel region and the trench electrode extraction region, respectively, after forming a deep trench filling layer. As shown in FIGS. 6j-1 and FIGS. 6j-2, a deep trench filling layer (107) is deposited, and the deep trench filling layer (107) covers the trench conductive layer (106) of the pixel region (A1) and the trench electrode extraction region (A2) and forms a certain thickness on the second hard mask layer (104). The deep trench filling layer (107) may include silicon oxide or other isolation dielectrics. Here, the linear oxide layer (105) and the deep trench filling layer (107) are collectively referred to as the first isolation dielectric. The trench electrode (E1) is embedded within the first isolation dielectric and is insulated from the semiconductor substrate (100).

[0076] FIGS. 6k-1 and FIGS. 6k-2 are cross-sectional views of a pixel area and a trench electrode extraction area, respectively, after performing a planarization treatment on a deep trench filling layer. As shown in FIGS. 6k-1 and FIGS. 6k-2, a planarization treatment (e.g., CMP) is performed on the deep trench filling layer (107) to expose the top surface of the second hard mask layer (104). Through the above steps, a deep trench isolation (DTI) embedded in the semiconductor substrate (100) is formed on one side of the semiconductor substrate (100). Here, in the pixel area (A1), the deep trench isolation (DTI) includes a linear oxide layer (105) filled within the deep trench (DT), a portion of the trench electrode (E1), and a deep trench filling layer (107). In the trench electrode extraction region (A2), the deep trench isolation (DTI) comprises a linear oxide layer (105) formed within the deep trench (DT) and some trench electrodes (E1). The trench electrodes (E1) extend from the pixel region (A1) to the trench electrode extraction region (A2).

[0077] Referring to step S3 of FIG. 5, a gate dielectric layer, a floating gate (FG), an inter-gate dielectric layer, and a control gate (CG) are subsequently formed on the surface of the substrate unit (110), extending from the photosensitive region (110a) to the charge reading region (110b). Additionally, a source region and a drain region are formed, respectively, located on both sides of the control gate (CG) corresponding to the charge reading region (110b). A detailed description is as follows.

[0078] FIGS. 6L-1 and FIGS. 6L-2 are cross-sectional views of the pixel area and the trench electrode extraction area, respectively, after removing the hard mask layer. As shown in FIGS. 6L-1 and FIGS. 6L-2, the second hard mask layer (104) and the first hard mask layer (102) are removed. After removal, the deep trench isolation (DTI) protrudes from the surface of the semiconductor substrate (100) and is higher than the shallow trench isolation (STI). The deep trench isolation (DTI) of the pixel area (A1) is installed to surround the outer periphery of each substrate unit (110). Subsequently, ion implantation can be performed to form a body area (not shown) in the charge reading area (110b). The ion implantation is, for example, P-type implantation. Subsequently, the pad oxide layer (101) is removed. Also, a gate dielectric layer (108) is formed on the surface of the semiconductor substrate (100) after removal.

[0079] FIGS. 6m-1 and FIGS. 6m-2 are cross-sectional views of the pixel region and the trench electrode extraction region, respectively, after forming a floating gate material layer. As shown in FIGS. 6m-1 and FIGS. 6m-2, polycrystalline silicon is subsequently deposited to form a floating gate material layer (109). The floating gate material layer (109) fills the gap between the shallow trench isolation (STI) and the deep trench isolation (DTI) and is higher than the deep trench isolation (DTI) by a certain thickness.

[0080] FIGS. 6n-1 and FIGS. 6n-2 are cross-sectional views of a pixel region and a trench electrode extraction region, respectively, after performing a planarization process on the floating gate material layer. As shown in FIGS. 6n-1 and FIGS. 6n-2, a planarization process is performed on the floating gate material layer (109) to expose the deep trench filling layer (107) of the pixel region (A1) and the trench electrode (E1) of the trench electrode extraction region (A2). The remaining floating gate material layer (109) is separated by deep trench isolation (DTI).

[0081] FIGS. 60-1 and FIGS. 60-2 are schematic cross-sectional views of a pixel region and a trench electrode extraction region, respectively, after forming an inter-gate dielectric layer. As shown in FIGS. 60-1 and FIGS. 60-2, the deep trench filling layer (107) is etched back to lower the height of the deep trench isolation (DTI) in the pixel region (A1) (still not lower than the surface of the semiconductor substrate (100)). A concave groove (T1) is formed corresponding to the gap between the substrate units (110). Then, an inter-gate dielectric layer (111) is conformally formed on the semiconductor substrate (100). After that, the inter-gate dielectric layer (111) in the trench electrode extraction region (A2) is removed to expose the floating gate material layer (109). The inter-gate dielectric layer (111) is, for example, an ONO layer comprising a lower silicon oxide layer, a silicon nitride layer, and an upper silicon oxide layer.

[0082] FIGS. 6p-1 and FIGS. 6p-2 are cross-sectional views of a pixel region and a trench electrode extraction region, respectively, after forming a control gate material layer. As shown in FIGS. 6p-1 and FIGS. 6p-2, a control gate material layer (112) is formed by depositing doped polycrystalline silicon on a semiconductor substrate (100). Before forming the control gate material layer (112), the floating gate material layer (109) of the trench electrode extraction region (A2) can be preserved or removed.

[0083] FIGS. 6q-1 and FIGS. 6q-3 are cross-sectional views of a pixel area after forming a control gate and a floating gate. FIG. 6q-1 is cut at the position of line AA' of the plan view shown in FIG. 3, for example. FIG. 6q-3 is cut at the position of line CC' of the plan view shown in FIG. 3, for example. FIG. 6q-2 is a cross-sectional view of a trench electrode extraction area after forming a trench electrode connection block. FIG. 6q-2 is cut at the position of line BB' of the plan view shown in FIG. 3, FIG. 6q-1, FIG. 6q-2 and FIG. 6q-3 are shown. A photolithography process is performed. Additionally, a floating gate (FG) and a control gate (CG) are formed on each substrate unit (110) through one or more etching steps. In addition, the control gate material layer (112) of the trench electrode extraction region (A2) is etched to form a trench electrode connection block (E1-T) in the trench electrode extraction region (A2).

[0084] Specifically, an anisotropic etching process is adopted to sequentially etch the control gate material layer (112), the inter-gate dielectric layer (111), and the floating gate material layer (109) of the pixel region (A1). This causes the remaining control gate material layer (112) to form a plurality of word lines (WL) in the pixel region (A1). The word lines are located between two or more substrate units (110) and the deep trench isolation (DTI) between them. They are also spaced apart from the inter-gate dielectric layer (111) and covered on the floating gate (FG). The word lines are used as control gates (CG).

[0085] A trench electrode connection block (E1-T) is formed in a trench electrode extraction area (A2) to connect the trench electrode (E1). The trench electrode connection block (E1-T) is isolated from the control gate (CG) of the pixel area (A1). Voltage can be applied to the trench electrode (E1) using the trench electrode connection block (E1-T). It should be noted that in FIG. 3, multiple ends of the deep trench (DT) of the pixel area (A1) are all laterally extended to the trench electrode extraction area (A2), but the present invention is not limited thereto. Since the deep trench (DT) of the pixel area (A1) can be interconnected, in some embodiments, the structure of the deep trench (DT) extending to the surrounding area can be set as needed. For example, one end of the deep trench (DT) of the pixel area (A1) can be extended to the trench electrode extraction area (A2).

[0086] Referring to FIG. 3, within the substrate unit (110), the width of the control gate (CG) in the photosensitive area (110a) is, for example, greater than the width of the control gate (CG) in the charge reading area (110b). In the charge reading area (110b), some gate dielectric layers (108) are exposed on both sides of the control gate (CG) through etching. Based on this, further, the exposed gate dielectric layers (108) are removed. In addition, sidewalls are formed on the sides of the gate dielectric layer (108), floating gate (FG), inter-gate dielectric layer (111), and control gate (CG). Then, source / drain ion implantation is performed on the exposed charge reading area (110b) on both sides of the control gate (CG) to form a source region (S) and a drain region (D).

[0087] Referring to step S4 of FIG. 5, the semiconductor substrate (100) is thinned from the other side to expose the deep trench isolation (DTI). Additionally, a substrate electrode (E2) is formed on the other side. The substrate electrode (E2) is in contact with each substrate unit (110) and is isolated from the trench electrode (E1). Voltage can be applied to each substrate unit (110) using the substrate electrode (E2).

[0088] FIG. 6r is a cross-sectional view after the semiconductor substrate has been thinned from the other side. The cross-section shown in FIG. 6r is cut, for example, at the position of line AA' of the plan view shown in FIG. 3. As shown in FIG. 6r, the semiconductor substrate (100) is thinned from one side far from the control gate (CG) to expose the deep trench isolation (DTI). For example, the trench electrode (E1) of the deep trench (DT) is exposed. Some of the trench electrode (E1) may be removed during the thinning process. At this time, the semiconductor substrate (100) of the pixel area (A1) is penetrated by the deep trench isolation (DTI) to form complete physical isolation between the substrate units (110).

[0089] As illustrated in FIG. 6s, a photolithography process and an etching process are performed on the surface of a thinned semiconductor substrate (100) to form a first concave groove (T2) in the exposed deep trench isolation (DTI) portion. The inner surface of the first concave groove (T2) exposes the trench electrode (E1) and the substrate unit (110) around the trench electrode. The cross-section of the first concave groove (T2) is, for example, an inverted trapezoid.

[0090] As illustrated in FIG. 6t, a dielectric material is deposited in the first concave groove (T2) and on the surface of the substrate unit (110) to form a second isolation dielectric (113). The second isolation dielectric (113) fills the first concave groove (T2) and covers the surface of the substrate unit (110).

[0091] As illustrated in FIG. 6u, a second concave groove (T3) is formed corresponding to a first concave groove (T2) through a photolithography process and an etching process. The bottom portion of the second concave groove (T3) is located above the first concave groove (T2). The side surface of the second concave groove (T3) exposes a substrate unit (110) around the deep trench isolation (DTI). The bottom surface of the second concave groove (T3) exposes a second isolation dielectric (113) covering the trench electrode (E1). The bottom surface of the second concave groove (T3) may further expose a substrate unit (110) around the deep trench isolation (DTI).

[0092] Here, the second isolation dielectric (113) may adopt a high dielectric constant material (dielectric constant k is greater than 3.9). Adopting a high dielectric constant material can increase the potential barrier (interface passivation) at the interface between the first concave groove (T2) and the semiconductor substrate (100) and reduce the probability of photoelectrons being captured at the interface. This helps to improve photoelectric conversion efficiency. The material of the high dielectric constant layer may include Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), or TiO2.

[0093] As shown in FIG. 6v, a substrate electrode (E2) is formed by filling the second concave groove (T3) with a conductive material. The substrate electrode (E2) may include one or a combination of titanium, titanium nitride, tantalum nitride, aluminum, copper alloy, and aluminum alloy.

[0094] The vertical charge transfer pixel sensor and the method for manufacturing the vertical charge transfer pixel sensor according to an embodiment of the present invention have the following technical effects. That is, the deep trench isolation (DTI) formed on one side of the semiconductor substrate (100) forms physical isolation between each pixel, thereby securing the photoelectric conversion efficiency of the vertical charge transfer pixel sensor, effectively preventing interference between pixels, and being advantageous for pixel scaling. The substrate electrode (E2) is formed on the other side of the semiconductor substrate (100) (i.e., the side far from the control gate (CG)), so it does not need to occupy the area of ​​the control gate (CG), which is advantageous for pixel scaling; the trench electrode (E1) of the deep trench isolation (DTI) provides one operable electrode terminal to the vertical charge transfer pixel sensor. This can realize a diversified mode of operation together with other electrode terminals of the sensor (e.g., electrode terminals connected to the control gate, source region, and drain region, respectively, and the substrate electrode). For example, the trench electrode (E1) can be used in combination with the substrate electrode (E2). By applying a positive bias voltage between the substrate electrode (E2) and the trench electrode (E1) during the photosensitive process, the potential barrier at the interface between the deep trench isolation and the substrate unit can be increased, thereby reducing the probability that photoelectrons will be trapped at the interface. This helps improve photoelectric conversion efficiency and address dark current and white pixel issues. Additionally, the positive bias voltage can be flexibly adjusted. The isolation dielectric interposed between the trench electrode and the substrate unit can adopt a low dielectric constant material (dielectric constant of 3.9 or less), resulting in a relatively low cost. For example, after one photosensitive and charge reading operation is completed, a negative bias voltage can be applied between the substrate electrode and the trench electrode to perform a reset, thereby releasing the charge trapped in the deep trench isolation boundary region. This helps improve background noise during the next photosensitive and charge reading operation.

[0095] It should be noted that the embodiments of this specification are described in a progressive manner. Each part is described with an emphasis on the differences from the previously described part, and identical and similar parts between the parts may refer to one another.

[0096] The foregoing description is merely a description of a relatively preferred embodiment of the present invention and does not limit the claims of the present invention. A person skilled in the art can make possible changes and modifications to the technical solution of the present invention using the methods and technical content disclosed above, without departing from the spirit and scope of the present invention. Accordingly, all simple modifications, equivalent changes, and variations made to the above embodiments based on the technical essence of the present invention, without departing from the content of the technical solution of the present invention, fall within the scope of protection of the technical solution of the present invention.

Claims

Claim 1 A vertical charge transfer pixel sensor comprises a semiconductor substrate, shallow trench isolation and deep trench isolation, a gate dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate, and a substrate electrode. The semiconductor substrate comprises a pixel region. The shallow trench isolation and deep trench isolation are formed on a first side of the semiconductor substrate. The deep trench isolation comprises a deep trench penetrating the semiconductor substrate, a trench electrode filled within the deep trench, and a first isolation dielectric. The first isolation dielectric insulates the trench electrode from the semiconductor substrate. The deep trench isolation defines a plurality of substrate units within the pixel region. Each of the substrate units includes a photosensitive region and a charge reading region separated by the shallow trench isolation. The gate dielectric layer, the floating gate, the inter-gate dielectric layer and the control gate are formed on the surface of each of the substrate units and extend from the photosensitive region to the charge reading region. In the charge reading region, a source region and a drain region are formed, respectively, located on both sides of the corresponding control gate. A vertical charge transfer pixel sensor characterized in that an electrode is formed on a second side of the semiconductor substrate, the substrate electrode is in contact with each of the substrate units and is isolated from the trench electrode, and in the pixel area, the first isolation dielectric filled within the deep trench comprises a linear oxide layer and a deep trench filling layer, the linear oxide layer is interposed between the trench electrode and the semiconductor substrate, and the deep trench filling layer covers the trench electrode and is located at the top of the deep trench. Claim 2 A vertical charge transfer pixel sensor according to claim 1, wherein the semiconductor substrate includes a trench electrode extraction region located at the outer periphery of the pixel region, and the trench electrode extends from the pixel region to the trench electrode extraction region along the deep trench, and extends from the bottom to the top of the deep trench in the trench electrode extraction region. Claim 3 A vertical charge transfer pixel sensor according to claim 2, further comprising a trench electrode connection block formed in the trench electrode extraction region and covering the trench electrode. Claim 4 delete Claim 5 A vertical charge transfer pixel sensor according to claim 1, wherein the substrate electrode is installed on a second side of the semiconductor substrate corresponding to the deep trench of the pixel region, and a second isolation dielectric is provided between the substrate electrode and the trench electrode. Claim 6 A vertical charge transfer pixel sensor according to claim 5, characterized in that the second isolation dielectric comprises a high dielectric constant material. Claim 7 A vertical charge transfer pixel sensor according to claim 1, wherein the control gate formed in each of the substrate units is connected to a plurality of word lines, and each of the word lines crosses the plurality of substrate units. Claim 8 A method for manufacturing a vertical charge transfer pixel sensor, comprising: providing a semiconductor substrate including a pixel region; forming a shallow trench isolation and a deep trench isolation on a first side of the semiconductor substrate, wherein the deep trench isolation comprises a deep trench penetrating a portion of the semiconductor substrate and a trench electrode and a first isolation dielectric filled within the deep trench, wherein the first isolation dielectric insulates the trench electrode and the semiconductor substrate, and wherein the deep trench isolation defines a plurality of substrate units in the pixel region, and each of the substrate units includes a photosensitive region and a charge reading region separated by the shallow trench isolation; and forming a gate dielectric layer, a floating gate, a gate-to-gate dielectric layer, and a control gate on the surface of each of the substrate units, wherein the gate dielectric layer, the floating gate, the gate-to-gate dielectric layer, and the control gate extend from the photosensitive region to the charge reading region and form a source region and a drain region respectively located on both sides of the control gate corresponding to the charge reading region. A method for manufacturing a vertical charge transfer pixel sensor, comprising the step of thinning the semiconductor substrate from a second side to expose the deep trench isolation and forming a substrate electrode on the second side - wherein the substrate electrode is in contact with each of the substrate units and is isolated from the trench electrode - and the step of forming the shallow trench isolation and the deep trench isolation on the first side of the semiconductor substrate comprises the step of forming a linear oxide layer within the deep trench and the step of forming a deep trench filling layer at the top of the deep trench, wherein the linear oxide layer is interposed between the trench electrode and the semiconductor substrate, and the deep trench filling layer covers the trench electrode. Claim 9 In claim 8, the step of forming the shallow trench isolation and the deep trench isolation on the first side of the semiconductor substrate comprises: forming a pad oxide layer and a first hard mask layer on the surface of the semiconductor substrate; and forming the shallow trench isolation that penetrates the first hard mask layer, the pad oxide layer, and a portion of the semiconductor substrate. A method for manufacturing a vertical charge transfer pixel sensor, further comprising: a step of forming a second hard mask layer covering the first hard mask layer and the shallow trench isolation layer; a step of forming a deep trench penetrating the second hard mask layer, the first hard mask layer, the pad oxide layer and a portion of the semiconductor substrate; a step of forming a trench conductive layer within the deep trench, wherein the linear oxide layer covers the semiconductor substrate exposed by the deep trench, the trench conductive layer covers the linear oxide layer and fills the deep trench, and the top surface of the trench conductive layer is higher than the surface of the semiconductor substrate; a step of etching back the trench conductive layer of the pixel area to below the surface of the semiconductor substrate to form an etching back space at the top of the deep trench of the pixel area, wherein the remaining trench conductive layer is a trench electrode; and a step of forming a deep trench filling layer within the etching back space, wherein the linear oxide layer and the deep trench filling layer are the first isolation dielectric. Claim 10 A method for manufacturing a vertical charge transfer pixel sensor according to claim 8 or 9, wherein the semiconductor substrate includes a trench electrode extraction region located at the outer periphery of the pixel region, and the trench electrode extends from the pixel region to the trench electrode extraction region along the deep trench, and extends from the bottom to the top of the deep trench in the trench electrode extraction region. Claim 11 A method for manufacturing a vertical charge transfer pixel sensor, wherein, in claim 8 or 9, the step of forming the substrate electrode comprises: forming a first concave groove in the deep trench isolation exposed from the second side of the semiconductor substrate, wherein the first concave groove exposes the trench electrode and the substrate unit surrounding the trench electrode; forming a second isolation dielectric on the second side, wherein the second isolation dielectric fills the first concave groove and covers the surface of the substrate unit; forming a second concave groove, wherein the bottom portion of the second concave groove is located above the first concave groove, the side surface of the second concave groove exposes the substrate unit surrounding the deep trench isolation, and the trench electrode is covered by the second isolation dielectric; and filling a conductive material into the second concave groove to form the substrate electrode.

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