Page buffer and semiconductor apparatus including the same

Abstract

The present technology may include an evaluation time setting unit configured to store an evaluation setting value as a first value or a second value; and a bit line control unit configured to precharge a sensing node in response to a first precharge signal and to precharge the sensing node in response to a second precharge signal and an evaluation setting value, wherein the deactivation timing is set differently from the first precharge signal.

Description

Technology Field

[0001] The present invention relates to a semiconductor circuit, and more particularly to a page buffer and a semiconductor device including the same. Background Technology

[0002] Semiconductor devices, such as memory devices, can be classified into volatile memory devices and nonvolatile memory devices. Nonvolatile memory devices can retain stored data even when the power supply is cut off. Therefore, nonvolatile memory devices are widely used in portable electronic devices to store data that must be maintained regardless of power supply.

[0003] Non-volatile memory devices can be classified into ROM (Read Only Memory), MROM (Mask ROM), PROM (Programmable ROM), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), Flash memory, PRAM (Phase change Random Access Memory), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (Ferro-electric RAM), etc., depending on how data is stored.

[0004] Unlike volatile memory, flash memory does not require a refresh function to rewrite data at regular intervals, so the demand for it is increasing. Flash memory can be electrically programmed and erased, and

[0005] Flash memory can be formed as a two-dimensional structure in which strings are arranged horizontally on a semiconductor substrate, or as a three-dimensional structure in which strings are stacked vertically on a semiconductor substrate. A three-dimensional memory device is a memory device designed to overcome the integration density limitations of a two-dimensional memory device and may include a plurality of memory cells stacked vertically on a semiconductor substrate.

[0006] Recently, active research is being conducted on multi-bit cells capable of storing multiple data points of two or more bits within a single memory cell to increase storage capacity in smaller chip sizes. Memory cells of this type are commonly referred to as Multi-Level Cells (MLCs). Unlike Single-Level Cells (SLCs), which have two states (program and erase), Multi-Level Cells can represent two, three, or four or more bits of data within a single cell, thereby enabling more than double the memory capacity compared to SLCs. Multi-Level Cells typically have two or more threshold voltage distributions and two or more corresponding data storage states. Prior art literature

[65535] Korean Published Patent No. 2014-0025164 The problem to be solved

[0007] An embodiment of the present invention provides a page buffer capable of improving program verification operation efficiency and a semiconductor device including the same. means of solving the problem

[0008] An embodiment of the present invention may include an evaluation time setting unit configured to store an evaluation setting value as a first value or a second value; and a bit line control unit configured to precharge a sensing node in response to a first precharge signal and to precharge the sensing node in response to a second precharge signal and an evaluation setting value, wherein the deactivation timing is set differently from the first precharge signal.

[0009] An embodiment of the present invention may include a memory cell array; a plurality of page buffers connected to each of a plurality of bit lines of the memory cell array, wherein each of the plurality of page buffers is configured to store an evaluation time setting value as a first value or a second value, and a bit line control unit configured to precharge a sensing node in response to a first precharge signal and to precharge the sensing node in response to a second precharge signal and an evaluation setting value, wherein the deactivation timing is set differently from the first precharge signal. Effects of the invention

[0010] This technology can improve the efficiency of program verification operations. Brief explanation of the drawing

[0011] FIG. 1 is a diagram showing the configuration of a memory system (1000) including a memory device according to an embodiment of the present invention. FIG. 2 is a diagram showing the configuration of the semiconductor memory device (100) of FIG. 1. FIG. 3 is a diagram showing memory blocks configured in three dimensions. FIG. 4 is a diagram showing the configuration of any one of the memory blocks illustrated in FIG. 3. FIG. 5 is a diagram showing the configuration of memory strings illustrated in FIG. 4. FIG. 6 is a diagram showing the configuration of a page buffer according to an embodiment of the present invention. FIGS. 7 and 8 are diagrams for explaining the operation of a page buffer when the evaluation setting value is set to a first value, and FIGS. 9 and FIGS. 10 are diagrams for explaining the operation of a page buffer when the evaluation setting value is set to a first value. Specific details for implementing the invention

[0012] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings.

[0013] FIG. 1 is a diagram showing the configuration of a memory system (1000) including a memory device according to an embodiment of the present invention.

[0014] Referring to FIG. 1, a memory system (1000) may include a memory device (1100), a controller (1200), and a host (1300). The memory device (1100) includes a plurality of semiconductor memory devices (100). The plurality of semiconductor memory devices (100) may be divided into a plurality of groups (GR1 to GRn). Each of the plurality of groups (GR1 to GRn) may communicate with the controller (1200) through the first to n channels (CH1 to CHn). In an embodiment of the present invention, the host (1300) is shown and described as being included in the memory system (1000), but the memory system (1000) may be configured to include only the controller (1200) and the memory device (1100), and the host (1300) may be placed outside the memory system (1000).

[0015] The controller (1200) may be configured to control multiple semiconductor memory devices (100) of the memory device (1100) through multiple channels (CH1~CHn). The controller (1200) is connected between the host (1300) and the memory device (1100). The controller (1200) is configured to access the memory device (1100) in response to a request from the host (1300). For example, the controller (1200) may be configured to control read, program, erase, and verify operations of the memory device (1100) in response to a host command (Host_CMD) received from the host (1300). During a program operation, the host (1300) may transmit an address (ADD) and data to be programmed (DATA) along with the host command (Host_CMD), and during a read operation, the address (ADD) may be transmitted along with the host command (Host_CMD). The controller (1200) can transmit a command corresponding to the program operation and data to be programmed (DATA) to the memory device (1100) when a program operation is performed. When a read operation is performed, the controller (1200) can transmit a command corresponding to the read operation to the memory device (1100), receive the read data (DATA) from the memory device (1100), and transmit the received data (DATA) to the host (1300). The controller (1200) can be configured to provide an interface between the memory device (1100) and the host (1300).

[0016] The host (1300) may include portable electronic devices such as a computer, PDA, PMP, MP3 player, camera, camcorder, mobile phone, etc. The host (1300) may request program operation, read operation, erase operation, etc. of the memory system (1000) through a host command (Host_CMD). For program operation of the memory device (1100), the host (1300) may transmit a host command (Host_CMD), data (DATA), and address (ADD) corresponding to the program operation to the controller (1200), and for read operation, the host may transmit a host command (Host_CMD) and address (ADD) corresponding to the read operation to the controller (1200).

[0017] The controller (1200) and the memory device (1100) can be integrated into a single semiconductor memory device. As an exemplary embodiment, the controller (1200) and the memory device (1100) can be integrated into a single semiconductor memory device to form a memory card. For example, the controller (1200) and the memory device (1100) can be integrated into a single semiconductor memory device to form a memory card such as a PC card (PCMCIA, personal computer memory card international association), Compact Flash card (CF), Smart Media card (SM, SMC), Memory Stick, Multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0018] As another example, the memory system (1000) is one of a computer, UMPC (Ultra Mobile PC), workstation, netbook, PDA (Personal Digital Assistants), portable computer, web tablet, wireless phone, mobile phone, smartphone, e-book, PMP (portable multimedia player), portable game console, navigation device, black box, digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network It can be provided as one of the various components of an electronic device, such as an RFID device or one of the various components constituting a computing system.

[0019] As an exemplary embodiment, the memory device (1100) or memory system (1000) may be mounted in various types of packages. For example, the memory device (1100) or memory system (1000) may be mounted in a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), wafer-level processed stack package (WSP), etc.

[0020] Figure 2 is a diagram showing the configuration of the semiconductor memory device (100) of Figure 1.

[0021] Referring to FIG. 2, a semiconductor memory device (100) may include a memory cell array (110), an address decoder (120), a read and write circuit (130), control logic (140), and a voltage generation circuit (150). The address decoder (120), the read and write circuit (130), and the voltage generation circuit (150) may be defined as peripheral circuits (160) that perform a read operation for the memory cell array (110).

[0022] A memory cell array (110) may include a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) may be connected to an address decoder (120) via word lines (WL). The plurality of memory blocks (BLK1 to BLKz) may be connected to a read and write circuit (130) via bit lines (BL1 to BLm). Each of the plurality of memory blocks (BLK1 to BLKz) may include a plurality of memory cells. As an example, the plurality of memory cells are non-volatile memory cells. A plurality of memory cells connected to one of the word lines of the plurality of memory cells may be defined as a single page. That is, the memory cell array (110) may be composed of a plurality of pages. Each of the plurality of memory blocks (BLK1 to BLKz) of the memory cell array (110) may include a plurality of memory strings, which will be specifically explained through FIGS. 4 and FIGS. 5 described later.

[0023] The address decoder (120) can be connected to the memory cell array (110) via word lines (WL). The address decoder (120) can be configured to operate on address decoder control signals (AD_signals) generated by the control logic (140). The address decoder (120) can receive an address (ADDR) through an input / output buffer (not shown) inside the memory device (100). The address decoder (120) can decode row addresses among the received addresses (ADDR) and apply a plurality of operating voltages, including a program voltage (Vpgm), read voltage (Vread), pass voltage (Vpass), and verification voltage (Vverify), generated by the voltage generation circuit (150) during program operation, to a plurality of memory cells of the memory cell array (110) according to the decoded row addresses. The address decoder (120) can be configured to decode column addresses among the received addresses (ADDR). The address decoder (120) can transmit the decoded column address (Yi) to the read and write circuit (130). The address (ADDR) received during a program operation or a read operation may include a block address, a row address, and a column address. The address decoder (120) may select one memory block and one word line according to the block address and the row address. The column address may be decoded by the address decoder (120) and provided to the read and write circuit (130). The address decoder (120) may include a block decoder, a row decoder, a column decoder, and an address buffer, etc.

[0024] The read and write circuit (130) may include a plurality of page buffers (PB1 to PBm). The plurality of page buffers (PB1 to PBm) may be connected to a memory cell array (110) through bit lines (BL1 to BLm). The plurality of page buffers (PB1 to PBm) may perform a sensing operation to sense the program state of memory cells connected to the bit lines (BL1 to BLm) during a read operation or a verification operation. During the sensing operation, each of the plurality of page buffers (PB1 to PBm) may precharge a sensing node within the page buffer to a certain level, control the potential level of the sensing node based on the current amount of the corresponding bit lines (BL1 to BLm), and then latch data corresponding to the potential level of the sensing node. Additionally, a plurality of page buffers (PB1 to PBm) receive data to be programmed during a program operation and temporarily store it, and can adjust the potential level of corresponding bit lines (BL1 to BLm) based on the temporarily stored data. The read and write circuit (130) can operate in response to page buffer control signals (PB_signals) output from the control logic (140). As an exemplary embodiment, the read and write circuit (130) may include page buffers (or page registers), a column selection circuit, etc.

[0025] A page buffer according to an embodiment of the present invention can store an evaluation setting value in a latch and enable the evaluation operation to be performed for a desired period of time simply by adjusting the deactivation timing of a plurality of precharge passes differently.

[0026] The control logic (140) may be connected to an address decoder (120), a read and write circuit (130), and a voltage generation circuit (150). The control logic (140) may receive a command (CMD) through an input / output buffer (not shown) of the semiconductor memory device (100). The control logic (140) may be configured to control the general operation of the semiconductor memory device (100) in response to the command (CMD). For example, the control logic (140) may receive a command (CMD) corresponding to a program operation and, in response to the received command (CMD), generate and output address decoder control signals (AD_signals) for controlling the address decoder (120), page buffer control signals (PB_signals) for controlling the read and write circuit (130), and voltage generation circuit control signals (VG_signals) for controlling the voltage generation circuit (150). Additionally, the control logic (140) receives a command (CMD) corresponding to a read operation and, in response to the received command (CMD), can generate and output address decoder control signals (AD_signals) for controlling the address decoder (120), page buffer control signals (PB_signals) for controlling the read and write circuit (130), and voltage generation circuit control signals (VG_signals) for controlling the voltage generation circuit (150).

[0027] The voltage generation circuit (150) can generate a program voltage (Vpgm), a pass voltage (Vpass), and a verification voltage (Vverify) according to the control of the voltage generation circuit control signals (VG_signals) output from the control logic (140) during a program operation, and output them to the address decoder (120). Additionally, the voltage generation circuit (150) can generate a read voltage (Vread) and a pass voltage (Vpass) according to the control of the voltage generation circuit control signals (VG_signals) output from the control logic (140) during a read operation, and output them to the address decoder (120).

[0028] Figure 3 is a diagram showing the configuration of memory blocks arranged in three dimensions.

[0029] Referring to FIG. 3, memory blocks (BLK1 to BLKz) configured in three dimensions may be arranged spaced apart from each other along the direction (Y) in which bit lines (BL1 to BLm) are extended. For example, the first to zth memory blocks (BLK1 to BLKz) may be arranged spaced apart from each other along the second direction (Y) and may include a plurality of memory cells stacked along the third direction (Z). The configuration of any one of the first to zth memory blocks (BLK1 to BLKz) will be described in detail through FIG. 4 and FIG. 5, which will be described later.

[0030] FIG. 4 is a diagram showing the configuration of one of the memory blocks shown in FIG. 3, and FIG. 5 is a diagram showing the configuration of memory strings shown in FIG. 4.

[0031] Referring to FIGS. 4 and 5, each memory string (ST) can be connected between bit lines (BL1~BLm) and source lines (SL). An example of a memory string (ST) connected between a first bit line (BL1) and a source line (SL) is described as follows.

[0032] A memory string (ST) may include a source select transistor (SST), memory cells (F1 to Fn; n is a positive integer), and a drain select transistor (DST) connected in series between a source line (SL) and a first bit line (BL1). The gates of the source select transistors (SST) included in different memory strings (ST) connected to different bit lines (BL1 to BLm) may be connected to a first source select line (SSL0) and may be connected to a second source select line (SSL1). For example, among the source select transistors (SST), source select transistors adjacent to each other in a second direction (Y) may be connected to the same source select line. For example, assuming that source select transistors (SST) are arranged sequentially along the second direction (Y), the gates of source select transistors (SST) arranged in the first direction (X) from the first source select transistor (SST) and included in other strings (ST), and the gates of source select transistors (SST) arranged in the first direction (X) from the second source select transistor (SST) and included in other strings (ST) can be connected to the first source select line (SSL0). Additionally, the gates of source select transistors (SST) arranged in the first direction (X) from the third source select transistor (SST) and included in other strings (ST), and the gates of source select transistors (SST) arranged in the first direction (X) from the fourth source select transistor (SST) and included in other strings (ST) can be connected to the second source select line (SSL1).

[0033] The gates of memory cells (F1 to Fn) can be connected to word lines (WL1 to WLn), and the gates of drain select transistors (DST) can be connected to any one of the first to fourth drain select lines (DSL0 to DSL3). Among the drain select transistors (DST), the gates of transistors arranged in the first direction (X) are commonly connected to the same drain select line (e.g., DSL0), but transistors arranged in the second direction (Y) can be connected to different drain select lines (DSL1 to DSL3). For example, assuming that drain select transistors (DST) are arranged sequentially along the second direction (Y), the gates of drain select transistors (DST) arranged in the first direction (X) from the first drain select transistor (DST) and included in other strings (ST) can be connected to the first drain select line (DSL0). Drain select transistors (DST) arranged in the second direction (Y) from the drain select transistors (DST) connected to the first drain select line (DSL0) can be sequentially connected to the second to fourth drain select lines (DSL1 to DSL3). Accordingly, within the selected memory block, memory strings (ST) connected to the selected drain select line can be selected, and memory strings (ST) connected to the remaining non-selected drain select lines can be non-selected.

[0034] Memory cells connected to the same word line can form a single page (PG). Here, a page refers to a physical page. For example, among strings (ST) connected to the first bit line (BL1) through the m-th bit line (BLm), a group of memory cells connected in the same word line in the first direction (X) is called a page (PG). For example, among the first memory cells (F1) connected to the first word line (WL1), memory cells arranged along the first direction (X) can form a single page (PG). Among the first memory cells (F1) connected in common to the first word line (WL1), cells arranged in the second direction (Y) can be distinguished as different pages. Accordingly, when the first drain selection line (DSL0) is the selected drain selection line and the first word line (WL1) is the selected word line, among the multiple pages (PG) connected to the first word line (WL1), the page connected to the first drain selection line (DSL0) becomes the selected page. Pages connected to the second to fourth drain selection lines (DSL1~DSL3) that are commonly connected to the first word line (WL1) but are not selected become the unselected pages.

[0035] In the drawing, it is shown that one source select transistor (SST) and one drain select transistor (DST) are each included within a single string (ST); however, depending on the semiconductor memory device, multiple source select transistors (SST) and drain select transistors (DST) may be included within a single string (ST). Additionally, depending on the memory device, dummy cells may be included between the source select transistor (SST), memory cells (F1~Fn), and drain select transistor (DST). Dummy cells do not store user data like general memory cells (F1~Fn), but can be used to improve the electrical characteristics of each string (ST). However, since dummy cells are not a critical component in this embodiment, a detailed description is omitted.

[0036] FIG. 6 is a diagram showing the configuration of a page buffer according to an embodiment of the present invention.

[0037] Referring to FIG. 6, a page buffer (PB1) according to an embodiment of the present invention may include a bit line control unit (131) and an evaluation time setting unit (133).

[0038] The bit line control unit (131) can precharge the sensing node (SO) during a precharge operation for a read operation or a verification operation, and control the potential level of the sensing node (SO) based on the amount of current of the bit line (BL1) that changes according to the program state of the memory cell connected to the bit line (BL1) during a sensing operation performed after the precharge operation.

[0039] The bit line control unit (131) can be configured to precharge the first node (ND1) using the power supply voltage (VCORE) in response to the first precharge signal (SA_PRC1), connect the first node (ND1) and the sensing node (SO) in response to the second precharge signal (SA_PRC2) in which the deactivation timing is different from the first precharge signal (SA_PRC1), that is, the deactivation timing is set later than the first precharge signal (SA_PRC1), and precharge the first node (ND1) using the power supply voltage (VCORE) in response to the evaluation setting value.

[0040] The bit line control unit (131) may include a first precharge unit (131-1), a second precharge unit (131-2), and a plurality of switching elements. The first precharge unit (131-1) may include a first transistor (P1) connected between a power supply voltage (VCORE) terminal and a first node (ND1). The first transistor (P1) may precharge the first node (ND1) using the power supply voltage (VCORE) in response to a first precharge signal (SA_PRC1).

[0041] The second precharge unit (131-2) may include a second transistor (P2) connected between the power supply voltage (VCORE) terminal and the first node (ND1) in parallel with the first transistor (P1), and a third transistor (P3) connected between the first node (ND1) and the sensing node (SO). The second transistor (P2) may connect the first node (ND1) and the sensing node (SO) in response to a second precharge signal (SA_PRC2) with a different deactivation timing than the first precharge signal (SA_PRC1). The activation timing of the first precharge signal (SA_PRC1) and the second precharge signal (SA_PRC2) may be the same or different. The second precharge signal (SA_PRC2) may be deactivated at a later timing compared to the first precharge signal (SA_PRC1). The third transistor (P3) can precharge the first node (ND1) using the power supply voltage (VCORE) in response to the evaluation setting value.

[0042] A plurality of switching elements may include 4th to 9th transistors (N1-N6). The 4th transistor (N1) is connected between the bit line (BL1) and the 2nd node (ND2) and can connect the bit line (BL1) and the 2nd node (ND2) in response to a page buffer select signal (PB_SEL). The 5th transistor (N2) is connected between the 2nd node (ND2) and the common sensing node (CSO) and can connect the 2nd node (ND2) and the common sensing node (CSO) in response to a page buffer sensing signal (PB_SENSE). The 6th transistor (N3) is connected between the power supply voltage (Vcore) terminal and the common sensing node (CSO) and can precharge the common sensing node (CSO) using the power supply voltage (Vcore) in response to a common sensing control signal (SA_CSOC1). At this time, the common sensing node (CSO) can be precharged to a potential level reduced by the threshold voltage of the sixth transistor (N3) from the power supply voltage (Vcore). The seventh transistor (N4) is connected between the sensing node (SO) and the common sensing node (CSO), and can connect the sensing node (SO) and the common sensing node (CSO) in response to the sensing signal (SA_SENSE). During the sensing node precharge operation, as the seventh transistor (N4) connects the common sensing node (CSO) and the sensing node (SO) in response to the sensing signal (SA_SENSE), the sensing node (SO) can be precharged to a potential level lower than the potential level of the common sensing node (CSO) by the threshold voltage of the seventh transistor (N4). The eighth transistor (N5) is connected to the third node (ND3) between the common sensing node (CSO) and the sensing node (SO), and can be turned on or turned off in response to the discharge signal (SA_DISCH). The ninth transistor (N6) is connected between the eighth transistor (N5) and the ground power supply (VSS), and can be turned on or turned off depending on the potential level of the latch output node (QS).For example, when the latch output node (QS) is logic high, the ninth transistor (N6) is turned on, so the eighth transistor (N5) can discharge the sensing node (SO) in response to the discharge signal (SA_DISCH).

[0043] The evaluation time setting unit (133) may include a latch (133-1) and a setting unit (133-2). The latch (133-1) may store an evaluation setting value. The latch (133-1) may include inverters (IV1 and IV2) connected in reverse parallel between latch output nodes (QS, QS_N). The setting unit (133-2) may set the evaluation setting value to be stored in the latch (133-1) to a first value or a second value according to evaluation control signals (SSET, SRST). The first value may be logic high (1), and the second value may be logic low (0). The setting unit (133-2) may include a 10th transistor (N7) connected to the latch output node (QS_N) and turned on or off according to the evaluation control signal (SSET), an 11th transistor (N8) connected to the latch output node (QS) and turned on or off according to the evaluation control signal (SRST), and a 12th transistor (N9) having one end commonly connected to the 10th transistor (N7) and the 11th transistor (N8) and the other end connected to the ground power supply (VSS) and turned on or off according to the potential level of the sensing node (SO). The evaluation control signal (SSET) can be generated as a logic high to set the evaluation setting value to a logic high, and accordingly, the potential level of the latch output node (QS) can be maintained at a logic high. The evaluation control signal (SRST) can be generated as a logic high to set the evaluation setting value to a logic low, and accordingly, the potential level of the latch output node (QS) can be maintained at a logic low.

[0044] Hereinafter, the operation of the page buffer in each case where the evaluation setting value is set to '1' and '0' will be explained with reference to FIGS. 7 to 10.

[0045] Figures 7 and 8 are diagrams for explaining the operation of a page buffer when the evaluation setting value is set to the first value, i.e., '1'.

[0046] First, prior to the evaluation operation, the evaluation control signal (SSET) can be generated as logic high to set the evaluation setting value to logic high.

[0047] The page buffer select signal (PB_SEL) becomes logic high, and the bit line (BL1) is selected.

[0048] As the page buffer sensing signal (PB_SENSE) and the common sensing control signal (SA_CSOC1) are activated to logic high, the common sensing node (CSO) is precharged by the power supply voltage (VCORE).

[0049] Since the evaluation setting value, i.e., the latch output node (QS), is at a logic high level, the second transistor (P2) is in a turned-off state. As the first precharge signal (SA_PRC1) and the second precharge signal (SA_PRC2) are activated to logic low, the first transistor (P1) and the third transistor (P3) are turned on so that the sensing node (SO) can be precharged using the power supply voltage (VCORE). After the activation of the first precharge signal (SA_PRC1) and the second precharge signal (SA_PRC2), the sensing signal (SA_SENSE) can be activated to logic high after a predetermined time delay.

[0050] After the first precharge signal (SA_PRC1) is deactivated to a logic high, the second precharge signal (SA_PRC2) is deactivated to a logic high after a predetermined time interval. Since the second transistor (P2) is in a turned-off state and the first transistor (P1) is also turned off from the point when the first precharge signal (SA_PRC1) is deactivated to a logic high, the current path for precharging the sensing node (SO) is blocked.

[0051] Therefore, when the evaluation setting value is '1', the evaluation time (tEVAL, QS=1) corresponds to the period from when the first precharge signal (SA_PRC1) is deactivated to logic high until the sensing signal (SA_SENSE) is deactivated to logic low, and the evaluation operation can be performed during that time.

[0052] Figures 9 and 10 are diagrams illustrating the operation of a page buffer when the evaluation setting value is set to '0'.

[0053] First, prior to the evaluation operation, the evaluation control signal (SRST) can be generated as logic high to set the evaluation setting value to logic low.

[0054] The page buffer select signal (PB_SEL) becomes logic high, and the bit line (BL1) is selected.

[0055] As the page buffer sensing signal (PB_SENSE) and the common sensing control signal (SA_CSOC1) are activated to logic high, the common sensing node (CSO) is precharged by the power supply voltage (VCORE).

[0056] Since the evaluation setting value, i.e., the latch output node (QS), is logic low, the second transistor (P2) is turned on. As the first precharge signal (SA_PRC1) and the second precharge signal (SA_PRC2) are activated to logic low, the first transistor (P1) and the third transistor (P3) are turned on, allowing the sensing node (SO) to be precharged using the power supply voltage (VCORE). After the activation of the first precharge signal (SA_PRC1) and the second precharge signal (SA_PRC2), the sensing signal (SA_SENSE) can be activated to logic high after a predetermined time delay.

[0057] After the first precharge signal (SA_PRC1) is deactivated to a logic high, the second precharge signal (SA_PRC2) is deactivated to a logic high after a predetermined time interval. As the first precharge signal (SA_PRC1) is deactivated to a logic high, the first transistor (P1) is turned off. However, since the second transistor (P2) is turned on, during the period when the second precharge signal (SA_PRC2) is logic low, the second transistor (P2) and the third transistor (P3) precharge the sensing node (SO) using the power supply voltage (VCORE).

[0058] Therefore, when the evaluation setting value is '0', the evaluation time (tEVAL, QS-0) corresponds to the interval from when the second precharge signal (SA_PRC2) is deactivated to logic high until the sensing signal (SA_SENSE) is deactivated to logic low, and the evaluation operation can be performed during that time. That is, when the evaluation setting value is set to '0', the evaluation operation can be performed for a relatively shorter time compared to when the evaluation setting value is set to '1'.

[0059] The above-described embodiment of the present invention can enable the evaluation operation to be performed for a desired time simply by storing the evaluation setting value in a latch and adjusting the deactivation timing of the first precharge signal (SA_PRC1) and the second precharge signal (SA_PRC2) differently.

[0060] As such, those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the present invention.

Claims

Claim 1 A page buffer comprising: an evaluation time setting unit configured to store an evaluation setting value as a first value or a second value; and a bit line control unit configured to precharge a sensing node in response to a first precharge signal, and to precharge the sensing node in response to a second precharge signal and the evaluation setting value, wherein the deactivation timing is set differently from the first precharge signal. Claim 2 In claim 1, the page buffer is configured to perform an evaluation operation for a relatively shorter time compared to the case where the evaluation setting value is the first value when the evaluation setting value is the second value. Claim 3 A page buffer according to claim 1, configured to deactivate the second precharge signal after a predetermined time delay following the deactivation of the first precharge signal. Claim 4 In claim 3, a page buffer configured to simultaneously activate the first precharge signal and the second precharge signal. Claim 5 In claim 1, the evaluation time setting unit comprises a latch configured to store the evaluation setting value, and a setting unit configured to set the evaluation setting value to be stored in the latch to a first value or a second value according to evaluation control signals, for a page buffer. Claim 6 In claim 1, the bit line control unit comprises a first precharge unit configured to precharge a first node in response to a first precharge signal, and a second precharge unit configured to connect the first node and the sensing node in response to a second precharge signal and to precharge the sensing node in response to an evaluation setting value, thereby forming a page buffer. Claim 7 A semiconductor device comprising: a memory cell array; a plurality of page buffers connected to each of a plurality of bit lines of the memory cell array, wherein each of the plurality of page buffers is configured to store an evaluation time setting value as a first value or a second value; and a bit line control unit configured to precharge a sensing node in response to a first precharge signal and to precharge the sensing node in response to a second precharge signal and an evaluation setting value, wherein the deactivation timing is set differently from the first precharge signal. Claim 8 In claim 7, the semiconductor device is configured to perform an evaluation operation for a relatively shorter time compared to the case where the evaluation setting value is the first value when the evaluation setting value is the second value. Claim 9 A semiconductor device according to claim 7, configured to deactivate the second precharge signal after a predetermined time delay following the deactivation of the first precharge signal. Claim 10 A semiconductor device configured to simultaneously activate the first precharge signal and the second precharge signal in claim 9. Claim 11 A semiconductor device according to claim 7, wherein the evaluation time setting unit comprises a latch configured to store the evaluation setting value, and a setting unit configured to set the evaluation setting value to be stored in the latch to a first value or a second value according to evaluation control signals. Claim 12 A semiconductor device according to claim 7, wherein the bit line control unit comprises a first precharge unit configured to precharge a first node in response to a first precharge signal, and a second precharge unit configured to connect the first node and the sensing node in response to a second precharge signal and to precharge the sensing node in response to an evaluation setting value.

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