Printed circuit board and method for data processing

Abstract

According to various embodiments of the present disclosure, a printed circuit board comprising a plurality of PBAs and an interface connecting the plurality of PBAs and an external device, wherein the interface comprises terminals having an N * M array, and terminals having an N * K array among the terminals having the N * M array are electrically connected to each of the plurality of PBAs, and each PBA comprises a volatile memory, a non-volatile memory, and a processor, and when power is supplied from a first terminal among the terminals having the N * K array, each PBA transmits a first parameter signal to a second terminal among the terminals having the N * K array, and in response to the transmission of the first parameter signal, stores boot-loader data received from the external device in the volatile memory, transmits a second parameter signal to a third terminal among the terminals having the N * K array, and in response to the storage of the boot-loader data, stores binary data received from the external device in the non-volatile memory.

Description

Technology Field

[0001] The embodiments disclosed in this document relate to a printed circuit board including a memory and a method for writing data thereto. Background Technology

[0002] For power to be input to an electronic device and for a program to be executed, the operating system booting process precedes program execution. For the operating system booting process to be performed, bootloader data must be stored in a memory device.

[0003] In order for a memory device containing bootloader data to be placed within an electronic device, a printed circuit board including a memory device can be placed in the electronic device. Specifically, a memory device containing bootloader data can be mounted within the electronic device by storing bootloader data in a non-volatile memory device and then placing the non-volatile memory device containing the bootloader data on the printed circuit board. The problem to be solved

[0004] To mount a memory device containing bootloader and binary data onto a printed circuit board, a reflow process utilizing bonding materials and high temperatures must be performed. During this process, the high heat generated when mounting the memory device onto the board can damage the data stored inside the device.

[0005] If data stored inside a memory device is damaged due to high heat, the damaged memory device mounted on the printed circuit board must be replaced. In order to replace the damaged memory device mounted on the printed circuit board, heat must be applied to the memory device again to separate it from the printed circuit board, which can cause the memory device to be damaged secondarily, and in this case, the damaged memory device may have to be discarded.

[0006] Therefore, if data stored in a memory device mounted on a printed circuit board is damaged due to high heat, replacement and disposal costs are incurred, leading to a problem of reduced productivity. means of solving the problem

[0007] According to various embodiments of the present disclosure, a printed circuit board comprising a plurality of PBAs and an interface connecting the plurality of PBAs and an external device, wherein the interface comprises terminals having an N * M array, and terminals having an N * K array among the terminals having the N * M array are electrically connected to each of the plurality of PBAs, and each PBA comprises a volatile memory, a non-volatile memory, and a processor, and when power is supplied from a first terminal among the terminals having the N * K array, each PBA transmits a first parameter signal to a second terminal among the terminals having the N * K array, and in response to the transmission of the first parameter signal, stores boot-loader data received from the external device in the volatile memory, transmits a second parameter signal to a third terminal among the terminals having the N * K array, and in response to the storage of the boot-loader data, stores binary data received from the external device in the non-volatile memory.

[0008] According to various embodiments of the present disclosure, a printed circuit board comprises a plurality of PBAs and an interface connecting the plurality of PBAs and an external device, and a method for processing data for a volatile memory and a non-volatile memory disposed within each PBA comprises, when power is supplied from a first terminal of the interface, an operation of transmitting a first parameter signal to at least one second terminal of the interface, an operation of storing bootloader data received from the external device in the volatile memory in response to the transmission of the first parameter signal, an operation of transmitting a second parameter signal to the at least one second terminal in response to the storage of the bootloader data, and an operation of storing binary data received from the external device in the non-volatile memory in response to the transmission of the second parameter signal, wherein the interface comprises terminals having an N * M array, and terminals having an N * K array among the terminals having an N * M array may be electrically connected to each of the plurality of PBAs.

[0009] According to various embodiments of the present disclosure, a printed circuit board comprising a plurality of PBAs includes an interface connecting the plurality of PBAs and an external device, wherein each of the plurality of PBAs includes a volatile memory, a non-volatile memory, and a processor, and each of the PBAs transmits a first parameter signal to at least one second terminal of the interface to which power is supplied from a first terminal of the interface, and in response to the transmission of the first parameter signal, stores bootloader data received from the external device in the volatile memory, transmits a second parameter signal to the at least one second terminal in response to the storage of the bootloader data, and in response to the transmission of the second parameter signal, stores binary data received from the external device in the non-volatile memory. Effects of the invention

[0010] According to the various embodiments disclosed in this document, data stored in a memory device can be prevented from being damaged by high heat.

[0011] According to the various embodiments disclosed in this document, productivity can be increased by preventing the cost and time required to replace a memory device when the memory device mounted on a printed circuit board is damaged.

[0012] In addition, various effects that can be identified directly or indirectly through this document may be provided. Brief explanation of the drawing

[0013] FIG. 1 shows a printed circuit board comprising a plurality of PBAs according to various embodiments. FIG. 2 is a block diagram of a printed circuit board including a plurality of PBAs according to various embodiments. FIG. 3 shows the connection relationship between a printed circuit board including a plurality of PBAs and an external device according to various embodiments. FIG. 4 shows an interface connecting a plurality of PBAs included in a printed circuit board and an external device according to various embodiments. FIG. 5 is a flowchart illustrating a method of storing data in a memory placed in each of a plurality of PBAs according to various embodiments. FIG. 6 is a flowchart illustrating a method for determining whether volatile memory and non-volatile memory included in each PBA in a printed circuit board including a plurality of PBAs according to various embodiments are properly mounted. FIG. 7 is a flowchart illustrating a power-on reset (POR) process according to various embodiments. FIG. 8 is a block diagram of an electronic device in a network environment according to various embodiments. Specific details for implementing the invention

[0014] Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings. However, this is not intended to limit the present disclosure to specific embodiments and should be understood to include various modifications, equivalents, or alternatives to the embodiments of the present disclosure.

[0015] FIG. 1 shows a printed circuit board (100) including a plurality of PBAs (120) according to various embodiments.

[0016] In one embodiment, the printed circuit board (100) may include a first surface (100a) and a second surface (100b) opposite to the first surface (100a).

[0017] In one embodiment, the printed circuit board (100) may include a plurality of PBAs (120) and an interface (110).

[0018] In one embodiment, the printed circuit board (100) may include a plurality of printed board assemblies (PBAs) (120). In one example, the plurality of PBAs (120) may include a first PBA (121), a second PBA (122), a third PBA (123), a fourth PBA (124), a fifth PBA (125), and a sixth PBA (126). Although the plurality of PBAs (120) is illustrated as including six PBAs, it is not limited thereto.

[0019] In one embodiment, a PBA for any one of the first PBA (121) to sixth PBA (126) included in a plurality of PBAs (120) may be referred to as each PBA.

[0020] In one embodiment, a plurality of PBAs (120) can be connected to a printed circuit board (100) through a plurality of bridges (111).

[0021] Referring to FIG. 1 (a), an interface (110) may be disposed on a first surface (100a) of a printed circuit board (100). In one example, each PBA disposed on the first surface (100a) of the printed circuit board (100) may include a non-volatile memory (230).

[0022] Referring to Fig. 1(b), a processor (210) and a volatile memory (220) may be placed on the second side (100b) of the printed circuit board (100).

[0023] In one embodiment, the processor (210) is shown as being placed on the second side (100b) of the printed circuit board (100), but depending on the placement design for the various devices mounted on each PBA, it may be placed on either the first side (100a) or the second side (100b).

[0024] In one embodiment, the printed circuit board (100) may include a plurality of slits (112) for separating a plurality of PBAs (120) from the printed circuit board (100). In one example, the printed circuit board (100) may include at least one of a first slit (1121), a second slit (1122), a third slit (1123), and a fourth slit (1124) for separating each PBA from the printed circuit board (100).

[0025] In one embodiment, the printed circuit board (100) may include a plurality of bridges (111). In one example, a plurality of PBAs (120) may be connected to the printed circuit board (100) through a plurality of bridges (111). In one example, each PBA may be connected to the printed circuit board (100) through a plurality of bridges (111). In one example, the plurality of bridges (111) may include at least one of a first bridge (111a), a second bridge (111b), and a third bridge (111c). In one example, the first bridge (111a) may be positioned between a first slit (1121) and a second slit (1122). The second bridge (111b) may be positioned between a second slit (1122) and a third slit (1123). The third bridge (111c) can be placed between the third slit (1123) and the fourth slit (1124).

[0026] In one embodiment, a plurality of bridges (111) may include bridges having a conductive pattern and bridges not having a conductive pattern. In one example, among the plurality of bridges (111), a bridge having a conductive pattern may be connected to at least one interface (110).

[0027] In one embodiment, the printed circuit board (100) may include a mounting area where a plurality of PBAs (120) are placed and a non-mounting area excluding the mounting area. An interface (110) may be placed in the non-mounting area.

[0028] In one embodiment, the printed circuit board (100) may include at least one interface (110). In one example, the interface (110) may be positioned at the bottom of the first surface (100a).

[0029] In one embodiment, the interface (110) can connect a plurality of PBAs (120) and an external device (e.g., the external device (300) of FIG. 3). In one example, the interface (110) can control the input and output of signals.

[0030] In one embodiment, the interface (110) may include a matrix type interface.

[0031] In one embodiment, the interface (110) may include a plurality of pins. In one example, the interface (110) may include a plurality of pins having an N * M array (where N and M are integers greater than or equal to 1).

[0032] In one embodiment, the processor (210) and the volatile memory (220) may be placed on a second side (100b) of the printed circuit board (100). In one example, the volatile memory (220) may be placed on the upper surface of the processor (210). In one example, the processor (210) and the volatile memory (220) are shown as being physically separated, but the volatile memory (220) may be included in the processor (210).

[0033] In one embodiment, the volatile memory (220) and non-volatile memory (230) included in each of the plurality of PBAs (120) may be blank memory in which no data is stored.

[0034] In one embodiment, a plurality of PBAs (120) disposed on a printed circuit board (100) can be separated from the printed circuit board (100) according to a cutting process.

[0035] In another embodiment, each PBA included in a plurality of PBAs (120) may include a main PBA (not shown) and an auxiliary PBA (not shown). In one example, the main PBA and the auxiliary PBA of each PBA may form a stacked structure. The main PBA and the auxiliary PBA may form a stacked structure through an interposer. In one example, an interface (110) and a non-volatile memory (230) may be placed in the main PBA. A processor (210) and a volatile memory (220) may be placed in the auxiliary PBA.

[0036] FIG. 2 is a block diagram of a printed circuit board (100) including a plurality of PBAs (120) according to various embodiments.

[0037] In one embodiment, the printed circuit board (100) may include an interface (110) and a plurality of PBAs (120).

[0038] In one embodiment, each PBA included in a plurality of PBAs (120) may include a processor (210), volatile memory (220), and non-volatile memory (230).

[0039] In one embodiment, the interface (110) can connect a plurality of PBAs (120) and an external device (e.g., the external device (300) of FIG. 3).

[0040] In one embodiment, the interface (110) may include a plurality of pins. In one example, the interface (110) may control a plurality of PBAs (120) according to input / output signals through the plurality of pins.

[0041] In one embodiment, the interface (110) may include a plurality of terminals having an N * M array. N and M may be integers greater than or equal to 1. In one example, among the plurality of terminals having an N * M array, a plurality of terminals having an N * K array may be electrically connected to each PBA included in a plurality of PBAs (120). K may be an integer smaller than M.

[0042] In one embodiment, the interface (110) can receive data from an external device through at least one of a plurality of terminals.

[0043] In one embodiment, the interface (110) can store data received from an external device in a volatile memory (220) or a non-volatile memory (230) according to input / output signals received through a plurality of terminals.

[0044] In one embodiment, the interface (110) can store bootloader data received from an external device in a volatile memory (220) when it receives a first signal through at least one of a plurality of terminals.

[0045] In one embodiment, the interface (110) can store binary data received from an external device in a non-volatile memory (230) when it receives a second signal through at least one of a plurality of terminals.

[0046] In one embodiment, the interface (110) can store data necessary to control the non-volatile memory (230) in the volatile memory (220).

[0047] In one embodiment, the function of each of the multiple terminals included in the interface (110) connecting multiple PBAs (120) and external devices (300) is explained in detail with reference to FIG. 4.

[0048] In one embodiment, the volatile memory (220) is a memory device in which the stored data is lost when the power supply is cut off.

[0049] In one embodiment, the volatile memory (220) may include at least one of RAM (random access memory), DRAM (dynamic RAM), SRAM (static RAM), SDRAM (Synchronous DRAM), PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FeRAM (Ferroelectric RAM).

[0050] In one embodiment, the non-volatile memory (230) is a memory device that retains data stored even when the power supply is cut off.

[0051] In one embodiment, the non-volatile memory (230) may include at least one of ROM (Read Only Memory), NAND flash memory, PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM).

[0052] In one embodiment, the processor (210) may be electrically connected to a volatile memory (220), a non-volatile memory (230), and an interface (110).

[0053] In one embodiment, the processor (210) may include an application processor (AP).

[0054] FIG. 3 shows the connection relationship between a printed circuit board (100) including a plurality of PBAs (120) and an external device (300) according to various embodiments.

[0055] In one embodiment, the printed circuit board (100) may include a plurality of PBAs (120) and an interface (110).

[0056] In one embodiment, the printed circuit board (100) may be electrically connected to an external device (300) through an interface (110). In one example, a plurality of PBAs (120) included in the printed circuit board (100) may be connected to an external device (300) through an interface (110).

[0057] In one embodiment, the printed circuit board (100) may include at least one interface (110).

[0058] In one embodiment, the interface (110) may include a first interface (110a) and a second interface (110b). In one example, one of the first interface (110a) and the second interface (110b) may control up to four PBAs.

[0059] In one embodiment, the first interface (110a) can connect at least one of the first PBA (121), the second PBA (122), the third PBA (123), and the fourth PBA (124) to the external device (300). The second interface (110b) can connect at least one of the fifth PBA (125), the sixth PBA (126), the seventh PBA (127), and the eighth PBA (128) to the external device (300).

[0060] In one embodiment, the interface (110) may be electrically connected to an external device (300) through a connection device (not shown). In one example, the first interface (110a) is shown as being electrically connected to the external device (300) through the connection device, but the second interface (110b) may also be electrically connected to the external device (300) through the connection device.

[0061] In one embodiment, the connection device (not shown) may include various interfaces such as an interface according to a first standard (e.g., a USB 2.0 port) and a second standard (e.g., a USB 3.0 port).

[0062] In one embodiment, the external device (300) may include a power module (310), a communication module (320), a processor (330), and a memory (340).

[0063] In one embodiment, a power module (310) included in an external device (300) can supply power to a printed circuit board (100). In one example, the power module (310) of the external device (300) can supply power through an interface (110) of the printed circuit board (100).

[0064] In one example, the power module (310) of the external device (300) can measure the current after supplying power through a power terminal (e.g., the first terminal (pin 1) of FIG. 4) among a plurality of terminals included in the interface (110).

[0065] In one embodiment, the printed circuit board (100) can receive power from the power module (310) of the external device (300) through a power terminal among a plurality of terminals included in the interface (110).

[0066] In one embodiment, the external device (300) can communicate with the printed circuit board (100) through the communication module (320).

[0067] In one embodiment, the printed circuit board (100) can communicate with an external device (300) through an interface (110). In one example, the printed circuit board (100) can transmit and receive data or signals with the external device (300) through a communication terminal (e.g., the third terminal (pin 3), the sixth terminal (pin 6), and the ninth terminal (pin 9) of FIG. 4) among a plurality of terminals included in the interface (110).

[0068] In one embodiment, a processor (330) included in an external device (300) can transmit a signal to an interface (110) of a printed circuit board (100). In one example, the processor (330) included in the external device (300) can transmit the specified signal to a terminal corresponding to the specified signal among a plurality of terminals included in the interface (110).

[0069] In one embodiment, the memory (340) included in the external device (300) may include bootloader data and binary data.

[0070] In one embodiment, the bootloader data contained in the memory (340) of the external device (300) may include data necessary to perform a boot procedure when power is supplied to the system. The bootloader data may include data necessary to run an operating system. In one example, the bootloader data may include data related to an operating system. For example, the operating system may include at least one of a Unix-based file system, a Linux-based file system, a Microsoft Windows file system, and a Mac OS file system.

[0071] In one embodiment, the binary data contained in the memory (340) of the external device (300) may include at least one of data required to run the operating system stored in the non-volatile memory (230), basic applications associated with the operating system, and data associated with firmware. In one example, the binary data may include bootloader data.

[0072] FIG. 4 shows an interface (110) connecting a plurality of PBAs (120) included in a printed circuit board (100) and an external device (300) according to various embodiments.

[0073] In one embodiment, the interface (110) of the printed circuit board (100) may include a plurality of terminals. In one example, the interface (110) may include terminals having an N * M arrangement. Among the N * M arrangement, terminals having an N * K arrangement may be electrically connected to each PBA.

[0074] Referring to FIG. 4, the interface (110) includes terminals having a 3*14 array, and among the terminals having a 3*14 array, terminals having a 3*3 array can be electrically connected to each PBA.

[0075] In one embodiment, in an interface (110) comprising terminals having a 3*14 array, the first terminal (pin 1) to the ninth terminal (pin 9) can control the first PBA (121). The tenth terminal (pin 10) to the eighth terminal (pin 18) included in the interface (110) can control the second PBA (122). The ninth terminal (pin 19) to the twentieth terminal (pin 27) included in the interface (110) can control the third PBA (123). The twentieth terminal (pin 28) to the thirteenth terminal (pin 36) included in the interface (110) can control the fourth PBA (124).

[0076] Hereinafter, the method of controlling each PBA by terminals having a 3*3 arrangement of the interface (110) is explained through the method of controlling the first PBA (121) by the first terminal (pin 1) to the ninth terminal (pin 9) included in the interface (110). Each of the remaining PBAs can also be controlled in the same way as the first PBA (121) through terminals configured in the same arrangement as the first PBA. For example, the ninth terminal (pin 9) in the tenth terminal (pin 10) to the eighth terminal (pin 18) controlling the second PBA (122) can correspond to the first terminal (pin 1) in the first terminal (pin 1) to the ninth terminal (pin 9) controlling the first PBA (121).

[0077] In one embodiment, the first PBA (121) may receive power from an external device (300) through an interface (110). In one example, the external device (300) may supply power to the first PBA (121) through a power module (310). In one example, the first PBA (121) may receive power from the external device (300) through a voltage input to a driving voltage terminal (Vbat) via a first terminal (pin 1) of the interface (110). In one example, a DC voltage may be applied to the driving voltage terminal (Vbat).

[0078] In one embodiment, when voltage is applied to the voltage bus (Vbus) through the third terminal (pin 3) of the interface (110), a differential signal may be input through the sixth terminal (pin 6) connected to the USB D+ line and the ninth terminal (pin 9) connected to the USB D- line. In one example, the printed circuit board (100) may communicate with an external device (300) through the sixth terminal (pin 6) and the ninth terminal (pin 9).

[0079] In one embodiment, the third terminal (pin 3), the sixth terminal (pin 6), and the ninth terminal (pin 9) of the interface (110) may be communication terminals for performing communication functions with an external device (300).

[0080] In one embodiment, the interface (110) can receive at least one of bootloader data and binary data from an external device (300) through a third terminal (pin 3), a sixth terminal (pin 6), and a ninth terminal (pin 9).

[0081] In one embodiment, the first PBA (121) can receive a parameter signal from an external device (300) through an interface (110). In one example, the external device (300) can transmit a parameter signal to the first PBA (121) through a processor (330).

[0082] In one embodiment, the first PBA (121) can transmit a first parameter signal through a second terminal (pin 2) connected to Boot 0 of the interface (110) and a fifth terminal (pin 5) connected to Boot 1. In one example, the first parameter signal transmitted through the second terminal (pin 2) and the fifth terminal (pin 5) may include an entry signal for storing bootloader data in volatile memory (220). In one example, the first parameter signal may correspond to a combination of the "0" signal of the second terminal (pin 2) and the "1" signal of the fifth terminal (pin 5).

[0083] In one embodiment, the eighth terminal (pin 8) of the interface (110) may include an identification resistance value (unit: KΩ). In one example, the identification resistance value may correspond to an identification value for an external device (300). In one example, the resistance value stored in the eighth terminal (pin 8) may include a first resistance value (e.g., 56 KΩ), a second resistance value (e.g., 301 KΩ), a third resistance value (e.g., 523 KΩ), and a fourth resistance value (e.g., 619 KΩ). In one example, different functions may be performed depending on the connected resistance value among the resistance values ​​included in the eighth terminal (pin 8).

[0084] In one embodiment, the first PBA (121) may transmit a second parameter signal to the eighth terminal (pin 8) of the interface (110). The second parameter signal may include an entry signal for storing binary data in the non-volatile memory (230). In one example, the second parameter signal received from the external device (300) may include a signal for connecting to a second resistance value included in the eighth terminal (pin 8) of the interface (110). When the second resistance value included in the eighth terminal (pin 8) of the interface (110) is connected by the second parameter signal received from the external device (300), the interface (110) may store binary data in the non-volatile memory (230).

[0085] In one embodiment, the interface (110) may include a fourth terminal (pin 4) connected to ground (GND).

[0086] FIG. 5 is a flowchart (500) showing a method of storing data in a memory placed in each of a plurality of PBAs (120) according to various embodiments.

[0087] According to one embodiment, in a printed circuit board (100) comprising a plurality of PBAs (120), each PBA can receive power through a first terminal of an interface (110) (e.g., the first terminal (pin 1) of FIG. 4) in operation 501.

[0088] In one embodiment, the power module (310) of an external device (e.g., the external device (300) of FIG. 3) can supply power to the first terminal (e.g., the first terminal (pin 1) of FIG. 4) of the interface (110).

[0089] In one embodiment, each PBA can activate a communication terminal of the interface (110) (e.g., the third terminal (pin 3), the sixth terminal (pin 6), and the ninth terminal (pin 9) of FIG. 4) in response to receiving power through the first terminal.

[0090] In one embodiment, in response to activating the communication terminals of the interface (110) (e.g., the third terminal (pin 3), the sixth terminal (pin 6), and the ninth terminal (pin 9) of FIG. 4), each PBA can receive a connection signal from the external device (300) between the modem port of the external device (300) and the printed circuit board (100).

[0091] In a printed circuit board (100) including a plurality of PBAs (120) according to one embodiment, each PBA can transmit a first parameter signal to a second terminal of an interface (110) (e.g., the second terminal (pin 2) and the fifth terminal (pin 5) of FIG. 4) in operation 503.

[0092] In one embodiment, the first parameter signal may include an entry signal for storing bootloader data in volatile memory (220).

[0093] In one embodiment, the first parameter signal may include a combination of signals input to the second terminal (e.g., the second terminal (pin 2) in FIG. 4) and the fifth terminal (e.g., the fifth terminal (pin 5) in FIG. 4) (e.g., a combination of '0 and 1'). The combination input to the second terminal and the fifth terminal may include various combinations depending on the type of processor (210).

[0094] According to one embodiment, in a printed circuit board (100) comprising a plurality of PBAs (120), each PBA can store bootloader data received from an external device (300) in operation 505 in a volatile memory (220).

[0095] In one embodiment, each PBA can store bootloader data received from an external device (300) in a volatile memory (220) when a first parameter signal is transmitted to a second terminal of the interface (110) (e.g., second terminal (pin 2) and fifth terminal (pin 5) of FIG. 4).

[0096] In one embodiment, the volatile memory (220) may include RAM (random access memory).

[0097] In one embodiment, when a first parameter signal is transmitted through the second terminal of the interface (110), the external device (300) can transmit bootloader data through the communication module (320) to the communication terminals of the interface (110) (e.g., the third terminal (pin 3), the sixth terminal (pin 6), and the ninth terminal (pin 9) of FIG. 4).

[0098] In one embodiment, when a first parameter signal is transmitted to the second terminal of the interface (110) and bootloader data is received from an external device (300), each PBA can store the bootloader data received from the external device (300) in a volatile memory (220).

[0099] In one embodiment, each PBA can temporarily store bootloader data received from an external device (300) in a volatile memory (220).

[0100] In one embodiment, when bootloader data received from an external device (300) is stored in volatile memory (220), the processor (210) can determine whether the bootloader data has been successfully stored in volatile memory (220). In one example, if the bootloader data has not been successfully stored in volatile memory (220), power may not be supplied to the processor (210). In one example, if the bootloader data has not been successfully stored in volatile memory (220), the processor (210) may have problems with the normal data writing or reading functions.

[0101] In one embodiment, when the processor (210) determines that the bootloader has been successfully stored in the volatile memory (220), it can transmit a signal to the interface (110).

[0102] In one embodiment, each PBA may temporarily store bootloader data in volatile memory (220) because bootloader data must be loaded into the processor (210) in order to store data in non-volatile memory (230).

[0103] In one embodiment, in response to bootloader data being stored in volatile memory (220), each PBA can receive a connection signal and a string signal from an external device (300) regarding the modem port of the external device (300) and the printed circuit board (100). In one example, a processor (210) can receive a string signal from the external device (300). In one example, when the external device (300) transmits an "ODIN" string signal to each PBA, the processor (210) included in each PBA can receive a "LOKE" string signal in response to the "ODIN" string signal transmitted by the external device (300).

[0104] In one embodiment, in response to a connection signal and a string signal received from an external device (300), each PBA can transmit a second parameter signal to a third terminal of the interface (110).

[0105] According to one embodiment, in a printed circuit board (100) comprising a plurality of PBAs (120), each PBA can transmit a second parameter signal to a third terminal of an interface (110) (e.g., the eighth terminal (pin 8) of FIG. 4) in operation 507.

[0106] In one embodiment, the second parameter signal may include an entry signal for storing binary data in non-volatile memory (230). The binary data may include bootloader data. The binary data may include data identical to the bootloader data stored in volatile memory (220).

[0107] In one embodiment, the second parameter signal may include a signal connected to a second resistance value (e.g., 301 KΩ) included in a third terminal (e.g., the eighth terminal (pin 8) of FIG. 4).

[0108] According to one embodiment, in a printed circuit board (100) comprising a plurality of PBAs (120), each PBA can store binary data received from an external device (300) in operation 509 in a non-volatile memory (230).

[0109] In one embodiment, when a second parameter signal is transmitted to the third terminal (e.g., the eighth terminal (pin 8) of FIG. 4) of the interface (110) to be connected to a second resistance value included in the third terminal, binary data received from an external device (300) can be stored in a non-volatile memory (230).

[0110] In one embodiment, the non-volatile memory (230) may include at least one of ROM (read only memory) and NAND flash memory.

[0111] In one embodiment, when a second parameter signal is transmitted through the third terminal of the interface (110), the external device (300) can transmit binary data to the communication terminals of the interface (110) (e.g., the third terminal (pin 3), the sixth terminal (pin 6), and the ninth terminal (pin 9) of FIG. 4) through the communication module (320).

[0112] In one embodiment, when a second parameter signal is transmitted to the third terminal of the interface (110) and binary data is received from an external device (300), each PBA can store the binary data received from the external device (300) in a non-volatile memory (230).

[0113] In one embodiment, in response to binary data being stored in non-volatile memory (230), the processor (210) can store a file system and a basic application in non-volatile memory (230) through the stored binary data.

[0114] In one example, bootloader data received from an external device (300) is temporarily stored in a volatile memory (220), and after the bootloader data is stored in the volatile memory (220), when a second parameter signal is transmitted through the third terminal of the interface (110), binary data including the bootloader data can be stored in a non-volatile memory (230).

[0115] In one embodiment, when binary data received from an external device (300) is stored in a non-volatile memory (230), the processor (210) can determine whether the binary data has been successfully stored in the non-volatile memory (230).

[0116] FIG. 6 is a flowchart (600) showing a method for determining whether volatile memory (220) and non-volatile memory (230) included in each PBA in a printed circuit board (100) including a plurality of PBAs (120) according to various embodiments are properly mounted.

[0117] In one embodiment, when the processor (210) determines that the bootloader has been successfully stored in the volatile memory (220), it can transmit a signal to the interface (110).

[0118] In a printed circuit board (100) including a plurality of PBAs (120) according to one embodiment, each PBA can receive power through a first terminal of an interface (110) (e.g., the first terminal (pin 1) of FIG. 4) in operation 601.

[0119] In one embodiment, a power module (310) included in an external device (300) can supply power to a first terminal of an interface (110).

[0120] According to one embodiment, after receiving power through the first terminal of the interface (110), the power module (310) included in the external device (300) can measure the current flowing through the printed circuit board (100) in operation 603.

[0121] According to one embodiment, the power module (310) included in the external device (300) determines in operation 605 whether the current measured in operation 603 is within a specified current range.

[0122] In one embodiment, if the current flowing through the printed circuit board (100) measured by the power module (310) included in the external device (300) is within a specified current range (e.g., about 0 to 2A), the power module (310) of the external device (300) can determine that the processor (210), volatile memory (220), and non-volatile memory (230) placed in each PBA are properly placed.

[0123] In one embodiment, if the current flowing through the printed circuit board (100) measured by the power module (310) included in the external device (300) is outside the specified range, the power module (310) of the external device (300) may determine that the processor (210), volatile memory (220), and non-volatile memory (230) placed in each PBA are abnormally placed. In one example, if the processor (210), volatile memory (220), and non-volatile memory (230) are not properly placed in each PBA of the printed circuit board (100), or if the terminal receiving power from the interface (110) is defective, the current flowing through the printed circuit board (100) may be outside the specified range.

[0124] In one embodiment, when the current flowing through the printed circuit board (100) measured through the power module (310) included in the external device (300) is within a specified range, the power module (310) of the external device (300) can transmit a first signal to the interface (110) of the printed circuit board (100).

[0125] In one embodiment, a printed circuit board (100) including a plurality of PBAs (120) can transmit a first parameter signal to a second terminal (e.g., the second terminal (pin 2) and the fifth terminal (pin 5) of FIG. 4) of the interface (110) when it receives the first signal from an external device (300) through the interface (110).

[0126] FIG. 7 is a flowchart illustrating a power-on reset (POR) process according to various embodiments.

[0127] In one embodiment, each BPA may transmit a signal connected to a third resistance value (e.g., 523 KΩ) among the identification resistors included in the eighth terminal (e.g., pin 8 of FIG. 4) of the interface (110) in response to binary data being stored in the non-volatile memory (230) in operation 509. In one example, when the signal connected to the third resistance value of the eighth terminal (pin) is transmitted, each PBA may perform a power-on reset process.

[0128] According to one embodiment, in a printed circuit board (100) comprising a plurality of PBAs (120), each PBA can reset the power of the printed circuit board (100) in operation 701.

[0129] In one embodiment, the processor (210) included in each PBA can be turned on again after the power to the printed circuit board (100) is turned off. In one example, when the power to the printed circuit board (100) is turned off, the bootloader data stored in the volatile memory (220) may be lost.

[0130] According to one embodiment, in a printed circuit board (100) comprising a plurality of PBAs (120), each PBA can transmit a signal designated to an external device (300) through an interface (110) in operation 703.

[0131] In one embodiment, the processor (210) can communicate with an external device (300) through an interface (110).

[0132] In one embodiment, a designated signal transmitted to an external device (300) through an interface (110) may include a signal requesting a determination of whether the printed circuit board (100) is booting normally.

[0133] According to one embodiment, when an external device (300) receives a specified signal from a printed circuit board (100), it can determine whether the printed circuit board (100) is booting normally.

[0134] In one embodiment, when the external device (300) determines that the printed circuit board (100) is booting normally, it can transmit a first signal to the printed circuit board (100).

[0135] In one embodiment, the external device (300) may determine that the printed circuit board (100) is booting abnormally due to an error in the binary data stored in the non-volatile memory (230) of each PBA or due to a lock-up occurring during the booting process. If the external device (300) determines that the printed circuit board (100) is booting abnormally, it may transmit a second signal, which is distinct from the first signal, to the printed circuit board (100).

[0136] According to one embodiment, in a printed circuit board (100) comprising a plurality of PBAs (120), each PBA can receive a response signal for the specified signal from an external device (300) in operation 705.

[0137] According to one embodiment, in a printed circuit board (100) comprising a plurality of PBAs (120), each PBA can determine whether the printed circuit board is booting normally based on a response signal to the specified signal in operation 707.

[0138] In one embodiment, when the printed circuit board (100) receives the first signal from an external device (300), it can determine that the printed circuit board (100) has been booted normally.

[0139] In one embodiment, when the printed circuit board (100) receives the second signal from an external device (300), it can determine that the printed circuit board (100) has been booted abnormally.

[0140] FIG. 8 is a block diagram of an electronic device (801) in a network environment (800) according to various embodiments.

[0141] Referring to FIG. 8, in a network environment (800), an electronic device (801) may communicate with an electronic device (802) through a first network (898) (e.g., a short-range wireless communication network) or with at least one of an electronic device (804) or a server (808) through a second network (899) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (801) may communicate with the electronic device (804) through the server (808). According to one embodiment, the electronic device (801) may include a processor (820), memory (830), input module (850), sound output module (855), display module (860), audio module (870), sensor module (876), interface (877), connection terminal (878), haptic module (879), camera module (880), power management module (888), battery (889), communication module (890), subscriber identification module (896), or antenna module (897). In some embodiments, at least one of these components (e.g., connection terminal (878)) may be omitted from the electronic device (801), or one or more other components may be added. In some embodiments, some of these components (e.g., sensor module (876), camera module (880), or antenna module (897)) may be integrated into a single component (e.g., display module (860)).

[0142] The processor (820) can control at least one other component (e.g., a hardware or software component) of the electronic device (801) connected to the processor (820) by executing software (e.g., a program (840)), and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (820) can store commands or data received from other components (e.g., a sensor module (876) or a communication module (890)) in volatile memory (832), process the commands or data stored in volatile memory (832), and store the resulting data in non-volatile memory (834). According to one embodiment, the processor (820) may include a main processor (821) (e.g., a central processing unit or an application processor) or an auxiliary processor (823) that can operate independently or together with it (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor). For example, if the electronic device (801) includes a main processor (821) and an auxiliary processor (823), the auxiliary processor (823) may be configured to use lower power than the main processor (821) or to be specialized for a designated function. The auxiliary processor (823) may be implemented separately from the main processor (821) or as part thereof.

[0143] The auxiliary processor (823) may control at least some of the functions or states associated with at least one component of the electronic device (801) (e.g., display module (860), sensor module (876), or communication module (890)) on behalf of the main processor (821) while the main processor (821) is in an inactive (e.g., sleep) state, or together with the main processor (821) while the main processor (821) is in an active (e.g., application execution) state. According to one embodiment, the auxiliary processor (823) (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module (880) or communication module (890)). According to one embodiment, the auxiliary processor (823) (e.g., neural network processing unit) may include a hardware structure specialized for processing an artificial intelligence model. The artificial intelligence model may be generated through machine learning. Such learning may be performed, for example, on the electronic device (801) itself where the artificial intelligence model is executed, or through a separate server (e.g., server (808)). The learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model may include a plurality of artificial neural network layers.An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially.

[0144] The memory (830) can store various data used by at least one component of the electronic device (801) (e.g., processor (820) or sensor module (876)). The data may include, for example, software (e.g., program (840)) and input or output data for related commands. The memory (830) may include volatile memory (832) or non-volatile memory (834).

[0145] The program (840) may be stored as software in memory (830) and may include, for example, an operating system (842), middleware (844), or an application (846).

[0146] The input module (850) can receive commands or data to be used for a component of the electronic device (801) (e.g., processor (820)) from outside the electronic device (801) (e.g., user). The input module (850) may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0147] The sound output module (855) can output a sound signal to the outside of the electronic device (801). The sound output module (855) may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as multimedia playback or recording playback. The receiver may be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part thereof.

[0148] The display module (860) can visually provide information to an external (e.g., user) of the electronic device (801). The display module (860) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling said device. According to one embodiment, the display module (860) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of the force generated by said touch.

[0149] The audio module (870) can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module (870) can acquire sound through the input module (850) or output sound through the sound output module (855) or an external electronic device (e.g., electronic device (802)) (e.g., speaker or headphones) connected directly or wirelessly to the electronic device (801).

[0150] The sensor module (876) can detect the operating state of the electronic device (801) (e.g., power or temperature) or the external environmental state (e.g., user state) and generate an electrical signal or data value corresponding to the detected state. According to one embodiment, the sensor module (876) may include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0151] The interface (877) may support one or more specified protocols that can be used for the electronic device (801) to be connected directly or wirelessly to an external electronic device (e.g., electronic device (802)). According to one embodiment, the interface (877) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0152] The connection terminal (878) may include a connector through which the electronic device (801) can be physically connected to an external electronic device (e.g., electronic device (802)). According to one embodiment, the connection terminal (878) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0153] The haptic module (879) can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic senses. According to one embodiment, the haptic module (879) may include, for example, a motor, a piezoelectric element, or an electric stimulation device.

[0154] The camera module (880) can capture still images and video. According to one embodiment, the camera module (880) may include one or more lenses, image sensors, image signal processors, or flashes.

[0155] The power management module (888) can manage power supplied to the electronic device (801). According to one embodiment, the power management module (888) can be implemented, for example, as at least part of a power management integrated circuit (PMIC).

[0156] The battery (889) can supply power to at least one component of the electronic device (801). According to one embodiment, the battery (889) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0157] The communication module (890) can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between an electronic device (801) and an external electronic device (e.g., electronic device (802), electronic device (804), or server (808)), and the performance of communication through the established communication channel. The communication module (890) may include one or more communication processors that operate independently of the processor (820) (e.g., application processor) and support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (890) may include a wireless communication module (892) (e.g., cellular communication module, short-range wireless communication module, or GNSS (global navigation satellite system) communication module) or a wired communication module (894) (e.g., LAN (local area network) communication module, or power line communication module). The corresponding communication module among these communication modules can communicate with an external electronic device (804) via a first network (898) (e.g., a short-range communication network such as Bluetooth, WiFi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network (899) (e.g., a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (892) can identify or authenticate the electronic device (801) within a communication network such as the first network (898) or the second network (899) using subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module (896).

[0158] The wireless communication module (892) can support 5G networks and next-generation communication technologies following 4G networks, for example, new radio access technology. NR access technology can support high-speed transmission of high-capacity data (enhanced mobile broadband (eMBB)), minimization of terminal power and connection of multiple terminals (massive machine type communications (mMTC)), or high reliability and low latency (ultra-reliable and low-latency communications (URLLC)). The wireless communication module (892) can support a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate, for example. The wireless communication module (892) can support various technologies for securing performance in the high-frequency band, such as beamforming, massive MIMO (multiple-input and multiple-output), full-dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large-scale antenna. The wireless communication module (892) can support various requirements specified in the electronic device (801), external electronic device (e.g., electronic device (804)), or network system (e.g., second network (899)). According to one embodiment, the wireless communication module (892) can support a Peak data rate (e.g., 20 Gbps or more) for eMBB realization, loss coverage (e.g., 164 dB or less) for mMTC realization, or U-plane latency (e.g., downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less) for URLLC realization.

[0159] An antenna module (897) can transmit a signal or power to or from an external source (e.g., an external electronic device). According to one embodiment, the antenna module (897) may include an antenna comprising a radiator made of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (897) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as a first network (898) or a second network (899), may be selected from the plurality of antennas, for example, by a communication module (890). A signal or power may be transmitted or received between the communication module (890) and an external electronic device through the selected at least one antenna. According to some embodiments, in addition to the radiator, other components (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module (897).

[0160] According to various embodiments, the antenna module (897) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., bottom surface) of the printed circuit board and capable of supporting a specified high frequency band (e.g., mmWave band), and a plurality of antennas (e.g., array antennas) disposed on or adjacent to a second surface (e.g., top surface or side surface) of the printed circuit board and capable of transmitting or receiving a signal of the specified high frequency band.

[0161] At least some of the above components can be connected to each other via a communication method between peripheral devices (e.g., bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)) and exchange signals (e.g., commands or data) with each other.

[0162] According to one embodiment, commands or data may be transmitted or received between the electronic device (801) and an external electronic device (804) through a server (808) connected to a second network (899). Each of the external electronic devices (802, or 804) may be the same or a different type of device as the electronic device (801). According to one embodiment, all or part of the operations performed on the electronic device (801) may be performed on one or more of the external electronic devices (802, 804, or 808). For example, if the electronic device (801) needs to perform a function or service automatically or in response to a request from a user or another device, the electronic device (801) may request one or more external electronic devices to perform at least part of the function or service instead of performing the function or service itself or additionally. One or more external electronic devices that receive the above request may execute at least part of the requested function or service, or additional function or service related to the request, and transmit the result of the execution to the electronic device (801). The electronic device (801) may provide the result as is or additionally processed as at least part of the response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device (801) may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device (804) may include an Internet of Things (IoT) device. The server (808) may be an intelligent server using machine learning and / or neural networks. According to one embodiment, the external electronic device (804) or the server (808) may be included within a second network (899).The electronic device (801) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0163] The electronic device according to the various embodiments disclosed in this document may be a device of various forms. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device according to the embodiments of this document is not limited to the devices described above.

[0164] The various embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of said embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of said items unless the relevant context clearly indicates otherwise. In this document, each of phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B, or C" may include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as “first,” “second,” or “first” or “second” may be used simply to distinguish a component from another component and do not limit the components in any other aspect (e.g., importance or order). Where any (e.g., first) component is referred to as “coupled” or “connected” to another (e.g., second) component, with or without the terms “functionally” or “communicationally,” it means that said component may be connected to said other component directly (e.g., wired), wirelessly, or through a third component.

[0165] The term “module” as used in the various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A module may be a component formed integrally, or a minimum unit of said component or a part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0166] Various embodiments of the present document may be implemented as software (e.g., program (840)) comprising one or more instructions stored in a storage medium (e.g., internal memory (836) or external memory (838)) readable by a machine (e.g., electronic device (801)). For example, a processor (e.g., processor (820)) of the machine (e.g., electronic device (801)) may call at least one of the one or more instructions stored in the storage medium and execute it. This enables the machine to be operated to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The storage medium readable by the machine may be provided in the form of a non-transitory storage medium. Here, 'non-temporary' simply means that the storage medium is a tangible device and does not contain a signal (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily.

[0167] According to one embodiment, the method according to the various embodiments disclosed herein may be provided by being included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)) or an application store (e.g., Play Store). TM It can be distributed online (e.g., downloaded or uploaded) through ) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0168] According to various embodiments, each component (e.g., module or program) of the components described above may include a singular or multiple entities, and some of the multiple entities may be separated and placed in other components. According to various embodiments, one or more of the components or operations among the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the corresponding component among the multiple components prior to integration. According to various embodiments, operations performed by the module, program, or other components may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

[0169] According to various embodiments, a printed circuit board comprising a plurality of PBAs and an interface connecting the plurality of PBAs and an external device, wherein the interface comprises terminals having an N * M array, and terminals having an N * K array among the terminals having the N * M array are electrically connected to each of the plurality of PBAs, and each PBA comprises a volatile memory, a non-volatile memory, and a processor, and when power is supplied from a first terminal among the terminals having the N * K array, each PBA transmits a first parameter signal to a second terminal among the terminals having the N * K array, and in response to the transmission of the first parameter signal, stores boot-loader data received from the external device in the volatile memory, transmits a second parameter signal to a third terminal among the terminals having the N * K array, and in response to the storage of the boot-loader data, stores binary data received from the external device in the non-volatile memory.

[0170] According to one embodiment, the binary data may include the bootloader data.

[0171] According to one embodiment, the volatile memory includes RAM (random access memory), and the non-volatile memory may include at least one of ROM (read only memory) and NAND flash memory.

[0172] According to one embodiment, it is possible to determine whether the volatile memory and the non-volatile memory are properly mounted in each PBA based on data regarding the current flowing through the printed circuit board.

[0173] According to one embodiment, the processor may perform a power-on reset (POR) in response to the binary data being stored in the non-volatile memory.

[0174] According to one embodiment, the processor can reset the power of the printed circuit board in response to the binary data being stored in the non-volatile memory, transmit a designated signal to the external device through the interface, receive a response signal for the designated signal from the external device in response to the transmission of the designated signal, and determine whether the printed circuit board has booted normally based on the response signal for the designated signal.

[0175] According to one embodiment, the processor can store a file system associated with an operating system and a basic application associated with the operating system in the non-volatile memory in response to the binary data being stored in the non-volatile memory.

[0176] According to one embodiment, the PBA can activate a communication terminal of the interface in response to power being supplied from the first terminal, receive a connection signal between the modem port of the external device and the printed circuit board from the external device, and transmit the first parameter signal to the second terminal in response to the reception of the connection signal.

[0177] According to one embodiment, in response to the bootloader data being stored in the volatile memory, a connection signal and a string signal between the modem port of the external device and the printed circuit board are received from the external device, and in response to the reception of the connection signal and the string signal, the second parameter signal can be transmitted to the third terminal.

[0178] According to one embodiment, the volatile memory may be placed on the processor.

[0179] According to one embodiment, the volatile memory and the non-volatile memory may include an empty memory in which no data is stored.

[0180] According to one embodiment, the printed circuit board includes a first surface and a second surface opposite to the first surface, and the interface and the non-volatile memory may be disposed on the first surface, and the volatile memory and the processor may be disposed on the second surface.

[0181] According to one embodiment, the processor may include an application processor (AP).

[0182] According to one embodiment, the printed circuit board includes a mounting area and a non-mounting area in addition to the mounting area, and the plurality of PBAs are disposed in the mounting area, and the interface may be disposed in the non-mounting area.

[0183] According to one embodiment, N and M include integers greater than 1, and N may include integers smaller than M.

[0184] According to one embodiment, the N * M array includes a 3 * 14 array, and the N * M array may include a 3 * 3 array.

[0185] According to various embodiments, a printed circuit board comprises a plurality of PBAs and an interface connecting the plurality of PBAs and an external device, and a data processing method for a volatile memory and a non-volatile memory disposed within each PBA comprises, when power is supplied from a first terminal of the interface, an operation of transmitting a first parameter signal to at least one second terminal of the interface, an operation of storing bootloader data received from the external device in the volatile memory in response to the transmission of the first parameter signal, an operation of transmitting a second parameter signal to the at least one second terminal in response to the storage of the bootloader data, and an operation of storing binary data received from the external device in the non-volatile memory in response to the transmission of the second parameter signal, wherein the interface comprises terminals having an N * M array, and among the terminals having an N * M array, terminals having an N * K array may be electrically connected to each of the plurality of PBAs.

[0186] According to one embodiment, the binary data may include the bootloader data.

[0187] According to one embodiment, the operation may include transmitting a third parameter signal to at least one second terminal in response to the operation of storing the binary data in the non-volatile memory, receiving a response signal for the third parameter signal through the external device in response to the transmission of the third parameter signal, and determining whether the printed circuit board has booted normally based on an alternative response signal to the third parameter signal.

[0188] According to one embodiment, in response to the binary data being stored in the non-volatile memory, the operation may include storing a file system associated with an operating system and a basic application associated with the operating system through the binary data.

[0189] According to various embodiments, in a printed circuit board comprising a plurality of PBAs, an interface connecting the plurality of PBAs and an external device, wherein each of the plurality of PBAs includes a volatile memory, a non-volatile memory, and a processor, and each of the PBAs transmits a first parameter signal to at least one second terminal of the interface to which power is supplied from a first terminal of the interface, and in response to the transmission of the first parameter signal, stores bootloader data received from the external device in the volatile memory, transmits a second parameter signal to the at least one second terminal in response to the storage of the bootloader data, and in response to the transmission of the second parameter signal, stores binary data received from the external device in the non-volatile memory.

Claims

Claim 1 A printed circuit board comprising a plurality of PBAs and an interface connecting the plurality of PBAs and an external device, wherein the interface comprises terminals having an N * M array, and among the terminals having the N * M array, terminals having an N * K array are electrically connected to each of the plurality of PBAs, and each PBA comprises a volatile memory, a non-volatile memory, and a processor, and each PBA: when power is supplied from a first terminal among the terminals having the N * K array, in response to receiving a connection signal between the external device and the printed circuit board from the external device, transmits a first parameter signal to a second terminal among the terminals having the N * K array, in response to the transmission of the first parameter signal, stores boot-loader data received from the external device in the volatile memory, transmits a second parameter signal to a third terminal among the terminals having the N * K array in response to the storage of the boot-loader data, and stores binary data received from the external device in the non-volatile memory in response to the transmission of the second parameter signal. A printed circuit board that stores. Claim 2 A printed circuit board according to claim 1, wherein the binary data includes the bootloader data. Claim 3 A printed circuit board according to claim 1, wherein the volatile memory includes RAM (random access memory) and the non-volatile memory includes at least one of ROM (read only memory) and NAND flash memory. Claim 4 A printed circuit board according to claim 1, wherein each PBA determines whether the volatile memory and the non-volatile memory are properly mounted on each PBA based on data regarding the current flowing through the printed circuit board. Claim 5 A printed circuit board according to claim 1, wherein the processor performs a power-on reset (POR) in response to the binary data being stored in the non-volatile memory. Claim 6 A printed circuit board according to claim 1, wherein the processor resets the power of the printed circuit board in response to the binary data being stored in the non-volatile memory, transmits a designated signal to the external device through the interface, receives a response signal for the designated signal from the external device in response to the transmission of the designated signal, and determines whether the printed circuit board has booted normally based on the response signal for the designated signal. Claim 7 A printed circuit board according to claim 1, wherein the processor stores a file system associated with an operating system and a basic application associated with the operating system in the non-volatile memory in response to the binary data being stored in the non-volatile memory. Claim 8 A printed circuit board according to claim 1, wherein the PBA activates a communication terminal of the interface in response to power being supplied from the first terminal and receives a connection signal from the external device between the modem port of the external device and the printed circuit board. Claim 9 A printed circuit board according to claim 1, wherein, in response to the bootloader data being stored in the volatile memory, it receives the connection signal and string signal between the modem port of the external device and the printed circuit board from the external device, and in response to the reception of the connection signal and the string signal, it transmits the second parameter signal to the third terminal. Claim 10 A printed circuit board according to claim 1, wherein the volatile memory and the non-volatile memory include an empty memory in which no data is stored. Claim 11 A printed circuit board according to claim 1, wherein the printed circuit board comprises a first surface and a second surface opposite to the first surface, wherein the interface and the non-volatile memory are disposed on the first surface, and the volatile memory and the processor are disposed on the second surface. Claim 12 A printed circuit board according to claim 1, wherein the processor includes an application processor (AP). Claim 13 A printed circuit board according to claim 1, wherein the printed circuit board comprises a mounting area and a non-mounting area in addition to the mounting area, and wherein a plurality of PBAs are disposed in the mounting area and an interface is disposed in the non-mounting area. Claim 14 A printed circuit board according to claim 1, wherein N and M comprise integers greater than 1, and N comprises an integer smaller than M. Claim 15 A printed circuit board according to claim 1, wherein the N * M array comprises a 3 * 14 array and the N * M array comprises a 3 * 3 array. Claim 16 A printed circuit board comprises a plurality of PBAs and an interface connecting the plurality of PBAs and an external device, and a method for processing data for a volatile memory and a non-volatile memory disposed within each PBA, wherein when power is supplied from a first terminal of the interface, in response to receiving a connection signal between the external device and the printed circuit board from the external device, the method comprises: an operation of transmitting a first parameter signal to at least one second terminal of the interface in response to the transmission of the first parameter signal, the operation of storing bootloader data received from the external device in the volatile memory; an operation of transmitting a second parameter signal to the at least one second terminal in response to the storage of the bootloader data; and an operation of storing binary data received from the external device in the non-volatile memory in response to the transmission of the second parameter signal, wherein the interface comprises terminals having an N * M array, and among the terminals having an N * M array, terminals having an N * K array are electrically connected to each of the plurality of PBAs. Claim 17 A method according to claim 16, wherein the binary data comprises the bootloader data. Claim 18 A method according to claim 16, comprising: an operation of transmitting a third parameter signal to at least one second terminal in response to an operation of storing the binary data in the non-volatile memory; an operation of receiving a response signal for the third parameter signal through the external device in response to the transmission of the third parameter signal; and an operation of determining whether the printed circuit board has booted normally based on an alternative response signal to the third parameter signal. Claim 19 A method according to claim 16, comprising the operation of storing a file system associated with an operating system and a basic application associated with the operating system through the binary data in response to the binary data being stored in the non-volatile memory. Claim 20 A printed circuit board comprising a plurality of PBAs, wherein the interface connecting the plurality of PBAs and an external device; wherein each of the plurality of PBAs comprises a volatile memory, a non-volatile memory, and a processor, and each of the PBAs: in response to receiving a connection signal between the external device and the printed circuit board from the external device, a first parameter signal is transmitted from a first terminal of the interface to at least one second terminal of the interface to which power is supplied, in response to the transmission of the first parameter signal, bootloader data received from the external device is stored in the volatile memory, in response to the storage of the bootloader data, a second parameter signal is transmitted to the at least one second terminal, and binary data received from the external device is stored in the non-volatile memory in response to the transmission of the second parameter signal.

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