Display device and method of manufacturing for the same

Abstract

A display device is provided. The display device comprises a first substrate, a semiconductor layer disposed on the first substrate, a first gate conductive layer disposed on the semiconductor layer and including a scan line, a sensing line, and gate electrodes, a first data conductive layer disposed on the first gate conductive layer and including a first data line, a second data line, and one electrode and another electrode of transistors, a second data conductive layer disposed on the first data conductive layer and including a first voltage line and a second voltage line, a first electrode and a second electrode disposed on the second data conductive layer, and light-emitting elements having both ends disposed on the first electrode and the second electrode, respectively, and a first transistor electrically connected to the first electrode and the first voltage line and a second transistor electrically connected to the second electrode and the first data line.

Description

Technology Field

[0001] The present invention relates to a display device and a method for manufacturing the same. Background Technology

[0002] The importance of display devices is increasing along with the development of multimedia. In response to this, various types of display devices, such as Organic Light Emitting Displays (OLEDs) and Liquid Crystal Displays (LCDs), are being used.

[0003] A device for displaying images of a display device includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. Among these, as a light-emitting display panel, it may include a light-emitting element; for example, in the case of a light-emitting diode (LED), there are organic light-emitting diodes (OLEDs) that use organic materials as fluorescent materials and inorganic light-emitting diodes that use inorganic materials as fluorescent materials.

[0004] Inorganic light-emitting diodes (LEDs) utilizing inorganic semiconductors as fluorescent materials possess durability even in high-temperature environments and have the advantage of higher blue light efficiency compared to organic light-emitting diodes (OLEDs). Furthermore, regarding the manufacturing process, which was previously identified as a limitation of conventional LED devices, a transfer method using dielectrophoresis (DEP) has been developed. Consequently, research on inorganic LEDs, which offer superior durability and efficiency compared to OLEDs, is continuing. Prior art literature

[65535] Published Patent Application No. 10-2021-0057891 (May 24, 2021) The problem to be solved

[0005] The problem that the present invention aims to solve is to provide an improved display device in which a parasitic electric field is generated between an electrode that applies an alignment signal and a conductive layer below the electrode during the manufacturing process.

[0006] Another problem that the present invention aims to solve is to provide a method for manufacturing an improved display device in which a parasitic electric field is generated between an electrode that applies an alignment signal and a conductive layer below the electrode during the manufacturing process.

[0007] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] A display device according to an embodiment for solving the above problem comprises: a first substrate; a semiconductor layer disposed on the first substrate and including a plurality of active layers; a first gate conductive layer disposed on the semiconductor layer and including a scan line and a sensing line extending in a first direction, a plurality of gate electrodes disposed to partially overlap with the semiconductor layer, and a first capacitance electrode; a first data conductive layer disposed on the first gate conductive layer and including a data line, one electrode and another electrode of a plurality of transistors, and a second capacitance electrode that overlaps with the first capacitance electrode; a second data conductive layer disposed on the first data conductive layer and including a first voltage line to which a first power supply voltage is applied, and a second voltage line to which a second power supply voltage is applied; a first electrode disposed on the second data conductive layer and extending in the second direction, and a second electrode spaced apart from the first electrode and extending in the second direction; and both ends each include a plurality of light-emitting elements disposed on the first electrode and the second electrode, the first capacitance electrode and the second capacitance electrode constitute a storage capacitor, the second capacitance electrode completely overlaps with the plurality of light-emitting elements in the thickness direction and partially overlaps with the first electrode and the second electrode, and in a manufacturing mode of a display device, a first alignment voltage is applied to the second capacitance electrode.

[0009] A method for manufacturing a display device according to an embodiment for solving the above other problems comprises the step of preparing a target substrate comprising: a first substrate; a semiconductor layer disposed on the first substrate and including a plurality of active layers; a first gate conductive layer disposed on the semiconductor layer and including a scan line and a sensing line extending in a first direction, a plurality of gate electrodes disposed to partially overlap with the semiconductor layer, and a first capacitance electrode; a first data conductive layer disposed on the first gate conductive layer and including a data line, one electrode and other electrodes of a plurality of transistors, and a second capacitance electrode that overlaps with the first capacitance electrode; a second data conductive layer disposed on the first data conductive layer and including a first voltage line to which a first power supply voltage is applied, and a second voltage line to which a second power supply voltage is applied; and a first electrode disposed on the second data conductive layer and extending in the second direction, and a second electrode spaced apart from the first electrode and extending in the second direction. The method includes the step of aligning a plurality of light-emitting elements such that both ends are respectively placed on the first electrode and the second electrode of the target substrate, wherein the first capacitance electrode and the second capacitance electrode constitute a storage capacitor, and the second capacitance electrode completely overlaps with the plurality of light-emitting elements in the thickness direction and partially overlaps with the first electrode and the second electrode, and in the step of aligning the plurality of light-emitting elements, a first alignment voltage is applied to the second capacitance electrode.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0011] According to a display device and a method for manufacturing the same according to one embodiment, the occurrence of a parasitic electric field between an electrode that applies an alignment signal and a conductive layer below the electrode during the manufacturing process can be improved.

[0012] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0013] FIG. 1 is a schematic plan view of a display device according to one embodiment. FIG. 2 is a schematic layout diagram showing wiring included in a display device according to one embodiment. FIG. 3 is an equivalent circuit diagram of a subpixel according to one embodiment. FIG. 4 is a schematic plan view showing wiring arranged in a pixel of a display device according to one embodiment. FIG. 5 is a layout diagram showing a plurality of conductive layers included in one subpixel of a display device according to one embodiment. FIG. 6 is a layout diagram showing a plurality of conductive layers included in a pixel of a display device according to one embodiment. FIG. 7 is a schematic plan view showing a plurality of electrodes and banks included in a pixel of a display device according to one embodiment. Figure 8 is a cross-sectional view taken along the Q1-Q1' line, Q2-Q2' line and Q3-Q3' line of Figure 7. FIG. 9 is a schematic cross-sectional view showing a part of a display device according to another embodiment. FIG. 10 is a schematic diagram of a light-emitting element according to one embodiment. FIG. 11 is a schematic plan view showing a plurality of electrodes and banks included in one pixel of a display device according to another embodiment. FIG. 12 is a schematic plan view showing a plurality of electrodes and banks included in one pixel of a display device according to another embodiment. FIG. 13 is a schematic plan view showing a plurality of electrodes and banks included in one pixel of a display device according to another embodiment. FIG. 14 is a schematic cross-sectional view showing a part of a display device according to another embodiment. FIG. 15 is a schematic cross-sectional view showing a part of a display device according to another embodiment. FIG. 16 is a schematic plan view showing a plurality of electrodes and light-emitting elements included in one pixel of a display device according to another embodiment. FIG. 17 is a cross-sectional view taken along the Q4-Q4' line, Q5-Q5' line and Q6-Q6' line of FIG. 16. FIG. 18 is a schematic plan view showing a plurality of electrodes and light-emitting elements included in one pixel of a display device according to another embodiment. FIG. 19 is a schematic plan view showing a plurality of electrodes and light-emitting elements included in one pixel of a display device according to another embodiment. FIG. 20 is a schematic plan view showing a plurality of electrodes and light-emitting elements included in one pixel of a display device according to another embodiment. FIG. 21 is a schematic plan view showing a plurality of electrodes and light-emitting elements included in one pixel of a display device according to another embodiment. Specific details for implementing the invention

[0014] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0015] Elements or layers referred to as "on" another element or layer include cases where another layer or element is interposed directly above or in the middle of another element. Likewise, "below," "left," and "right" refer to cases where they are interposed immediately adjacent to another element or where another layer or material is interposed in the middle. Throughout the specification, the same reference numerals refer to the same components.

[0016] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0017] Hereinafter, embodiments will be described with reference to the attached drawings.

[0018] FIG. 1 is a schematic plan view of a display device according to one embodiment.

[0019] In this specification, “top,” “top,” and “top surface” refer to an upward direction, i.e., one direction of the third direction (DR3), based on the display device (10), and “bottom,” “bottom,” and “bottom surface” refer to other directions of the third direction (DR3). Additionally, “left,” “right,” “up,” and “down” refer to directions when the display device (10) is viewed from a plane. For example, “left” refers to one direction of the first direction (DR1), “right” refers to another direction of the first direction (DR1), “up” refers to one direction of the second direction (DR2), and “down” refers to another direction of the second direction (DR2).

[0020] Referring to FIG. 1, the display device (10) displays a video or a still image. The display device (10) may refer to any electronic device that provides a display screen. For example, a television, laptop, monitor, billboard, Internet of Things, mobile phone, smartphone, tablet PC (Personal Computer), electronic watch, smart watch, watch phone, head-mounted display, mobile communication terminal, electronic notebook, electronic book, PMP (Portable Multimedia Player), navigation, game console, digital camera, camcorder, etc. that provide a display screen may be included in the display device (10).

[0021] The display device (10) includes a display panel that provides a display screen. Examples of display panels include an inorganic light-emitting diode display panel, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a plasma display panel, a field emission display panel, etc. In the following examples, an inorganic light-emitting diode display panel is used as an example of a display panel, but it is not limited thereto, and if the same technical concept is applicable, it can be applied to other display panels.

[0022] The shape of the display device (10) can be varied in many ways. For example, the display device (10) may have a shape such as a horizontally elongated rectangle, a vertically elongated rectangle, a square, a rectangle with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area (DPA) of the display device (10) may also be similar to the overall shape of the display device (10). In FIG. 1, a display device (10) and a display area (DPA) in the shape of a horizontally elongated rectangle are exemplified.

[0023] The display device (10) may include a display area (DPA) and a non-display area (NDA). The display area (DPA) is an area where the screen can be displayed, and the non-display area (NDA) is an area where the screen is not displayed. The display area (DPA) may also be referred to as an active area, and the non-display area (NDA) as an inactive area. The display area (DPA) may generally occupy the center of the display device (10).

[0024] The display area (DPA) may include a plurality of pixels (PX). The plurality of pixels (PX) may be arranged in a matrix direction. The shape of each pixel (PX) may be a planar rectangle or a square, but is not limited thereto, and may be a rhombus shape with each side tilted toward one direction. Each pixel (PX) may be arranged alternately in a stripe type or a pentile type. Additionally, each of the pixels (PX) may include one or more light-emitting elements (ED) that emit light of a specific wavelength range to display a specific color.

[0025] A non-display area (NDA) may be placed around a display area (DPA). The non-display area (NDA) may surround the display area (DPA) in whole or in part. The display area (DPA) is rectangular in shape, and the non-display area (NDA) may be placed adjacent to the four sides of the display area (DPA). The non-display area (NDA) may form the bezel of the display device (10). In each non-display area (NDA), wiring or circuit drivers included in the display device (10) may be placed, or external devices may be mounted.

[0026] FIG. 2 is a schematic layout diagram showing wiring included in a display device according to one embodiment.

[0027] Referring to FIG. 2, the display device (10) may include a plurality of wires. The plurality of wires may include a scan line (SCL), a sensing line (SSL), a data line (DTL), an initial voltage wire (VIL), a first voltage wire (VDL), and a second voltage wire (VSL). Additionally, although not shown in the drawing, other wires may be arranged in the display device (10).

[0028] Scan line (SCL) and sensing line (SSL) may be extended in a first direction (DR1). Scan line (SCL) and sensing line (SSL) may be connected to a scan driver (SDR). The scan driver (SDR) may include a driving circuit. The scan driver (SDR) may be positioned on one side of the first direction (DR1) of the display area (DPA), but is not limited thereto. The scan driver (SDR) is connected to a signal connection wire (CWL), and at least one end of the signal connection wire (CWL) may be connected to an external device by forming a pad (WPD_CW) on the non-display area (NDA).

[0029] Meanwhile, in this specification, the meaning of "connection" may refer not only to one component being connected to another through mutual physical contact, but also to being connected through another component. Furthermore, this can be understood as one part and another part being interconnected due to the integrated component. Moreover, the connection between one component and another component may be interpreted to include electrical connection through another component in addition to direct contact.

[0030] The data line (DTL) and the initial voltage line (VIL) may extend into a second direction (DR2) that intersects the first direction (DR1). The initial voltage line (VIL) may further include a portion branched from the first direction (DR1) in addition to the portion extended into the second direction (DR2). The first voltage line (VDL) and the second voltage line (VSL) may also include a portion extending into the second direction (DR2) and a portion connected thereto that extends into the first direction (DR1). The first voltage line (VDL) and the second voltage line (VSL) may have a mesh structure, but are not limited thereto. Although not shown in the drawing, each pixel (PX) of the display device (10) may be connected to at least one data line (DTL), an initial voltage line (VIL), a first voltage line (VDL), and a second voltage line (VSL).

[0031] Data line (DTL), initial voltage line (VIL), first voltage line (VDL), and second voltage line (VSL) may be electrically connected to at least one wiring pad (WPD). Each wiring pad (WPD) may be placed in a non-display area (NDA). In one embodiment, the wiring pad of the data line (DTL) (WPD_DT, hereinafter referred to as 'data pad') is placed in a pad area (PDA) on one side of the second direction (DR2) of the display area (DPA), and the wiring pad of the initial voltage line (VIL) (WPD_Vint, hereinafter referred to as 'initial voltage pad'), the wiring pad of the first voltage line (VDL) (WPD_VDD, hereinafter referred to as 'first power pad'), and the wiring pad of the second voltage line (VSL) (WPD_VSS, hereinafter referred to as 'second power pad') may be placed in a pad area (PDA) located on the other side of the second direction (DR2) of the display area (DPA). As another example, the data pad (WPD_DT), initialization voltage pad (WPD_Vint), first power pad (WPD_VDD), and second power pad (WPD_VSS) may all be placed in the same area, for instance, in a non-display area (NDA) located above the display area (DPA). An external device may be mounted on the wiring pad (WPD). The external device may be mounted on the wiring pad (WPD) through an anisotropic conductive film, ultrasonic bonding, etc.

[0032] Each pixel (PX) or subpixel (PXn, where n is an integer from 1 to 3) of the display device (10) includes a pixel driving circuit. The wiring described above may pass through each pixel (PX) or around it and apply a driving signal to each pixel driving circuit. The pixel driving circuit may include transistors and capacitors. The number of transistors and capacitors in each pixel driving circuit may vary. According to one embodiment, each subpixel (PXn) of the display device (10) may have a pixel driving circuit with a 3T1C structure that includes three transistors and one capacitor. Hereinafter, the pixel driving circuit is described using the 3T1C structure as an example, but is not limited thereto, and various other modified pixel (PX) structures such as 2T1C structure, 7T1C structure, and 6T1C structure may be applied.

[0033] FIG. 3 is an equivalent circuit diagram of a subpixel according to one embodiment.

[0034] Referring to FIG. 3, each subpixel (PXn) of a display device (10) according to one embodiment includes, in addition to a light-emitting diode (EL), three transistors (T1, T2, T3) and one storage capacitor (Cst).

[0035] A light-emitting diode (EL) emits light according to the current supplied through a first transistor (T1). The light-emitting diode (EL) includes a first electrode, a second electrode, and at least one light-emitting element disposed between them. The light-emitting element can emit light of a specific wavelength range by means of an electrical signal transmitted from the first electrode and the second electrode.

[0036] One end of the light-emitting diode (EL) is connected to the source electrode of the first transistor (T1), and the other end can be connected to the second voltage wiring (VSL) to which a low potential voltage (hereinafter referred to as the second power supply voltage) lower than the high potential voltage (hereinafter referred to as the first power supply voltage) of the first voltage wiring (VDL) is supplied.

[0037] The first transistor (T1) adjusts the current flowing from the first voltage line (VDL), to which the first power supply voltage is supplied, to the light-emitting diode (EL) according to the voltage difference between the gate electrode and the source electrode. For example, the first transistor (T1) may be a driving transistor for driving the light-emitting diode (EL). The gate electrode of the first transistor (T1) may be connected to the source electrode of the second transistor (T2), the source electrode may be connected to the first electrode of the light-emitting diode (EL), and the drain electrode may be connected to the first voltage line (VDL), to which the first power supply voltage is applied.

[0038] The third transistor (T3) is turned on by a scan signal of the scan line (SCL) to connect the data line (DTL; DTLk, DTLk+1) to the gate electrode of the first transistor (T1). The gate electrode of the third transistor (T3) is connected to the scan line (SCL), the source electrode is connected to the gate electrode of the first transistor (T1), and the drain electrode can be connected to the k-th data line (DTLk, where k is an integer greater than or equal to 1).

[0039] The fourth transistor (T4) is turned on by a sensing signal from the sensing line (SSL) to connect the initialization voltage wire (VIL) to one end of the light-emitting diode (EL). The gate electrode of the fourth transistor (T4) is connected to the sensing line (SSL), the drain electrode is connected to the initialization voltage wire (VIL), and the source electrode can be connected to one end of the light-emitting diode (EL) or the source electrode of the first transistor (T1).

[0040] In one embodiment, the source electrode and drain electrode of each transistor (T1, T2, T3) are not limited to those described above and may be the opposite.

[0041] A storage capacitor (Cst) is formed between the gate electrode and the source electrode of the first transistor (T1). The storage capacitor (Cst) stores the difference voltage between the gate voltage and the source voltage of the first transistor (T1).

[0042] Each of the transistors (T1, T2, T3) can be formed as a thin film transistor. Additionally, while FIG. 3 describes each transistor (T1, T2, T3) as being formed as an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), it is not limited thereto. That is, each transistor (T1, T2, T3) may be formed as a P-type MOSFET, or some may be formed as an N-type MOSFET and others as a P-type MOSFET.

[0043] Hereinafter, the structure of a pixel (PX) of a display device (10) according to one embodiment will be described in detail with further reference to other drawings.

[0044] FIG. 4 is a schematic plan view showing wiring arranged in a pixel of a display device according to one embodiment. FIG. 4 illustrates a plurality of wirings arranged in each pixel (PX) of a display device (10) and a schematic shape of a second bank (45), while the members arranged in the light-emitting region (EMA) of each sub-pixel (PXn) and some conductive layers arranged below them are omitted. In the following drawings, both sides of the first direction (DR1) may be referred to as the left and right sides, respectively, and both sides of the second direction (DR2) may be referred to as the upper side and the lower side, respectively.

[0045] Referring to FIG. 4, each of the plurality of pixels (PX) of the display device (10) may include a plurality of subpixels (PXn, where n is an integer from 1 to 3). For example, one pixel (PX) may include a first subpixel (PX1), a second subpixel (PX2), and a third subpixel (PX3). The first subpixel (PX1) may emit light of a first color, the second subpixel (PX2) may emit light of a second color, and the third subpixel (PX3) may emit light of a third color. The first color may be blue, the second color may be green, and the third color may be red. However, not limited thereto, each subpixel (PXn) may emit light of the same color.

[0046] Each subpixel (PXn) of the display device (10) may include a light-emitting region (EMA) and a non-light-emitting region (not shown). The light-emitting region (EMA) is an area where a light-emitting element ('30' in FIG. 7) is placed and light of a specific wavelength range is emitted, and the non-light-emitting region may be an area where a light-emitting element (ED) is not placed and light emitted from the light-emitting element (ED) does not reach, so no light is emitted. The light-emitting region may include an area where a light-emitting element (ED) is placed and an area adjacent to the light-emitting element (ED) where light emitted from the light-emitting element (ED) is emitted.

[0047] Not limited thereto, the light-emitting region may also include a region where light emitted from a light-emitting element (ED) is reflected or refracted by another member and emitted. A plurality of light-emitting elements (EDs) are arranged in each subpixel (PXn), and a light-emitting region may be formed by including the region where they are arranged and an adjacent region.

[0048] Additionally, each subpixel (PXn) may include a cutting area (CBA) placed in a non-emissive region. The cutting area (CBA) may be placed on one side of the second direction (DR2) of the emitting region (EMA). The cutting area (CBA) may be placed between the emitting regions (EMA) of the subpixels (PXn) adjacent in the second direction (DR2). A plurality of emitting regions (EMA) and cutting areas (CBA) may be arranged in the display area (DPA) of the display device (10). For example, a plurality of emitting regions (EMA) and cutting areas (CBA) may be arranged repeatedly in the first direction (DR1), while the emitting regions (EMA) and cutting areas (CBA) may be arranged alternately in the second direction (DR2). Additionally, the spacing of the cutting areas (CBA) in the first direction (DR1) may be smaller than the spacing of the emitting regions (EMA) in the first direction (DR1). As described below, a second bank (45) is disposed between the cutting regions (CBA) and the light-emitting regions (EMA), and the spacing between them may vary depending on the width of the second bank (45). Light is not emitted because a light-emitting element (ED) is not disposed in the cutting regions (CBA), but some of the electrodes (21) disposed in each subpixel (PXn) may be disposed therein. The electrodes (21) disposed in each subpixel (PXn) may be disposed separated from each other in the cutting regions (CBA).

[0049] The second bank (45) may be arranged in a grid pattern across the entire front of the display area (DPA), including a portion extending in the first direction (DR1) and the second direction (DR2) on the plane. The second bank (45) may be arranged across the boundaries of each sub-pixel (PXn) to distinguish neighboring sub-pixels (PXn). Additionally, the second bank (45) may be arranged to surround the light-emitting region (EMA) and the cut-off region (CBA) placed for each sub-pixel (PXn) to distinguish them. The portion of the second bank (45) extending in the second direction (DR2) may have a greater width between the portions placed between the light-emitting regions (EMA) than between the portions placed between the cut-off regions (CBA). Accordingly, the spacing between the cut-off regions (CBA) may be smaller than the spacing between the light-emitting regions (EMA).

[0050] A plurality of wirings are arranged in each pixel (PX) and subpixel (PXn) of the display device (10). For example, the display device (10) includes a scan line (SCL) and a sensing line (SSL) arranged extending in a first direction (DR1), in addition to an initial voltage distribution line (IDL) arranged across several subpixels (PXn). Additionally, the display device (10) includes a data line (DTL), an initial voltage wiring (VIL), a first voltage wiring (VDL), and a second voltage wiring (VSL) arranged extending in a second direction (DR2).

[0051] A scan line (SCL) extends in a first direction (DR1) and is positioned across a plurality of subpixels (PXn) arranged in the first direction (DR1). Additionally, a plurality of scan lines (SCL) are spaced apart from each other in a second direction (DR2) across the entire front of the display area (DPA). The scan line (SCL) may be positioned above the center of each pixel (PX) or subpixel (PXn). The scan line (SCL) may be electrically connected to the gate electrode of a second transistor (T2) and may apply a scan signal to the second transistor (T2).

[0052] Similarly, the sensing line (SSL) extends in a first direction (DR1) and is positioned across a plurality of subpixels (PXn) arranged in the first direction (DR1). Additionally, the plurality of sensing lines (SSL) are spaced apart from each other in a second direction (DR2) across the entire front of the display area (DPA). The sensing line (SSL) may be positioned below the center of each pixel (PX) or subpixel (PXn). The sensing line (SSL) may be electrically connected to the gate electrode of the second transistor (T3) and may apply a sensing signal to the third transistor (T3).

[0053] The initialization voltage divider line (IDL) is positioned for each pixel (PX) and can be positioned across three subpixels (PXn). The initialization voltage divider line (IDL) may be positioned above the sensing line (SSL) and have a shape that extends in the first direction (DR1). The initialization voltage divider line (IDL) is electrically connected to the initialization voltage wiring (VIL) to transmit the initialization voltage (Vint) applied to each pixel (PX) to each subpixel (PXn). For example, the initialization voltage divider line (IDL) may make direct contact with the initialization voltage wiring (VIL) through a contact hole ('CT11' in FIG. 5). The initialization voltage divider line (IDL) may be electrically connected to the drain electrode of the third transistor (T3) of each subpixel (PXn). The initialization voltage divider line (IDL) can apply the initialization voltage applied from the initialization voltage wiring (VIL) to the third transistor (T3).

[0054] The scan line (SCL), sensing line (SSL), and initialization voltage divider line (IDL) may be composed of the first gate conductive layer described below. The first gate conductive layer may include additional conductive layers in addition to the lines.

[0055] A data line (DTL) extends in a second direction (DR2) and is positioned across a plurality of subpixels (PXn) arranged in the second direction (DR2). Additionally, a plurality of data lines (DTL) are spaced apart from each other in a first direction (DR1) across the entire front of the display area (DPA). A data line (DTL) may be positioned to the right of each subpixel (PXn). A data line (DTL) that transmits a data signal to one subpixel (PXn) is positioned to the right of another subpixel (PXn) adjacent in the first direction (DR1), and a data line (DTL) positioned to the right of the corresponding subpixel (PXn) may transmit a data signal to another subpixel (PXn). That is, a data line (DTL) may not be positioned in the area occupied by the connected subpixel (PXn). However, it is not limited thereto. A data line (DTL) may be electrically connected to the drain electrode of a second transistor (T2) and may apply a data signal to the second transistor (T2).

[0056] The initial voltage wiring (VIL) extends in a second direction (DR2) and is positioned across a plurality of pixels (PX) arranged in the second direction (DR2). Additionally, the plurality of initial voltage wirings (VIL) are spaced apart from each other in a first direction (DR1) across the entire front of the display area (DPA). The initial voltage wiring (VIL) can be positioned for each of three subpixels (PXn) or one pixel (PX). For example, the initial voltage wiring (VIL) can be positioned to the left of a data line (DTL) connected to any one subpixel (PXn). In the drawing, the initial voltage wiring (VIL) is exemplified as being positioned to the left of a data line (DTL) located in the area occupied by the first subpixel (PX1), as a data line (DTL) connected to the second subpixel (PX2), but is not limited thereto. The initial voltage wiring (VIL) can be electrically connected to an initial voltage distribution line (IDL) to transmit an initial voltage to each subpixel (PXn). The initialization voltage wiring (VIL) can be electrically connected to the drain electrode of the third transistor (T3) and can apply an initialization voltage to the third transistor (T3).

[0057] The data line (DTL) and initial voltage wiring (VIL) may be composed of a first data conductive layer described below. The first data conductive layer may include additional conductive layers in addition to the line and wiring.

[0058] The first voltage line (VDL) and the second voltage line (VSL) may be extended in the second direction (DR2) and positioned across a plurality of subpixels (PXn) adjacent in the second direction (DR2). Additionally, a plurality of first voltage lines (VDL) and second voltage lines (VSL) are spaced apart from each other in the first direction (DR1) across the entire front surface of the display area (DPA). The first voltage line (VDL) and the second voltage line (VSL) may be positioned between a plurality of data lines (DTL) on a plane. The first voltage line (VDL) may be positioned to the left of the center of each subpixel (PXn), and the second voltage line (VSL) may be positioned to the right. However, the first voltage line (VDL) may be bent in a portion while extending in the second direction (DR2). For example, the first voltage line (VDL) may include a portion that is bent toward the second voltage line (VSL) in addition to a portion that extends from the upper side to the lower side of each subpixel (PXn). Accordingly, the spacing between the first voltage line (VDL) and the second voltage line (VSL) placed in each subpixel (PXn) may vary partially.

[0059] The first voltage line (VDL) can be electrically connected to the drain electrode of the first transistor (T1) and can apply a first power supply voltage to the first transistor (T1). The second voltage line (VSL) can be electrically connected to the second electrode of the light-emitting diode (EL) and can apply a second power supply voltage to the light-emitting element. The first voltage line (VDL) and the second voltage line (VSL) may be formed of a second data conductive layer described later.

[0060] FIG. 5 is a layout diagram showing a plurality of conductive layers included in a subpixel of a display device according to one embodiment. FIG. 6 is a layout diagram showing a plurality of conductive layers included in a pixel of a display device according to one embodiment. FIG. 7 is a schematic plan view showing a plurality of electrodes and banks included in a pixel of a display device according to one embodiment. FIG. 8 is a cross-sectional view cut along the lines Q1-Q1', Q2-Q2', and Q3-Q3' of FIG. 7.

[0061] FIG. 5 illustrates a layout of conductive layers, wirings, and transistors connected thereto, arranged in a first subpixel (PX1), as circuit element layers arranged in each subpixel (PXn), and FIG. 6 illustrates a layout of conductive layers, wirings, and transistors connected thereto, arranged in a single pixel (PX). FIG. 5 and FIG. 6 omit the first voltage wiring (VDL) and the second voltage wiring (VSL). The subpixels (PXn) shown in FIG. 6 are not depicted by distinguishing the areas they occupy, but rather by distinguishing the circuit element layers connected to the light-emitting diode (EL) arranged in each subpixel (PXn).

[0062] Additionally, FIG. 7 illustrates the arrangement of a plurality of banks (40, 45) and contact electrodes (26, 27) in addition to the electrodes (21) forming the light-emitting diode (EL) and the light-emitting element (ED) as a display element layer placed in each pixel (PX). FIG. 8 illustrates a cross-section across both ends of the light-emitting element (ED) in addition to the first transistor (T1).

[0063] Referring to FIG. 5 to FIG. 8 in conjunction with FIG. 4, the display device (10) may include a circuit element layer and a display element layer. The display element layer is a layer in which a first electrode (21) and a second electrode (21) are arranged, including a light-emitting element (ED) of a light-emitting diode (EL), and the circuit element layer may be a layer in which a plurality of wirings are arranged, including pixel circuit elements for driving the light-emitting diode (EL). For example, the circuit element layer may include each transistor (T1, T2, T3) in addition to a scan line (SCL), a sensing line (SSL), a data line (DTL), an initialization voltage wiring (VIL), a first voltage wiring (VDL), and a second voltage wiring (VSL).

[0064] Specifically, the display device (10) includes a first substrate (11) on which circuit element layers and display element layers are arranged. The first substrate (11) may be an insulating substrate and may be made of an insulating material such as glass, quartz, or polymer resin. Additionally, the first substrate (11) may be a rigid substrate, but may also be a flexible substrate capable of bending, folding, rolling, etc.

[0065] A light-blocking layer (BML) may be disposed on the first substrate (11). The light-blocking layer (BML) is disposed to overlap the first active layer (ACT1) of the first transistor (T1) of the display device (10). The light-blocking layer (BML1) may include a material that blocks light, thereby preventing light from being incident on the active layer (ACT1) of the first transistor. As an example, the light-blocking layer (BML) may be formed of an opaque metallic material that blocks the transmission of light. However, it is not limited thereto, and in some cases, the light-blocking layer (BML) may be omitted and may be disposed to overlap the active layers of other transistors (T1, T2, T3).

[0066] The buffer layer (12) may be disposed over the entire surface of the first substrate (11), including a light-blocking layer (BML). The buffer layer (12) is formed on the first substrate (11) to protect each transistor (T1, T2, T3) from moisture penetrating through the first substrate (11), which is susceptible to moisture permeability, and can perform a surface planarization function. The buffer layer (12) may be composed of a plurality of inorganic layers that are alternately stacked. For example, the buffer layer (12) may be formed as a multilayer in which inorganic layers comprising at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) are alternately stacked.

[0067] The semiconductor layer is placed on the buffer layer (12). The semiconductor layer may include active layers (ACT1, ACT2, ACT3) of each transistor (T1, T2, T3). The first active layer (ACT1) of the first transistor (T1) may be placed adjacent to the center of each subpixel (PXn) and positioned below it. The second active layer (ACT2) of the second transistor (T2) may be placed above the center of each subpixel (PXn), and the third active layer (ACT3) of the third transistor (T3) may be placed below the first active layer (ACT1).

[0068] Meanwhile, in an exemplary embodiment, the semiconductor layer may include polycrystalline silicon, single-crystal silicon, oxide semiconductor, etc. Polycrystalline silicon may be formed by crystallizing amorphous silicon. When the semiconductor layer includes an oxide semiconductor, each active layer (ACT1, ACT2, ACT3) may include a plurality of conductive regions (ACTa, ACTb) and a channel region (ACTc) between them. The oxide semiconductor may be an oxide semiconductor containing indium (In). In some embodiments, the oxide semiconductor may be indium-tin oxide (ITO), indium-zinc oxide (IZO), indium-gallium oxide (IGO), indium-zinc-tin oxide (IZTO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-gallium-zinc-tin oxide (IGZTO), etc.

[0069] In another exemplary embodiment, the semiconductor layer may include polycrystalline silicon. Polycrystalline silicon may be formed by crystallizing amorphous silicon, in which case the conductive regions of the active layers (ACT1, ACT2, ACT3) may each be doped regions doped with impurities. However, it is not limited thereto.

[0070] The first gate insulating layer (13) is disposed on the semiconductor layer and the buffer layer (12). The first gate insulating layer (13) may be disposed on the buffer layer (12) by including a semiconductor layer. The first gate insulating layer (13) may function as a gate insulating film for each transistor. The first gate insulating layer (13) may be composed of an inorganic layer including an inorganic material, such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), or may be formed in a stacked structure.

[0071] The first gate conductive layer is disposed on the first gate insulating layer (13). The first gate conductive layer may include gate electrodes (G1, G2, G3) of each transistor (T1, T2, T3), a scan line (SCL), a sensing line (SSL), an initial voltage divider line (IDL), and a first capacitance electrode (CSE1) of a storage capacitor. Since the description of the scan line (SCL), the sensing line (SSL), and the initial voltage divider line (IDL) is the same as described above, the following description will focus on the plurality of gate electrodes and the first capacitance electrode (CSE1).

[0072] The gate electrodes (G1, G2, G3) of the first gate conductive layer can each be arranged to partially overlap with the active layer of the transistors (T1, T2, T3). For example, the first gate electrode (G1) of the first transistor (T1) can be arranged to partially overlap with the first active layer (ACT1). The first gate electrode (G1) can be connected to and integrated with the first capacitance electrode (CSE1) of the storage capacitor described later.

[0073] The second gate electrode (G2) is electrically connected to the scan line (SCL), and the second transistor (T2) can receive a scan signal. The third gate electrode (G3) is electrically connected to the sensing line (SSL), and the third transistor (T3) can receive a sensing signal on the gate electrode.

[0074] The first capacitance electrode (CSE1, or Cst1) of the storage capacitor (Cst) is positioned between the scan line (SCL) and the sensing line (SSL). The first capacitance electrode (CSE1) can be electrically connected to the first gate electrode (G1) of the first transistor (T1) and the source electrode of the second transistor (T2). For example, the first capacitance electrode (CSE1) can be formed integrally with the first gate electrode (G1) and can be connected to the source electrode of the second transistor (T2) through a contact hole (CT7).

[0075] The first gate conductive layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, it is not limited thereto.

[0076] The first protective layer (15) is disposed on the first gate conductive layer. The first protective layer (15) is disposed to cover the first gate conductive layer and can perform the function of protecting it. The first protective layer (15) may be composed of an inorganic layer including an inorganic material, such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), or may be formed in a stacked structure.

[0077] The first data conductive layer is disposed on the first protection layer (15). The first data conductive layer may include a plurality of conductive patterns (DP1, DP2) in addition to the source electrodes and drain electrodes of each transistor (T1, T2, T3), a data line (DTL), an initial voltage line (VIL), and a second capacitance electrode (CSE2 or Cst2) of the storage capacitor. Since the description of the data line (DTL) and the initial voltage line (VIL) is the same as described above, the following description will focus on the plurality of source electrodes, drain electrodes, the second capacitance electrode (CSE2), and the conductive patterns.

[0078] The first source electrode (S1) and the first drain electrode (D1) of the first transistor (T1) are arranged to partially overlap with the first active layer (ACT1). The first source electrode (S1) and the first drain electrode (D1) can each contact the first active layer (ACT1) through a contact hole (CT1) penetrating the first protection layer (15) and the first gate insulating layer (13). Additionally, the first source electrode (S1) can contact the light-blocking layer (BML) through a contact hole (CT5) penetrating the first protection layer (15), the first gate insulating layer (13), and the buffer layer (12). The first drain electrode (D1) can be electrically connected to the first voltage wiring (VDL), and the first source electrode (S1) can be connected to the second capacitance electrode (CSE2) of the storage capacitor, which is connected to the first electrode (21) of the light-emitting diode (EL). For example, the first drain electrode (D1) can be directly contacted with the first voltage wiring (VDL) through a contact hole, and the first source electrode (S1) can be integrated and connected with the second capacitance electrode (CSE2).

[0079] The second source electrode (S2) and the second drain electrode (D2) of the second transistor (T2) are arranged to partially overlap with the second active layer (ACT2). The second source electrode (S2) and the second drain electrode (D2) can each contact the second active layer (ACT2) through a contact hole (CT3) penetrating the first protection layer (15) and the first gate insulating layer (13). The second drain electrode (D2) can be connected in an integrated manner with the data line (DTL), and the second source electrode (S2) can contact the first capacitance electrode (CSE1) through a contact hole (CT7) penetrating the first protection layer (15). The second transistor (T2) can be turned on by a scan signal to transmit a data signal applied from the data line (DTL) to the first gate electrode (G1) of the first transistor (T1).

[0080] The third source electrode (S3) and the third drain electrode (D3) of the third transistor (T3) are arranged to partially overlap with the third active layer (ACT3). The third source electrode (S3) and the third drain electrode (D3) can each contact the third active layer (ACT3) through a contact hole (CT4) penetrating the first protection layer (15) and the first gate insulation layer (13). The third drain electrode (D3) contacts the initialization voltage distribution line (IDL) through a contact hole (CT9) penetrating the first protection layer (15), and the third source electrode (S3) can be connected to the second capacitance electrode (CSE2) of the storage capacitor. For example, the third source electrode (S3) can be integrated and connected to the second capacitance electrode (CSE2). Additionally, the initialization voltage distribution line (IDL) can be connected to the initialization voltage wiring (VIL) through a contact hole (CT11) penetrating the first protection layer (15) so that the initialization voltage can be applied, and the third drain electrode (D3) can receive the initialization voltage. The third transistor (T3) can be turned on by a sensing signal and deliver the initialization voltage to the first electrode of the light-emitting diode (EL) through the second capacitance electrode (CSE2).

[0081] The second capacitance electrode (CSE2) of the storage capacitor (Cst) is positioned to overlap with the first capacitance electrode (CSE1). The second capacitance electrode (CSE2) can be integrated and connected with the first source electrode (S1) of the first transistor (T1) and the third source electrode (S3) of the third transistor (T3).

[0082] The first conductive pattern (DP1) is positioned to overlap with the scan line (SCL) and the third gate electrode (G3). The first conductive pattern (DP1) can contact the scan line (SCL) and the third gate electrode (G3) through a contact hole (CT6) penetrating the first protective layer (15). The third gate electrode (G3) can be electrically connected to the scan line (SCL) through the first conductive pattern (DP1). The second conductive pattern (DP2) is positioned to overlap with the sensing line (SSL) and the fourth gate electrode (G4). The second conductive pattern (DP2) can contact the sensing line (SSL) and the fourth gate electrode (G4) through a contact hole (CT8) penetrating the first protective layer (15). The fourth gate electrode (G4) can be electrically connected to the sensing line (SSL) through the second conductive pattern (DP2).

[0083] The first data conductive layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, it is not limited thereto.

[0084] The first interlayer insulating layer (17) is disposed on the first data conductive layer. The first interlayer insulating layer (17) can function as an insulating film between the first data conductive layer and other layers disposed thereon. Additionally, the first interlayer insulating layer (17) can cover the first data conductive layer and perform the function of protecting the first data conductive layer. The first interlayer insulating layer (17) may be composed of an inorganic layer including an inorganic material, such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), or may be formed in a stacked structure.

[0085] A second data conductive layer is disposed on the first interlayer insulating layer (17). The second data conductive layer includes a first voltage line (VDL) and a second voltage line (VSL). However, it is not limited thereto, and the second data conductive layer may further include a plurality of conductive patterns. The first voltage line (VDL) can be electrically connected to the first drain electrode (D1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (17). The first power supply voltage applied to the first voltage line (VDL) can be transmitted to the first electrode (21) of the light-emitting diode (EL) through the first transistor (T1). The second voltage line (VSL) can be electrically connected to the second electrode (21) of the light-emitting diode (EL) and can transmit the second power supply voltage to the second electrode (21). Since the description of the first voltage line (VDL) and the second voltage line (VSL) is the same as described above, a detailed description will be omitted.

[0086] The second data conductive layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, it is not limited thereto.

[0087] The first flattening layer (19) is disposed on the second data conductive layer. The first flattening layer (19) may include an organic insulating material, such as polyimide (PI), and may perform a surface flattening function.

[0088] A plurality of first banks (40), a plurality of electrodes (21), a light-emitting element (ED), a second bank (45), and a plurality of contact electrodes (26, 27) are disposed on the first flattening layer (19). Additionally, a plurality of insulating layers (51, 52, 53, 54) may be further disposed on the first flattening layer (19).

[0089] A plurality of first banks (40) may be placed directly on the first planarization layer (19). A plurality of first banks (40) may be placed within a light-emitting region (EMA) such that they extend in a second direction (DR2) within each subpixel (PXn) but do not extend to other adjacent subpixels (PXn) in the second direction (DR2). Additionally, a plurality of first banks (40) may be spaced apart from each other in a first direction (DR1) to form a region where a light-emitting element (ED) is placed between them. A plurality of first banks (40) may be placed for each subpixel (PXn) to form a linear pattern in the display region (DPA) of the display device (10). Although two first banks (40) are shown in the drawing, they are not limited thereto. Depending on the number of electrodes (21) described later, a larger number of first banks (40) may be placed.

[0090] The first bank (40) may have a structure in which at least a portion protrudes with respect to the upper surface of the first flattening layer (19). The protruding portion of the first bank (40) may have an inclined side, and light emitted from the light-emitting element (ED) may proceed toward the inclined side of the first bank (40). The electrodes (21) placed on the first bank (40) may include a material with high reflectivity, and light emitted from the light-emitting element (ED) may be reflected from the electrodes (21) placed on the side of the first bank (40) and emitted toward the upper direction of the first flattening layer (19). That is, the first bank (40) may provide an area where the light-emitting element (ED) is placed, and at the same time, perform the function of a reflective barrier that reflects light emitted from the light-emitting element (ED) toward the upper direction. The side of the first bank (40) may be inclined in a linear shape, but is not limited thereto, and the first bank (40) may have a curved outer surface in the shape of a semicircle or semi-ellipse. In an exemplary embodiment, the first banks (40) may include an organic insulating material such as polyimide (PI), but are not limited thereto.

[0091] A plurality of electrodes (21) are disposed on the first bank (40) and the first flattening layer (19). The plurality of electrodes (21) may include a first electrode (21) and a second electrode (21). The first electrode (21) and the second electrode (21) extend in a second direction (DR2), and may be disposed so as to be spaced apart from each other in a first direction (DR1).

[0092] The first electrode (21) and the second electrode (21) may each extend in a second direction (DR2) within a subpixel (PXn) and may be separated from other electrodes (21) in a cutting region (CBA). In some embodiments, a cutting region (CBA) may be placed between the light-emitting regions (EMA) of subpixels (PXn) adjacent to the second direction (DR2), and the first electrode (21) and the second electrode (21) may be separated from other first electrodes (21) and second electrodes (21) placed in subpixels (PXn) adjacent to the second direction (DR2) in the cutting region (CBA). However, this is not limited thereto, and some electrodes (21) may be placed extending beyond subpixels (PXn) adjacent to the second direction (DR2) without being separated for each subpixel (PXn), or only one of the first electrode (21) or the second electrode (21) may be separated.

[0093] The first electrode (21) is connected to the second voltage wiring (VSL) through an electrode contact hole (CTS) penetrating the first flattening layer (19) and the first interlayer insulating layer (17), and the second electrode (21) can be connected to the second voltage wiring (VSL) through an electrode contact hole (CTS) penetrating the first flattening layer (19) and the first interlayer insulating layer (17).

[0094] For example, the first electrode (21) and the second electrode (21) overlap with the portion extending in the first direction (DR1) of the second bank (45), and an electrode contact hole (CTS) may be formed in the area where each electrode (21) and the second bank (45) overlap.

[0095] Additionally, the first electrode (21) and the second electrode (21) can each come into contact with an electrode conduction pattern disposed on the second data conduction layer, and the position of the electrode contact hole (CTS) may vary depending on the arrangement of the electrode conduction pattern. For example, all electrode contact holes (CTS) may be formed within the light-emitting region (EMA).

[0096] In the drawings, one first electrode (21) and one second electrode (21) are exemplified for each subpixel (PXn), but are not limited thereto. In some embodiments, the number of first electrodes (21) and second electrodes (21) occupied for each subpixel (PXn) may be greater. Additionally, the first electrode (21) and the second electrode (21) occupied for each subpixel (PXn) may not necessarily have a shape that extends in one direction, and the first electrode (21) and the second electrode (21) may be occupied in various structures. For example, the first electrode (21) and the second electrode (21) may have a partially curved or bent shape, and one electrode may be occupied to surround the other electrode.

[0097] The first electrode (21) and the second electrode (21) may each be placed on the first bank (40). In some embodiments, the first electrode (21) and the second electrode (21) may each be formed to have a width greater than that of the first bank (40). For example, the first electrode (21) and the second electrode (21) may each be placed to cover the outer surface of the first bank (40). The first electrode (21) and the second electrode (21) are each placed on the side of the first bank (40), and the gap between the first electrode (21) and the second electrode (21) may be narrower than the gap between the first bank (40). Additionally, at least some portions of the first electrode (21) and the second electrode (21) may be placed directly on the first flattening layer (19).

[0098] Each electrode (21) may include a highly reflective conductive material. For example, each electrode (21) may include a metal such as silver (Ag), copper (Cu), or aluminum (Al) as a highly reflective material, or an alloy including aluminum (Al), nickel (Ni), or lanthanum (La). Each electrode (21) may reflect light emitted from the light-emitting element (ED) and traveling toward the side of the first bank (BNL1) toward the upper direction of each subpixel (PXn).

[0099] However, each electrode (21) may further include a transparent conductive material, not limited thereto. For example, each electrode (21) may include a material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin-Zinc Oxide), etc. In some embodiments, each electrode (21) may have a structure in which a transparent conductive material and a metal layer with high reflectivity are each stacked one or more times, or may be formed as a single layer including these. For example, each electrode (21) may have a stacked structure such as ITO / Silver (Ag) / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0100] The plurality of electrodes (21) may be electrically insulated from the contact electrodes (26, 27) to be described later. That is, the plurality of electrodes (21) are electrodes for aligning the light-emitting element (ED) in the manufacturing mode of the display device, and the contact electrodes (26, 27) to be described later may be electrodes electrically connected to the light-emitting element (ED) to cause the light-emitting element (ED) to emit light.

[0101] As described above, each electrode (21) may be utilized to form an electric field within a subpixel (PXn) to align a light-emitting element (ED). The light-emitting element (ED) may be positioned between the first electrode (21) and the second electrode (21) by an electric field formed between the first electrode (21) and the second electrode (21) and the lower second capacitive electrode (CSE2). In an exemplary embodiment, the light-emitting element (ED) of the display device (10) may be sprayed onto the electrodes (21) through an inkjet printing process. When ink containing the light-emitting element (ED) is sprayed onto the electrode (21), an electric field is generated by applying an alignment signal to the second capacitive electrode (CSE2) and the electrode (21), respectively. For example, a first alignment signal (or a first alignment voltage) may be applied to the second capacitive electrode (CSE2), and a second alignment signal (or a second alignment voltage) may be applied to the electrodes (21). A predetermined electric field can be generated between the second capacitive electrode (CES2) and the electrodes (21) through the first alignment signal and the second alignment signal.

[0102] The light-emitting element (ED) dispersed in the ink can be aligned on the electrode (21) by receiving a dielectrophoretic force from the electric field generated between the electrode (21) and the second capacitive electrode (CSE2).

[0103] In order to form an electric field through alignment signals between the electrodes (21) and the second capacitance electrode (CSE2), the second capacitance electrode (CSE2) may overlap with the first electrode (21) and the second electrode (21), respectively, in the thickness direction. The second capacitance electrode (CSE2) may overlap with a portion of the first electrode (21) and a portion of the second electrode (21), respectively, in the thickness direction. For example, the second capacitance electrode (CSE2) may overlap with a portion of the first electrode (21) that does not overlap with the first bank (40), and a portion of the second electrode (21) that does not overlap with the first bank (40), in the thickness direction. Light-emitting elements (EDs) aligned on the electrode (21) may completely overlap with the second capacitance electrode (CSE2) in the thickness direction.

[0104] In an embodiment in which a light-emitting element (ED) is placed between the first electrode and the second electrode by means of an electric field formed on the first electrode and the second electrode when aligning the light-emitting element (ED) on the first electrode and the second electrode, for example, when the first alignment signal is applied to the first electrode and the second alignment signal is applied to the second electrode, a parasitic electric field may be formed between the first electrode and / or the second electrode by other conductive layers located below the first electrode and the second electrode.

[0105] However, in the case of a display device according to one embodiment, a first alignment signal (or a first alignment voltage) is applied to a second capacitive electrode (CES2) in the manufacturing mode of the display device, and a second alignment signal (or a second alignment voltage) is applied to the electrodes (21), and by forming a predetermined electric field between the second capacitive electrode (CES2) and the electrodes (21) through the first alignment signal and the second alignment signal to align the light-emitting elements (ED), it is possible to prevent a parasitic electric field from being formed between the first electrode and / or the second electrode by other conductive layers located below the first electrode and the second electrode.

[0106] A first insulating layer (51) is disposed on the first flattening layer (19), the first electrode (21), and the second electrode (21). The first insulating layer (51) is disposed to partially cover the first electrode (21) and the second electrode (21), including the area between them. For example, the first insulating layer (51) may be disposed to cover most of the upper surfaces of the first electrode (21) and the second electrode (21), while exposing a portion of the first electrode (21) and the second electrode (21). In other words, the first insulating layer (51) may be formed substantially over the first flattening layer (19) and may include an opening (not shown) that partially exposes the first electrode (21) and the second electrode (21).

[0107] In an exemplary embodiment, the first insulating layer (51) may have a step formed such that a portion of the upper surface is recessed between the first electrode (21) and the second electrode (21). However, it is not limited thereto. The first insulating layer (51) may have a flat upper surface so that a light-emitting element (ED) is placed thereon.

[0108] The first insulating layer (51) can protect the first electrode (21) and the second electrode (21) while simultaneously insulating them from each other. Additionally, it can prevent the light-emitting element (ED) placed on the first insulating layer (51) from being damaged by direct contact with other components. However, the shape and structure of the first insulating layer (51) are not limited thereto.

[0109] The second bank (45) may be placed on the first insulating layer (51). The second bank (45) may be arranged in a grid pattern across the entire front of the display area (DPA), including portions extending in the first direction (DR1) and the second direction (DR2) in a planar manner. The second bank (45) may be placed across the boundaries of each subpixel (PXn) to distinguish neighboring subpixels (PXn). Additionally, according to one embodiment, the second bank (45) may be formed to have a greater height than the first bank (40). The second bank (45) may perform the function of preventing ink from overflowing into adjacent subpixels (PXn) during the inkjet printing process of the manufacturing process of the display device (10). The second bank (45) may separate the ink in which different light-emitting elements (EDs) are dispersed for each different subpixel (PXn) so that they do not mix with each other.

[0110] Additionally, the second bank (45) is positioned to surround the light-emitting region (EMA) and the cut-off region (CBA) placed for each subpixel (PXn), thereby distinguishing them. The first electrode (21) and the second electrode (21) may be extended in the second direction (DR2) and positioned across the portion of the second bank (45) extended in the first direction (DR1). The portion of the second bank (45) extended in the second direction (DR2) may have a greater width than the portion of the cut-off region (CBA) positioned between the light-emitting regions (EMA). Accordingly, the spacing between the cut-off regions (CBA) may be smaller than the spacing between the light-emitting regions (EMA). The second bank (45) may include polyimide (PI) as in the first bank (40), but is not limited thereto.

[0111] A light-emitting element (ED) may be disposed on the first insulating layer (51). A plurality of light-emitting elements (ED) may be spaced apart from each other along the second direction (DR2) in which each electrode (21) is extended and may be aligned substantially parallel to each other. The spacing between the light-emitting elements (ED) is not particularly limited. Additionally, the light-emitting element (ED) may have a shape that extends in one direction, and the direction in which each electrode (21) is extended and the direction in which the light-emitting element (ED) is extended may be substantially perpendicular. However, this is not limited thereto, and the light-emitting element (ED) may be disposed obliquely rather than perpendicular to the direction in which each electrode (21) is extended.

[0112] A light-emitting element (ED) may include a light-emitting layer (76) containing different materials and emit light of different wavelengths to the outside. A display device (10) may include light-emitting elements (EDs) that emit light of different wavelengths. Accordingly, light of the first color, the second color, and the third color may be emitted from the first subpixel (PX1), the second subpixel (PX2), and the third subpixel (PX3), respectively. However, it is not limited thereto. In some cases, each subpixel (PXn) may include the same type of light-emitting element (ED) and emit light of substantially the same color.

[0113] Additionally, the light-emitting element (ED) may have both ends placed on each electrode (21) between the first banks (40). For example, the light-emitting element (ED) may be placed such that one end is placed on the first electrode (21) and the other end is placed on the second electrode (21). The extended length of the light-emitting element (ED) is longer than the distance between the first electrode (21) and the second electrode (21), and both ends of the light-emitting element (ED) may be placed on the first electrode (21) and the second electrode (21), respectively.

[0114] A plurality of layers of light-emitting elements (ED) may be arranged in a direction perpendicular to the upper surface of the first substrate (11) or the first flattening layer (19). The light-emitting elements (ED) of the display device (10) are arranged such that one extended direction is parallel to the first flattening layer (19), and a plurality of semiconductor layers included in the light-emitting elements (ED) may be arranged sequentially along a direction parallel to the upper surface of the first flattening layer (19). However, this is not limited thereto. In some cases, when the light-emitting elements (ED) have a different structure, a plurality of layers may be arranged in a direction perpendicular to the first flattening layer (19).

[0115] Additionally, both ends of the light-emitting element (ED) may each come into contact with contact electrodes (26, 27). According to one embodiment, since the insulating film (78) is not formed on the extended one-way end surface of the light-emitting element (ED) and a portion of the semiconductor layer is exposed, the exposed semiconductor layer may come into contact with the contact electrodes (26, 27). However, this is not limited thereto. In some cases, at least a portion of the insulating film (78) of the light-emitting element (ED) may be removed, and the insulating film (78) may be removed so that the sides of both ends of the semiconductor layers are partially exposed. The sides of the exposed semiconductor layer may come into direct contact with the contact electrodes (26, 27).

[0116] The second insulating layer (52) may be partially disposed on the light-emitting element (ED). For example, the second insulating layer (52) is disposed to partially wrap the outer surface of the light-emitting element (ED) so as not to cover one end and the other end of the light-emitting element (ED). The contact electrodes (26, 27) described later may come into contact with both ends of the light-emitting element (ED) that are not covered by the second insulating layer (52). The portion of the second insulating layer (52) disposed on the light-emitting element (ED) may be disposed to extend in a second direction (DR2) on the planar first insulating layer (51) to form a linear or island pattern within each subpixel (PXn). The second insulating layer (52) can protect the light-emitting element (ED) and, at the same time, fix the light-emitting element (ED) during the manufacturing process of the display device (10).

[0117] A plurality of contact electrodes (26, 27) and a third insulating layer (53) may be disposed on the second insulating layer (52).

[0118] A plurality of contact electrodes (26, 27) may have a shape that extends in one direction. The first contact electrode (26) and the second contact electrode (27) of the contact electrodes (26, 27) may each be placed on a part of the first electrode (21) and the second electrode (21). The first contact electrode (26) is placed on the first electrode (21), and the second contact electrode (27) is placed on the second electrode (21), and the first contact electrode (26) and the second contact electrode (27) may each have a shape that extends in the second direction (DR2). The first contact electrode (26) and the second contact electrode (27) may be spaced apart from each other in the first direction (DR1), and they may form a stripe-shaped pattern within the light-emitting region (EMA) of each subpixel (PXn).

[0119] In some embodiments, the width of the first contact electrode (26) and the second contact electrode (27) measured in one direction may be equal to or smaller than the width of the first electrode (21) and the second electrode (21) measured in one direction, respectively.

[0120] The first contact electrode (26) and the second contact electrode (27) can each contact one end and the other end of the light-emitting element (ED).

[0121] Either one of the first contact electrode (26) and the second contact electrode (27) may be electrically connected to the anode electrode of the light-emitting element (ED), and the other may be electrically connected to the cathode electrode of the light-emitting element (ED). However, this is not limited thereto, and the opposite may also be true.

[0122] In the drawing, a first contact electrode (26) and a second contact electrode (27) are shown disposed in one subpixel (PXn), but are not limited thereto. The number of first contact electrodes (26) and second contact electrodes (27) may vary depending on the number of first electrodes (21) and second electrodes (21) disposed in each subpixel (PXn).

[0123] A third insulating layer (53) is disposed on the first contact electrode (26). The third insulating layer (53) can electrically insulate the first contact electrode (26) and the second contact electrode (27) from each other. The third insulating layer (53) is disposed to cover the first contact electrode (26), but may not be disposed on the other end of the light-emitting element (ED) so that the light-emitting element (ED) can contact the second contact electrode (27). The third insulating layer (53) may partially contact the first contact electrode (26) and the second insulating layer (52) on the upper surface of the second insulating layer (52). The side of the third insulating layer (53) in the direction in which the second electrode (21) is disposed may be aligned with one side of the second insulating layer (52). Additionally, the third insulating layer (53) may also be disposed on a non-luminous region, for example, on the first insulating layer (51) disposed on the first flattening layer (19). However, it is not limited to this.

[0124] The second contact electrode (27) is disposed on the second electrode (21), the second insulating layer (52), and the third insulating layer (53). The second contact electrode (27) can be in contact with the other end of the light-emitting element (ED).

[0125] The second contact electrode (27) may partially contact the second insulating layer (52), the third insulating layer (53), and the light-emitting element (ED). The first contact electrode (26) and the second contact electrode (27) may be kept out of contact with each other by the second insulating layer (52) and the third insulating layer (53). However, this is not limited thereto, and the third insulating layer (53) may be omitted depending on the case.

[0126] The contact electrodes (26, 27) may include a conductive material. For example, they may include ITO, IZO, ITZO, aluminum (Al), etc. As an example, the contact electrodes (26, 27) may include a transparent conductive material, and light emitted from the light-emitting element (ED) may pass through the contact electrodes (26, 27) and proceed toward the electrodes (21). However, they are not limited thereto.

[0127] The fourth insulating layer (54) can be placed entirely on the first substrate (11). The fourth insulating layer (54) can function to protect the external environment of the members placed on the first substrate (11).

[0128] Each of the first insulating layer (51), the second insulating layer (52), the third insulating layer (53), and the fourth insulating layer (54) may include an inorganic insulating material or an organic insulating material. In an exemplary embodiment, the first insulating layer (51), the second insulating layer (52), the third insulating layer (53), and the fourth insulating layer (54) may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. Alternatively, these may include, as organic insulating materials, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, cardo resin, siloxane resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate, polymethyl methacrylate-polycarbonate synthetic resin, etc. However, they are not limited thereto.

[0129] Meanwhile, the first electrode (21) and the second electrode (21) can transmit a driving signal to a light-emitting element (ED) during the operation of the display device (10) so that the light-emitting element (ED) can emit light. During the operation of the display device (10) or in a driving mode, the first electrode (21) receives a first power supply voltage through the first transistor (T1), and the second electrode (21) receives a second power supply voltage through the second voltage wiring (VSL). Additionally, a data signal is applied to the first gate electrode (G1) of the first transistor (T1) through the second transistor (T2), and an initialization voltage can be transmitted to the first source electrode (S1) or the first electrode (21) through the third transistor (T3).

[0130] FIG. 9 is a schematic cross-sectional view showing a part of a display device according to another embodiment.

[0131] Referring to FIG. 9, the display device (10) may omit the third insulating layer (53). A portion of the second contact electrode (27) may be placed directly on the second insulating layer (52), and the first contact electrode (26) and the second contact electrode (27) may be spaced apart from each other on the second insulating layer (52). According to one embodiment, even if the third insulating layer (53) is omitted, the second insulating layer (52) may perform the function of fixing the light-emitting element (ED) by including an organic insulating material. Additionally, the first contact electrode (26) and the second contact electrode (27) may be formed simultaneously through a patterning process. The embodiment of FIG. 9 is identical to the embodiment of FIG. 8 except that the third insulating layer (53) is further omitted. Redundant descriptions below will be omitted.

[0132] FIG. 10 is a schematic diagram of a light-emitting element according to one embodiment.

[0133] The light-emitting element (ED) may be a light-emitting diode, and specifically, the light-emitting element (ED) may be an inorganic light-emitting diode made of inorganic material having a size in the micrometer or nanometer range. The inorganic light-emitting diode can be aligned between two electrodes where polarity is formed when an electric field is formed in a specific direction between two electrodes facing each other. The light-emitting element (ED) can be aligned between the electrodes by the electric field formed on the two electrodes.

[0134] A light-emitting element (ED) according to one embodiment may have a shape that extends in one direction. The light-emitting element (ED) may have a shape such as a rod, wire, or tube. In an exemplary embodiment, the light-emitting element (ED) may be cylindrical or rod-shaped. However, the shape of the light-emitting element (ED) is not limited thereto, and the light-emitting element (ED) may have various shapes, such as a polygonal prism shape like a cube, a rectangular prism, or a hexagonal prism, or a shape that extends in one direction with a partially inclined outer surface. A plurality of semiconductors included in the light-emitting element (ED) described below may have a structure in which they are sequentially arranged or stacked along the one direction.

[0135] The light-emitting element (ED) may include a semiconductor layer doped with any type of conductivity impurity (e.g., p-type or n-type). The semiconductor layer can emit light of a specific wavelength range when an electrical signal applied from an external power source is transmitted.

[0136] Referring to FIG. 10, the light-emitting element (ED) may include a first semiconductor layer (71), a second semiconductor layer (72), a light-emitting layer (76), an electrode layer (77), and an insulating film (78).

[0137] The first semiconductor layer (71) may be an n-type semiconductor. For example, when the light-emitting device (ED) emits light in the blue wavelength range, the first semiconductor layer (71) may include a semiconductor material having the chemical formula AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, it may be one or more of n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer (71) may be doped with an n-type dopant, and for example, the n-type dopant may be Si, Ge, Sn, etc. In an exemplary embodiment, the first semiconductor layer (71) may be n-GaN doped with n-type Si. The length of the first semiconductor layer (71) may be in the range of 1.5 μm to 5 μm, but is not limited thereto.

[0138] The second semiconductor layer (72) is disposed on the light-emitting layer (76) described later. The second semiconductor layer (72) may be a p-type semiconductor, and for example, when the light-emitting element (ED) emits light in the blue or green wavelength range, the second semiconductor layer (72) may include a semiconductor material having the chemical formula AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, it may be one or more of p-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer (72) may be doped with a p-type dopant, and for example, the p-type dopant may be Mg, Zn, Ca, Se, Ba, etc. In an exemplary embodiment, the second semiconductor layer (72) may be p-GaN doped with p-type Mg. The length of the second semiconductor layer (72) may be in the range of 0.05㎛ to 0.10㎛, but is not limited thereto.

[0139] Meanwhile, the drawing shows the first semiconductor layer (71) and the second semiconductor layer (72) as being composed of a single layer, but is not limited thereto. According to some embodiments, depending on the material of the light-emitting layer (76), the first semiconductor layer (71) and the second semiconductor layer (72) may further include a greater number of layers, such as a clad layer or a TSBR (Tensile strain barrier reducing) layer.

[0140] The light-emitting layer (76) is disposed between the first semiconductor layer (71) and the second semiconductor layer (72). The light-emitting layer (76) may include a material having a single or multiple quantum well structure. If the light-emitting layer (76) includes a material having a multiple quantum well structure, it may have a structure in which a quantum layer and a well layer are alternately stacked in multiple layers. The light-emitting layer (76) may emit light through the coupling of electron-hole pairs according to an electrical signal applied through the first semiconductor layer (71) and the second semiconductor layer (72). For example, if the light-emitting layer (76) emits light in the blue wavelength range, it may include a material such as AlGaN or AlGaInN. In particular, if the light-emitting layer (76) has a structure in which a quantum layer and a well layer are alternately stacked in a multiple quantum well structure, the quantum layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN or AlInN. In an exemplary embodiment, the light-emitting layer (76) may include AlGaInN as the quantum layer and AlInN as the well layer, and the light-emitting layer (76) may emit blue light having a central wavelength band in the range of 450 nm to 495 nm.

[0141] However, it is not limited thereto, and the light-emitting layer (76) may have a structure in which semiconductor materials with a large band gap energy and semiconductor materials with a small band gap energy are alternately stacked, or it may include different Group 3 to Group 5 semiconductor materials depending on the wavelength range of the emitted light. The light emitted by the light-emitting layer (76) is not limited to light in the blue wavelength range, and may emit light in the red or green wavelength range depending on the case. The length of the light-emitting layer (76) may have a range of 0.05㎛ to 0.10㎛, but is not limited thereto.

[0142] Meanwhile, light emitted from the light-emitting layer (76) can be emitted not only to the outer surface in the longitudinal direction of the light-emitting element (ED), but also to both sides. The light emitted from the light-emitting layer (76) is not limited to a single direction.

[0143] The electrode layer (77) may be an ohmic contact electrode. However, it is not limited thereto and may be a Schottky contact electrode. The light-emitting element (ED) may include at least one electrode layer (77). FIG. 11 illustrates the light-emitting element (ED) including one electrode layer (77), but it is not limited thereto. Depending on the case, the light-emitting element (ED) may include a larger number of electrode layers (77) or may omit them. The description of the light-emitting element (ED) described below can be applied equally even if the number of electrode layers (77) changes or other structures are included.

[0144] The electrode layer (77) can reduce the resistance between the light-emitting element (ED) and the electrode or contact electrode when the light-emitting element (ED) is electrically connected to the electrode or contact electrode in a display device (10) according to one embodiment. The electrode layer (77) may include a conductive metal. For example, the electrode layer (77) may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and ITZO (Indium Tin-Zinc Oxide). Additionally, the electrode layer (77) may include an n-type or p-type doped semiconductor material. The electrode layer (77) may include the same material, different materials, and is not limited thereto.

[0145] An insulating film (78) is arranged to surround the outer surface of a plurality of semiconductor layers and electrode layers. In an exemplary embodiment, the insulating film (78) is arranged to surround the outer surface of at least the light-emitting layer (76) and may extend in one direction in which the light-emitting element (ED) is extended. The insulating film (78) may perform the function of protecting the members. For example, the insulating film (78) may be formed to surround the side portions of the members, but the longitudinal ends of the light-emitting element (ED) may be formed to be exposed.

[0146] In the drawing, the insulating film (78) is shown extending in the longitudinal direction of the light-emitting element (ED) to cover from the first semiconductor layer (71) to the side of the electrode layer (77), but is not limited thereto. The insulating film (78) may cover only the outer surface of a portion of the semiconductor layer, including the light-emitting layer (76), or cover only a portion of the outer surface of the electrode layer (77), so that the outer surface of each electrode layer (77) is partially exposed. Additionally, the insulating film (78) may be formed with a rounded upper surface in cross-section in an area adjacent to at least one end of the light-emitting element (ED).

[0147] The thickness of the insulating film (78) may be in the range of 10 nm to 1.0 μm, but is not limited thereto. Preferably, the thickness of the insulating film (78) may be around 40 nm.

[0148] The insulating film (78) may include materials having insulating properties, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlN), aluminum oxide (Al2O3), etc. Accordingly, it is possible to prevent an electrical short circuit that may occur when the light-emitting layer (76) comes into direct contact with the electrode through which an electrical signal is transmitted to the light-emitting element (ED). In addition, since the insulating film (78) protects the outer surface of the light-emitting element (ED) including the light-emitting layer (76), it is possible to prevent a decrease in light-emitting efficiency.

[0149] Additionally, in some embodiments, the outer surface of the insulating film (78) may be surface-treated. The light-emitting element (ED) may be sprayed onto the electrode and aligned in a dispersed state within a predetermined ink. Here, in order for the light-emitting element (ED) to remain dispersed without aggregating with other adjacent light-emitting elements (ED) within the ink, the surface of the insulating film (78) may be treated to be hydrophobic or hydrophilic.

[0150] The light-emitting element (ED) may have a length (h) ranging from 1 μm to 10 μm or from 2 μm to 6 μm, and preferably from 3 μm to 5 μm. Additionally, the diameter of the light-emitting element (ED) may range from 30 nm to 700 nm, and the aspect ratio of the light-emitting element (ED) may range from 1.2 to 100. However, not limited thereto, a plurality of light-emitting elements (ED) included in the display device (10) may have different diameters depending on the difference in the composition of the light-emitting layer (76). Preferably, the diameter of the light-emitting element (ED) may range from approximately 500 nm.

[0151] Hereinafter, a manufacturing process of a display device (10) according to one embodiment will be described. The manufacturing process of the display device (10) will be described with reference to FIGS. 1 to 8. Furthermore, detailed descriptions of parts already described in FIGS. 1 to 8 will be omitted.

[0152] A method for manufacturing a display device (10) according to one embodiment comprises: a first substrate (11); a semiconductor layer disposed on the first substrate (11) and comprising a plurality of active layers (ACT); a first gate conductive layer disposed on the semiconductor layer and comprising a scan line (SCL) and a sensing line (SSL) extended in a first direction (DR1), a plurality of gate electrodes (G1, G2, G3) disposed to partially overlap with the semiconductor layer and a first capacitance electrode (CSE1); a first data conductive layer disposed on the first gate conductive layer and comprising a data line (DTL), a first electrode and other electrodes of a plurality of transistors (T1, T2, T3), and a second capacitance electrode (CSE2) that overlaps with the first capacitance electrode (CSE1); and a second data conductive layer disposed on the first data conductive layer and comprising a first voltage line (VDL) to which a first power supply voltage is applied, and a second voltage line (VSL) to which a second power supply voltage is applied. The method may include the step of preparing a target substrate comprising a first electrode (21) disposed on the second data conductive layer and extended in a second direction (DR2), and a second electrode (21) spaced apart from the first electrode (21) and extended in a second direction (DR2); and the step of aligning a plurality of light-emitting elements (ED) such that both ends are disposed on the first electrode (21) and the second electrode (21) of the target substrate, respectively.

[0153] A first capacitance electrode (CSE1) and a second capacitance electrode (CSE2) constitute a storage capacitor, and the second capacitance electrode (CSE2) completely overlaps with a plurality of light-emitting elements (ED) in the thickness direction and partially overlaps with the first electrode (21) and the second electrode (21), and in the step of aligning the plurality of light-emitting elements (ED), a first alignment voltage is applied to the second capacitance electrode (CSE2), and a second alignment voltage different from the first alignment voltage can be applied to each electrode (21).

[0154] Other embodiments of the display device are described below.

[0155] FIG. 11 is a schematic plan view showing a plurality of electrodes and banks included in one pixel of a display device according to another embodiment.

[0156] Referring to FIG. 11, the display device according to the present embodiment is different from the display device according to FIG. 7 in that it additionally includes a third electrode (21) between the first electrode (21) and the second electrode (21) on a planar surface.

[0157] More specifically, the third electrode (21) extends in the second direction (DR2), and each electrode (21) may be arranged to be spaced apart from each other in the first direction (DR1). Although not illustrated, the third electrode (21) may also overlap with the portion of the second bank (45) extended in the first direction (DR1), and an electrode contact hole (CTS) may be formed in the area where the third electrode (21) and the second bank (45) overlap. In the manufacturing mode of the display device, the third electrode (210) may be connected to the second voltage wiring (VSL) through the electrode contact hole (CTS). The third electrode (21) may include a highly reflective conductive material. For example, the third electrode (21) may include a metal such as silver (Ag), copper (Cu), or aluminum (Al) as a highly reflective material, or an alloy including aluminum (Al), nickel (Ni), or lanthanum (La). The third electrode (21) can reflect light emitted from the light-emitting element (ED) and traveling toward the side of the first bank (BNL1) toward the upper direction of each subpixel (PXn). However, the third electrode (21) may further include a transparent conductive material, not limited thereto. For example, each electrode (21) may include a material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin-Zinc Oxide), etc. In some embodiments, the third electrode (21) may have a structure in which a transparent conductive material and a metal layer with high reflectivity are each stacked one or more times, or may be formed as a single layer including these. For example, the third electrode (21) may have a stacked structure such as ITO / Silver (Ag) / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0158] The third electrode (21) may be utilized to form an electric field within the subpixel (PXn) to align the light-emitting element (ED). The light-emitting element (ED) may be positioned between the first electrode (21) and the second electrode (21) and between the second electrode (21) and the third electrode (21) by the electric field formed between the first electrode (21) to the third electrode (21) and the lower second capacitive electrode (CSE2).

[0159] In the case of a display device according to the present embodiment, in the manufacturing mode of the display device, a first alignment signal (or a first alignment voltage) is applied to the second capacitive electrode (CES2) and a second alignment signal (or a second alignment voltage) is applied to the electrodes (21), and by forming a predetermined electric field between the second capacitive electrode (CES2) and the electrodes (21) through the first alignment signal and the second alignment signal to align the light-emitting elements (ED), it is possible to prevent a parasitic electric field from being formed between the first electrode and / or the second electrode by other conductive layers located below the first electrode and the second electrode.

[0160] FIG. 12 is a schematic plan view showing a plurality of electrodes and banks included in one pixel of a display device according to another embodiment.

[0161] Referring to FIG. 12, the display device according to the present embodiment differs from the display device according to FIG. 11 in that the third electrode (21) is composed of a plurality of patterns. More specifically, the third electrode (21) may be composed of three plurality of patterns. Each of the patterns extends along the second direction (DR2) and may be spaced apart from each other in the first direction (DR1).

[0162] In the case of the display device according to the present embodiment, in the manufacturing mode of the display device, a first alignment signal (or a first alignment voltage) is applied to the second capacitive electrode (CES2) and a second alignment signal (or a second alignment voltage) is applied to the electrodes (21), and by forming a predetermined electric field between the second capacitive electrode (CES2) and the electrodes (21) through the first alignment signal and the second alignment signal to align the light-emitting elements (ED), it is possible to prevent a parasitic electric field from being formed between the first electrode and / or the second electrode by other conductive layers located below the first electrode and the second electrode.

[0163] FIG. 13 is a schematic plan view showing a plurality of electrodes and banks included in one pixel of a display device according to another embodiment.

[0164] Referring to FIG. 13, the display device according to the present embodiment differs from the display device according to FIG. 12 in that the third electrode (21) is composed of four patterns. More specifically, the third electrode (21) may be composed of four multiple patterns. Each of the patterns extends along the second direction (DR2) and may be spaced apart from each other in the first direction (DR1).

[0165] In the case of the display device according to the present embodiment, in the manufacturing mode of the display device, a first alignment signal (or a first alignment voltage) is applied to the second capacitive electrode (CES2) and a second alignment signal (or a second alignment voltage) is applied to the electrodes (21), and by forming a predetermined electric field between the second capacitive electrode (CES2) and the electrodes (21) through the first alignment signal and the second alignment signal to align the light-emitting elements (ED), it is possible to prevent a parasitic electric field from being formed between the first electrode and / or the second electrode by other conductive layers located below the first electrode and the second electrode.

[0166] FIG. 14 is a schematic cross-sectional view showing a part of a display device according to another embodiment.

[0167] Referring to FIG. 14, the light-emitting elements (30) of the display device according to the present embodiment differ from the display device according to FIG. 8 in that they do not overlap with the lower second electrodes (21). More specifically, one end of the light-emitting element (30) may be spaced apart in a plane without overlapping with the lower second electrode (21), and the other end of the light-emitting element (30) may be spaced apart in a plane without overlapping with the lower second electrode (21).

[0168] Other explanations are detailed in Fig. 8, so redundant explanations below will be omitted.

[0169] FIG. 15 is a schematic cross-sectional view showing a part of a display device according to another embodiment.

[0170] Referring to FIG. 15, the light-emitting elements (30) of the display device according to the present embodiment differ from the display device according to FIG. 8 in that they do not overlap with the lower second electrodes (21). More specifically, one end of the light-emitting element (30) may be spaced apart in a plane without overlapping with the lower second electrode (21), and the other end of the light-emitting element (30) may be spaced apart in a plane without overlapping with the lower second electrode (21).

[0171] Other explanations are detailed in Fig. 9, so redundant explanations below will be omitted.

[0172] FIG. 16 is a schematic plan view showing a plurality of electrodes and light-emitting elements included in one pixel of a display device according to another embodiment. FIG. 17 is a cross-sectional view taken along the lines Q4-Q4', Q5-Q5' and Q6-Q6' of FIG. 16.

[0173] Referring to FIGS. 16 and 17, the display device according to the present embodiment differs from the display device according to FIGS. 7 and 8 in that the contact electrodes (26_1, 27_1, 28) and light-emitting elements (EDa, EDb) are different. More specifically, the display device according to the present embodiment may include contact electrodes (26_1, 27_1, 28) and light-emitting elements (EDa, EDb). The first contact electrode (26_1) may overlap with the second electrode (21) on the other side of the first direction (DR1). The second contact electrode (27_1) may overlap with the second electrode (21) on one side of the first direction (DR1). The first contact electrode (26_1) may include a first-1 extension extending along a second direction (DR2), a first-2 extension extending by being bent from the first-1 extension toward the first direction (DR1), and a first-3 extension extending by being bent again toward the other side of the second direction (DR2) from the first-2 extension.

[0174] As shown in FIG. 22, the other end of the second direction (DR2) of the first-1 extension may overlap with the second electrode (21) of the other side of the first direction (DR1) and be connected to the second voltage wiring (VSL) through the electrode contact hole (CTS). In this embodiment, the other end of the second direction (DR2) of the first-1 extension is illustrated as being connected to the second voltage wiring (VSL), but is not limited thereto and other parts of the first-1 extension may be connected to the second voltage wiring (VSL).

[0175] As illustrated in FIG. 22, one end of the second direction (DR2) of the second contact electrode (27_1) may overlap with the first voltage line (VDL) and be connected to the first voltage line (VDL) through an electrode contact hole (CTA). In this embodiment, although the second end of the second direction (DR2) of the second contact electrode (27_1) is illustrated as overlapping with the first voltage line (VDL) and being connected to the first voltage line (VDL) through an electrode contact hole (CTA), it is not limited thereto and other parts of the second contact electrode (27_1) may overlap with the first voltage line (VDL) and be connected to the first voltage line (VDL) through an electrode contact hole (CTA).

[0176] The third contact electrode (28) may include a third-1 extension extending along the second direction (DR2), a third-2 extension extending by being bent from the third-1 extension toward the first direction (DR1), and a third-3 extension extending by being bent from the third-2 extension toward the second direction (DR2). The third-1 extension may be positioned in a planar manner between the first-1 extension and the first-3 extension, and the third-3 extension may be positioned in a planar manner between the first-3 extension and the second contact electrode (27_1).

[0177] The light-emitting elements (EDa, EDb) may include a first light-emitting element (EDa) disposed between the third-1 extension and the first-3 extension on a plane, and a second light-emitting element (EDb) disposed between the third-3 extension and the second contact electrode (27_1) on a plane. Each light-emitting element (EDa, EDb) may be arranged along a second direction (DR2).

[0178] FIG. 18 is a schematic plan view showing a plurality of electrodes and light-emitting elements included in a pixel of a display device according to another embodiment. FIG. 18 illustrates a plurality of electrodes and light-emitting elements arranged in one subpixel of a pixel.

[0179] Referring to FIG. 18, the second electrodes (21) of the display device according to the present embodiment differ from the display device according to FIG. 16 in that they further include four second electrodes (21) extended along a second direction (DR2) and a second electrode (21) connected to the four second electrodes (21) and extended along a first direction (DR1) in one subpixel.

[0180] More specifically, the second electrodes (21) of the display device according to the present embodiment may include four second electrodes (21) extended along a second direction (DR2) and a second electrode (21) extended along a first direction (DR1) connected to the four second electrodes (21) in one subpixel. Although the second electrode (21) extended along the first direction (DR1) has been exemplified as being connected to one end of the second direction (DR2) of each second electrode (21) extended along the second direction (DR2), it is not limited thereto and may be connected to the other end of the second direction (DR2) of each second electrode (21) extended along the second direction (DR2). Hereinafter, the second electrodes (21) extended along the second direction (DR2) are referred to as the second-1 electrode, the second-2 electrode, the second-3 electrode, and the second-4 electrode from the other side of the first direction (DR1), and the second electrode (21) connected to one end of the second direction (DR2) of the second electrodes (21) extended along the second direction (DR2) is referred to as the second-5 electrode.

[0181] The display device according to the present embodiment may include a plurality of contact electrodes (26_2, 27_2, 28_1, 29). The first contact electrode (26_2) overlaps with the second-1 electrode, the second-2 electrode, and the second-5 electrode, and the first-1 extension may overlap with the second-1 electrode, the first-2 extension may overlap with the second-5 electrode, and the first-3 extension may overlap with the second-2 electrode. The first-1 extension may be connected to a first voltage wiring (see VDL in FIG. 17) through an electrode contact hole (CTA).

[0182] The second contact electrode (27_2) may include a second-1 extension extending along a second direction (DR2), a second-2 extension extending along a first direction (DR1) by being bent from the second-1 extension, a second-3 extension extending along a second direction (DR2) by being bent from the second-2 extension, a second-4 extension extending along a first direction (DR1) by being bent from the second-3 extension, and a second-5 extension extending along a second direction (DR2) by being bent from the second-4 extension to a second direction (DR2). The above 2-1 extension portion is positioned in a planar manner between the 2-2 electrode and the 2-3 electrode, and one end of the 2-2 extension portion in the first direction (DR1) overlaps with the 2-3 electrode, the 2-3 extension portion overlaps with the 2-3 electrode, the 2-4 extension portion overlaps with the 2-5 electrode, and the 2-5 extension portion overlaps with the 2-4 electrode. The 2-5 extension portion is connected to the 2-4 electrode, and the 2-4 electrode can be connected to the second voltage wiring (see VSL in FIG. 17) through the electrode contact hole (CTS).

[0183] The third-1 extension of the third contact electrode (28_1) is positioned between the second-1 electrode and the second-2 electrode, and one end of the third-2 extension in the first direction (DR1) overlaps with the second-2 electrode, and the third-3 extension may overlap with the second-2 electrode. Meanwhile, the third contact electrode (28_1) may further include a third-4 extension that is bent in the first direction (DR1) from the third-3 extension and extends along the first direction (DR1), and a third-5 extension that is bent in the second direction (DR2) from the third-4 extension and extends along the second direction (DR2). The third-4 extension may overlap with the second-5 electrode, and the third-5 extension may overlap with the second-3 electrode.

[0184] The fourth contact electrode (29) may include a fourth-1 extension extending along a second direction (DR2), and a fourth-2 extension bent from the fourth-1 extension toward a first direction (DR1) and extending along the first direction (DR1). The fourth-1 extension is positioned in a planar manner between the second-3 electrode and the second-4 electrode, and one end of the fourth-2 extension in the first direction (DR1) may overlap with the second-4 electrode.

[0185] The light-emitting elements (EDa, EDb) may include first light-emitting elements (EDa) respectively disposed between the first-1 extension and the third-1 extension, between the second-1 extension and the third-5 extension, and between the second-3 extension and the fourth-1 extension, and second light-emitting elements (EDb) respectively disposed between the third-1 extension and the first-3 extension, between the third-3 extension and the second-1 extension, and between the fourth-1 extension and the second-5 extension. Each light-emitting element (EDa, EDb) may be arranged along a second direction (DR2).

[0186] FIG. 19 is a schematic plan view showing a plurality of electrodes and light-emitting elements included in one pixel of a display device according to another embodiment.

[0187] Referring to FIG. 19, the second electrode (21) of the display device according to the present embodiment is different from the display device according to FIG. 18 in that it further includes a second-sixth electrode spaced apart from the second-fourth electrode and the first direction (DR1), and further includes a fifth contact electrode (30).

[0188] More specifically, the 2-3 electrode and the 2-6 electrode may be spaced apart with the 2-4 electrode in between. The other end of the 2-6 electrode in the second direction (DR2) may be connected to the 2-5 electrode. The 4th contact electrode (29_1) may further include a 4-3 extension that is bent in the second direction (DR2) from the 4-2 extension and extends along the second direction (DR2), a 4-4 extension that is bent in the first direction (DR1) from the 4-3 extension and extends along the first direction (DR1), and a 4-5 extension that is bent in the second direction (DR2) from the 4-4 extension and extends along the second direction (DR2). The 4-3 extension may overlap with the 2-4 electrode, the 4-4 extension may overlap with the 2-5 electrode, and the 4-5 extension may overlap with the 2-6 electrode. The fifth contact electrode (30) includes a fifth-1 extension extending along a second direction (DR2), and a fifth-2 extension bent from the fifth-1 extension in a first direction (DR1) and extending along the first direction (DR1), wherein the fifth-1 extension is positioned between the fourth-3 extension and the fourth-5 extension in a planar manner, and one end of the fifth-2 extension in the first direction (DR1) may overlap with the second-6 electrode.

[0189] Furthermore, unlike in FIG. 18, the 2-5 extension of the second contact electrode (27_2) is not extended to the second voltage wiring (VSL) through the electrode contact hole (CTS), and the 5-2 extension of the fifth contact electrode (30) is connected to the 2-6 electrode, and the 2-6 electrode can be connected to the second voltage wiring (VSL) through the electrode contact hole (CTS).

[0190] The first light-emitting elements (EDa) may be further disposed between the 5-1 extension and the 4-5 extension, and the second light-emitting elements (EDb) may be further disposed between the 4-3 extension and the 5-1 extension.

[0191] Other explanations are described in detail in Fig. 18, so further detailed explanations below will be omitted.

[0192] FIG. 20 is a schematic plan view showing a plurality of electrodes and light-emitting elements included in one pixel of a display device according to another embodiment.

[0193] Referring to FIG. 20, the display device according to the present embodiment is different from the display device according to FIG. 18 in that the second electrode (21) does not include the second-4 electrode, and the second electrode (27_3) includes only the second-1 extension and the second-2 extension.

[0194] The above 2-2 extension is connected to the above 2-3 electrode, and the above 2-3 electrode can be connected to the second voltage wiring (see VSL in FIG. 17) through the electrode contact hole (CTS).

[0195] Other explanations are described in detail in Fig. 18, so further detailed explanations below will be omitted.

[0196] FIG. 21 is a schematic plan view showing a plurality of electrodes and light-emitting elements included in one pixel of a display device according to another embodiment.

[0197] Referring to FIG. 21, the display device according to the present embodiment differs from the display device according to FIG. 19 and FIG. 20 in that the first contact electrode (26_3) includes only the first-1 extension, and the third contact electrode (28_2) includes only the third-1 extension, the third-2 extension, and the third-3 extension. More specifically, the display device according to the present embodiment, like the display device of FIG. 20, may have the second electrode (21) include only the second-1 to second-4 electrodes. The display device according to the present embodiment may further include sixth and seventh contact electrodes (31, 32). The 6th contact electrode (31) may include a 6-1 extension extending along the 2nd direction (DR2), a 6-2 extension extending along the 1st direction (DR1) and bent from the 6-1 extension, and a 6-3 extension extending along the 2nd direction (DR2) and bent from the 6-2 extension, and the 7th contact electrode (32) may include a 7-1 extension extending along the 2nd direction (DR2), a 7-2 extension extending along the 1st direction (DR1) and bent from the 7-1 extension, and a 7-3 extension extending along the 2nd direction (DR2) and bent from the 7-2 extension. The 6-1 extension portion may be disposed in a planar position between the 3-1 extension portion and the 3-3 extension portion, the 6-2 extension portion may overlap with the 2-5 electrode, the 6-3 extension portion may overlap with the 2-2 electrode, and the 6-3 extension portion may be disposed in a planar position between the 3-3 extension portion and the 7-1 extension portion. The 7-1 extension portion may be disposed in a planar position between the 6-3 extension portion and the 5-1 extension portion, the 7-2 extension portion may overlap with the 2-5 electrode, and the 7-3 extension portion may overlap with the 2-3 electrode.The above 5-1 extension is positioned between the 2-2 electrode and the 2-3 electrode, and one end of the 5-2 extension in the first direction (DR1) overlaps with the 2-3 electrode, and one end of the 5-2 extension in the first direction (DR1) is connected to the 2-3 electrode, and the 2-3 electrode can be connected to the second voltage wiring (VSL in FIG. 17) through the electrode contact hole (CTS).

[0198] First light-emitting elements (EDa) may be positioned between the first contact electrode (26_3) and the third-1 extension, between the sixth-1 extension and the third-3 extension, and between the fifth-1 extension and the seventh-3 extension, and second light-emitting elements (EDb) may be positioned between the third-3 extension and the sixth-3 extension. Each light-emitting element (EDa, EDb) may be arranged along the second direction (DR2).

[0199] Other explanations are described in detail in FIGS. 19 and FIGS. 20, so further detailed explanations will be omitted below.

[0200] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0201] 10: Display device 21: First electrode 26: First contact electrode 27: Second contact electrode 28: Third contact electrode 30: Light-emitting element 40: 1st Bank 45: Second Bank 41: 1st Sub Bank 42: 2nd sub-bank 51: First insulating layer 52: Second insulating layer 53: Third insulating layer 54: 4th insulating layer

Claims

Claim 1 A first substrate; a semiconductor layer disposed on the first substrate and comprising a plurality of active layers; a first gate conductive layer disposed on the semiconductor layer and comprising a scan line and a sensing line extending in a first direction, a plurality of gate electrodes disposed to partially overlap with the semiconductor layer, and a first capacitance electrode; a first data conductive layer disposed on the first gate conductive layer and comprising a data line, one electrode and another electrode of a plurality of transistors, and a second capacitance electrode that overlaps with the first capacitance electrode; a second data conductive layer disposed on the first data conductive layer and comprising a first voltage line to which a first power supply voltage is applied, and a second voltage line to which a second power supply voltage is applied; a first electrode disposed on the second data conductive layer and extending in a second direction intersecting the first direction, and a second electrode spaced apart from the first electrode and extending in the second direction; A display device comprising a plurality of light-emitting elements disposed on the first electrode and the second electrode, each having both ends, wherein the first capacitance electrode and the second capacitance electrode constitute a storage capacitor, wherein the second capacitance electrode completely overlaps the plurality of light-emitting elements in the thickness direction and partially overlaps the first electrode and the second electrode, and wherein, in a manufacturing mode of the display device, a first alignment voltage is applied to the second capacitance electrode. Claim 2 In claim 1, the transistor comprises a first transistor, and the first transistor is a display device in which one electrode is electrically connected to one end of each of the plurality of light-emitting elements and the other electrode is electrically connected to the first voltage wiring. Claim 3 In claim 2, the storage capacitor is a display device electrically connected to the gate electrode and one electrode of the first transistor. Claim 4 A display device according to claim 3, wherein the first capacitance electrode is connected to the gate electrode of the first transistor and the second capacitance electrode is connected to one electrode of the first transistor, so that the first alignment voltage is applied. Claim 5 In claim 3, the transistor further comprises a second transistor, and the second transistor is a display device in which one electrode is connected to the gate electrode of the first transistor and the other electrode is electrically connected to the data line. Claim 6 A display device according to claim 5, further comprising: a scan line to which a scan signal is applied and which is electrically connected to the gate electrode of the second transistor; and a sensing line to which a sensing signal is applied. Claim 7 In claim 6, the display device further comprises an initial voltage wiring that extends in the second direction and applies an initial voltage to the first data conductive layer. Claim 8 In claim 7, the transistor further comprises a third transistor, wherein the third transistor has a gate electrode electrically connected to the sensing line, one electrode electrically connected to one end of each of the plurality of light-emitting elements, and another electrode connected to the initialization voltage wiring, forming a display device. Claim 9 A display device according to claim 4, wherein, in the manufacturing mode, a second alignment voltage is applied to the first electrode and the second electrode. Claim 10 In claim 9, in the above manufacturing mode, the first electrode is a display device connected to the second voltage wiring. Claim 11 In claim 10, in the above manufacturing mode, the second electrode is a display device connected to the second voltage wiring. Claim 12 A display device according to claim 11, further comprising a first interlayer insulating layer between the first data conductive layer and the second data conductive layer, and a first flattening layer disposed between the second data conductive layer and the first electrode and the second electrode. Claim 13 In claim 12, the first electrode and the second electrode are each connected to the second voltage wiring through a contact hole penetrating the first flattening layer, in a display device. Claim 14 A display device according to claim 9, further comprising a third electrode disposed on the same layer as the first electrode and extended in the second direction, wherein the planar third electrode is disposed between the first electrode and the second electrode, and in the manufacturing mode, the same alignment voltage as the first electrode is applied to the third electrode. Claim 15 In claim 14, the third electrode is a display device comprising a plurality of patterns spaced apart along the first direction. Claim 16 A step of preparing a target substrate comprising: a first substrate; a semiconductor layer disposed on the first substrate and including a plurality of active layers; a first gate conductive layer disposed on the semiconductor layer and including a scan line and a sensing line extending in a first direction, and a plurality of gate electrodes and a first capacitance electrode disposed to partially overlap with the semiconductor layer; a first data conductive layer disposed on the first gate conductive layer and including a data line, one electrode and another electrode of a plurality of transistors, and a second capacitance electrode that overlaps with the first capacitance electrode; a second data conductive layer disposed on the first data conductive layer and including a first voltage line to which a first power supply voltage is applied, and a second voltage line to which a second power supply voltage is applied; and a first electrode disposed on the second data conductive layer and extending in a second direction intersecting the first direction, and a second electrode spaced apart from the first electrode and extending in the second direction. A method for manufacturing a display device comprising the step of aligning a plurality of light-emitting elements such that both ends are respectively disposed on the first electrode and the second electrode of the target substrate, wherein the first capacitance electrode and the second capacitance electrode constitute a storage capacitor, the second capacitance electrode completely overlaps the plurality of light-emitting elements in the thickness direction and partially overlaps the first electrode and the second electrode, and in the step of aligning the plurality of light-emitting elements, a first alignment voltage is applied to the second capacitance electrode. Claim 17 A method for manufacturing a display device according to claim 16, wherein, in the alignment step, a second alignment voltage different from the first alignment voltage is applied to the first electrode and the second electrode. Claim 18 In claim 17, a method for manufacturing a display device in which, in the alignment step, the first electrode is connected to the second voltage wiring. Claim 19 In claim 18, a method for manufacturing a display device in which, in the alignment step, the second electrode is connected to the second voltage wiring. Claim 20 A method for manufacturing a display device according to claim 19, further comprising a third electrode disposed on the same layer as the first electrode and extended in the second direction, wherein the planar third electrode is disposed between the first electrode and the second electrode, and in the alignment step, the same alignment voltage as the first electrode is applied to the third electrode.

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