Semiconductor device including multi capping layer and method for manufacturing the same

Abstract

A semiconductor device according to the present disclosure comprises a substrate; a transistor connected to the substrate; and a wiring structure comprising contact wirings electrically connected to the transistor. The wiring structure further comprises a first wiring insulating film, a first material film in contact with the first wiring insulating film, a second material film in contact with the first material film, and a second wiring insulating film in contact with the second material film. The first material film comprises SiN, and the second material film comprises SiCN. The dielectric constant of the first wiring insulating film is greater than the dielectric constant of the second wiring insulating film.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. More specifically, the present disclosure relates to a semiconductor device comprising multiple capping films and a method for manufacturing the same. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements. As the electronics industry advances, demands regarding the characteristics of semiconductor devices are steadily increasing. For example, there is a growing demand for high reliability, high speed, and / or multifunctionality in semiconductor devices. To meet these requirements, the internal structures of semiconductor devices are becoming increasingly complex, and the devices are becoming more highly integrated. The problem to be solved

[0003] The objective of the present invention is to provide a semiconductor device with improved reliability. means of solving the problem

[0004] A semiconductor device according to some embodiments of the present disclosure comprises a substrate; a transistor connected to the substrate; and a wiring structure comprising contact wirings electrically connected to the transistor, wherein the wiring structure further comprises a first wiring insulating film, a first material film in contact with the first wiring insulating film, a second material film in contact with the first material film, and a second wiring insulating film in contact with the second material film, wherein the first material film comprises SiN and the second material film comprises SiCN, and the dielectric constant of the first wiring insulating film may be greater than the dielectric constant of the second wiring insulating film.

[0005] A semiconductor device according to some embodiments of the present disclosure comprises a substrate; an insulating film covering the substrate; a transistor provided between the substrate and the insulating film; and a wiring structure covering the insulating film, wherein the wiring structure comprises a first wiring insulating film, a first material film in contact with the first wiring insulating film, a second material film in contact with the first material film, and a second wiring insulating film in contact with the second material film, wherein the first material film comprises SiN, the second material film comprises SiCN, and the first and second wiring insulating films comprise an insulating material comprising carbon and oxygen, and the carbon concentration of the first wiring insulating film may be smaller than the carbon concentration of the second wiring insulating film.

[0006] A semiconductor device according to some embodiments of the present disclosure comprises a substrate; an insulating film covering the substrate; a transistor provided between the substrate and the insulating film; and a wiring structure covering the insulating film, wherein the wiring structure comprises a first wiring and a second wiring in contact with each other, a first wiring insulating film surrounding the first wiring, a second wiring insulating film surrounding the second wiring, and a multiple capping film interposed between the first and second wiring insulating films, wherein the dielectric constant of the first wiring insulating film is greater than the dielectric constant of the second wiring insulating film, and the multiple capping film may comprise a first material film and a second material film having different carbon concentrations. Effects of the invention

[0007] A semiconductor device according to the embodiments of the present disclosure may have improved reliability by including a multiple capping film comprising a plurality of material films. Brief explanation of the drawing

[0008] FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a graph illustrating the effects of a semiconductor device according to some embodiments of the present disclosure. FIGS. 3a, 3b, 3c, 3d, 3e, and 3f are cross-sectional views illustrating a method for manufacturing a semiconductor device according to FIG. 1. FIG. 4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 5 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 6 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 7 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. Specific details for implementing the invention

[0009] Preferred embodiments of the present invention are described below with reference to the attached drawings. Unless otherwise specifically stated, terms such as "top," "top surface," "bottom," "bottom surface," and "side surface" in this specification are based on the drawings and may actually vary depending on the direction in which the components are arranged. Additionally, ordinal numbers such as "first," "second," and "third" may be used as labels for specific elements, steps, directions, etc., to distinguish various elements, steps, directions, etc. from one another. Terms not described using "first," "second," etc. in the specification may still be referred to as "first" or "second" in the claims. Furthermore, terms referred to by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or another claim). Preferred embodiments of the present invention are described below with reference to the attached drawings. The following embodiments may be combined with one another unless otherwise stated. FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0010] Referring to FIG. 1, a semiconductor device may include a substrate (100). The substrate (100) may have the form of a plate extending along a plane defined by a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) may intersect each other. For example, the first direction (D1) and the second direction (D2) may be orthogonal to each other. In some embodiments, the substrate (100) may be a semiconductor substrate. For example, the substrate (100) may include silicon, germanium, silicon-germanium, GaP, or GaAs.

[0011] A substrate (100) may include a first surface (101) and a second surface (102) facing each other. The first surface (101) may be an active surface of the substrate (100). In the view according to FIG. 1, the first surface (101) may be an upper surface of the substrate (100), and the second surface (102) may be a lower surface of the substrate (100).

[0012] A first insulating film (110) covering a first surface (101) of a substrate (100) may be provided. The lower surface of the first insulating film (110) may be in contact with the first surface (101) of the substrate (100). The first insulating film (110) may include an insulating material. In some embodiments, the first insulating film (110) may be a multiple insulating film.

[0013] A second insulating film (120) covering a second surface (102) of a substrate (100) may be provided. The upper surface of the second insulating film (120) may be in contact with the second surface (102) of the substrate (100). The second insulating film (120) may include an insulating material. In some embodiments, the second insulating film (120) may be a multiple insulating film.

[0014] A transistor (TR) may be provided between the substrate (100) and the first insulating film (110). For example, the transistor (TR) may be a cell transistor or a peripheral transistor constituting a memory element, a logic element, or an image sensor element. The transistor (TR) may be covered by the first insulating film (110). The transistor (TR) may be placed on the first surface (101) of the substrate (100). The transistor (TR) may be connected to the substrate (100).

[0015] The transistor (TR) may include impurity regions (IR), a channel and a gate structure disposed between the impurity regions (IR). The gate structure may include gate spacers (GS), a gate insulating film (GI) disposed between the gate spacers (GS), a gate electrode (GE), and a gate capping film (GP). The impurity regions (IR) may be formed by implanting impurities into the substrate (100). The gate spacers (GS), the gate insulating film (GI), and the gate capping film (GP) may include insulating materials. The gate electrode (GE) may include a conductive material. The structure of the transistor (TR) is not limited to that shown and described. In some embodiments, the transistor may include a buried gate electrode. In some embodiments, the transistor may include a vertical gate electrode. In some embodiments, the transistor may include a gate all around structure.

[0016] Device isolation layers (IS) may be provided within the substrate (100). A transistor (TR) may be placed between the device isolation layers (IS). The device isolation layers (IS) may define an active region of the substrate (100). The device isolation layers (IS) may include an insulating material.

[0017] First contacts (CT1) and first conductive lines (CL1) may be provided within the first insulating film (110). The first contact (CT1) may be in contact with a transistor (TR), and the first conductive line (CL1) may be in contact with the first contact (CT1). The first contacts (CT1) and the first conductive lines (CL1) may include a conductive material. The number of first contacts (CT1) and first conductive lines (CL1) is not limited to that illustrated, and the contacts and conductive lines provided within the first insulating film (110) may each be defined as the first contact and the first conductive line.

[0018] A through-via (PV) penetrating a substrate (100), a first insulating film (110), and a second insulating film (120) may be provided. The through-via (PV) may penetrate the first surface (101) and the second surface (102) of the substrate (100). The lower surface of the through-via (PV) may form a co-plane with the lower surface of the second insulating film (120). The through-via (PV) may extend in a third direction (D3). The third direction (D3) may intersect with the first direction (D1) and the second direction (D2). For example, the third direction (D3) may be orthogonal to the first direction (D1) and the second direction (D2). The width of the through-via (PV) in the first direction (D1) may increase as it approaches the wiring structure (WS) described later.

[0019] In some embodiments, the through-via (PV) may include a conductive film and a barrier film. The conductive film of the through-via (PV) may include, for example, copper, aluminum, or tungsten, and the barrier film of the through-via (PV) may include, for example, titanium or tantalum.

[0020] A via insulating film (VI) surrounding the outer wall of a through-via (PV) may be provided. The inner wall of the via insulating film (VI) may be in contact with the outer wall of the through-via (PV). The via insulating film (VI) may penetrate the first insulating film (110) and the substrate (100). The through-via (PV) may be spaced apart from the first insulating film (110) and the substrate (100) by the via insulating film (VI). The via insulating film (VI) may be interposed between the through-via (PV) and the first insulating film (110), and between the through-via (PV) and the substrate (100). The lower surface of the via insulating film (VI) may be in contact with the upper surface of the second insulating film (120). The via insulating film (VI) may include an insulating material. For example, the via insulating film (VI) may include an oxide.

[0021] A wiring structure (WS) covering the first insulating film (110) may be provided. The lower surface of the wiring structure (WS) may be in contact with the upper surface of the first insulating film (110). The first insulating film (110) may be provided between the wiring structure (WS) and the substrate (100). A transistor (TR) may be provided between the wiring structure (WS) and the substrate (100). The wiring structure (WS) may be connected to through-vias (PV) and via insulating films (VI).

[0022] The wiring structure (WS) may include a first wiring insulating film (210), a first single capping film (220), a second wiring insulating film (230), a multiple capping film (240), a third wiring insulating film (250), a second single capping film (260), and a fourth wiring insulating film (270) provided sequentially in a third direction (D3). Each of the first wiring insulating film (210), the first single capping film (220), the second wiring insulating film (230), the multiple capping film (240), the third wiring insulating film (250), the second single capping film (260), and the fourth wiring insulating film (270) may be parallel to the substrate (100). Each of the first wiring insulating film (210), the first single capping film (220), the second wiring insulating film (230), the multiple capping film (240), the third wiring insulating film (250), the second single capping film (260), and the fourth wiring insulating film (270) may have the shape of a plate extending along a plane defined by the first direction (D1) and the second direction (D2).

[0023] The first wiring insulating film (210) can cover the first insulating film (110). The lower surface of the first wiring insulating film (210) can be in contact with the upper surface of the first insulating film (110). The first wiring insulating film (210) may include an insulating material containing oxygen and carbon. As an example, the first wiring insulating film (210) may include TEOS (tetraethyl orthosilicate).

[0024] The first single capping film (220) can cover the first wiring insulating film (210). The lower surface of the first single capping film (220) can be in contact with the upper surface of the first wiring insulating film (210). The first single capping film (220) may include an insulating material containing nitrogen. For example, the first single capping film (220) may include SiN.

[0025] The second wiring insulating film (230) may cover the first single capping film (220). The lower surface of the second wiring insulating film (230) may be in contact with the upper surface of the first single capping film (220). The first single capping film (220) may be interposed between the second wiring insulating film (230) and the first wiring insulating film (210). The second wiring insulating film (230) may contain the same material as the first wiring insulating film (210). The second wiring insulating film (230) may contain an insulating material containing oxygen and carbon. As an example, the second wiring insulating film (230) may contain TEOS.

[0026] The multiple capping film (240) can cover the second wiring insulating film (230). The lower surface of the multiple capping film (240) can be in contact with the upper surface of the second wiring insulating film (230). The multiple capping film (240) may include a first material film (241) and a second material film (242) provided sequentially in a third direction (D3).

[0027] The first material film (241) can cover the second wiring insulating film (230). The lower surface of the first material film (241) can be in contact with the upper surface of the second wiring insulating film (230). The first material film (241) may contain the same material as the first single capping film (220). The first material film (241) may contain an insulating material containing nitrogen. As an example, the first material film (241) may contain SiN.

[0028] The second material film (242) may cover the first material film (241). The lower surface of the second material film (242) may be in contact with the upper surface of the first material film (241). The second material film (242) may contain a material different from the first material film (241) and the first single capping film (220). The carbon concentration of the second material film (242) may be different from the carbon concentration of the first material film (241). The carbon concentration of the second material film (242) may be greater than the carbon concentration of the first material film (241). The second material film (242) may contain an insulating material containing nitrogen and carbon. As an example, the second material film (242) may contain SiCN.

[0029] The third wiring insulating film (250) may cover the second material film (242) of the multi-capping film (240). The lower surface of the third wiring insulating film (250) may be in contact with the upper surface of the second material film (242) of the multi-capping film (240). The multi-capping film (240) may be interposed between the second and third wiring insulating films (230, 250). The third wiring insulating film (250) may include a material different from that of the first and second wiring insulating films (210, 230). The dielectric constant of the third wiring insulating film (250) may be smaller than the dielectric constant of the first and second wiring insulating films (210, 230). The third wiring insulating film (250) may include a low dielectric material. The carbon concentration of the third wiring insulating film (250) may be greater than the carbon concentration of each of the first and second wiring insulating films (210, 230). The third wiring insulating film (250) may include an insulating material containing oxygen and carbon. As an example, the third wiring insulating film (250) may include porous SiOCH.

[0030] The second single capping film (260) may cover the third wiring insulating film (250). The lower surface of the second single capping film (260) may be in contact with the upper surface of the third wiring insulating film (250). The second single capping film (260) may contain the same material as the second material film (242) of the multiple capping film (240). The second single capping film (260) may contain an insulating material containing nitrogen and carbon. As an example, the second single capping film (260) may contain SiCN.

[0031] The fourth wiring insulating film (270) may cover the second single capping film (260). The lower surface of the fourth wiring insulating film (270) may be in contact with the upper surface of the second single capping film (260). The second single capping film (260) may be interposed between the third and fourth wiring insulating films (250, 270). The fourth wiring insulating film (270) may include the same material as the third wiring insulating film (250). The fourth wiring insulating film (270) may include a different material from the first and second wiring insulating films (210, 230). The dielectric constant of the fourth wiring insulating film (270) may be smaller than the dielectric constant of the first and second wiring insulating films (210, 230). The fourth wiring insulating film (270) may include a low dielectric material. The carbon concentration of the fourth wiring insulating film (270) may be greater than the carbon concentration of each of the first and second wiring insulating films (210, 230). The fourth wiring insulating film (270) may include an insulating material containing oxygen and carbon. As an example, the fourth wiring insulating film (270) may include porous SiOCH.

[0032] The wiring structure (WS) may further include a second contact (CT2), first wires (WR1), second wires (WR2), and third wires (WR3).

[0033] A second contact (CT2) may be provided within the first wiring insulating film (210). The second contact (CT2) may be surrounded by the first wiring insulating film (210). The lower surface of the first single capping film (220) may be in contact with the upper surface of the second contact (CT2). The second contact (CT2) may be in contact with the first conductive line (CL1).

[0034] The first wiring (WR1) may be provided within a structure in which the first wiring insulating film (210), the first single capping film (220), and the second wiring insulating film (230) are combined. The first wiring (WR1) may be placed at the same level as each other. Each of the first wiring insulating film (210), the first single capping film (220), and the second wiring insulating film (230) may surround each of the first wiring (WR1). The first wiring (WR1) may penetrate the second wiring insulating film (230) and the first single capping film (220). The lowest portion of each of the first wiring (WR1) may be provided within the first wiring insulating film (210). The upper surfaces of the first wiring (WR1) may be in contact with the lower surface of the first material film (241) of the multiple capping film (240). The upper surfaces of the first wiring (WR1) can form a co-surface with the upper surface of the second wiring insulating film (230).

[0035] The first wiring (WR1) may include a first via wiring (VW1) in contact with a through via (PV). The first wiring (WR1) may include a first contact wiring (CW1) in contact with a second contact (CT2).

[0036] The second wiring (WR2) may be provided within a structure in which a multi-capping film (240) and a third wiring insulating film (250) are combined. The second wiring (WR2) may be placed at the same level as each other. Each multi-capping film (240) and the third wiring insulating film (250) may surround each of the second wiring (WR2). At least some of the second wiring (WR2) may include a wiring portion and a via portion. The wiring portion of the second wiring (WR2) may be a portion placed within the third wiring insulating film (250), and the via portion of the second wiring (WR2) may be a portion penetrating the multi-capping film (240). The upper surfaces of the second wiring (WR2) may be in contact with the lower surface of the second single capping film (260). The upper surfaces of the second wiring (WR2) may be co-surfaces with the upper surface of the third wiring insulating film (250).

[0037] The second wiring (WR2) may include a second via wiring (VW2) that contacts the first via wiring (VW1). The second wiring (WR2) may include a second contact wiring (CW2) that contacts the first contact wiring (CW1).

[0038] The third wiring (WR3) may be provided within a structure in which the second single capping film (260) and the fourth wiring insulating film (270) are combined. The third wiring (WR3) may be placed at the same level as each other. Each of the second single capping film (260) and the fourth wiring insulating film (270) may surround each of the third wiring (WR3). At least some of the third wiring (WR3) may include a wiring portion and a via portion. The wiring portion of the third wiring (WR3) may be a portion placed within the fourth wiring insulating film (270), and the via portion of the third wiring (WR3) may be a portion penetrating the second single capping film (260). The upper surfaces of the third wiring (WR3) may form a co-surface with the upper surface of the fourth wiring insulating film (270).

[0039] The third wiring (WR3) may include a third via wiring (VW3) that contacts the second via wiring (VW2). The third wiring (WR3) may include a third contact wiring (CW3) that contacts the second contact wiring (CW2).

[0040] The third via wiring (VW3), the second via wiring (VW2), and the first via wiring (VW1) can be electrically connected to a through-via (PV). The third contact wiring (CW3), the second contact wiring (CW2), the first contact wiring (CW1), the second contact (CT2), the first conductive line (CL1), and the first contact (CT1) can be electrically connected to a transistor (TR).

[0041] In some embodiments, each of the first to third wirings (WR1, WR2, WR3) may include a conductive film and a barrier film. The conductive film of each of the first to third wirings (WR1, WR2, WR3) may include, for example, copper, aluminum, or tungsten, and the barrier film of each of the first to third wirings (WR1, WR2, WR3) may include, for example, titanium or tantalum.

[0042] The number of wiring insulating films (210, 230, 250, 270) is not limited to that shown and described. In some embodiments, the number of wiring insulating films may be three or fewer, or five or more. In some embodiments, the number of single and multiple capping films, and the number of wires may correspond to the number of wiring insulating films.

[0043] In some embodiments, a first wiring insulating film, a first single capping film, a second wiring insulating film, a first multiple capping film, a third wiring insulating film, a second multiple capping film, a fourth wiring insulating film, a second single capping film, and a fifth wiring insulating film may be sequentially laminated on a first insulating film. In this case, first wirings surrounded by the second wiring insulating film, second wirings surrounded by the third wiring insulating film, third wirings surrounded by the fourth wiring insulating film, and fourth wirings surrounded by the fifth wiring insulating film may be provided.

[0044] A first protective film (310) covering the lower surface of the second insulating film (120) may be provided. The upper surface of the first protective film (310) may be in contact with the lower surface of the second insulating film (120). The first protective film (310) may include an insulating material.

[0045] A pad (PD) may be provided within the first protective layer (310). The pad (PD) may penetrate the first protective layer (310). The pad (PD) may be connected to a through-via (PV). The upper surface of the pad (PD) may be in contact with the lower surface of the through-via (PV). The pad (PD) may include a conductive material.

[0046] A second protective film (320) covering the upper surface of the fourth wiring insulating film (270) may be provided. The lower surface of the second protective film (320) may be in contact with the upper surface of the fourth wiring insulating film (270). The second protective film (320) may include an insulating material.

[0047] Terminals (TE) penetrating the second protective film (320) may be provided. The terminals (TE) may be in contact with the third wiring (WR3). The lower surface of each terminal (TE) may be in contact with the upper surface of each third wiring (WR3). The terminals (TE) may include a conductive material.

[0048] A semiconductor device according to some embodiments of the present disclosure may include a multi-capping film (240) comprising a first material film (241) and a second material film (242) comprising different materials. Accordingly, wiring insulating films in contact with the multi-capping film (240) may be adhered relatively strongly to the multi-capping film (240), and the reliability of the semiconductor device may be improved.

[0050] FIG. 2 is a graph illustrating the effects of a semiconductor device according to some embodiments of the present disclosure.

[0051] Referring to FIG. 2, a TEOS film and a SiN film in contact with each other, a TEOS film and a SiCN film in contact with each other, a porous SiOCH film and a SiN film in contact with each other, and a porous SiOCH film and a SiCN film in contact with each other were formed. Interfacial fracture energies were measured at multiple locations between the TEOS film and the SiN film, interfacial fracture energies were measured at multiple locations between the TEOS film and the SiCN film, interfacial fracture energies were measured at multiple locations between the porous SiOCH film and the SiN film, and interfacial fracture energies were measured at multiple locations between the porous SiOCH film and the SiCN film. The average interfacial fracture energies between the TEOS film and the SiN film were measured to be greater than the average interfacial fracture energies between the TEOS film and the SiCN film, and the average interfacial fracture energies between the porous SiOCH film and the SiCN film were measured to be greater than the average interfacial fracture energies between the porous SiOCH film and the SiN film. Accordingly, the adhesion between the TEOS film and the SiN film may be greater than the adhesion between the TEOS film and the SiCN film, and the adhesion between the porous SiOCH film and the SiCN film may be greater than the adhesion between the porous SiOCH film and the SiN film.

[0052] A semiconductor device according to some embodiments of the present disclosure can prevent the phenomenon of delamination of the films of the semiconductor device by providing a SiN film in contact with a TEOS film and a SiCN film in contact with a porous SiOCH film.

[0054] FIGS. 3a, 3b, 3c, 3d, 3e, and 3f are cross-sectional views illustrating a method for manufacturing a semiconductor device according to FIG. 1.

[0055] Referring to FIG. 3a, a transistor (TR) and a device isolation film (IS) can be formed on a first surface (101) of a substrate (100). A first insulating film (110) on the first surface (101) of the substrate (100), and first contacts (CT1) and first conductive lines (CL1) within the first insulating film (110) can be formed. A first wiring insulating film (210) can be formed on the first insulating film (110). A second contact (CT2) can be formed within the first wiring insulating film (210). A first single capping film (220) can be formed on the first wiring insulating film (210).

[0056] A through-via (PV) and a via insulating film (VI) can be formed. Forming the through-via (PV) and the via insulating film (VI) may include forming a hole penetrating the upper portion of the first single capping film (220), the first wiring insulating film (210), the first insulating film (110), and the substrate (100), forming a via insulating material film and a through-via material film that fill the hole, and removing the upper portions of the via insulating material film and the through-via material film to form the via insulating film (VI) and the through-via (PV).

[0057] A second wiring insulating film (230) can be formed on the first single capping film (220). First wirings (WR1) can be formed penetrating the second wiring insulating film (230) and the first single capping film (220).

[0058] Referring to FIG. 3b, a first material film (241) can be formed on the second wiring insulating film (230). The first material film (241) can cover the upper surfaces of the first wirings (WR1).

[0059] Referring to FIG. 3c, a second material film (242) can be formed on the first material film (241).

[0060] Referring to FIG. 3d, a third wiring insulating film (250) can be formed on the second material film (242). Second wiring (WR2) can be formed penetrating the third wiring insulating film (250), the second material film (242), and the first material film (241).

[0061] A second single capping film (260) can be formed on the third wiring insulating film (250), and a fourth wiring insulating film (270) can be formed on the second single capping film (260). Third wirings (WR3) can be formed penetrating the fourth wiring insulating film (270) and the second single capping film (260).

[0062] A second protective film (320) can be formed on the fourth wiring insulating film (270). Terminals (TE) penetrating the second protective film (320) can be formed.

[0063] Referring to FIG. 3e, the back surface of the substrate (100) can be etched. The etched back surface of the substrate (100) can be defined as a second surface (102). As the back surface of the substrate (100) is etched, a portion of the through-via (PV) may be exposed.

[0064] Referring to FIG. 3f, a second insulating film (120) may be formed to cover the second surface (102) of the substrate (100) and the exposed through-via (PV). Subsequently, a portion of the second insulating film (120) and a portion of the through-via (PV) may be removed so that the through-via (PV) is exposed again.

[0065] Referring to FIG. 1, a first protective film (310) covering the lower surface of the second insulating film (120) may be formed. A pad (PD) may be formed within the first protective film (310).

[0067] FIG. 4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0068] Referring to FIG. 4, the semiconductor device may include a substrate (100a), a first insulating film (110a) on the substrate (100a), and a wiring structure (WSa) on the first insulating film (110a).

[0069] The wiring structure (WSa) may include first to fourth wiring insulating films (210a, 230a, 250a, 270a). The first to fourth wiring insulating films (210a, 230a, 250a, 270a) may include an insulating material containing carbon and oxygen. The third wiring insulating film (250a) may include a low dielectric material. The carbon concentration of each of the first, second, and fourth wiring insulating films (210a, 230a, 270a) may be lower than the carbon concentration of the third wiring insulating film (250a). The first, second, and fourth wiring insulating films (210a, 230a, 270a) may have a higher dielectric constant than the third wiring insulating film (250a). For example, the first, second, and fourth wiring insulating films (210a, 230a, 270a) may include TEOS, and the third wiring insulating film (250a) may include porous SiOCH.

[0070] The wiring structure (WSa) may include a single capping film (220a) between the first and second wiring insulating films (210a, 230a), a first multi-capping film (240a) between the second and third wiring insulating films (230a, 250a), and a second multi-capping film (260a) between the third and fourth wiring insulating films (250a, 270a).

[0071] A single capping film (220a) may include an insulating material containing nitrogen. As an example, the single capping film (220a) may include SiN.

[0072] The first multi-capping film (240a) may include a first material film (241a) in contact with the second wiring insulating film (230a) and a second material film (242a) in contact with the third wiring insulating film (250a). The first material film (241a) may include an insulating material containing nitrogen, and the second material film (242a) may include an insulating material containing nitrogen and carbon. As an example, the first material film (241a) may include SiN, and the second material film (242a) may include SiCN.

[0073] The second multi-capping film (260a) may include a third material film (261a) in contact with the third wiring insulating film (250a) and a fourth material film (262a) in contact with the fourth wiring insulating film (270a). The third material film (261a) may include an insulating material containing nitrogen and carbon, and the fourth material film (262a) may include an insulating material containing nitrogen. As an example, the third material film (261a) may include SiCN, and the fourth material film (262a) may include SiN.

[0075] FIG. 5 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0076] Referring to FIG. 5, the semiconductor device may include a substrate (100b), a first insulating film (110b) on the substrate (100b), and a wiring structure (WSb) on the first insulating film (110b).

[0077] The wiring structure (WSb) may include first to fourth wiring insulating films (210b, 230b, 250b, 270b). The first to fourth wiring insulating films (210b, 230b, 250b, 270b) may include an insulating material containing carbon and oxygen. The first, second, and fourth wiring insulating films (210b, 230b, 270b) may include a low dielectric material. The third wiring insulating film (250b) may have a greater dielectric constant than the first, second, and fourth wiring insulating films (210b, 230b, 270b). The carbon concentration of each of the first, second, and fourth wiring insulating films (210b, 230b, 270b) may be greater than the carbon concentration of the third wiring insulating film (250b). For example, the first, second, and fourth wiring insulating films (210b, 230b, 270b) may include porous SiOCH, and the third wiring insulating film (250b) may include TEOS.

[0078] The wiring structure (WSb) may include a single capping film (220b) between the first and second wiring insulating films (210b, 230b), a first multi-capping film (240b) between the second and third wiring insulating films (230b, 250b), and a second multi-capping film (260b) between the third and fourth wiring insulating films (250b, 270b).

[0079] A single capping film (220b) may include an insulating material containing nitrogen and carbon. As an example, the single capping film (220b) may include SiCN.

[0080] The first multi-capping film (240b) may include a first material film (241b) in contact with the second wiring insulating film (230b) and a second material film (242b) in contact with the third wiring insulating film (250b). The first material film (241b) may include an insulating material containing nitrogen and carbon, and the second material film (242b) may include an insulating material containing nitrogen. As an example, the first material film (241b) may include SiCN, and the second material film (242b) may include SiN.

[0081] The second multi-capping film (260b) may include a third material film (261b) in contact with the third wiring insulating film (250b) and a fourth material film (262b) in contact with the fourth wiring insulating film (270b). The third material film (261b) may include an insulating material containing nitrogen, and the fourth material film (262b) may include an insulating material containing nitrogen and carbon. As an example, the third material film (261b) may include SiN, and the fourth material film (262b) may include SiCN.

[0083] FIG. 6 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0084] Referring to FIG. 6, the semiconductor device may include a substrate (100c), a first insulating film (110c) on the substrate (100c), and a wiring structure (WSc) on the first insulating film (110c).

[0085] The semiconductor device may further include through-vias (PVc). The width of the through-vias (PVc) in the first direction (D1) may decrease as it approaches the wiring structure (WSc). The through-vias (PVc) may be formed on the rear side of the substrate (100c).

[0086] The wiring structure (WSc) may include a first wiring insulating film (210c) in contact with a first insulating film (110c) and a second wiring insulating film (230c) in contact with the first wiring insulating film (210c). The first and second wiring insulating films (210c, 230c) may include an insulating material containing carbon and oxygen.

[0088] FIG. 7 is a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0089] Referring to FIG. 7, the semiconductor package may include a package substrate (400d). For example, the package substrate (400d) may be a printed circuit board (PCB). First terminals (TE1d) connected to the package substrate (400d) may be provided.

[0090] An interposer (500d) may be provided on a package substrate (400d). Second terminals (TE2d) connecting the package substrate (400d) and the interposer (500d) may be provided. An underfill film (UNd) may be provided between the package substrate (400d) and the interposer (500d).

[0091] A processor chip (600d) may be provided on the interposer (500d). For example, the processor chip (600d) may be a graphics processing unit (GPU) or a central processing unit (CPU). Third terminals (TE3d) connecting the processor chip (600d) and the interposer (500d) may be provided.

[0092] A plurality of semiconductor chips (SCd) arranged along a third direction (D3) on an interposer (500d) may be provided. The semiconductor chips (SCd) may be spaced apart from the processor chip (600d) in a first direction (D1). Each semiconductor chip (SCd) may include a wiring structure. At least some of the semiconductor chips (SCd) may include through vias. Fourth terminals (TE4d) may be provided to connect the semiconductor chips (SCd) or to connect the semiconductor chips (SCd) and the interposer (500d).

[0093] A molding film (MDd) surrounding semiconductor chips (SCd) and processor chips (600d) may be provided.

[0094] Although embodiments according to the technical concept of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. The embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0095] 100: Substrate 110: First insulating layer WS: Wiring structure TR: Transistor PV: Penetrating via

Claims

Claim 1 A semiconductor device comprising a substrate; a transistor connected to the substrate; and a wiring structure including contact wirings electrically connected to the transistor, wherein the wiring structure further comprises a first wiring insulating film, a first material film in contact with the first wiring insulating film, a second material film in contact with the first material film, and a second wiring insulating film in contact with the second material film, wherein the first material film comprises SiN and the second material film comprises SiCN, wherein the dielectric constant of the first wiring insulating film is greater than the dielectric constant of the second wiring insulating film, the interfacial fracture energy between the first wiring insulating film and the first material film is greater than the interfacial fracture energy between the first wiring insulating film and the second material film, and the interfacial fracture energy between the second wiring insulating film and the second material film is greater than the interfacial fracture energy between the second wiring insulating film and the first material film. Claim 2 A semiconductor device according to claim 1, wherein the carbon concentration of the first wiring insulating film is smaller than the carbon concentration of the second wiring insulating film. Claim 3 A semiconductor device according to claim 2, wherein the first wiring insulating film comprises TEOS (tetraethyl orthosilicate) and the second wiring insulating film comprises porous SiOCH. Claim 4 A semiconductor device according to claim 1, further comprising a through-via penetrating the substrate, and the wiring structure further comprising via wirings electrically connected to the through-via. Claim 5 A semiconductor device according to claim 4, wherein the via wirings include a first via wiring in contact with the through-via, and the upper surface of the first via wiring is in contact with the lower surface of the first material film. Claim 6 A semiconductor device according to claim 5, wherein the contact wirings include a first contact wiring disposed at the same level as the first via wiring, and the upper surface of the first contact wiring contacts the lower surface of the first material film. Claim 7 A semiconductor device according to claim 5, wherein the via wirings include a second via wiring in contact with the first via wiring, and the second via wiring is surrounded by the second wiring insulating film. Claim 8 A semiconductor device comprising: a substrate; an insulating film covering the substrate; a transistor provided between the substrate and the insulating film; and a wiring structure covering the insulating film, wherein the wiring structure comprises a first wiring insulating film, a first material film in contact with the first wiring insulating film, a second material film in contact with the first material film, and a second wiring insulating film in contact with the second material film, wherein the first material film comprises SiN, the second material film comprises SiCN, and the first and second wiring insulating films comprise insulating materials comprising carbon and oxygen, wherein the carbon concentration of the first wiring insulating film is smaller than the carbon concentration of the second wiring insulating film, the interfacial fracture energy between the first wiring insulating film and the first material film is greater than the interfacial fracture energy between the first wiring insulating film and the second material film, and the interfacial fracture energy between the second wiring insulating film and the second material film is greater than the interfacial fracture energy between the second wiring insulating film and the first material film. Claim 9 A semiconductor device according to claim 8, wherein the first wiring insulating film comprises TEOS and the second wiring insulating film comprises porous SiOCH. Claim 10 In claim 8, the wiring structure further comprises a third material film in contact with the second wiring insulating film, and the third material film comprises SiCN.

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