Memory device and manufacturing method of the memory device

Abstract

The present invention includes a memory device and a method for manufacturing the same, comprising: first vertical plugs and second vertical plugs arranged adjacent to each other; a first selection line in contact with the first vertical plug; a second selection line formed on the same layer as the first selection line and in contact with the second vertical plug; and a separation pattern that overlaps a portion of the first vertical plugs and a portion of the second vertical plugs and separates the first and second selection lines from each other.

Description

Technology Field

[0001] The present invention relates to a memory device and a method for manufacturing the same, and more specifically, to a memory device having a three-dimensional structure and a method for manufacturing the same. Background Technology

[0002] Memory devices can be classified into volatile memory devices, in which stored data is lost when the power supply is cut off, and non-volatile memory devices, in which stored data is retained even when the power supply is cut off.

[0003] Non-volatile memory devices may include NAND flash memory, NOR flash memory, resistive random access memory (ReRAM), phase-change memory (PRAM), magneto-resistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin transfer torque random access memory (STT-RAM).

[0004] Among these, memory cells included in the NAND flash memory may be included in a string connected between a bit line and a source line. The string may include first select transistors, memory cells, and second select transistors connected between a bit line and a source line. The gates of the first select transistors may be connected to first select lines, the gates of the memory cells may be connected to word lines, and the gates of the second select transistors may be connected to second select lines. The problem to be solved

[0006] An embodiment of the present invention provides a memory device capable of forming a separation pattern that separates selection lines without loss of vertical plugs, and a method for manufacturing the same. means of solving the problem

[0007] A memory device according to an embodiment of the present invention comprises: first vertical plugs and second vertical plugs arranged adjacent to each other; a first selection line in contact with the first vertical plug; a second selection line formed on the same layer as the first selection line and in contact with the second vertical plug; and a separation pattern that overlaps a part of the first vertical plugs and a part of the second vertical plugs and separates the first and second selection lines from each other.

[0008] A memory device according to an embodiment of the present invention comprises: source lines, first selection lines, word lines, and second selection lines stacked on a substrate; first and second vertical plugs arranged spaced apart from each other and penetrating vertically the first selection lines, word lines, and second selection lines; and a separation pattern that overlaps with a portion of the first and second vertical plugs between the first and second vertical plugs and separates the first selection lines in a vertical direction.

[0009] A memory device according to an embodiment of the present invention comprises: a peripheral circuit structure formed on a substrate; a cell structure that contacts the peripheral circuit structure through bonding pads and includes a bit line, first selection lines, word lines, second selection lines, and a source line; first and second vertical plugs that penetrate the cell structure vertically and are spaced apart from each other; a first separation pattern that overlaps with a part of the first and second vertical plugs at the bottom of the first and second vertical plugs and separates the first selection lines in a vertical direction; and a second separation pattern that overlaps with a part of the first and second vertical plugs at the top of the first and second vertical plugs and separates the second selection lines in a vertical direction.

[0010] A method for manufacturing a memory device according to an embodiment of the present invention comprises: forming a stacked structure in which first selection lines, word lines, and second selection lines are stacked on a source line; forming first and second vertical plugs that penetrate the first selection lines, word lines, and second selection lines and are spaced apart from each other; forming a trench that overlaps with a part of the first and second vertical plugs and separates the second selection lines; and forming a separation pattern inside the trench.

[0011] A method for manufacturing a memory device according to an embodiment of the present invention comprises: forming a peripheral circuit structure on a first substrate in which first junction pads are exposed; forming a cell structure on a second substrate in which first selection lines, word lines, second selection lines, and second junction pads are stacked; forming first and second vertical plugs that penetrate the first selection lines, word lines, and second selection lines included in the cell structure and are spaced apart from each other; forming a first trench that overlaps a portion of the first and second vertical plugs and separates the second selection lines; forming a first separation pattern inside the first trench; flipping the entire structure formed on the second substrate and the second substrate, and attaching the second junction pads included in the flipped cell structure to the upper portion of the first junction pads included in the peripheral circuit structure; removing the second substrate; and forming a second trench that overlaps a portion of the first and second vertical plugs and separates the first selection lines. and includes the step of forming a second separation pattern inside the second trench. Effects of the invention

[0013] According to the present technology, a separation pattern of selection lines can be formed without loss of vertical plugs, and since there is no loss of vertical plugs, an increase in the size of the memory device can be prevented. Brief explanation of the drawing

[0014] FIG. 1 is a drawing for explaining a memory device according to an embodiment of the present invention. Figure 2 is a diagram illustrating a memory cell array. FIG. 3 is a circuit diagram for explaining a memory block according to a first embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a string according to a first embodiment of the present invention. FIG. 5 is a plan view for illustrating a first separation pattern according to a first embodiment of the present invention. FIGS. 6a and FIGS. 6b are cross-sectional views illustrating the structure of a memory device according to a first embodiment of the present invention. FIG. 7 is a perspective view illustrating the structure of a vertical plug that overlaps with a first separation pattern. FIGS. 8a to 8e are drawings for explaining a method for manufacturing a memory device according to a first embodiment of the present invention. FIG. 9 is a circuit diagram for explaining a memory block according to a second embodiment of the present invention. FIG. 10 is a perspective view illustrating the arrangement of a memory array and peripheral circuits according to a second embodiment of the present invention. FIG. 11 is a plan view for illustrating first and second separation patterns according to a second embodiment of the present invention. FIGS. 12a to 12h are drawings for explaining a method for manufacturing a memory device according to a second embodiment of the present invention. FIG. 13 is a drawing for explaining a memory device according to a third embodiment. FIG. 14 is a drawing showing a memory card system to which the memory device of the present invention is applied. FIG. 15 is a drawing showing a Solid State Drive (SSD) system to which the memory device of the present invention is applied. Specific details for implementing the invention

[0015] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0017] FIG. 1 is a drawing for explaining a memory device according to an embodiment of the present invention.

[0018] Referring to FIG. 1, a memory device (1100) may include a memory cell array (110) in which data is stored, and peripheral circuits (120 to 170) capable of performing program, read, or erase operations.

[0019] The memory cell array (110) may include a plurality of memory blocks in which data is stored. Each of the memory blocks includes memory cells, and the memory cells may be implemented in a three-dimensional structure that is stacked vertically on a substrate.

[0020] Peripheral circuits (120 to 170) may include a row decoder (120), a voltage generator (130), a page buffer group (140), a column decoder (150), an input / output circuit (160), and a control logic circuit (170).

[0021] The row decoder (120) can select one memory block among the memory blocks included in the memory cell array (110) according to the row address (RADD) and transmit operating voltages (Vop) to the selected memory block.

[0022] The voltage generation unit (130) can generate and output operating voltages (Vop) required for various operations in response to an operation code (OPCD). For example, the voltage generation unit (130) can generate a program voltage, a read voltage, an erase voltage, a pass voltage, a turn-on voltage, and a ground voltage in response to an operation code (OPCD), and can selectively output the generated voltages.

[0023] A page buffer group (140) may be connected to a memory cell array (110) via bit lines. For example, the page buffer group (140) may include page buffers connected to each of the bit lines. The page buffers may operate simultaneously in response to page buffer control signals (PBSIG) and may temporarily store data during a program, read, or verify operation. During a read or verify operation, the page buffers may sense the current of the bit lines, which varies according to the threshold voltage of the memory cells.

[0024] The column decoder (150) can transmit data (DATA) between the input / output circuit (160) and the page buffer group (140) according to the column address (CADD).

[0025] The input / output circuit (160) can be connected to an external device through input / output lines (IO). For example, the external device may be a controller capable of transmitting a command (CMD), an address (ADD), or data (DATA) to the memory device (1100). The input / output circuit (160) can input and output a command (CMD), an address (ADD), and data (DATA) through the input / output lines (IO). For example, the input / output circuit (160) can transmit a command (CMD) and an address (ADD) received from an external device through the input / output lines (IO) to a control logic circuit (170), and transmit data (DATA) received from an external device through the input / output lines (IO) to a column decoder (150). The input / output circuit (160) can output data (DATA) received from the column decoder (150) to an external device through input / output lines (IO).

[0026] The control logic circuit (170) can output an operation code (OPCD), a row address (RADD), page buffer control signals (PBSIG), and a column address (CADD) in response to a command (CMD) and an address (ADD). For example, the control logic circuit (170) may include software that performs an algorithm in response to a command (CMD), and hardware configured to output an address (ADD) and various control signals.

[0028] Figure 2 is a diagram illustrating a memory cell array.

[0029] Referring to FIG. 2, the memory cell array (110) may include first to kth memory blocks (1BLK to kBLK; k is a positive integer). Each of the first to kth memory blocks (1BLK to kBLK) may include a plurality of memory cells stacked vertically from the substrate. The first to kth memory blocks (1BLK to kBLK) may be arranged between a source line (SL) and first to nth bit lines (BL1 to BLn). For example, if the first to nth bit lines (BL1 to BLn) are arranged spaced apart from each other in a first direction (X direction) and formed to extend in a second direction (Y direction) perpendicular to the first direction (X direction), the first to kth memory blocks (1BLK to kBLK) may be arranged spaced apart from each other along the second direction (Y direction). Accordingly, memory cells included in the first to kth memory blocks (1BLK~kBLK) can be stacked along a third direction (Z) perpendicular to the first and second directions (X, Y directions).

[0031] FIG. 3 is a circuit diagram for explaining a memory block according to a first embodiment of the present invention.

[0032] Referring to FIG. 3, the first to kth memory blocks (1BLK to kBLK in FIG. 2) are configured identically to each other, so the kth memory block (kBLK) is shown as an example.

[0033] The k-th memory block (kBLK) includes strings (ST) connected between the first to n-th bit lines (BL1 to BLn) and the source line (SL). Since the first to n-th bit lines (BL1 to BLn) are extended along the second direction (Y direction) and arranged spaced apart from each other along the first direction (X direction), the strings (ST) can also be arranged spaced apart from each other along the first and second directions (X and Y directions). For example, strings (ST) can be connected between the first bit line (BL1) and the source line (SL), and strings (ST) can be arranged between the second bit line (BL2) and the source line (SL). In this way, strings (ST) can be arranged between the n-th bit line (BLn) and the source line (SL). Strings (ST) can be extended along the third direction (Z direction).

[0034] For example, if one of the strings (ST) connected to the n-th bit line (BLn) is described, the string (ST) may include first to third source select transistors (SST1 to SST3), first to i-th memory cells (MC1 to MCi), and first to third drain select transistors (DST1 to DST3). Since the k-th memory block (kBLK) illustrated in FIG. 3 is a diagram for understanding the structure of the memory block, the number of source select transistors, memory cells, and drain select transistors included in the strings (ST) may change depending on the memory device.

[0035] The gates of the first to third source selection transistors (SST1~SST3) included in different strings can be connected to the first to third source selection lines (SSL1~SSL3), the gates of the first to i memory cells (MC1~MCi) can be connected to the first to i word lines (WL1~WLi), and the gates of the first to third drain selection transistors (DST1~DST3) can be connected to the 11th, 12th, 21st, 22nd, 31st and 32nd drain selection lines (DSL11, DSL12, DSL21, DSL22, DSL31, DSL32).

[0036] For example, a first source selection line (SSL1) may be commonly connected to first source selection transistors (SST1) arranged at equal distances from the substrate. In other words, first source selection transistors (SST1) formed on the same layer may be commonly connected to the first source selection line (SSL1). In this way, second source selection transistors (SST2) formed on a different layer from the first source selection transistors (SST1) may be commonly connected to the second source selection line (SSL2), and third source selection transistors (SST3) formed on a different layer from the second source selection transistors (SST2) may be commonly connected to the third source selection line (SSL3). The first to third source selection lines (SSL1 to SSL3) may each be formed on different layers.

[0037] In the manner described above, i-th memory cells (MCi) formed on the same layer can be commonly connected to the i-th word line (WLi), and the first to i-th word lines (WL1~WLi) can be formed on different layers, respectively. A group of memory cells included in different strings (ST) and connected to the same word line becomes a page (PG).

[0038] The first to third drain selection transistors (DST1 to DST3) included in different strings (ST) can be connected to separate drain selection lines. Specifically, each of the first to third drain selection transistors (DST1 to DST3) arranged along the first direction (X direction) is connected to the same drain selection line, and the first to third drain selection transistors (DST1 to DST3) arranged along the second direction (Y direction) can be connected to separate drain selection lines. For example, some of the first drain selection transistors (DST1) can be connected to the eleventh drain selection line (DSL11), and the rest can be connected to the twelfth drain selection line (DSL12). The twelfth drain selection line (DSL12) is a line separated from the eleventh drain selection line (DSL11). Accordingly, the voltage applied to the 11th drain select line (DSL11) may be different from the voltage applied to the 12th drain select line (DSL12). In this way, part of the 2nd drain select transistors (DST2) may be connected to the 21st drain select line (DSL21), and the remainder may be connected to the 22nd drain select line (DSL22). Part of the 3rd drain select transistors (DST3) may be connected to the 31st drain select line (DSL31), and the remainder may be connected to the 32nd drain select line (DSL32).

[0039] Although not shown in FIG. 3, dummy lines may be placed between the drain selection line and the word line, and dummy lines may also be placed between the source selection line and the word line.

[0041] FIG. 4 is a cross-sectional view illustrating a string according to a first embodiment of the present invention.

[0042] Referring to FIG. 4, a cross-sectional view of one of the strings (ST) shown in FIG. 3 is shown.

[0043] Source lines (SL), insulating films (IS), and first conductive films (CDa) may be formed on a substrate (SB). In FIG. 4, a source line (SL) is formed on the upper surface of the substrate (SB), but a peripheral circuit may be formed between the substrate (SB) and the source line (SL). The source line (SL) may be formed of a conductive material.

[0044] Insulating films (IS) and first conductive films (CDa) may be stacked alternately. Insulating films (IS) may be formed of an oxide film or a silicon oxide film. The first conductive films (CDa) may be formed of a metallic material such as tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), or a semiconductor material such as silicon (Si) or polysilicon (Poly-Si), but are not limited thereto. A portion of the first conductive films (CDa) may be the 11th to 31st source selection lines (SSL11~SSL31), the 1st to ith word lines (WL1~WLi), or the 11th to 31st drain selection lines (DSL11~DSL31). Additionally, a portion of the first conductive films (CDa) may be the 1st to 4th dummy lines (1DL~4DL). The first to fourth dummy lines (1DL~4DL) may be connected to the gates of dummy cells included in the vertical plug (VPL). Dummy cells refer to cells that are not substantially used within the memory block. For example, dummy cells may store dummy data. The first to fourth dummy lines (1DL~4DL) and dummy cells may be formed to prevent damage to normal lines during the manufacturing process of the memory block. In the memory block containing the dummy cells, the eleventh to thirteenth source selection lines (SSL11~SSL31), the first and second dummy lines (1DL, 2DL), the first to ith word lines (WL1~WLi), the third and fourth dummy lines (3DL, 4DL), and the eleventh to thirteenth drain selection lines (DSL11~DSL31) may be sequentially stacked spaced apart from each other on the source line (SL). Insulating films (IS) may be formed between the 11th to 31st source selection lines (SSL11~SSL31), the 1st and 2nd dummy lines (1DL, 2DL), the 1st to ith word lines (WL1~WLi), the 3rd and 4th dummy lines (3DL, 4DL), and the 11th to 31st drain selection lines (DSL11~DSL31).

[0045] Source select transistors, dummy cells, memory cells, and drain select transistors may be formed within a vertical plug (VPL), and the vertical plug (VPL) may be formed to penetrate vertically the insulating films (IS) and the first conductive films (CDa). The vertical plug (VPL) may be formed in a cylindrical shape. For example, a memory layer (ML) may be formed at the outermost edge of the vertical plug (VPL), and a channel layer (CH) and a core pillar (CP) may be sequentially formed inside the memory layer (ML). The core pillar (CP) may be formed in a cylindrical shape, and the channel layer (CH) may be formed in a cylindrical shape that wraps around the side of the core pillar (CP). The memory layer (ML) may be formed in a cylindrical shape that wraps around the side of the channel layer (CH). The core pillar (CP) may be formed of an insulating material such as an oxide film or a silicon oxide film. The channel film (CH) can be formed from a silicon film or a polysilicon film. Depending on the memory device, the core pillar (CP) may be omitted. In a structure without a core pillar (CP), the channel film (CH) can be formed in a cylindrical shape.

[0046] The memory layer (ML) may include a tunnel isolation layer (TO), a charge trap layer (CT), and a blocking layer (BX). The tunnel isolation layer (TO) may be made of an oxide film or a silicon oxide film and may be formed in a cylindrical shape that surrounds the side of the channel layer (CH). The charge trap layer (CT) may be made of a nitride film and may be formed in a cylindrical shape that surrounds the side of the tunnel isolation layer (TO). The blocking layer (BX) may be made of an oxide film or a silicon oxide film and may be formed in a cylindrical shape that surrounds the side of the charge trap layer (CT). The drawing corresponding to reference numeral '41' shows the structure of the memory cell in a plan view in the first and second directions (X, Y directions). As shown in the plan view (41), the memory cell may be composed of a channel layer (CH), a tunnel isolation layer (TO), a charge trap layer (CT), and a blocking layer (BX) that sequentially surround the core pillar (CP).

[0047] The first upper insulating film (1ISu) formed at the top of the insulating films (IS) may be formed thicker than the remaining insulating films (IS) formed at the bottom. In the portion corresponding to the layer where the first upper insulating film (1ISu) is formed, a second conductive film (CDb) may be formed on the upper portion of the core pillar (CP). The second conductive film (CDb) may be formed to lower the resistance of the channel film (CH) in the region where drain select transistors are formed, and may be made of a polysilicon film.

[0048] Since FIG. 4 is a cross-sectional view for explaining the structure of a string (ST) according to one embodiment, the number of lines (SSL11~DSL31) shown in FIG. 4 is not limited to the number shown in the drawing.

[0050] FIG. 5 is a plan view for illustrating a first separation pattern according to a first embodiment of the present invention.

[0051] Referring to FIG. 5, the first separation pattern (1SP) is a pattern for separating drain select lines formed on the same layer. For example, assuming that the 31st drain select line (DSL31) and the 32nd drain select line (DSL32) are lines formed on the same layer, the 31st drain select line (DSL31) and the 32nd drain select line (DSL32) are formed with the same first conductive film formed on the same layer, but can be electrically separated from each other by the first separation pattern (1SP). Accordingly, different voltages can be applied to the 31st drain select line (DSL31) and the 32nd drain select line (DSL32).

[0052] A plurality of vertical plugs are connected to the 31st drain selection line (DSL31) and the 32nd drain selection line (DSL32). The first separation pattern (1SP) may be formed to overlap the vertical plugs adjacent to the 32nd drain selection line (DSL32) among the vertical plugs connected to the 31st drain selection line (DSL31), and the vertical plugs adjacent to the 31st drain selection line (DSL31) among the vertical plugs connected to the 32nd drain selection line (DSL32). For example, the vertical plugs adjacent to the 32nd drain selection line (DSL32) among the vertical plugs connected to the 31st drain selection line (DSL31) are defined as the first vertical plug group (1GVPL), and the vertical plugs adjacent to the 31st drain selection line (DSL31) among the vertical plugs connected to the 32nd drain selection line (DSL32) are defined as the second vertical plug group (2GVPL). The first separation pattern (1SP) can be formed in the shape of a line that overlaps a part of the first vertical plug group (1GVPL) and a part of the second vertical plug group (2GVPL). Since a channel film remains in the part of the vertical plugs included in the first vertical plug group (1GVPL) that does not overlap with the first separation pattern (1SP), the turn-on or turn-off operation of the transistor can be performed through the remaining channel film.

[0053] Unlike the present embodiment, when the first separation pattern (1SP) is formed to overlap the entire vertical plugs arranged in the first direction (X direction), the channel film is removed from the layer overlapping the first separation pattern (1SP), so the turn-on or turn-off operation of the transistor cannot be performed. The vertical plugs that are not used in this way become dummy plugs.

[0054] In this embodiment, since the first separation pattern (1SP) is formed to overlap only a portion of the vertical plugs arranged in a specific area rather than overlapping the entire set, a portion of the channel membranes may remain in all layers where drain selection lines are formed. Therefore, in this embodiment, even if the first separation pattern (1SP) is formed, all vertical plugs can be used as normal plugs.

[0055] When the vertical plugs included in the first vertical plug group (1GVPL) and the vertical plugs included in the second vertical plug group (2GVPL) are arranged in a zigzag direction relative to each other, since the areas overlapping in the first separation pattern (1SP) are different, the structure of each area is described as follows by referring to the cross-sections cut along the A-A' and B-B' cross-sections.

[0057] FIGS. 6a and 6b are cross-sectional views for explaining the structure of a memory device according to a first embodiment of the present invention, wherein FIG. 6a shows the A-A' cross-section of FIG. 5 and FIG. 6b shows the B-B' cross-section of FIG. 5.

[0058] Referring to FIG. 6a, in the A-A' section, a first separation pattern (1SP) may be formed to overlap a portion of the vertical plugs included in the first vertical plug group (1GVPL). The vertical plugs shown by dashed lines in FIG. 6a are other vertical plugs that do not appear in the A-A' section. The first separation pattern (1SP) may be formed to separate the drain select lines connected to the vertical plugs but not the word lines. For example, the 11th, 21st, and 31st drain select lines (DSL11, DSL21, DSL31) may be located to the left of the first separation pattern (1SP), and the 12th, 22nd, and 32nd drain select lines (DSL12, DSL22, DSL32) may be located to the right of the first separation pattern (1SP).

[0059] The bottom of the first separation pattern (1SP) may be located between the bottom of the drain selection line positioned at the bottom of the stacked drain selection lines and the word line. For example, the bottom of the first separation pattern (1SP) may have a depth that separates all the drain selection lines, a depth that separates the drain selection lines and the fourth dummy line (4DL), or a depth that separates the drain selection lines and the third and fourth dummy lines (3DL, 4DL). However, the first separation pattern (1SP) is formed so as not to come into contact with the word line located at the top.

[0060] The first separation pattern (1SP) can be formed to the right of the center of the vertical plug included in the first vertical plug group (1GVPL). Accordingly, a channel membrane (CH) may remain in the vertical plug remaining to the left of the area where the first separation pattern (1SP) is formed. Since the vertical plug in the portion that does not overlap with the first separation pattern (1SP) is surrounded by the 11th, 21st, and 31st drain selection lines (DSL11, DSL21, DSL31), a channel may or may not be formed in the channel membrane (CH) depending on the voltage applied to the 11th, 21st, and 31st drain selection lines (DSL11, DSL21, DSL31). Accordingly, among the drain selection transistors connected to the 11th, 21st, and 31st drain selection lines (DSL11, DSL21, DSL31), the drain selection transistors superimposed on the first separation pattern (1SP) can perform normal switching operations as transistors. For example, when a turn-off voltage of 0V or a negative voltage is applied to the 11th, 21st, and 31st drain selection lines (DSL11, DSL21, DSL31), the current path in the channel film (CH) remaining on the left side of the first separation pattern (1SP) is blocked, so the drain selection transistors can be turned off. When a positive turn-on voltage higher than 0V is applied to the 11th, 21st, and 31st drain select lines (DSL11, DSL21, DSL31), a current path is formed in the channel film (CH) remaining on the left side of the first separation pattern (1SP), so the drain select transistors can be turned on.

[0061] Referring to FIG. 6b, in the B-B' section, a first separation pattern (1SP) may be formed to overlap a portion of the vertical plugs included in the second vertical plug group (2GVPL). The vertical plugs shown by dashed lines in FIG. 6b are other vertical plugs that do not appear in the B-B' section. The first separation pattern (1SP) may be formed to separate the drain select lines connected to the vertical plugs but not the word lines. For example, the 11th, 21st, and 31st drain select lines (DSL11, DSL21, DSL31) may be located to the left of the first separation pattern (1SP), and the 12th, 22nd, and 32nd drain select lines (DSL12, DSL22, DSL32) may be located to the right of the first separation pattern (1SP).

[0062] The bottom of the first separation pattern (1SP) may be located between the bottom of the drain selection line positioned at the bottom of the stacked drain selection lines and the word line. For example, the bottom of the first separation pattern (1SP) may have a depth that separates all the drain selection lines, a depth that separates the drain selection lines and the fourth dummy line (4DL), or a depth that separates the drain selection lines and the third and fourth dummy lines (3DL, 4DL). However, the first separation pattern (1SP) is formed so as not to come into contact with the word line located at the top.

[0063] Since the first separation pattern (1SP) is the same pattern as the first separation pattern (1SP) shown in FIG. 6a, it can be formed to the left of the center of the vertical plug included in the second vertical plug group (2GVPL). Accordingly, a channel membrane (CH) may remain in the vertical plug remaining to the right of the area where the first separation pattern (1SP) is formed. Since the vertical plug in the portion that does not overlap with the first separation pattern (1SP) is surrounded by the 12th, 22nd, and 32nd drain selection lines (DSL12, DSL22, DSL32), a channel may or may not be formed in the channel membrane (CH) depending on the voltage applied to the 12th, 22nd, and 32nd drain selection lines (DSL12, DSL22, DSL32). Accordingly, among the drain selection transistors connected to the 12th, 22nd, and 32nd drain selection lines (DSL12, DSL22, DSL32), the drain selection transistors superimposed on the first separation pattern (1SP) can perform normal switching operations as transistors. For example, when a turn-off voltage of 0V or a negative voltage lower than that is applied to the 12th, 22nd, and 32nd drain selection lines (DSL12, DSL22, DSL32), the current path in the channel film (CH) remaining on the right side of the first separation pattern (1SP) is blocked, so the drain selection transistors can be turned off. When a positive turn-on voltage higher than 0V is applied to the 12th, 22nd, and 32nd drain select lines (DSL12, DSL22, DL32), a current path is formed in the channel film (CH) remaining to the right of the first separation pattern (1SP), so the drain select transistors can be turned on.

[0065] FIG. 7 is a perspective view illustrating the structure of a vertical plug that overlaps with a first separation pattern.

[0066] Referring to FIG. 7, even if the first separation pattern (1SP) overlaps with a portion of the vertical plug (VPL) included in the first vertical plug group (1GVPL), if a channel film (CH) remains in the portion of the vertical plug (VPL) that does not overlap with the first separation pattern (1SP), the transistor can operate using the remaining channel film (CH). Additionally, to prevent the occurrence of leakage current that may occur at the surface (SF) of the portion of the vertical plug (VPL) cut by the first separation pattern (1SP), impurities may be additionally injected into the surface (SF) of the cut portion.

[0067] The method for manufacturing a memory device according to the first embodiment described above is as follows.

[0069] FIGS. 8a to 8e are drawings for explaining a method for manufacturing a memory device according to a first embodiment of the present invention.

[0070] Referring to FIG. 8a, first to third source selection lines (SSL1~SSL3), first and second dummy lines (1DL, 2DL), first to i word lines (WL1~WLi), third and fourth dummy lines (3DL, 4DL), and first to third drain selection lines (DSL1~DSL3) are stacked spaced apart from each other on a source line (SL), and vertical plugs (VPL) can be formed that vertically penetrate the first to third source selection lines (SSL1~SSL3), first and second dummy lines (1DL, 2DL), first to i word lines (WL1~WLi), third and fourth dummy lines (3DL, 4DL), and first to third drain selection lines (DSL1~DSL3). Insulating films (IS) may be formed between the first to third source selection lines (SSL1~SSL3), the first and second dummy lines (1DL, 2DL), the first to i-th word lines (WL1~WLi), the third and fourth dummy lines (3DL, 4DL), and the first to third drain selection lines (DSL1~DSL3). The first to third source selection lines (SSL1~SSL3), the first to i-th word lines (WL1~WLi), and the first to third drain selection lines (DSL1~DSL3) may be formed of metallic materials such as tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), or semiconductor materials such as silicon (Si) or polysilicon (Poly-Si), but are not limited thereto. The insulating films (IS) may be formed of an oxide film or a silicon oxide film.

[0071] Vertical plugs (VPL) may be formed inside a vertical hole that vertically penetrates the first to third source selection lines (SSL1 to SSL3), first and second dummy lines (1DL, 2DL), first to i word lines (WL1 to WLi), third and fourth dummy lines (3DL, 4DL), and first to third drain selection lines (DSL1 to DSL3). The vertical plugs (VPL) may include a core pillar (CP) having a cylindrical shape, and a channel film (CH), a tunnel insulating film (TO), a charge trap film (CT), and a blocking film (BX) that sequentially wrap around the sides of the core pillar (CP). The tunnel insulating film (TO), the charge trap film (CT), and the blocking film (BX) may be memory films (ML). A second conductive film (CDb) may be formed on the upper part of the core pillar (CP). The core pillar (CP) can be formed from an insulating material such as an oxide film or a silicon oxide film. The channel film (CH) can be formed from a silicon film or a polysilicon film. Depending on the memory device, the core pillar (CP) may be omitted. In a structure without the core pillar (CP), the channel film (CH) may be formed in a cylindrical shape. The memory film (ML) may include a tunnel isolation layer (TO), a charge trap layer (CT), and a blocking layer (BX). The tunnel isolation layer (TO) may be made of an oxide film or a silicon oxide film. The charge trap layer (CT) may be made of a nitride film. The blocking layer (BX) may be made of an oxide film or a silicon oxide film. The vertical plugs (VPL) may be arranged in a zigzag shape in the planes of the first and second directions (X, Y directions), as shown in FIG. 5.

[0072] Referring to FIG. 8b, among the vertical plugs, a first trench (1Tc) may be formed that overlaps a portion of the vertical plugs included in the first vertical plug group (1GVPL) and the second vertical plug group (2GVPL) that are adjacent to each other. For example, the first trench (1Tc) may overlap a portion of the vertical plugs included in the first vertical plug group (1GVPL) and a portion of the vertical plugs included in the second vertical plug group (2GVPL). The first trench (1Tc) may be formed by sequentially etching structures formed on top of the vertical plugs. The etching process for forming the first trench (1Tc) may be performed until the third to first drain selection lines (DSL3~DSL1) are separated along the second direction (Y direction), and may be performed so that a portion of the channel film (CH) included in the vertical plug remains from the top. In order for the third to first drain selection lines (DSL3~DSL1) to be completely separated along the second direction (Y direction) by the first trench (1Tc), the first trench (1Tc) may be formed to be separated up to the fourth dummy line (4DL) or to be separated up to the third dummy line (3DL). Additionally, if a dummy line is formed between the drain selection line and the word line, defects in which the word line is exposed by the dummy line can be prevented during the etching process for forming the first trench (1Tc).

[0073] If the depth from the top of the vertical plugs to the bottom of the drain selection lines is defined as the minimum depth (DEn) and the depth from the top of the vertical plugs to the bottom of the dummy lines is defined as the maximum depth (DEm), then the depth (DE) of the first trench (1Tc) may be deeper than the minimum depth (DEn) and shallower than the maximum depth (DEm). FIG. 8B illustrates, as an example, a first trench (1Tc) separating the first to third drain selection lines (DSL1~DSL3) and the fourth dummy line (4DL).

[0074] Since the first trench (1Tc) is formed by etching a portion of the vertical plug, a portion of the second conductive film (CDb), core pillar (CP), channel film (CH), tunnel insulating film (TO), charge trap film (CT), and blocking film (BX) may be exposed through the side of the first trench (1Tc).

[0075] By the first trench (1Tc), the third drain selection line (DSL3) can be separated into 31st and 32nd drain selection lines (DSL31, DSL32), the second drain selection line (DSL2) can be separated into 21st and 22nd drain selection lines (DSL21, DSL22), and the first drain selection line (DSL1) can be separated into 11th and 12th drain selection lines (DSL11, DSL12). The fourth dummy line (4DL) can also be separated into dummy lines arranged to the left and right of the first trench (1Tc). The 31st, 21st, and 11th drain selection lines (DSL31, DSL21, DSL11) can be connected to vertical plugs included in the 1st vertical plug group (1GVPL), and the 32nd, 22nd, and 12th drain selection lines (DSL32, DSL22, DSL12) can be connected to vertical plugs included in the 2nd vertical plug group (2GVPL).

[0076] Referring to FIG. 8c, an impurity (DP) injection process can be performed on the inner surface of the first trench (1Tc). The impurity (DP) injection process can be performed to reduce leakage current that may occur in the drain select transistors included in the vertical plugs where the first trench (1Tc) is formed. For example, the impurity (DP) may be phosphorus, boron, argon, or arsenic ions, and various other ions may be used to prevent current leakage. As shown in FIG. 7, since the channel film (CH) is exposed through the surface (SF) of the first trench (1Tc) where the first separation pattern (1SP) is to be formed, the impurity (DP) injection process can be performed in a tilting manner. In the tilting type impurity (DP) injection process, the incident angle for injecting impurities (DP) is not limited to 90 degrees with respect to the substrate, and impurities (DP) can be injected into the target film at an incident angle lower or greater than 90 degrees. Accordingly, impurities (DP) can be uniformly injected into the channel film (CH) exposed through the side and bottom surfaces of the first trench (1Tc).

[0077] Referring to FIG. 8d, a first separation pattern (1SP) may be formed inside a first trench (1Tc) into which impurities (DP) are injected onto the surface. The first separation pattern (1SP) may be formed from an insulating material such as an oxide film or a silicon oxide film. For example, an insulating material may be applied over the entire structure in which the first trench (1Tc) is formed, and a flattening process may be performed until the upper surface of the vertical plug (VPL) is exposed, thereby forming a first separation pattern (1SP) remaining in the first trench (1Tc).

[0078] Referring to FIG. 8e, an interlayer insulating film (1ITL) may be formed on the entire structure including the first separation pattern (1SP). The interlayer insulating film (1ITL) may be made of an oxide film or a silicon oxide film. Subsequently, contact holes may be formed so that channel films (CH) included in the vertical plugs are exposed, and bit line contacts (BCT) made of a conductive material may be formed inside the contact holes. A bit line (BL) may be formed on the upper portion of the bit line contacts (BCT) and the interlayer insulating film (1ITL). Since the channel films (CH) of the vertical plugs that partially overlap with the first separation pattern (1SP) are also electrically connected to the bit line (BL) through the bit line contacts (BCT), not only the vertical plugs that do not overlap with the first separation pattern (1SP) but also the vertical plugs that partially overlap with the first separation pattern (1SP) may be used as normal plugs.

[0080] FIG. 9 is a circuit diagram for explaining a memory block according to a second embodiment of the present invention.

[0081] Referring to FIG. 9, in the memory block according to the second embodiment, the connection configuration of the remaining circuits, excluding the connection configuration of the source selection lines, is the same as the circuit shown in FIG. 3. Therefore, the description of the circuit connection identical to FIG. 3 is omitted, and the source selection lines are described as follows.

[0082] In the memory block according to the second embodiment, source selection lines can be separated from each other along a second direction (Y direction), like drain selection lines. For example, first to third source selection transistors (SST1 to SST3) included in different strings (ST) can be connected to source selection lines separated from each other by a second separation pattern. Specifically, each of the first to third source selection transistors (SST1 to SST3) arranged along the first direction (X direction) can be connected to the same source selection line, and the first to third source selection transistors (SST1 to SST3) arranged along the second direction (Y direction) can be connected to source selection lines separated from each other. For example, some of the first source selection transistors (SST1) can be connected to the eleventh source selection line (SSL11), and the rest can be connected to the twelfth source selection line (SSL12). The 12th source selection line (SSL12) is a line separated from the 11th source selection line (SSL11). Therefore, the voltage applied to the 11th source selection line (SSL11) may be different from the voltage applied to the 12th source selection line (SSL12). In this way, part of the 2nd source selection transistors (SST2) may be connected to the 21st source selection line (SSL21), and the remainder may be connected to the 22nd source selection line (SSL22). Part of the 3rd source selection transistors (SST3) may be connected to the 31st source selection line (SSL31), and the remainder may be connected to the 32nd source selection line (SSL32).

[0083] Although not shown in FIG. 9, dummy lines may be placed between the drain selection line and the word line, and dummy lines may also be placed between the source selection line and the word line.

[0085] FIG. 10 is a perspective view illustrating the arrangement of a memory array and peripheral circuits according to a second embodiment of the present invention.

[0086] Referring to FIG. 10, a memory cell array (110) may be placed on top of a peripheral circuit structure (PERI). A peripheral circuit structure (PERI) may be formed on a substrate, and a memory cell array (110) may be formed along a third direction (Z direction) from the peripheral circuit structure (PERI). That is, a memory cell array (110) may be stacked on top of the peripheral circuit structure (PERI). For example, the peripheral circuit structure (PERI) placed on the bottom of the memory cell array (110) may include a page buffer group or a row decoder.

[0088] FIG. 11 is a plan view for illustrating first and second separation patterns according to a second embodiment of the present invention.

[0089] Referring to FIG. 11, the 11th, 12th, 13th, and 14th drain selection lines (DSL11, DSL12, DSL13, DSL14) formed on the same layer can be separated from each other by a first separation pattern (1SP), and the 11th and 12th source selection lines (SSL11, SSL12) formed on the same layer can be separated from each other by a second separation pattern (2SP). For example, the first and second separation patterns (1SP, 2SP) can be formed in the form of lines extending in a first direction (X direction) and can be spaced apart from each other along a second direction (Y direction).

[0090] Within the memory block, vertical plugs (VPL) can be arranged in a zigzag pattern on the planes of the first and second directions (X, Y directions). The first and second separation patterns (1SP, 2SP) can overlap parts of adjacent vertical plugs along the first direction (X direction).

[0092] FIGS. 12a to 12h are drawings for explaining a method for manufacturing a memory device according to a second embodiment of the present invention.

[0093] Referring to FIG. 12a, a peripheral circuit structure (PERI) may be formed on a first substrate (1SB). For example, the peripheral circuit structure (PERI) may include a transistor (TR) capable of transmitting various voltages to memory cells included in a memory cell array or receiving voltages or currents changed by memory cells, first to third peripheral contacts (1PCT to 3PCT) configured to electrically connect the transistor (TR) to a cell structure (e.g., a memory block), first and second peripheral wirings (1PML, 2PML), and first junction pads (1BPA). For example, junction regions (JC) may be formed within the first substrate (1SB), and a gate insulating film (GIS) and a gate conductive pattern (GPT) may be formed on the first substrate (1SB) between the junction regions (JC). The junction region (JC), the gate insulating film (GIS), and the gate conductive pattern (GPT) may become the transistor (TR). A first or second peripheral contact (1PCT or 2PCT) may be formed on the upper portion of the junction regions (JC) included in the transistor (TR). A first peripheral wiring (1PML) may be formed on the upper portion of the first peripheral contact (1PCT), and a second peripheral wiring (2PML) may be formed on the upper portion of the second peripheral contact (2PCT). The first peripheral wiring (1PML) may be connected to a voltage generator configured to supply voltage to a cell structure. The transistor (TR), the first and second peripheral contacts (1PCT, 2PCT), and the first peripheral wiring (1PML) may be formed inside the second interlayer insulating film (2ITL). A second peripheral wiring (2PML) in contact with the second peripheral contact (2PCT) may be formed on the upper portion of the second interlayer insulating film (2ITL). A third interlayer insulating film (3ITL) may be formed on the upper portion of the second peripheral wiring (2PML), and third peripheral contacts (3PCT) and first bonding pads (1BPA) may be formed inside the third interlayer insulating film (3ITL).For example, third peripheral contacts (3PCT) may be formed on top of second peripheral wiring (2PML), and first bonding pads (1BPA) may be formed on top of third peripheral contacts (3PCT). The first bonding pads (1BPA) are pads for contacting the cell structure and the peripheral circuit structure (PERI) with each other, and may be formed of a high dielectric material capable of conducting electricity or of a conductive adhesive material. For example, the conductive adhesive material may be formed of a fluid material whose viscosity can be controlled through a solvent such as acetone, alcohol, etc., or of an epoxy resin, or of a composite having silver nanoparticles, boron nitride, and epoxy.

[0094] In addition to the structure shown in FIG. 12a, the peripheral circuit structure (PERI) may include various structures included in the peripheral circuit.

[0095] Referring to FIG. 12b, a cell structure (STK) including vertical pillars (VPL) and a first separation pattern (1SP) may be formed on a second substrate (2SB). A separation pattern (DPA) may be formed between the second substrate (2SB) and the cell structure (STK). The separation pattern (DPA) may be formed as a film to facilitate separation of the second substrate (2SB) from the cell structure (STK) in a subsequent process.

[0096] The cell structure (STK) may have first to third source selection lines (SSL1~SSL3), a first dummy line (1DL), first to i word lines (WL1~WLi), a second dummy line (2DL), and first to third drain selection lines (DSL1~DSL3) stacked spaced apart from each other on a separation pattern (DPA), and vertical plugs (VPL) that vertically penetrate the first to third source selection lines (SSL1~SSL3), the first dummy line (1DL), the first to i word lines (WL1~WLi), the second dummy line (2DL), and the first to third drain selection lines (DSL1~DSL3) may be formed. Insulating films (IS) may be formed between the first to third source selection lines (SSL1~SSL3), the first dummy line (1DL), the first to i-th word lines (WL1~WLi), the second dummy line (2DL), and the first to third drain selection lines (DSL1~DSL3). The first to third source selection lines (SSL1~SSL3), the first dummy line (1DL), the first to i-th word lines (WL1~WLi), the second dummy line (2DL), and the first to third drain selection lines (DSL1~DSL3) may be formed from metallic materials such as tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), or semiconductor materials such as silicon (Si) or polysilicon (Poly-Si), but are not limited thereto. The insulating films (IS) may be formed from an oxide film or a silicon oxide film.

[0097] A first upper insulating film (1ISu) formed on the upper part of the vertical plugs (VPL) among the insulating films (IS), and a fourth interlayer insulating film (4ITL) and first bit line contacts (1BCT) may be formed on the upper part of the vertical plugs (VPL). For example, the first bit line contacts (1BCT) may be formed to contact the channel film (CH) included in the vertical plugs (VPL). A bit line (BL) may be formed on the upper part of the fourth interlayer insulating film (4ITL) and the first bit line contacts (1BCT). A fifth interlayer insulating film (5ITL), second bit line contacts (2BCT), and second junction pads (2BPA) may be formed on the upper part of the bit line (BL). For example, the second bit line contacts (2BCT) may have a bit line (BL) formed on top, and the second bonding pads (2BPA) may be formed on top of the second bit line contacts (2BCT).

[0098] Referring to FIG. 12c, the cell structure (STK), the separation pattern (DPA), and the second substrate (2SB) are flipped, and the flipped cell structure (STK) is attached to the peripheral circuit structure (PERI). For example, the second junction pads (2BPA) are exposed at the bottom of the flipped cell structure (STK), and the first junction pads (1BPA) are exposed at the top of the peripheral circuit structure (PERI), so that the cell structure (STK) and the peripheral circuit structure (PERI) can come into contact with each other by bringing the first and second junction pads (1BPA, 2BPA) into contact with each other.

[0100] Referring to FIG. 12d, the second substrate (2SB) and the separation pattern (DPA) located on the top of the cell structure (STK) are separated from the cell structure (STK). For example, the second substrate (2SB) can be removed, and the separation pattern (DPA) remaining on the top of the cell structure (STK) can be removed by performing a cleaning or etching process.

[0101] Referring to FIG. 12e, among the vertical plugs, a second trench (2Tc) may be formed that overlaps a portion of the vertical plugs included in the first vertical plug group (1GVPL) and the second vertical plug group (2GVPL) that are adjacent to each other. For example, the second trench (2Tc) may overlap a portion of the vertical plugs included in the first vertical plug group (1GVPL) and a portion of the vertical plugs included in the second vertical plug group (2GVPL). The second trench (2Tc) may be formed by sequentially etching structures formed on top of the vertical plugs. The etching process for forming the second trench (2Tc) may be performed until the first to third source selection lines (SSL1 to SSL3) are separated along the second direction (Y direction), and may be performed so that a portion of the channel film (CH) included in the vertical plug remains from the top. Since the second trench (2Tc) is formed by etching a portion of the vertical plug, a portion of the core pillar (CP), channel film (CH), tunnel insulating film (TO), charge trap film (CT), and blocking film (BX) may be exposed through the side of the second trench (2Tc). Alternatively, the etching process to form the second trench (2Tc) may be performed until the first dummy line (1DL) is separated.

[0102] By the second trench (2Tc), the first source selection line (SSL1) can be separated into 11th and 12th source selection lines (SSL11, SSL12), the second source selection line (SSL2) can be separated into 21st and 22nd source selection lines (SSL21, SSL22), and the third source selection line (SSL3) can be separated into 31st and 32nd source selection lines (SSL31, SSL32). The 11th, 21st, and 31st source selection lines (SSL11, SSL21, SSL31) can be connected to vertical plugs included in the first vertical plug group (1GVPL), and the 12th, 22nd, and 32nd source selection lines (SSL12, SSL22, SSL32) can be connected to vertical plugs included in the second vertical plug group (2GVPL).

[0103] Referring to FIG. 12f, an impurity (DP) implantation process may be performed on the inner surface of the second trench (2Tc). The impurity (DP) implantation process may be performed to reduce leakage current that may occur in source-select transistors included in the vertical plugs in which the second trench (2Tc) is formed. For example, the impurity (DP) may be phosphorus, boron, argon, or arsenic ions, and various other ions may be used to prevent current leakage. The impurity (DP) implantation process may be performed in a tilting manner so that the impurity (DP) can be uniformly implanted on the inner surface of the second trench (2Tc). In the tilting impurity (DP) implantation process, the angle of incidence for implanting the impurity (DP) is not limited to 90 degrees with respect to the substrate, and the impurity (DP) may be implanted into the target film at an angle of incidence lower or greater than 90 degrees. Therefore, impurities (DP) can be uniformly injected into the channel membrane (CH) exposed through the side and bottom surfaces of the second trench (2Tc).

[0104] Referring to FIG. 12g, a second separation pattern (2SP) may be formed inside a second trench (2Tc) into which impurities (DP) are injected onto the surface. The second separation pattern (2SP) may be formed from an insulating material such as an oxide film or a silicon oxide film. For example, an insulating material may be applied over the entire structure in which the second trench (2Tc) is formed, and a flattening process may be performed until the upper surface of the vertical plug (VPL) is exposed, thereby forming a second separation pattern (2SP) remaining in the second trench (2Tc).

[0105] Referring to FIG. 12h, a source line (SL) may be formed on the entire structure including a second separation pattern (2SP). The source line (SL) may be formed of a conductive film or a metal film.

[0106] Since the channel membranes (CH) of the vertical plugs that overlap with the second separation pattern (2SP) in some areas are electrically connected to the source line (SL), not only the vertical plugs that do not overlap with the second separation pattern (2SP) but also the vertical plugs that overlap with the second separation pattern (2SP) in some areas can be used as normal plugs.

[0108] FIG. 13 is a drawing for explaining a memory device according to a third embodiment.

[0109] Referring to FIG. 13, first and second junction pads (1BPA, 2BPA) that bring the peripheral circuit structure (PERI) and the cell structure (STK) into contact with each other may be formed spaced apart from the third peripheral contacts (3CPT) and the second bit line contacts (2BCT). For example, the first junction pads (1BPA) may be formed in an area spaced apart from the third peripheral contacts (3PCT) within the third interlayer insulating film (3ITL), and the second junction pads (2BPA) may be formed in an area spaced apart from the second bit line contacts (2BCT) within the fifth interlayer insulating film (5ITL). When the first junction pads (1BPA) included in the peripheral circuit structure (PERI) and the second junction pads (2BPA) included in the cell structure (STK) come into contact with each other, the third peripheral contacts (3PCT) included in the peripheral circuit structure (PERI) can come into contact with the second bit line contacts (2BCT) included in the cell structure (STK).

[0111] FIG. 14 is a drawing showing a memory card system to which the memory device of the present invention is applied.

[0112] Referring to FIG. 14, the memory card system (3000) includes a controller (3100), a memory device (3200), and a connector (3300).

[0113] The controller (3100) is connected to the memory device (3200). The controller (3100) is configured to access the memory device (3200). For example, the controller (3100) may be configured to control program, read, or erase operations of the memory device (3200), or to control background operations. The controller (3100) is configured to provide an interface between the memory device (3200) and a host. The controller (3100) is configured to run firmware for controlling the memory device (3200). For example, the controller (3100) may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0114] The controller (3100) can communicate with an external device through a connector (3300). The controller (3100) can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller (3100) is configured to communicate with an external device through at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. For example, the connector (3300) may be defined by at least one of the various communication standards described above.

[0115] The memory device (3200) may include a plurality of memory cells and may be configured in the same way as the memory device (1100) shown in FIG. 1.

[0116] The controller (3100) and the memory device (3200) can be integrated into a single semiconductor device to form a memory card. For example, the controller (3100) and the memory device (3200) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash Card (CF), Smart Media Card (SM, SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro, eMMC), SD Card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0118] FIG. 15 is a drawing showing a Solid State Drive (SSD) system to which the memory device of the present invention is applied.

[0119] Referring to FIG. 15, the SSD system (4000) includes a host (4100) and an SSD (4200). The SSD (4200) transmits and receives signals with the host (4100) through a signal connector (4001) and receives power through a power connector (4002). The SSD (4200) includes a controller (4210), a plurality of memory devices (4221 to 422n), an auxiliary power supply (4230), and a buffer memory (4240).

[0120] The controller (4210) can control a plurality of memory devices (4221 to 422n) in response to a signal received from the host (4100). For example, the signal may be a signal based on an interface between the host (4100) and the SSD (4200). For example, the signal may be a signal defined by at least one of interfaces such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc.

[0121] A plurality of memory devices (4221 to 422n) may include a plurality of memory cells configured to store data. Each of the plurality of memory devices (4221 to 422n) may be configured identically to the memory device (1100) shown in FIG. 1. The plurality of memory devices (4221 to 422n) may communicate with the controller (4210) through channels (CH1 to CHn).

[0122] The auxiliary power supply unit (4230) is connected to the host (4100) via a power connector (4002). The auxiliary power supply unit (4230) receives power voltage from the host (4100) and can charge. The auxiliary power supply unit (4230) can provide power voltage to the SSD (4200) when power supply from the host (4100) is not smooth. For example, the auxiliary power supply unit (4230) may be located inside the SSD (4200) or outside the SSD (4200). For example, the auxiliary power supply unit (4230) may be located on the main board and provide auxiliary power to the SSD (4200).

[0123] The buffer memory (4240) operates as a buffer memory of the SSD (4200). For example, the buffer memory (4240) may temporarily store data received from the host (4100) or data received from a plurality of flash memories (4221 to 422n), or may temporarily store metadata (e.g., mapping tables) of the memory devices (4221 to 422n). The buffer memory (4240) may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc. Explanation of the symbols

[0125] 1SB: First substrate 2SB: Second substrate SL: Source line SSL: Source selection line DSL: Drain Select Line WL: Word Line BL: Bit line 1SP: First separation pattern 2SP: Second Isolation Pattern PERI: Peripheral Circuit Structure STK: Cell structure BPA: Bonding pad

Claims

Claim 1 A memory device comprising: first vertical plugs and second vertical plugs arranged adjacent to each other; a first selection line in contact with the first vertical plugs; a second selection line formed on the same layer as the first selection line and in contact with the second vertical plugs; a separation pattern that overlaps a portion of the first vertical plugs and a portion of the second vertical plugs and separates the first and second selection lines from each other; and impurities injected to prevent leakage current in a portion where the first and second vertical plugs and the separation pattern contact each other, wherein the lowest surface of the separation pattern is positioned at a lower level than the upper surfaces of the first and second vertical plugs, and the portion where the first and second vertical plugs and the separation pattern contact each other includes a portion where the first and second vertical plugs and the lowest surface of the separation pattern contact each other. Claim 2 In claim 1, the first and second vertical plugs are a memory device comprising select transistors and memory cells. Claim 3 A memory device according to claim 1, wherein the first and second vertical plugs comprise a core pillar vertically penetrating the first and second selection lines, a channel membrane surrounding the side of the core pillar; a tunnel insulating membrane surrounding the side of the channel membrane; a charge trap membrane surrounding the side of the tunnel insulating membrane; and a blocking membrane surrounding the side of the charge trap membrane. Claim 4 A memory device according to paragraph 3, wherein a portion of the channel membrane is removed by the separation pattern, and the remainder of the channel membrane remains in the layer where the separation pattern is formed. Claim 5 A memory device according to claim 1, further comprising: word lines stacked spaced apart from each other and in contact with the first and second vertical plugs; and dummy lines formed between the word lines and the first and second selection lines. Claim 6 A memory device according to claim 5, wherein among the word lines, the word lines formed on the same layer and in contact with the first and second vertical plugs are electrically connected to each other. Claim 7 In claim 5, the memory device in which the dummy lines formed on the same layer are separated from each other by the separation pattern. Claim 8 In claim 1, the separation pattern is a memory device formed of an insulating material. Claim 9 delete Claim 10 A memory device comprising: source lines, first selection lines, word lines, and second selection lines stacked on a substrate; first and second vertical plugs arranged spaced apart from each other and penetrating vertically the first selection lines, word lines, and second selection lines; a first separation pattern that overlaps with a portion of each of the first and second vertical plugs between the first and second vertical plugs and separates the first selection lines in a vertical direction; and a second separation pattern that overlaps with a portion of each of the first and second vertical plugs above the first and second vertical plugs and separates the second selection lines in the vertical direction, wherein the first separation pattern overlaps with a portion of the lower surface and a portion of the side wall of each of the first and second vertical plugs. Claim 11 In claim 10, each of the first and second vertical plugs comprises: a core pillar formed in a cylindrical shape; a channel membrane formed in a cylindrical shape surrounding the side of the core pillar; a tunnel insulating membrane formed in a cylindrical shape surrounding the outer surface of the channel membrane; a charge trap membrane formed in a cylindrical shape surrounding the outer surface of the tunnel insulating membrane; and a blocking membrane formed in a cylindrical shape surrounding the outer surface of the charge trap membrane. Claim 12 A memory device according to claim 11, wherein the core pillar, the channel membrane, the tunnel insulating membrane, the charge trap membrane, and the blocking membrane are removed in the portion where the first and second vertical plugs and the separation pattern overlap, and the core pillar, the channel membrane, the tunnel insulating membrane, the charge trap membrane, and the blocking membrane remain in the portion where the first and second vertical plugs and the separation pattern do not overlap. Claim 13 A memory device according to claim 12, further comprising: a bit line contact formed on the upper portion of the remaining channel membrane; and a bit line formed on the upper portion of the bit line contact. Claim 14 In paragraph 10, the above word lines are a memory device commonly connected to the first and second vertical plugs. Claim 15 In claim 10, the first selection lines separated from each other by the first separation pattern are electrically isolated from each other in a memory device. Claim 16 A memory device comprising: a peripheral circuit structure formed on a substrate; a cell structure that contacts the peripheral circuit structure through junction pads and includes a bit line, first selection lines, word lines, second selection lines, and a source line; first and second vertical plugs arranged spaced apart from each other and penetrating the cell structure vertically; a first separation pattern that overlaps a portion of the first and second vertical plugs at the bottom of the first and second vertical plugs and separates the first selection lines in a vertical direction; and a second separation pattern that overlaps a portion of the first and second vertical plugs at the top of the first and second vertical plugs and separates the second selection lines in a vertical direction, wherein the first separation pattern overlaps a portion of the bottom surface and a portion of the bottom sidewall of each of the first and second vertical plugs, and the second separation pattern overlaps a portion of the top surface and a portion of the top sidewall of each of the first and second vertical plugs. Claim 17 In claim 16, each of the first and second vertical plugs comprises: a core pillar formed in a cylindrical shape; a channel membrane formed in a cylindrical shape surrounding the side of the core pillar; a tunnel insulating membrane formed in a cylindrical shape surrounding the outer surface of the channel membrane; a charge trap membrane formed in a cylindrical shape surrounding the outer surface of the tunnel insulating membrane; and a blocking membrane formed in a cylindrical shape surrounding the outer surface of the charge trap membrane. Claim 18 A memory device according to claim 17, wherein a portion of the channel membrane adjacent to the first separation pattern is electrically connected to the bit line, and a portion of the channel membrane adjacent to the second separation pattern is electrically connected to the source line. Claim 19 In paragraph 16, the first and second separation patterns are memory devices formed of insulating material. Claim 20 In paragraph 16, the word lines are a memory device that is commonly connected to the first and second vertical plugs. Claim 21 A memory device according to claim 16, further comprising impurities injected into the surface in contact with the first and second vertical plugs and the first or second separation pattern. Claim 22 A method for manufacturing a memory device comprising: forming a stacked structure in which first selection lines, word lines, and second selection lines are stacked on a source line; forming first and second vertical plugs that penetrate the first selection lines, word lines, and second selection lines and are spaced apart from each other; forming a trench that overlaps a portion of the first and second vertical plugs and separates the second selection lines; injecting an impurity for preventing leakage current into the inner surface of the trench; and forming a separation pattern inside the trench, wherein the lower surface of the separation pattern is positioned at a lower level than the upper surfaces of the first and second vertical plugs, and the impurity for preventing leakage current is injected into a portion where the first and second vertical plugs and the lower surface of the separation pattern come into contact with each other. Claim 23 A method for manufacturing a memory device according to claim 22, wherein the step of forming the first and second vertical plugs comprises: forming first and second vertical holes penetrating the first selection lines, word lines and second selection lines; and forming a blocking film, a charge trap film, a tunnel insulating film, a channel film, and a core pillar along the inner surface of each of the first and second vertical holes. Claim 24 A method for manufacturing a memory device according to claim 23, wherein the step of forming the trench is performed by an etching process to remove a portion of the blocking film, the charge trap film, the tunnel insulating film, the channel film and the core pillar adjacent to each other at the first and second vertical plugs, and a portion of the second selection lines. Claim 25 delete Claim 26 A method for manufacturing a memory device according to claim 22, wherein the step of injecting the impurity to prevent leakage current is performed by controlling the angle of incidence of the impurity. Claim 27 A step of forming a peripheral circuit structure on a first substrate in which first junction pads are exposed; a step of forming a cell structure on a second substrate in which first selection lines, word lines, second selection lines, and second junction pads are stacked; a step of forming first and second vertical plugs arranged spaced apart from each other, penetrating the first selection lines, word lines, and second selection lines included in the cell structure; a step of forming a first trench that overlaps a portion of the first and second vertical plugs and separates the second selection lines; a step of injecting impurities for preventing leakage current into the inner surface of the first trench; a step of forming a first separation pattern inside the first trench; a step of flipping the entire structure formed on the second substrate and the second substrate, and adhering the second junction pads included in the flipped cell structure to the upper portion of the first junction pads included in the peripheral circuit structure; a step of removing the second substrate; A method for manufacturing a memory device comprising: a step of forming a second trench that overlaps a portion of the first and second vertical plugs and separates the first selection lines; a step of injecting the impurity for preventing leakage current into the inner surface of the second trench; and a step of forming a second separation pattern inside the second trench, wherein the uppermost surface of the first separation pattern is positioned at a higher level than the lower surface of the first and second vertical plugs, and the lowermost surface of the second separation pattern is positioned at a lower level than the upper surface of the first and second vertical plugs, and the impurity for preventing leakage current is injected into the portion where the first and second vertical plugs and the uppermost surface of the first separation pattern contact each other, and the portion where the first and second vertical plugs and the lowermost surface of the second separation pattern contact each other. Claim 28 A memory device according to claim 10, further comprising impurities injected to prevent leakage current in the portion where the first and second vertical plugs and the first separation pattern come into contact with each other and the portion where the first and second vertical plugs and the second separation pattern come into contact with each other. Claim 29 A memory device according to claim 16, further comprising impurities injected to prevent leakage current in the portion where the first and second vertical plugs and the first separation pattern come into contact with each other and the portion where the first and second vertical plugs and the second separation pattern come into contact with each other. Claim 30 In claim 22, the step of forming the trench is a method for manufacturing a memory device in which an etching process is performed such that the upper sidewall of each of the first and second vertical plugs is partially etched. Claim 31 In claim 27, the step of forming the first trench is a method for manufacturing a memory device in which an etching process is performed such that the upper sidewalls of each of the first and second vertical plugs are partially etched. Claim 32 In claim 27, the step of forming the second trench is a method for manufacturing a memory device in which an etching process is performed such that the upper sidewalls of each of the first and second vertical plugs are partially etched.

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