Test device and test system for semiconductor device

Abstract

A test device is provided. The test device comprises a main board, first and second DUT boards on which first and second semiconductor devices are respectively mounted as Device Under Test (DUT) on the main board, and first and second connectors spaced apart from each other at one end and the other end of the first DUT board, respectively, and transmitting first and second signals respectively, wherein the first signal forms a first electrical path input to the first DUT board via the first connector, and the second signal forms a second electrical path output from the first DUT board via the second connector and input to the second DUT board.

Description

Technology Field

[0001] The technical concept of the present invention relates to a test device and a test system for a semiconductor device, and more specifically, to a test device and a test system in which a plurality of semiconductor devices are mounted as Device Under Test (DUT). Background Technology

[0002] Driven by the rapid advancement of the electronics industry and user demands, electronic products are becoming smaller, more functional, and larger in capacity. Consequently, testing of semiconductor devices included in electronic products is also becoming more complex.

[0003] For example, in a test environment, dozens or hundreds of semiconductor devices may be tested simultaneously as Device Under Test (DUT). To this end, there is a need for test devices and test systems capable of meeting various test environments. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a test device for a semiconductor device with improved signal characteristics.

[0005] The technical problem that the present invention aims to solve is to provide a test system for a semiconductor device with improved signal characteristics.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A test device according to some embodiments of the present invention for achieving the above technical problem comprises a main board, first and second DUT boards on which first and second semiconductor devices are respectively mounted as Device Under Test (DUT) on the main board, and first and second connectors respectively spaced apart at one end and the other end of the first DUT board and transmitting first and second signals respectively, wherein the first signal forms a first electrical path input to the first DUT board via the first connector, and the second signal forms a second electrical path output from the first DUT board via the second connector and input to the second DUT board.

[0008] A test device according to some embodiments of the present invention for achieving the above technical problem comprises a main board, first and second DUT boards each having a first and second semiconductor device mounted on the main board as a Device Under Test (DUT), a first transmission line connected to an input terminal of the first DUT board and transmitting a first signal input to the first DUT board, and a second transmission line connected to an output terminal of the first DUT board and transmitting a second signal output from the first DUT board and input to the second DUT board, wherein the first and second transmission lines are not shared with each other.

[0009] A test system according to some embodiments of the present invention for achieving the above technical problem comprises a main board, first and second DUT boards each having a first and second semiconductor device mounted on the main board as a Device Under Test (DUT), a first transmission line connected to an input terminal of the first DUT board and transmitting a first signal input to the first DUT board, and a second transmission line connected to an output terminal of the first DUT board and transmitting a second signal output from the first DUT board and input to the second DUT board, wherein within the main board, no transmission line is formed between the input terminal and the output terminal.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIG. 1 is a drawing for explaining a test device according to some embodiments of the present invention. FIGS. 2 and FIGS. 3 are drawings for illustrating a test device according to some embodiments of the present invention. FIGS. 4 and FIGS. 5 are drawings for illustrating a test apparatus according to some embodiments of the present invention. FIG. 6 is a drawing for illustrating a test system according to some embodiments of the present invention. FIG. 7 is a diagram showing a semiconductor wafer on which a semiconductor device, which is a device under test (DUT), is placed. FIG. 8 is a block diagram showing how a semiconductor device, which is a device under test (DUT), is implemented as a memory element. Figure 9 is a diagram showing a semiconductor device, which is a device under test (DUT), being implemented as a semiconductor package. Specific details for implementing the invention

[0012] Embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0013] FIG. 1 is a drawing for explaining a test device according to some embodiments of the present invention.

[0014] Referring to FIG. 1, the test device (10) may include a test host area (110) and a DUT board mounting area (140). The test device (10) may include a main board (100), a connection part (101) disposed on one side of the main board (100), a test memory (120) and a test control part (130) disposed on the main board (100), a DUT board (200) connected to the main board (100) and on which a semiconductor device (300) is mounted as a Device Under Test (DUT), and a connector (250) connected to the DUT board (200).

[0015] The connection portion (101) may be disposed on one side of the main board (100) and may include a port (103) and a recess (105). The connection portion (101) may be a means for physically connecting a test device (10) to a test system (1000, see FIG. 6).

[0016] The port (103) may include a plurality of pins, and the number, size, and arrangement of the pins may be determined based on an interface connected to the test system (1000, see FIG. 6). The plurality of pins may be electrically connected to a socket included in the test system (1000, see FIG. 6). At least one recess (105) may be included in the connection part (101) to stably mount and secure the test device (10) to the test system (1000, see FIG. 6).

[0017] Test logic may be placed in the test host area (110). The test logic may be implemented as a semiconductor chip such as a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), or an Application Processor (AP), and may transmit and receive various information according to a parallel (or serial) communication method with the semiconductor device (300) which is the DUT. For example, the test logic may be configured using an FPGA such as Xilinx, Altera, Lattice Semiconductor, Microsemi, Achronix, QuickLogic, e2v, Atmel, etc., but is not limited thereto.

[0018] Additionally, the test logic may be placed on the main board (100), or the test logic may be placed outside the main board (100).

[0019] In some embodiments, a test input signal and / or test power (hereinafter collectively referred to as test input) can be provided from a test host area (110) to a DUT board mounting area (140) via a transmission line (150). A DUT board (200) within the DUT board mounting area (140) can receive the test input signal from the test host area (110).

[0020] This test logic can process data or interpret commands and execute. The test program executed in the test logic can perform a test by inputting a signal generated by an algorithm pattern generator into a semiconductor device (300) that is the subject of the test, reading a signal applied from the semiconductor device (300), and comparing the read output signal with an expected pattern.

[0021] Meanwhile, the test logic can identify the semiconductor device (300) to be tested as defective if the output signal does not match the expected pattern. For example, if the semiconductor device (300) is a memory element, the test program can record data generated by an algorithm pattern generator into the semiconductor device (300), read the recorded data from the semiconductor device (300), and compare the expected pattern with the read pattern.

[0022] The test memory (120) can store instructions of a test pattern or data read from a semiconductor device (300) and test results performed by test logic. The test memory (120) may be composed of a buffer and storage. For example, the buffer may be composed of volatile memory and the storage may be composed of non-volatile memory. In some embodiments, the buffer may be composed of DRAM and the storage may be composed of flash memory, an SSD (Solid State Drive), or an HDD (Hard Disk Drive). In some embodiments, the buffer may temporarily store signals or store data read from a semiconductor device (300) and test results to be transmitted. The storage may store instructions of a test pattern or test results.

[0023] The test control unit (130) can provide a bit stream having one or more bit information and test power to a DUT board (200) within a DUT board mounting area (140) using a transmission line (150). Additionally, the test control unit (130) can control the timing of when power is provided to the DUT board (200). For example, the test control unit (130) can control the signal applied to the semiconductor device (300) to have a frequency within 400 MHz.

[0024] The transmission line (150) can provide a test input from the test host area (110) to the DUT board mounting area (140). The transmission line (150) can provide a test input from the test host area (110) to the semiconductor device (300) within the DUT board (200).

[0025] Although not specifically illustrated, the DUT board (200) may include a substrate base and a DUT socket. Depending on the shape and type of the DUT to be tested, i.e., the semiconductor device (300), it may have various shapes and types of DUT sockets to accommodate it. For example, the DUT board (200) may include a DUT socket having a shape corresponding to a Ball grid array (BGA), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flatpack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), or Thin Quad Flatpack (TQFP), or it may include a universal DUT socket capable of accommodating various shapes. Of course, the DUT sockets included in the DUT board (200) are not limited to these.

[0026] A connector (250) may be arranged to be connected to each DUT board (200). A plurality of connectors (250_1 to 250_N) may be arranged at the ends of a plurality of DUT boards (200_1 to 200_N) to transmit input / output signals to each of the plurality of DUT boards (200_1 to 200_N).

[0027] A test process for determining whether a semiconductor device (300) is defective can be performed at various stages of the semiconductor manufacturing process, for example, including testing at the wafer stage and testing after the wafer stage. Testing at the wafer stage may correspond to testing individual semiconductor dies at the wafer stage. Additionally, testing after the wafer stage may be testing on semiconductor dies before packaging is performed, or testing on semiconductor packages after packaging of semiconductor dies is performed.

[0028] In particular, a burn-in test may refer to a test process for determining how much a semiconductor device (300) can withstand thermal stress, etc. when an electrical signal is applied to and operated on a semiconductor device (300).

[0029] Meanwhile, the semiconductor device (300) may be a device that performs various functions. In some embodiments, each of the plurality of semiconductor devices (300_1 to 300_N) may be a memory device including a memory cell array. For example, the memory device may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, or RDRAM (Rambus Dynamic Random Access Memory). Alternatively, the memory device may be a non-volatile memory such as flash memory, MRAM (Magnetic RAM), FRAM (Ferroelectric RAM), PRAM (Phase change RAM), RRAM (Resistive RAM), etc.

[0030] FIGS. 2 and FIGS. 3 are drawings for illustrating a test device according to some embodiments of the present invention.

[0031] Referring to FIGS. 2 and FIGS. 3, the test device (10) may include a main board (100), a DUT board (200), and a connector (250).

[0032] Each of the main board (100) and the DUT board (200) may be a printed circuit board (PCB).

[0033] The main board (100) may include a substrate base (100S), internal wiring (100L) contained within the substrate base (100S), and an electrode pad (100P) formed on the upper surface of the substrate base (100S). The aforementioned test memory (120), test control unit (130), and DUT board (200) may be electrically connected to the internal wiring (100L) through the electrode pad (100P).

[0034] The substrate base (100S) may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the substrate base (100S) may include at least one material selected from FR-4, tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (Bismaleimide triazine), Thermount, cyanate ester, polyimide, and liquid crystal polymer.

[0035] The electrode pad (100P) may be made of copper, nickel, stainless steel, or beryllium copper. The internal wiring (100L) may be formed on only one side of the substrate base (100S) or on both sides. The internal wiring (100L) may serve as a transmission line (150, see FIG. 1) in the main board (100).

[0036] Although not specifically illustrated, the number of copper foil layers can be formed to be three or more using prepreg, and by forming three or more layers of internal wiring (100L) according to the number of copper foil layers formed, a multilayer structure printed circuit board can be realized.

[0037] The test memory (120) and the test control unit (130) may be attached to the same side of the main board (100). Alternatively, the test memory (120) and the test control unit (130) may be attached to different sides of the main board (100).

[0038] The DUT board (200) can be placed on the main board (100) in a vertical direction (Z). A semiconductor device (300) can be mounted on each DUT board (200) as a Device Under Test (DUT).

[0039] Specifically, the DUT board (200) may include a first DUT board (200_1) on which a first semiconductor device (300_1) is mounted as a device to be tested, a second DUT board (200_2) on which a second semiconductor device (300_2) is mounted as a device to be tested, a third DUT board (200_3) on which a third semiconductor device (300_3) is mounted as a device to be tested, and a fourth DUT board (200_4) on which a fourth semiconductor device (300_4) is mounted as a device to be tested.

[0040] The DUT boards (200) may be spaced apart from each other in first and second directions (X, Y) that are parallel to and intersect with the upper surface of the main board (100). Referring to FIG. 2, the first to fourth DUT boards (200_1, 200_2, 200_3, 200_4) may be spaced apart from each other in the first direction (X). Referring to FIG. 1, parts of the first to Nth DUT boards (200_1 to 200_N) may be spaced apart from each other in the second direction (Y).

[0041] Meanwhile, although FIG. 2 shows that the number of semiconductor devices and the number of DUT boards are each 4, the number of semiconductor devices and the number of DUT boards are not limited to this and may be formed with a number other than 4.

[0042] The connector (250) is connected to the input / output terminals of the DUT board (200) and can transmit signals to and from each DUT board (200).

[0043] Specifically, the connector (250) may include a first connector (250_1) connected to a first semiconductor device (300_1), a second connector (250_2) connected to a second semiconductor device (300_2), a third connector (250_3) connected to a third semiconductor device (300_3), and a fourth connector (250_4) connected to a fourth semiconductor device (300_4).

[0044] In some embodiments, one end of the DUT board (200) may represent an area where the input terminal of the DUT board (200) is placed, and the other end of the DUT board (200) may represent an area where the output terminal of the DUT board (200) is placed.

[0045] The connector (250) may include a conductive material. For example, a material with low resistance may be used in the connector (250).

[0046] The first connector (250_1) may include a first connector (250_1a) and a first connector (250_1b) spaced apart at one end and the other end, respectively, of the first DUT board (200_1).

[0047] The 1a connector (250_1a) can be placed between the main board (100) and the first DUT board (200_1). The 1b connector (250_1b) can be placed between the main board (100) and the first DUT board (200_1).

[0048] The first connector (250_1a) can transmit a first input signal (IS1) input to the first DUT board (200_1), and the first connector (250_1b) can transmit a first output signal (OS1) output from the first DUT board (200_1).

[0049] The first input signal (IS1) can form a first electrical path that is input to the first DUT board (200_1) via the firsta connector (250_1a). The first input signal (IS1) can be transmitted from the main board (100) to the first DUT board (200_1) via the firsta connector (250_1a).

[0050] The first output signal (OS1) can form a second electrical path that is output from the first DUT board (200_1) via the first-b connector (250_1b) and input to the second DUT board (200_2). The first output signal (OS1) can be transmitted from the first DUT board (200_1) to the main board (100) via the first-b connector (250_1b). The first output signal (OS1) can be transmitted from the main board (100) to the second DUT board (200_2) via the second-a connector (250_2a) described later.

[0051] The transmission lines through which the first input signal (IS1) and the first output signal (OS1) are transmitted can each be implemented independently. That is, the first input signal (IS1) and the first output signal (OS1) can each be transmitted by the first a connector (250_1a) and the first b connector (250_1b), which are not shared with each other.

[0052] Accordingly, within the main board (100), a transmission line in which these signals are directly connected may not be formed between the first input signal (IS1) and the first output signal (OS1). The first output signal (OS1) may be connected back to the main board (100) through the first DUT board (200_1) and the first b connector (250_1b).

[0053] The second connector (250_2) may be spaced apart from the first connector (250_1). The second connector (250_2) may include a second connector (250_2a) and a second connector (250_2b) spaced apart from one end and the other end, respectively, of the second DUT board (200_2).

[0054] The 2a connector (250_2a) can be placed between the main board (100) and the second DUT board (200_2). The 2b connector (250_2b) can be placed between the main board (100) and the second DUT board (200_2).

[0055] The 2a connector (250_2a) transmits a second input signal (IS2) input to the second DUT board (200_2), and the 2b connector (250_2b) transmits a second output signal (OS2) output from the second DUT board (200_2).

[0056] The second input signal (IS2) can form a third electrical path that is input to the second DUT board (200_2) via the seconda connector (250_2a). The second input signal (IS2) can be transmitted from the main board (100) to the second DUT board (200_2) via the seconda connector (250_2a).

[0057] The second output signal (OS2) can form a fourth electrical path that is output from the second DUT board (200_2) via the second-b connector (250_2b) and input to the third DUT board (200_3). The second output signal (OS2) can be transmitted from the second DUT board (200_2) to the main board (100) via the second-b connector (250_2b). The second output signal (OS2) can be transmitted from the main board (100) to the third DUT board (200_3) via the third-a connector (250_3a) described later.

[0058] The transmission lines through which the second input signal (IS2) and the second output signal (OS2) are transmitted can each be implemented independently. That is, the second input signal (IS2) and the second output signal (OS2) can each be transmitted by the seconda connector (250_2a) and the secondb connector (250_2b), which are not shared with each other.

[0059] Accordingly, within the main board (100), a transmission line in which these signals are directly connected may not be formed between the second input signal (IS2) and the second output signal (OS2). The second output signal (OS2) can be connected back to the main board (100) through the second DUT board (200_2) and the secondb connector (250_2b).

[0060] The third connector (250_3) may be spaced apart from the second connector (250_2). The third connector (250_3) may include a third connector (250_3a) and a third connector (250_3b) spaced apart from one end and the other end, respectively, of the third DUT board (200_3).

[0061] The third-a connector (250_3a) can transmit a third input signal (IS3) input to the third DUT board (200_3), and the third-b connector (250_3b) can transmit a third output signal (OS3) output from the third DUT board (200_3).

[0062] The third input signal (IS3) can form a fifth electrical path that is input to the third DUT board (200_3) via the thirda connector (250_3a). The third input signal (IS3) can be transmitted from the main board (100) to the third DUT board (200_3) via the thirda connector (250_3a).

[0063] The third output signal (OS3) can form a sixth electrical path that is output from the third DUT board (200_3) via the third-b connector (250_3b) and input to the fourth DUT board (200_4). The third output signal (OS3) can be transmitted from the third DUT board (200_3) to the main board (100) via the third-b connector (250_3b). The third output signal (OS3) can be transmitted from the main board (100) to the fourth DUT board (200_4) via the fourth-a connector (250_4a) described later.

[0064] The transmission lines through which the third input signal (IS3) and the third output signal (OS3) are transmitted can each be implemented independently. That is, the third input signal (IS3) and the third output signal (OS3) can each be transmitted by the thirda connector (250_3a) and the thirdb connector (250_3b), which are not shared with each other.

[0065] Accordingly, within the main board (100), a transmission line in which these signals are directly connected may not be formed between the third input signal (IS3) and the third output signal (OS3). The third output signal (OS3) can be connected back to the main board (100) through the third DUT board (200_3) and the thirdb connector (250_3b).

[0066] The fourth connector (250_4) may be spaced apart from the third connector (250_3). The fourth connector (250_4) may include a fourth connector (250_4a) and a fourth connector (250_4b) spaced apart from one end and the other end, respectively, of the fourth DUT board (200_4).

[0067] The 4a connector (250_4a) transmits a fourth input signal (IS4) input to the fourth DUT board (200_4), and the 4b connector (250_4b) transmits a fourth output signal (OS4) output from the fourth DUT board (200_4).

[0068] The fourth input signal (IS4) can form a seventh electrical path that is input to the fourth DUT board (200_4) via the fourtha connector (250_4a). The fourth input signal (IS4) can be transmitted from the main board (100) to the fourth DUT board (200_4) via the fourtha connector (250_4a).

[0069] The fourth output signal (OS4) can form an eighth electrical path output from the fourth DUT board (200_4) via the fourth-b connector (250_4b). The fourth output signal (OS4) can be transmitted from the fourth DUT board (200_4) to the main board (100) via the fourth-b connector (250_4b). The fourth output signal (OS4) can be transmitted from the fourth DUT board (200_4) to the termination point (160) via the transmission line (150).

[0070] The transmission lines through which the fourth input signal (IS4) and the fourth output signal (OS4) are transmitted can each be implemented independently. That is, the fourth input signal (IS4) and the fourth output signal (OS4) can each be transmitted by the fourtha connector (250_4a) and the fourthb connector (250_4b), which are not shared with each other.

[0071] Accordingly, within the main board (100), a transmission line in which these signals are directly connected may not be formed between the fourth input signal (IS4) and the fourth output signal (OS4). The fourth output signal (OS4) can be connected back to the main board (100) through the fourth DUT board (200_4) and the fourthb connector (250_4b).

[0072] Referring to FIG. 3, the test device (10) is equipped with a DUT board (200) on which each semiconductor device (300) is placed, and the DUT board (200) can be classified into first and second groups (Group_1, Group_2).

[0073] Although only the first and second groups (Group_1, Group_2) are shown in the drawing, the number of groups is not limited thereto. Additionally, although the first and second groups (Group_1, Group_2) are shown as including the same number of DUT boards (200), they are not limited thereto. For example, the first and second groups (Group_1, Group_2) may include different numbers of DUT boards (200). Furthermore, the semiconductor device (300) on which the test is performed may be a semiconductor die or a semiconductor package.

[0074] With respect to the 5th to 8th DUT boards (200_5 to 200_8), 5th to 8th semiconductor devices (300_5 to 300_8), and 5th to 8th connectors (250_5 to 250_8), the description of the 1st to 4th DUT boards (200_1 to 200_4), 1st to 4th semiconductor devices (300_1 to 300_4), and 1st to 4th connectors (250_1 to 250_4) described above may be applied in the same way.

[0075] In addition, with respect to the 5th to 8th input signals (IS5 to IS8) and the 5th to 8th output signals (OS5 to OS8), the description regarding the 1st to 4th input signals (IS1 to IS4) and the 1st to 4th output signals (OS1 to OS4) described above may be applied in the same way.

[0076] According to some embodiments, in a semiconductor device, an input test signal and an output test signal can implement independent electrical paths. That is, the input test signal and the output test signal are not structured to branch within the main board via a single electrical path, but rather pass through different electrical paths. Accordingly, the stub of the test signal is reduced, and signal characteristics can be further improved.

[0077] FIGS. 4 and 5 are drawings for explaining a test apparatus according to some embodiments of the present invention. For convenience of explanation, descriptions of content identical to those described using FIGS. 1 to 3 may be omitted.

[0078] Referring to FIGS. 4 and 5, the test device (10) may further include connection boards (201, 202) that connect DUT boards (200). For example, the connection boards (201, 202) may be formed as part of the DUT board (200), but are not limited thereto.

[0079] The first connection board (201) may be positioned between the other end of the first DUT board (200_1) and one end of the second DUT board (200_2). That is, the first connection board (201) may be positioned between the output terminal of the first DUT board (200_1) and the input terminal of the second DUT board (200_2). The first connection board (201) may be spaced apart from the main board (100) in the vertical direction (Z).

[0080] The first output signal (OS1) and the second input signal (IS2) can be transmitted from the first DUT board (200_1) to the second DUT board (200_2) via the first connection board (201). The second output signal (OS2) can be transmitted from the second DUT board (200_2) to the main board (100) via the secondb connector (250_2b).

[0081] The second connection board (202) may be positioned between the other end of the third DUT board (200_3) and one end of the fourth DUT board (200_4). That is, the second connection board (202) may be positioned between the output terminal of the third DUT board (200_3) and the input terminal of the fourth DUT board (200_4). The second connection board (202) may be spaced apart from the main board (100) in the vertical direction (Z).

[0082] The third output signal (OS3) and the fourth input signal (IS4) can be transmitted from the third DUT board (200_3) to the fourth DUT board (200_4) via the second connection board (202). The fourth output signal (OS4) can be transmitted from the fourth DUT board (200_4) to the main board (100) via the fourthb connector (250_4b).

[0083] FIG. 6 is a drawing for illustrating a test system according to some embodiments of the present invention.

[0084] Referring to FIG. 6, the test system (1000) may be composed of a test facility including a test server (TS) and a test chamber (TC).

[0085] The test server (TS) can collectively refer to the main part of the test facility capable of storing the test program of the test system (1000), executing test commands, and determining the test results.

[0086] A test device (10) may be mounted in the test chamber (TC). In some embodiments, each test device (10) may receive test power from the power supply unit of the test server (TS) through a connection unit (101) while mounted in the test chamber (TC).

[0087] A DUT board (200) on which a semiconductor device (300) is placed can be connected to each test device (10). The semiconductor device (300) which is the DUT can be electrically connected to each test device (10) through the DUT board (200). The semiconductor device (300) can be received in a DUT socket and connected to the DUT board (200). Meanwhile, the DUT board (200) can be placed in the test device (10) first before receiving the semiconductor device (300) in the DUT socket.

[0088] In a test system (1000), a plurality of test devices (10) to which a semiconductor device (300) is connected are placed in a test chamber (TC) and exchange signals through communication with a test server (TS), and can perform a test on the semiconductor device (300).

[0089] Tests for the semiconductor device (300) may include, for example, burn-in tests, DC tests, AC tests, and functional tests. Specifically, a burn-in test may refer to a test to determine how much the semiconductor device (300) can withstand thermal stress, etc., when an electrical signal is applied to the semiconductor device (300) and it is operated. A DC test may involve inputting a voltage or current as a non-changing analog signal and then measuring the current in response to the voltage application or measuring the voltage in response to the current application. An AC test may involve inputting a voltage as a changing analog signal and then measuring the point in time when the measurement signal changes relative to a reference signal. The functional test may involve inputting a changing digital signal and then determining whether there is a logic error.

[0090] Tests on the semiconductor device (300) can be performed under ambient temperature conditions, low temperature conditions, high temperature conditions, etc., depending on the temperature set in the test chamber (TC). Additionally, tests on the semiconductor device (300) can be performed under dry conditions, high humidity conditions, etc., depending on the humidity set in the test chamber (TC). That is, according to the command of the test server (TS), the test chamber (TC) can provide various temperature and / or humidity environments.

[0091] After the test is completed, the semiconductor device (300) connected to the DUT board (200) can be disconnected. In some embodiments, the test server (TS) can separate the semiconductor device (300) that passed the test and the semiconductor device (300) that did not pass the test (i.e. failed the test) and disconnect them from the DUT board (200). In some embodiments, the test server (TS) can separate the semiconductor device (300) that failed the test from the DUT board (200) into a repairable semiconductor device (300), a semiconductor device (300) to be re-tested, and a semiconductor device (300) to be discarded. In other embodiments, the semiconductor device (300) to be re-tested may be re-tested without being disconnected from the DUT board (200). Alternatively, the semiconductor device (300) to be re-tested may be disconnected from the DUT board (200) where the test was performed, and then connected to another DUT board (200) to perform the re-test.

[0092] FIG. 7 is a diagram showing a semiconductor wafer on which a semiconductor device, which is a device under test (DUT), is placed.

[0093] Referring to FIG. 7, a plurality of semiconductor dies (400) manufactured by a semiconductor manufacturing process can be arranged in an array form on a semiconductor wafer (WF), and each of the plurality of semiconductor dies (400) can constitute a DUT during testing at the wafer stage.

[0094] The semiconductor wafer (WF) may be a silicon wafer (Si wafer). The semiconductor wafer (WF) may contain semiconductor elements such as germanium (Ge), or semiconductor compounds such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). Meanwhile, the semiconductor wafer (WF) may have a silicon-on-insulator (SOI) structure. For example, the semiconductor wafer (WF) may include a buried oxide layer. The semiconductor wafer (WF) may include conductive regions, for example, impurity-doped wells and / or impurity-doped structures. Additionally, the semiconductor wafer (WF) may have various device isolation structures, such as a shallow trench isolation (STI) structure.

[0095] The semiconductor device (300, see FIG. 1) on which the test is performed may be a semiconductor die (400). A plurality of semiconductor dies (400) may be composed of volatile memory devices or non-volatile memory devices. Volatile memory devices may be implemented in various ways, such as DRAM, SRAM, DDR DRAM (Double Data Rate DRAM), etc. Additionally, non-volatile memory devices may be implemented in various ways, such as flash memory, PRAM (Phase-change RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), MRAM (Magnetic RAM), etc. Contact pads capable of electrically connecting internal circuits and external devices may be formed on each of the plurality of semiconductor dies (400).

[0096] FIG. 8 is a block diagram showing a semiconductor device, which is a device under test (DUT), implemented as a memory element. For convenience of explanation, the description of content identical to that described using FIG. 1 to 5 may be omitted.

[0097] Referring to FIG. 8, the memory element (500) may include a memory cell array (511), a row decoder (512), and a column decoder (513) for memory operations of storing and reading data, and may include a control logic (520) that controls the overall operation inside the memory element (500) and a data buffer (530) that temporarily stores input / output data.

[0098] The control logic (520) can control memory operations according to various signals from the memory controller. For example, the control logic (520) can receive an address from the memory controller, provide a row address for selecting word lines of the memory cell array (511) to the row decoder (512), and provide a column address for selecting bit lines of the memory cell array (511) to the column decoder (513). Additionally, the control logic (520) may include a command decoder (521) that decodes a command from the memory controller to control the operation inside the memory element (500).

[0099] Meanwhile, the semiconductor device (300, see FIG. 1) on which the test is performed may be a memory device (500). In some embodiments, in a test environment for the memory device (500), information corresponding to a command / address from a test logic may be provided to the memory device (500) as a test input, and information corresponding to data may be provided to the memory device (500) as a test input. Additionally, in the test environment of the memory device (500), the memory device (500) may perform signal processing using the test input and, as a result, generate a test output and provide it to an external test logic.

[0100] FIG. 9 is a diagram showing a semiconductor device, which is a device under test (DUT), implemented as a semiconductor package. For convenience of explanation, descriptions identical to those described using FIG. 1 to 5 may be omitted.

[0101] Referring to FIG. 9, the semiconductor package (600) may include a plurality of semiconductor dies and may include one or more core dies (620) including a logic die (610) and a memory cell array (621).

[0102] The semiconductor package (600) may have increased bandwidth by including a plurality of channels (CH1 to CH8) having independent interfaces. The number of core dies (620) and the number of channels (CH1 to CH8) provided in the semiconductor package (600) may be varied.

[0103] The logic die (610) may include a TSV region (611), a physical region (612), and a direct access region (613). Additionally, the logic die (610) may further include control logic that controls the overall operation within the semiconductor package (600), and, for example, may perform internal control operations in response to a command from an external controller.

[0104] Meanwhile, the TSV area (611) corresponds to an area where a TSV is formed for communication with the core dies (620). Additionally, the physical area (612) may include a plurality of input / output circuits for communication with an external controller, and the direct access area (613) may communicate with a test server (TS, see FIG. 6) through a conductive means placed on the outer surface of the semiconductor package (600) during testing of the semiconductor package (600). Various signals provided from the test server (TS, see FIG. 6) may be provided to the core dies (620) through the direct access area (613) and the TSV area (611).

[0105] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0106] 100: Main board 200: DUT board 250: Connector 300: DUT 10: Test device 1000: Test System

Claims

Claim 1 A test device comprising: a main board; first and second DUT boards, each having a first and second semiconductor device mounted on the main board as a Device Under Test (DUT); and first and second connectors, each spaced apart from one end and the other end of the first DUT board and each transmitting a first and second signal, respectively, wherein the first signal forms a first electrical path input to the first DUT board via the first connector, and the second signal forms a second electrical path output from the first DUT board via the second connector and input to the second DUT board, and the second connector is positioned between the other end of the first DUT board and the one end of the second DUT board and spaced apart from the main board. Claim 2 In claim 1, the test device in which the first and second electrical paths are not shared with each other. Claim 3 In claim 1, the first connector is a test device positioned between the main board and the first DUT board. Claim 4 In paragraph 3, the first signal is a test device transmitted from the main board to the first DUT board via the first connector. Claim 5 A test device comprising: a main board; first and second DUT boards, each having a first and second semiconductor device mounted on the main board as a Device Under Test (DUT); and first and second connectors spaced apart from each other at one end and the other end of the first DUT board, respectively, and transmitting a first and a second signal, respectively, wherein the first signal forms a first electrical path input to the first DUT board via the first connector, and the second signal forms a second electrical path output from the first DUT board via the second connector and input to the second DUT board, and the second connector is positioned between the main board and the first DUT board. Claim 6 A test device according to claim 5, further comprising third and fourth connectors spaced apart at one end and the other end of the second DUT board, respectively, and transmitting third and fourth signals, respectively, wherein the second signal is transmitted from the first DUT board to the main board via the second connector and input from the main board to the second DUT board via the third connector. Claim 7 delete Claim 8 A test device according to claim 1, further comprising a third connector disposed at the other end of the second DUT board so as to be spaced apart from the second connector and transmitting a third signal, wherein the second signal is transmitted from the first DUT board to the second DUT board via the second connector, and the third signal is transmitted from the second DUT board to the main board via the third connector. Claim 9 A test device according to claim 1, further comprising third and fourth DUT boards spaced apart from the second DUT board, wherein third and fourth semiconductor devices are mounted as devices to be tested. Claim 10 A test device comprising: a main board; first and second DUT boards, each having a first and second semiconductor device mounted on the main board as a Device Under Test (DUT); a first transmission line connected to an input terminal of the first DUT board and transmitting a first signal input to the first DUT board; a second transmission line connected to an output terminal of the first DUT board and transmitting a second signal output from the first DUT board and input to the second DUT board; and first and second connectors spaced apart at one end and the other end of the first DUT board, respectively, wherein the first and second transmission lines are formed therein, the first and second transmission lines are not shared with each other, and the second connector is positioned between the main board and the first DUT board.

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