A memory device

Abstract

An electronic device including a memory device is provided. The electronic device includes a host that outputs an external clock signal, a chip enable signal, and at least one external enable signal, and a memory device that is activated according to the external clock signal and the chip enable signal and operates by generating an internal enable signal according to the at least one external enable signal, and the memory device generates and outputs a monitoring signal that monitors whether it operates according to the control of the host.

Description

Technology Field

[0001] The present invention relates to a memory device, specifically a static random access memory device (SRAM). Background Technology

[0002] The processor is configured to execute various entities such as firmware, operating systems, and applications, and to control peripheral devices. When the processor is operating, operational memory stores intermediate results resulting from computational operations.

[0003] Random Access Memory (RAM) is used as operational memory. RAM can be volatile or non-volatile. Volatile RAM loses information stored in volatile random access memory whenever power is removed, whereas non-volatile random access memory can retain its memory contents even when power is removed from the memory.

[0004] For automotive devices, reliability is critical for the operation and control of individual units. For processors and operating memory installed in automotive devices, while processing speed is important, data accuracy and the management of malfunctions are also critical. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a memory device capable of monitoring the command processing status of a host in real time.

[0006] The problem that the present invention aims to solve is to provide an electronic device and an automotive device that monitors the malfunction of a memory device.

[0007] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] An electronic device according to some embodiments of the present invention for solving the above problem comprises a host that outputs an external clock signal, a chip enable signal, and at least one external enable signal, and a memory device that is activated according to the external clock signal and the chip enable signal and operates by generating an internal enable signal according to the at least one external enable signal, wherein the memory device generates and outputs a monitoring signal that monitors whether it operates according to the control of the host.

[0009] An automotive device according to some embodiments of the present invention for solving the above problem comprises an automotive processor that outputs a target address, data, an external clock signal, a chip enable signal, and at least one external enable signal, and a processor embedded memory that is activated according to the external clock signal and the chip enable signal, generates an internal enable signal according to the at least one external enable signal, and performs a data access operation for the target address, wherein the processor embedded memory generates and outputs a real-time operation status according to the chip enable signal and at least one external enable signal as a monitoring signal. Brief explanation of the drawing

[0010] FIG. 1 shows a host and memory device according to an embodiment of the present invention. Figure 2 specifically illustrates the memory device shown in Figure 1. FIG. 3 specifically illustrates one embodiment of the memory device illustrated in FIG. 1. FIG. 4 specifically illustrates another embodiment of the memory device illustrated in FIG. 1. FIG. 5 is a flowchart for explaining the operation method of the memory device illustrated in FIG. 1. FIG. 6 is a flowchart for explaining the operation method of the memory device illustrated in FIG. 1. Figure 7 is an operation timing diagram when the memory device illustrated in Figure 1 is operating normally. Figure 8 is an operation timing diagram in the case where the memory device illustrated in Figure 1 malfunctions. FIG. 9 shows an electronic device according to an embodiment of the present invention. FIG. 10 shows an automotive processor and automotive devices according to an embodiment of the present invention. Specific details for implementing the invention

[0011] An embodiment of the present disclosure will be described in more detail below with reference to the attached drawings.

[0012] FIG. 1 shows a host and a memory device according to an embodiment of the present invention, and FIG. 2 specifically shows the memory device illustrated in FIG. 1.

[0013] Referring to FIG. 1, a host (10) is connected to a memory device (100) and controls the overall data access operations of the memory device (100). Data access operations include, for example, writing data to the memory device (100), reading data stored in the memory device (100), or deleting data. The memory device (100) may, for example, be placed separately from the host (10) and electrically connected, or, for another example, be included within the host (10) and embedded.

[0014] The host (10) may be a data processing device implemented in hardware having a circuit having a physical structure for executing desired operations. For example, the desired operations may include code or instructions included in a program. For example, the data processing device implemented in hardware may include a microprocessor, a central processing unit, a processor core, a multi-core processor, a main processor unit, a multiprocessor, a neural processor, an automotive processor, an application-specific integrated circuit (ASIC), and a field programmable gate array (FPGA).

[0015] The host (10) executes computer-readable code (e.g., software) stored in a memory device (e.g., non-volatile memory (not shown)) and instructions triggered by the host (10).

[0016] The memory device (100) may be, for example, a Static Random Access Memory (SRAM), and the following description will focus on an embodiment in which the memory device (100) is an SRAM. However, the present invention is not limited thereto, and the memory device (100) may be a volatile memory device other than SRAM.

[0017] The host (10) and the memory device (100) transmit and receive signals through a plurality of pins. The memory device (100) may include first to 16th pins A[16:8], peripheral pins (CK, CS, WE, OE) and monitoring pins (OPR, OPW).

[0018] The first to 16 pins A[16:8] can transmit and receive target addresses and data between the host (10) and the memory device (100). For example, the first to 8 pins A[16:8] can transmit and receive a first target address, and the 9th to 16 pins AD[7:0] can transmit and receive data or a second target address. For example, the first target address may be a row address of the target location to be accessed, and the second target address may be a column address of the target location to be accessed. Alternatively, the first target address may be a column address of the target location to be accessed, and the second target address may be a row address of the target location to be accessed.

[0019] A latch circuit (15) may be further included between the host (10) and the memory device (100). The latch circuit (15) may be connected differently depending on an Address Latch Enable (ALE) signal from the host (10). For example, when the ALE signal is enabled, the signal received by the 9th to 16th pins AD[7:0] of the host (10) may be viewed as a command or address and transmitted to A[7:0] of the memory device (100), and when the ALE signal is disabled, the signal may be viewed as data and transmitted to the input / output pin I / O[7:0] of the memory device (100), or the data output from the input / output pin I / O[7:0] of the memory device (100) may be transmitted to the pin AD[7:0] of the host (10).

[0020] The host (10) can provide a clock signal (CK, hereinafter referred to as an external clock signal) to the memory device (100).

[0021] The host (10) can output at least one external enable signal, for example, a chip enable signal (Chip Select, CS), a write enable signal ( / WR), and a read enable signal ( / RD), to peripheral pins of the memory device (100) (chip enable pin (CK), write enable pin (WE), and read enable pin (output enable signal, OE)).

[0022] In an exemplary embodiment, the write enable signal (WE) may maintain a static state (e.g., a high level or a low level) and then toggle between the high level and the low level. For example, the write enable signal (WE) may toggle during the interval in which a command (CMD) or an address (ADDR) is transmitted. Accordingly, the memory device (100) may obtain a command (CMD) or an address (ADDR) based on the toggle timings of the write enable signal (WE).

[0023] In the data (DATA) output operation of the memory device (100), the memory device (100) may receive a read enable signal ( / RD) that toggles before outputting the data (DATA). For example, the memory device (100) may transmit a data signal (DQ) based on the toggling of the read enable signal ( / RD).

[0024] The memory device (100) can output monitoring signals (OPR, OPW). The monitoring signal may be a signal of at least one bit output from at least one pin. For example, a read monitoring signal (OPR) and a light monitoring signal (OPW) may be output sequentially from one pin as at least two bits in a preset order. For example, a read monitoring signal (OPR) and a light monitoring signal (OPW) may be output from two pins, respectively.

[0025] The comparison unit (20) receives clock signals and control signals (CK, CS, WE, OE) output from the host (10) to the memory device (100), and monitoring signals (OPR, OPW) output from the memory device (100). It compares the output signals of the host (10) with the monitoring signals of the memory device (100) to monitor in real time whether the operation of the memory device (100) is normal, and transmits the comparison result (C) to the host (10). A detailed explanation of the operation of the comparison unit (20) will be described in FIGS. 5 and 6.

[0026] Referring to FIG. 2, the memory device (100) of FIG. 1 specifically includes a memory cell array (110), a row decoder (120), a column input / output unit (130), an input / output data circuit (140), and a control circuit (150).

[0027] The memory cell array (110) includes a plurality of memory cells, and operation data of the host (10) is written to the memory cells, or data stored in the memory cells is read or deleted.

[0028] The control circuit (150) controls the overall operation of the memory device (100). For example, it receives external enable signals (CS, WE, OE) and controls the operation of the row decoder (120), column input / output unit (130), and input / output data circuit (140), respectively.

[0029] The row decoder (120) receives an address from the host (10) through the first to eighth pins A[16:8] and enables the target row address of the memory cell array (110) according to the internal enable signal of the control circuit (150).

[0030] The input / output data circuit (140) transmits and receives commands, addresses, or data transmitted through the 9th to 16th pins A[7:0] or input / output pin IO[7:0] to the control circuit (150) or column input / output unit (130).

[0031] The column input / output unit (130) may, for example, write data received from the input / output data circuit (140) to at least one memory cell of the memory cell array (110) according to an internal enable signal. Alternatively, the column input / output unit (130) may, for example, read data from a memory cell at a target address according to an internal enable signal and output it to the input / output data circuit (140). Alternatively, the column input / output unit (130) may, for example, delete data from a memory cell at a target address according to an internal enable signal.

[0032] FIG. 3 specifically illustrates one embodiment of the memory device illustrated in FIG. 1.

[0033] The memory device (200) of FIG. 3 may include an internal clock generator (210), an internal enable signal generator (220), and a monitoring signal generator (230) according to some embodiments.

[0034] Each component within the memory device (200) of FIG. 3 may be included in the memory device (100) of FIG. 2. For example, each of the internal clock generator (210), internal enable signal generator (220), and monitoring signal generator (230) may be included in the control circuit (150). Alternatively, as another example, the internal clock generator (210) may be included separately from each component (110 to 150) of FIG. 2, and each of the internal enable signal generator (220) and monitoring signal generator (230) may be included in the control circuit (150). Alternatively, as yet another example, each of the internal clock generator (210), internal enable signal generator (200), and monitoring signal generator (230) may be included in the memory device separately from each component (110 to 150) of FIG. 2.

[0035] The internal clock generator (210) receives the chip enable signal (CS) and the external clock signal (CK) and generates an internal clock signal (ick). The internal clock signal (ick) is generated based on the external clock signal (CK) only when the chip enable signal (CS) is enabled. The internal clock signal (ick) may, for example, have the same frequency as the external clock signal (CK), or, for another example, have a frequency that is a multiple of the external clock signal (CK).

[0036] The internal enable signal generator (220) can generate an internal enable signal by receiving an internal clock signal (ick) and an external enable signal. For example, the internal enable signal generator (220) can generate an internal write enable signal (wre) synchronized with the internal clock signal (ick) from a write enable signal ( / WE) received from the host (10). For another example, the internal enable signal generator (220) can generate an internal sense amplifier enable signal (sae) synchronized with the internal clock signal (ick) from a read enable signal ( / RD) received from the host (10).

[0037] The internal sense amplifier enable signal (sae) is applied to the input / output data circuit (140) and the column input / output unit (130) of FIG. 2, respectively, so that data from the memory cell is read and output to the input / output data circuit (140) through the column input / output unit (130).

[0038] The internal write enable signal (wre) is applied to the input / output data circuit (140) and the column input / output unit (130) of FIG. 2, respectively, so that data received by the input / output data circuit (140) can be written to the memory cell through the column input / output unit (130).

[0039] The monitoring signal generator (230) receives an external clock signal (CK), an internal clock signal (ick), and internal enable signals (wre, sae) to generate and output a monitoring signal (OPR, OPW). For example, the monitoring signal generator (230) generates a monitoring signal based on at least one of the internal clock signal (ick) and the internal enable signals (wre, sae). The host (10) may continuously send multiple external enable signals to perform a desired operation, and the internal enable signal generator (220) generates internal enable signals in the order in which the external enable signals are received. After all operations of the memory device (100) according to the internal enable signals are performed, the monitoring signal generator (230) indicates the operation status as a monitoring signal. For example, a low-level monitoring signal is transitioned to a high level. As another example, the monitoring signal may indicate the operation status with an opposite logic level.

[0040] The monitoring signal generator (230) resets the monitoring signal based on an external clock signal (CK). For example, when the external clock signal (CK) rises, the monitoring signal can be reset to a preset logic level. Depending on various embodiments, the preset logic level may be a low level or a high level.

[0041] FIG. 4 specifically illustrates another embodiment of the memory device illustrated in FIG. 1.

[0042] Referring to FIG. 4, the monitoring signal generator (320) may include a plurality of flip-flop circuits (321-1 to 321-n). The plurality of flip-flop circuits (321-1 to 321-n) may be connected to each other in a chain. That is, at least one flip-flop circuit may be connected between the input flip-flop circuit (321-1) and the output flip-flop circuit (321-n).

[0043] "Connected in a chain" means that the output of the first flip-flop circuit is connected to the input of the second flip-flop circuit, and the output of the second flip-flop circuit is connected to the input of the third flip-flop circuit.

[0044] Each of the flip-flop circuits (321-1 to 321-n) is reset by an external clock signal (CK).

[0045] Each of the flip-flop circuits (321-1 to 321-n) outputs an output signal (Q) when it receives an input signal (D) and at least one of the internal enable signals (Internal Signal [A-1] to [An]) is applied. Specifically, the input signal (D) received by the flip-flop circuit in the preceding stage is output as an output signal (Q) when the internal enable signal (A) is rising or falling.

[0046] The input flip-flop circuit (321-1, or the first flip-flop circuit) stores the first logic signal upon receiving it, and then transmits the stored first logic signal to the next flip-flop circuit when the internal enable signal [A-1] transitions. In the same principle, the flip-flop circuits connected in a chain generate internal enable signals sequentially when the memory device (300) operates normally, and transmit the first logic signal to the next stage to be output through the output flip-flop circuit (321-n, or the final flip-flop circuit). The output flip-flop circuit (321-n) can output the output signal as a monitoring signal to the monitoring pin of the memory device (300).

[0047] Each of the multiple flip-flop circuits receives internal enable signals [A-1] to [An] respectively and outputs the stored data to the next stage. At this time, the internal enable signals [A-1] to [An] are internal enable signals that are sequentially generated in the memory device (300) based on external enable signals, and are generated in the order of the external enable signals output from the host (10).

[0048] For example, when the host (10) outputs an external enable signal in the order of the first lead (OE1), the second lead (OE2), the first write (WE1), and the second write (WE2), the internal enable signals [A-1] to [An] can be generated in the order of the internal clock signal (ick), the first sense amplifier enable (sae1), the second internal sense amplifier enable (sae2), the first internal write enable (wre1), and the second internal write enable (wre2). In this case, the first logic signal (H) is transmitted to the next flip-flop according to the internal clock signal (ick), and is transmitted from the flip-flop circuit of the preceding stage to the flip-flop circuit of the next stage according to the signals of the first sense amplifier enable (sae1), the second internal sense amplifier enable (sae2), the first internal write enable (wre1), and the second internal write enable (wre2). If the memory device (300) does not operate normally, for example, if the second internal write enable (wre2) is not properly generated, the first logic signal (H) is not output to the output of the output flip-flop (321-n), and a preset default state signal is output as a monitoring signal (OPR / OPW).

[0049] The comparison unit (20) compares the monitoring signal with the signal transmitted by the host (10) to determine which operation is not normal. In the above example, if a signal of a preset default state, rather than the first logic signal (H), is output, the comparison unit (20) detects this as a malfunction and can transmit a comparison result signal (C) to the host (10).

[0050] FIG. 5 is a flowchart for explaining the operation method of the monitoring signal generator illustrated in FIG. 2.

[0051] Referring to FIGS. 4 and 5, when the external clock signal (CK) rises from a low level to a high level (S10), the monitoring signal generator (230) resets all of the plurality of flip-flop circuits (321-1 to 321-n) to reset the monitoring signal (OPR) to a preset default state (e.g., low level) (S11).

[0052] When the chip enable signal (CS) is enabled and the internal clock signal (ick) is output, and the internal clock signal (ick) rises from a low level to a high level (S12), the input flip-flop circuit (321-1) transmits the first logic signal (H) that is initially input to the next flip-flop circuit (321-2). When the internal clock signal (ick) falls from a high level to a low level (S13), the flip-flop circuit (321-2) transmits the stored first logic signal (H) to the flip-flop circuit (321-3). When the internal write enable signal (wre) is enabled (rising) (S14), the flip-flop circuit (321-3) transmits the stored first logic signal (H) to the final flip-flop circuit (321-4). When the internal write-enable signal (wre) of the final flip-flop circuit (321-4) is polled (S15), the stored first logic signal (H) is output as a monitoring signal (OPW) from the final flip-flop circuit (321-4) (S17).

[0053] On the other hand, if the chip enable signal (CS) is not enabled and the internal clock signal is not polled (S13, No), or if the internal write enable signal (wre) is not raised (S14, No) or is not polled (S15, No), then the memory device (200) does not operate properly with respect to the write enable signal (WE) or the chip enable signal (CS), and the monitoring signal (OPW) is not output with the first logic signal transmitted, and can be output according to the preset default state (opposite level to the first logic signal) after reset.

[0054] FIG. 6 is a flowchart for explaining the operation method of the monitoring signal generator illustrated in FIG. 2.

[0055] Referring to FIGS. 4 and 6, when the external clock signal (CK) rises from a low level to a high level (S10), the monitoring signal generator (230) resets all of the plurality of flip-flop circuits (321-1 to 321-n) to reset the monitoring signal (OPW) to a preset default state (e.g., low level) (S21).

[0056] When the chip enable signal (CS) is enabled and the internal clock signal (ick) is output, and when the internal clock signal (ick) rises from a low level to a high level (S22), the input flip-flop circuit (321-1) transmits the first logic signal (H) that is initially input to the next flip-flop circuit (321-2). When the internal clock signal (ick) falls from a high level to a low level (S13), the flip-flop circuit (321-2) transmits the stored first logic signal (H) to the flip-flop circuit (321-3). When the sense amplifier enable signal (sae) is enabled (rising) (S24), the flip-flop circuit (321-3) transmits the stored first logic signal (H) to the final flip-flop circuit (321-4). When the sense amplifier enable signal (sae) is polled (S25), the final flip-flop circuit (321-4) outputs the stored first logic signal (H) as a monitoring signal (OPR) from the final flip-flop circuit (321-4) (S27).

[0057] On the other hand, if the chip enable signal (CS) is not enabled and the internal clock signal is not polled (S13, No), or if the sense amplifier enable signal (sae) is not raised (S24, No) or is not polled (S25, No), then the memory device (200) does not operate properly with respect to the read enable signal (RD) or the chip enable signal (CS), and the monitoring signal (OPW) is not output with the first logic signal transmitted, and can be output according to the preset default state (level opposite to the first logic signal) after reset.

[0058] FIG. 7 is an operation timing diagram when the memory device illustrated in FIG. 1 is operating normally, and FIG. 8 is an operation timing diagram when the memory device illustrated in FIG. 1 is operating incorrectly.

[0059] Let us assume that, according to some embodiments, FIGS. 7 and 8 operate in the order of a first write, a second write, a first read, and a second read according to the command sequence, and then enter a standby state after the four operations. The memory device (200) receives an external clock signal and an external enable signal from the host (10). Specifically, the memory device (200) enables the chip enable signal (CS) according to the external clock signal (CK) and outputs it at a high level, and outputs the write enable signal (WE) at a low level according to the first write and second write (interval t0 - t5).

[0060] The monitoring signal (OPW) is reset and maintains a low level when the external clock signal (CK) rises at t0, and then receives the first logic signal (H) and outputs a high level at t1 because the first internal write enable signal (wre) is enabled according to the first write. When the external clock signal (CK) rises at t3, the monitoring signal (OPW) is reset and becomes a low level. When the second internal write enable signal (wre) is enabled according to the second write, the monitoring signal (OPW) transitions from a low level back to a high level at t4 and outputs. Meanwhile, the write enable signal (WE) transitions from a low level to a high level at t5 when the write operation is finished.

[0061] Meanwhile, the monitoring signal (OPR) is reset and maintains a low level when the external clock signal (CK) rises at t7, and when the first read is input, the first sense amplifier enable signal (sae) is enabled according to the read enable signal (RD), so the first logic signal (H) is received and output at a high level at t8. When the external clock signal (CK) rises at t9, the monitoring signal (OPR) is reset and becomes a low level. When the second sense amplifier enable signal (sae) is enabled according to the second read, the monitoring signal (OPR) transitions from a low level back to a high level at t10 and is output.

[0062] Meanwhile, if the second lead operation is completed and no additional external enable signal is received, the chip enable signal (CS) is transitioned to a low level at t11, and the monitoring signals (OPR, OPW) are both reset at t12, which is the next rising time of the external clock signal (CK).

[0063] On the other hand, the signal diagram of the memory device (200) in FIG. 8 illustrates the case where the command for the second write, the chip enable signal (CS), and the write enable signal (WE) are normally output from the host (10).

[0064] Even though the commands and signals output from the host (10) are output normally, the memory device (200) does not properly perform flip-flop operations based on the rising or falling of the internal write enable signal (wre), so the first logic signal is not transmitted, and at t4, the monitoring signal (OPW) in the reset state (low level) is output.

[0065] Alternatively, even though the commands and signals (CK, CS, RD) output from the host (10) are output normally, the memory device (200) does not properly perform flip-flop operations based on the rising or falling of the sense amplifier enable signal (sae), so the first logic signal is not transmitted, and the monitoring signal (OPR) in a reset state (low level) at t8 can be seen output.

[0066] Alternatively, even though the chip enable signal from the host (10) is disabled, the monitoring signal (OPR) is output at a high level, so that the memory device (200) can be seen operating.

[0067] That is, the monitoring signals (OPR, OPW) can be compared in real time with the signals (CK, CS, WE, RD) input to the host (10) to perform intended operations on the memory device (200). Accordingly, the memory device according to the embodiments of the present invention can detect potential problems early on, such as when it performs an incorrect operation for the intended operation or operates on its own when the host does not give an operation command.

[0068] FIG. 9 shows an electronic device according to an embodiment of the present invention.

[0069] For example, the electronic device (1000) can be implemented as a smartphone, tablet computer, desktop computer, laptop computer, or wearable device. Furthermore, the electronic device (1000) can be implemented as one of various types of electronic devices required to operate an unmanned security system, the Internet of Things, or an autonomous vehicle.

[0070] The electronic device (1000) may include a main processor (1100), working memory (1300), storage (1400), display (1500), communication block (1600), and user interface (1700).

[0071] The main processor (1100) may be the host (10) described in FIGS. 1 to 8. The main processor (1100) may include an embedded memory (1200). The embedded memory (1200) may be the memory device (100) described in FIGS. 1 to 8.

[0072] The working memory (1300) can store data used for the operation of the electronic device (1000). For example, the working memory (1300) can temporarily store packets or frames processed by the processor (1120). For example, the working memory (1300) may include volatile memory such as DRAM (Dynamic RAM), SDRAM (Synchronous RAM), and / or non-volatile memory such as PRAM (Phase-change RAM), MRAM (Magneto-resistive RAM), ReRAM (Resistive RAM), FRAM (Ferro-electric RAM).

[0073] Storage (1400) may store firmware or software for performing an event reward scheme. Firmware or software for performing an event reward scheme may be read from storage (1400) and loaded into working memory (1300) upon a request or command from the main processor (1200). Storage (1400) may include non-volatile memory such as flash memory, PRAM, MRAM, ReRAM, FRAM, etc.

[0074] The display (1500) may include a display panel and a DSI (display serial interface) peripheral circuit. For example, the display panel may be implemented as various devices such as an LCD (Liquid Crystal Display) device, an LED (Light Emitting Diode) display device, an OLED (Organic LED) display device, an AMOLED (Active Matrix OLED) display device, etc. A DSI host embedded in the main processor (1200) can perform serial communication with the display panel via the DSI. The DSI peripheral circuit may include a timing controller, a source driver, etc., necessary to drive the display panel.

[0075] The communication block (1600) can exchange signals with an external device / system through an antenna. The transceiver (1610) and MODEM (Modulator / Demodulator, 1620) of the communication block (1600) can process signals exchanged with an external device / system according to wireless communication protocols such as LTE (Long Term Evolution), WIMAX (Worldwide Interoperability for Microwave Access), GSM (Global System for Mobile communication), CDMA (Code Division Multiple Access), Bluetooth, NFC (Near Field Communication), Wi-Fi (Wireless Fidelity), RFID (Radio Frequency Identification), etc.

[0076] The user interface (1700) may include at least one of input interfaces such as a keyboard, mouse, keypad, button, touch panel, touch screen, touchpad, touch ball, gyroscope sensor, vibration sensor, accelerometer sensor, etc.

[0077] The components of the electronic device (1000) can exchange data based on one or more of various interface protocols such as USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCIe (Peripheral Component Interconnect Express), M-PCIe (Mobile PCIe), ATA (Advanced Technology Attachment), PATA (Parallel ATA), SATA (Serial ATA), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), EIDE (Enhanced IDE), NVMe (Nonvolatile Memory Express), UFS (Universal Flash Storage).

[0078] Fig. 10 is Automotive processors and automotive devices according to embodiments of the present invention are shown.

[0079] Referring to FIG. 10, the automotive device (2000) may include an automotive processor (10), a memory device (100), and other individual devices (2100). The automotive processor (10) may be the host (10) described with reference to FIGS. 1 through 8.

[0080] Individual devices may include a brake controller (2100), a steering controller (2110), a power train controller (2120), a lamp controller (2130), an image sensor (2140), an engine controller (2150), a battery controller (2160), a wiper controller (2170), a safety controller (2180), and a display controller (2190).

[0081] The brake controller (2100) may include sensors that detect the state of the brake. The brake controller (2100) may transmit the detection results of the sensors to the automotive processor (10). The brake controller (2100) may further include a controller for controlling the brake. The brake controller (2100) may receive a control command from the automotive processor (10). The brake controller (2100) may control the brake according to the control command.

[0082] The steering controller (2110) may include sensors that detect the state of the steering wheel. The steering controller (2110) may transmit the detection results of the sensors to the automotive processor (10). The steering controller (2110) may further include a controller for controlling the steering wheel. The steering controller (2110) may receive a control command from the automotive processor (10) and control the steering wheel according to the control command.

[0083] Likewise, the power train controller (2120) can transmit the detection results of the sensors for the power train to the automotive processor (10). The power train controller (2120) can control the power train according to control commands from the automotive processor (10). The lamp controller (2130) can transmit the detection results of the sensors for the lamps to the automotive processor (10). The lamp controller (2130) can control the lamps according to control commands from the automotive processor (10).

[0084] The image sensor (2140) can encode a scene within the field of view into image data and transmit the image data to the automotive processor (10). The engine controller (2150) can transmit the detection results of the sensors regarding the engine to the automotive processor (10). The engine controller (2150) can control the engine according to a control command from the automotive processor (10).

[0085] The battery controller (2160) can transmit information about the state of the battery to the automotive processor (10). The battery controller (2160) can control the settings of the battery according to a control command from the automotive processor (10). The wiper controller (2170) can transmit the detection results of sensors regarding the external environment (e.g., whether it is raining) to the automotive processor (10). The wiper controller (2170) can control the wipers according to a control command from the automotive processor (10).

[0086] The safety controller (2180) can transmit detection results from sensors for safety devices, such as seat belts, airbags, and electronically controlled suspension (ECS), to the automotive processor (10). As another example, the safety controller (2180) can transmit detection results for an external environment (e.g., tilting, falling, collision, etc.) to the automotive processor (10). The safety controller (2180) can control the safety devices according to control commands from the automotive processor (10).

[0087] The display controller (2190) can transmit the detection results of sensors regarding the external environment (e.g., illuminance, movement speed, etc.) to the automotive processor (10). According to a control command from the automotive processor (10), the display controller (2190) can adjust the illuminance of the display device or limit the content displayed.

[0088] In the embodiments described above, components according to embodiments of the present invention are referred to using the terms “part,” “module,” or “block.” A “part,” “module,” or “block” may be implemented in the form of various hardware devices such as IC (Integrated Circuit), ASIC (Application Specific IC), FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device), software such as firmware or applications running on hardware devices, or a combination of hardware devices and software. Additionally, a “part,” “module,” or “block” may include circuits composed of semiconductor devices within an IC or IP (Intellectual Property).

[0089] Even if not otherwise defined in the embodiments described above, the components mentioned in the embodiments described above may be implemented as various hardware devices, software such as firmware or applications running on the hardware devices, a combination of hardware devices and software, or IP.

[0090] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0091] 10 : Host 15: Latch circuit 20 : Comparison section 100, 200, 300: Memory device

Claims

Claim 1 An electronic device comprising: a host that outputs an external clock signal, a chip enable signal, and at least one external enable signal; a memory device that is activated according to the external clock signal and the chip enable signal and operates by generating an internal enable signal according to the at least one external enable signal, wherein the memory device generates and outputs a monitoring signal for monitoring whether it operates according to the control of the host, and comprises a plurality of flip-flop circuits connected in a multi-chain manner, wherein an internal clock signal or at least one of the internal enable signals is applied to each of the memory devices, wherein the first flip-flop circuit among the plurality of flip-flop circuits outputs a first logic signal to the next flip-flop circuit according to the internal clock signal, and the final flip-flop circuit among the plurality of flip-flop circuits outputs the output of the previous flip-flop circuit as the monitoring signal according to at least one of the internal enable signals. Claim 2 An electronic device according to claim 1, wherein the host determines whether the memory device is operating normally by comparing the chip enable signal and the external enable signal with the monitoring signal. Claim 3 In claim 1, the memory device is an electronic device that generates the external clock signal as an internal clock signal when the chip enable signal is activated. Claim 4 In paragraph 3, the memory device is an electronic device that generates the external enable signal as the internal enable signal when the internal clock signal is activated. Claim 5 An electronic device according to claim 1, wherein the memory device comprises: an internal clock generator that generates the external clock signal received from the host into the internal clock signal according to the chip enable signal; an internal enable signal generator that operates with the internal clock signal and generates the external enable signal into the internal enable signal; and a monitoring signal generator that outputs a monitoring signal generated based on at least one of the internal clock signal and the internal enable signal to the host. Claim 6 In paragraph 5, the monitoring signal generator is an electronic device that generates the monitoring signal by monitoring whether the internal clock signal or the internal enable signal rises or falls in the operating order of the external enable signal. Claim 7 An electronic device according to claim 5, wherein the plurality of flip-flop circuits are all reset based on the external clock signal. Claim 8 An automotive device comprising: an automotive processor that outputs a target address, data, an external clock signal, a chip enable signal, and at least one external enable signal; a processor embedded memory that is activated according to the external clock signal and the chip enable signal, generates an internal enable signal according to the at least one external enable signal, and performs a data access operation for the target address, wherein the processor embedded memory generates and outputs a real-time operation state according to the chip enable signal and at least one external enable signal as a monitoring signal, and the processor embedded memory includes a plurality of flip-flop circuits connected in a daisy chain, to which an internal clock signal or the internal enable signal is applied, wherein the first flip-flop of the daisy chain outputs a first logic signal to the next flip-flop according to the internal clock signal, and the last flip-flop of the daisy chain outputs the output of the previous flip-flop as the monitoring signal according to at least one internal enable signal. Claim 9 An automotive device according to claim 8, wherein the processor embedded memory generates the internal enable signal according to the order in which the multiple external enable signals are received consecutively, and displays the monitoring signal after all the consecutively generated internal enable signals have been executed. Claim 10 In paragraph 8, the internal enable signal is an automotive device in which the internal enable signal is a sense amplifier enable signal or an internal light enable signal.

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