Method for detecting errors in electronic memory

Abstract

The present invention relates to a method for detecting at least one error caused by photoelectric or radiation effects in a non-volatile semiconductor memory, wherein the memory comprises a plurality of memory cells (CM) having MOS transistors, possibly floating gate transistors, each memory cell is located at the intersection of a base bit line (BLE) and a word line (WL), and the binary content of the memory cell is read by detecting a read current (Ilecture) flowing through the memory cell during a read after the memory cell is selected by the base bit line and the word line. In the method, when reading or programming the memory cell, the possible presence of at least one error is detected by performing a comparison between the total current flowing through the base bit line where detection occurs and a predefined threshold (Ialarm) indicating the presence of at least one error.

Description

Technology Field

[0001] The present invention relates to the detection of read and write defects in electronic memory, more specifically, in non-volatile semiconductor memories. Background Technology

[0002] The injection of transient faults into integrated circuits is commonly used to attack integrated circuits and security systems. Pulsed lasers provide a convenient and easily controllable method for injecting such faults by generating transient currents in PN junctions or transistor channels through the photoelectric effect.

[0003] Many types of countermeasures to counter these laser attacks have been reported in the literature, namely physical barriers (e.g., metal shields), device architectures with small sensitive volumes (e.g., fully depleted silicon-on-insulator: FD-SOI), hardware redundancy to detect malfunctions in compromised circuits, and scrambling and encryption techniques.

[0004] These approaches have disadvantages and / or weaknesses.

[0005] Shielding approaches may be incompatible with integrated circuit manufacturing limits (e.g., metal density rules) or may limit performance. Devices with inherently low photon sensitivity generally compromise other aspects of device performance and, in some cases, can be neutralized by increasing the incident light intensity. Hardware redundancy is effective but requires redundant circuit functions, is costly in terms of silicon footprint, and can be bypassed using attacks that affect redundancy paths in the same way. Scrambling and encryption can also be disrupted through reverse engineering.

[0006] Publications such as Colombier et al.'s "Laser-induced Single bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller", Garb et al.'s "Temporary Laser Fault Injection into Flash Memory: Calibration, Enhanced Attacks, and Countermeasures", Menu et al.'s "Single-bit Laser Fault Model in NOR Flash Memories: Analysis and exploitation", Sakamoto et al.'s "Laser-Induced Controllable Instruction Replacement Fault Attack", and Viera et al.'s "Permanent Laser Fault Injection into the Flash Memory of a Microcontroller" disclose attacks based on the injection of faults into memories and specific techniques to counter them. The problem to be solved

[0007] There remains a need to further improve methods for detecting defects in memory, particularly in terms of efficiency, practicality, reliability, and cost. means of solving the problem

[0008] The present invention aims to satisfy these objectives, and according to one embodiment, relates to a method for detecting at least one defect caused by a photoelectric or radiative effect in a non-volatile semiconductor memory, wherein the memory is, in particular, a NOR flash memory, an EEPROM, or a ROM, and the memory comprises a plurality of memory cells including MOS transistors, potentially floating-gate MOS transistors, and each memory cell is located at the intersection of a basic bit line and an associated word line, and

[0009] The binary content of a memory cell is read by detecting the read current flowing through this memory cell during a read after this memory cell has been selected by the basic bit line and word line associated with this memory cell, and

[0010] In the method, to detect the potential presence of at least one defect during the reading of one or more memory cells, a comparison is made between the total current flowing through one or more associated basic bit lines and a predefined threshold indicating the presence of at least one defect in these one or more memory cells.

[0011] In particular, according to one of its embodiments, the present invention relates to a method for detecting at least one defect caused by a photoelectric or radiation effect in a non-volatile semiconductor memory, wherein the memory is, in particular, a NOR flash memory, an EEPROM, or a ROM, and the memory comprises a plurality of memory cells including MOS transistors, potentially floating-gate MOS transistors, and each memory cell is located at the intersection of a basic bit line and a word line, and

[0012] In that method:

[0013] - To detect the potential presence of at least one defect during the reading of a memory cell, the binary content of the memory cell is read by detecting the read current flowing through the memory cell during the reading after the memory cell is selected by the basic bit line and the word line, and

[0014] A comparison is performed between the total current flowing through the basic bit line to which the memory cell being read belongs, or through at least one basic bit line other than to which the memory cell being read belongs, and a predefined threshold indicating the presence of at least one defect in one or more memory cells other than the one being read, and / or

[0015] - During programming of at least one memory cell, particularly when at least one memory cell is a NOR flash memory or EEPROM, in order to detect the potential presence of at least one defect, a comparison is made between the current flowing through at least one basic bit line other than the one to which the memory cell being programmed belongs and a predefined threshold indicating the presence of at least one defect in this line.

[0016] Programming, also referred to as writing, consists of storing electrons in the floating gate of a floating gate transistor of a flash memory or a floating gate state transistor of an EEPROM memory cell.

[0017] The present invention makes it possible to obtain a method for detecting read or write defects that are reliable and relatively simple to implement.

[0018] The method according to the present invention protects the process of writing a program or data to memory.

[0019] Reading or writing defects

[0020] Read or write defects affect the instructions of a program or the words of data used by the program, and these instructions or data are stored in memory.

[0021] These defects may be created by exposing an integrated circuit to laser pulses for attack purposes. The parameters of the laser pulses are selected to ionize the semiconductor material through the photoelectric effect and to cause the appearance of a transient photoelectric current between the drain of a MOS transistor (possibly a floating-gate MOS transistor) and the substrate. In the case of a read operation, this current causes one or more bits of the read word to be misread. In the case of a write operation, this current causes one or more bits of the written word to be misprogrammed.

[0022] Defects may also be created as a result of exposure to ionizing radiation, whether intentionally or accidentally, for the purpose of attack, when the memory is exposed to a radiation source that emits ionizing particles (heavy ions or protons, neutrons, X-rays and gamma rays).

[0023] Whether generated by ionizing particles or through the photoelectric effect, the disrupting current is I below PH It will be written as.

[0024] In the case of a readout defect, the defect is generally transient and ceases after the induced charge is withdrawn.

[0025] The defect may affect one or more memory cells simultaneously.

[0026] It should be noted that while a read fault does not alter the binary value stored in the memory cell affected by the fault, it causes temporary corruption of the read binary value. In the case of a write fault, the corrupted value is stored in the memory cell affected by the fault. This corruption is temporary and can be corrected by writing the correct value when the memory cell is programmed next.

[0027] The detection method according to the present invention is preferably activated during the reading or programming of a memory cell. The detection method according to the present invention may also be activated before and / or after the reading or programming of the memory cell.

[0028] predefined threshold

[0029] The predefined threshold, in the case of a current, is also referred to as the alarm current.

[0030] A predefined threshold is selected based on the architecture of the detection circuit and, depending on the situation, may correspond to a current lower or higher than the reading current generally observed in the absence of a defect, which is, for example, substantially equal to twice the intensity of the reading current generally observed in specific embodiments of the present invention. The current for which comparison is performed may flow through the same basic bit line selected for reading, or through at least one other line, particularly an adjacent line, as described below.

[0031] Basic bit line where detection is performed

[0032] In the case of detecting a read defect, the at least one basic bit line on which defect detection is performed may be associated with the memory cell being read.

[0033] The at least one basic bit line where defect detection is performed may be adjacent to one associated with the memory cell being read or programmed.

[0034] Defect detection may also be performed through a single line adjacent to that associated with the memory cell being read or programmed.

[0035] Defect detection may also be performed through two lines next to the basic bit line associated with the memory cell being read or programmed.

[0036] The at least one basic bit line for which defect detection is performed may belong to the same block as the memory cell being read or programmed; the block is typically defined as a set of basic bit lines, of which only one is selected to be read or programmed.

[0037] The at least one basic bit line on which defect detection is performed may belong to a block that follows or precedes a memory cell being read or programmed; these blocks are generally located near the memory.

[0038] Error detection may be performed through one or more base bit lines that may be affected, and these bit lines may be relatively far from the memory cell being read or programmed, and may not necessarily be adjacent to the line associated with the memory cell being read or programmed. Error detection through one or more lines located near the memory cell being read or programmed, in particular, adjacent lines, is preferred.

[0039] Detection may be performed in the region of influence of the interference mechanism, that is, in the region where the induced interference current is high enough to generate a defect. This region may extend across multiple lines and / or may relate to multiple transistors (or memory cells) of each line in the region of influence.

[0040] Error detection by splitting word lines

[0041] In some examples of implementation, the memory comprises divided word lines, and each pair of word lines (of index (p)) has a word line of even index (2k) and a word line of odd index (2k+1), and the gates of the transistors of the memory cells are alternately connected to the word line of even index and the corresponding word line of odd index, and at least one pair of word lines causes one of the lines to be raised to a read potential or write potential to activate the connected memory cells and the other of the lines to be raised to a potential to deactivate the connected memory cells, thereby enabling the read memory cells of all other basic bit lines or programming all other basic bit lines, and performing fault detection on said at least one basic bit line adjacent to that associated with the memory cell being read or programmed. Thus, said at least one basic bit line adjacent to that associated with the memory cell being read or programmed is electrically isolated and thus allows current to pass only in the event of a laser attack or radiation event. Accordingly, the threshold of the alarm current may be set lower than when an adjacent basic bit line also passes a read current. In particular, in this case, the predefined threshold may be set lower than twice the magnitude of the read current typically observed.

[0042] Error detection through modification of transistor source connections

[0043] In some examples of implementation, the sources of the transistors associated with each basic bit line are connected to an individual common line raised to a given potential, in particular, to ground, at least during the reading or programming of the corresponding memory cells, and the sources of the transistors associated with at least one adjacent basic bit line are electrically isolated from the given potential, in particular, to ground, at least during fault detection. Thus, the at least one adjacent basic bit line does not have a path of electrical connection to the given potential and thus passes current only in the case of a laser attack or radiation event. Accordingly, the threshold of the alarm current may be set lower than when the adjacent basic bit line also passes a read current. Even in this case, the predefined threshold may also be set lower than twice the magnitude of the generally observed read current.

[0044] When applied to a basic bit line, the term “electrically isolated” should be understood to mean that the common line to which the sources are connected prevents the current typically observed during reading from flowing any further, and thus, no current other than photoelectric or radiation current should be observed, and that it will not flow through this basic bit line between the drain of one or more transistors affected by the disturbance and the substrate. The given potential biasing the sources of the transistors may be selected depending on the type of memory, and is equal to a given voltage (V), typically 0 V (electrical ground).

[0045] Repetition of reading or writing words

[0046] In the case of detection of a read defect on a basic bit line, if the defect is still detected on that line, the read of that line is preferably repeated a predetermined number of times.

[0047] When programming a word in memory, if a defect is detected, the programming of this word is repeated a predetermined number of times.

[0048] If the detection of a fault is interrupted before the detection loop reaches its end, reading or programming of the memory cells may resume, and the fault temporarily affects the reading or programming of the memory. If the fault is still detected at the end of the detection loop, a predefined action may be performed—for example, programs using the memory may be made secure, or redundant security circuits may be employed.

[0049] In the case of defect detection, for example, a signal may be generated to warn the user of the presence of an attempt to damage the memory or interference.

[0050] The defect detection method may be autonomously implemented by one or more specialized circuits present within the memory chip; as a variation, the method is implemented by one or more circuits outside the memory chip.

[0051] The memory where detection is performed may have any capacity, for example, 512 MB or more.

[0052] memory circuit

[0053] According to other aspects of the present invention, the present invention also relates to a non-volatile semiconductor memory circuit, in particular, a NOR flash memory circuit, an EEPROM memory circuit or a ROM memory circuit, wherein the detection method defined above is implemented; thus, the memory circuit may be configured to detect the potential presence of at least one defect caused by a photoelectric or radiative effect, and comprises a plurality of memory cells including MOS transistors, potentially floating-gate MOS transistors, each memory cell being located at the intersection of a base bit line and an associated word line, and the binary content of the memory cell is read by detecting a read current flowing through the memory cell during a read after the memory cell is selected by the base bit line and word line associated with the memory cell, and the memory circuit comprises at least one alarm circuit having its input connected to at least one base bit line where defect detection is performed, and the alarm circuit is configured to have an output and to perform a comparison between the total current flowing through one or more associated base bit lines during detection and a predefined threshold indicating the presence of at least one defect in these one or more memory cells; The state of the output of the alarm circuit indicates whether the above-mentioned at least one defect exists.

[0054] In particular, according to other aspects of the present invention, another subject of the present invention is a non-volatile semiconductor memory circuit, in particular a NOR flash memory circuit, an EEPROM memory circuit, or a ROM memory circuit, wherein the detection method defined above is implemented; thus, the memory circuit may be configured to detect the potential presence of at least one defect caused by a photoelectric or radiative effect, and comprises a plurality of memory cells including MOS transistors, potentially floating-gate MOS transistors, each memory cell being located at the intersection of a basic bit line and a word line, and the memory circuit comprises at least one alarm circuit whose input is connected to at least one basic bit line where defect detection is performed, the alarm circuit has an output, the state of the output indicates whether the at least one defect is present, and the alarm circuit,

[0055] - Detecting the potential presence of at least one defect during the reading of a memory cell by performing a comparison between the total current flowing through the at least one basic bit line where defect detection is performed and a predefined threshold indicating the presence of at least one defect in one or more memory cells other than the one being read, wherein the binary content of the memory cell detects the potential presence of at least one defect during the reading of the memory cell by detecting the read current flowing through the memory cell during the reading after the memory cell is selected by the basic bit line and the word line, and / or

[0056] - During programming of at least one memory cell, particularly when at least one memory cell is a NOR flash memory or EEPROM, it is configured to detect the potential presence of at least one defect by performing a comparison between the current flowing through at least one basic bit line other than the one to which the memory cell being programmed belongs and a predefined threshold indicating the presence of at least one defect in this line.

[0057] Such memory circuits may be encapsulated within a memory chip, a microcontroller chip, or any other microprocessor circuit.

[0058] The present invention is applicable to many types of memory.

[0059] NOR flash memory

[0060] In the case of NOR flash memory, each memory cell may include a floating gate MOS transistor, its control gate is connected to the corresponding word line and its drain is connected to the corresponding basic bit line.

[0061] EEPROM

[0062] In the case of an EEPROM, each memory cell may include two transistors in series: namely, a MOS select transistor and a floating gate state transistor, the gate of the select transistor is connected to the word line associated with the cell, the drain of the select transistor is connected to the basic bit line associated with the cell, and the control gate of the state transistor is connected to a bias voltage, the bias voltage being, in particular, the supply voltage or ground in read mode.

[0063] The EEPROM may include an address decoder that transmits a bias voltage to the control gates of state transistors for each basic bit line. This ensures that the sources of the transistors of the basic bit line adjacent to the line containing the memory cell being read are electrically isolated from ground. Therefore, the basic bit lines adjacent to the cell being read do not have a path of electrical connection to ground and thus allow current to pass only in the event of a laser attack or radiation event. Accordingly, the threshold for the alarm current may be set lower than when the adjacent basic bit line also allows read current to pass.

[0064] ROM

[0065] In the case of ROM, each memory cell may include a MOS transistor, the gate of which is connected to an associated word line and the drain of which is connected to an associated basic bit line, and the memory circuit includes a read device connected to each basic bit line, and the read device includes a MOS pull-up transistor.

[0066] As a variation, the sources of the MOS transistors associated with each basic bit line are connected to an individual common line raised to a given potential, in particular, to ground, at least during the reading of the corresponding memory cells, and the sources of the transistors associated with at least one adjacent basic bit line are electrically isolated from the given potential, in particular, to ground, at least during fault detection.

[0067] column decoder

[0068] The memory circuit preferably includes a selection transistor connected to each basic bit line for its selection, and for each basic bit line where fault detection is performed, includes a column decoder including an alarm transistor connected in parallel with the selection transistor, wherein the alarm transistor is connected to the at least one alarm circuit.

[0069] Alarm circuit

[0070] Preferably, the alarm circuit includes at least one detection circuit, the detection circuit includes a voltage comparator having a first input connected to a reference voltage and a second input connected to an alarm transistor of a basic bit line where fault detection is performed, and a fault is detected when the voltage on the second input is lower than the reference voltage, and the alarm transistor is turned on during fault detection.

[0071] In the case of ROM, the at least one detection circuit may be separated from the read device.

[0072] In the case of a ROM and a variant in which the sources of the MOS transistors associated with each basic bit line are connected to an individual common line raised to a given potential, the alarm circuit preferably includes a read device, particularly without any separate additional detection circuit. Specifically, this configuration of the sources of the transistors in the ROM eliminates the need for any additional detection circuit because the alarm is triggered by detecting current on an adjacent basic bit line using the latter read device, and the output of this device can generate an alarm bit. Brief explanation of the drawing

[0073] The present invention will potentially be better understood by reading the following detailed description of non-limiting examples of its implementation and by examining the accompanying drawings: [Fig. 1] Fig. 1 is a schematic diagram of a memory architecture. [Fig. 2] Fig. 2 is a diagram similar to Fig. 1 of a modified memory architecture. [Fig. 3] Fig. 3 schematically illustrates a NOR flash memory cell. [Fig. 4] Fig. 4 schematically illustrates the reading of bits in the memory cell exemplified in Fig. 3. [Fig. 5] Fig. 5 schematically illustrates a model of the passage of ionized particles through the memory cell of Fig. 3 and the resulting defect in the transistor. [Fig. 6] Fig. 6 is a diagram similar to Fig. 4 with added interference current. [Fig. 7] Fig. 7 schematically illustrates a basic bit line of a NOR flash memory having an amplifier that detects read defects according to the method of the present invention. [Fig. 8] Fig. 8 schematically illustrates a NOR flash memory architecture having a conventional column decoder. [Fig. 9] Fig. 9 schematically illustrates a NOR flash memory architecture having a column decoder modified according to the present invention to detect read defects in a basic bit line adjacent to what is being read. [Fig. 10] Fig. 10 schematically illustrates a NOR flash memory architecture having a column decoder modified according to the present invention to detect read defects in two basic bit lines adjacent to what is being read. [Fig. 11] Fig. 11 schematically illustrates a NOR flash memory architecture having a column decoder modified according to the present invention to detect read defects in a basic bit line located at a block edge. [Fig. 12] Fig. 12 schematically illustrates a NOR flash memory architecture having a column decoder and split word lines modified according to the present invention. [Fig. 13] Fig. 13 schematically illustrates a NOR flash memory architecture having a conventional electrical connection of sources of a column decoder and floating gate transistors modified according to the present invention. [Fig. 14] Fig. 14 schematically illustrates a NOR flash memory architecture having modified electrical connections of the sources of a column decoder and floating gate transistors modified according to the present invention. [Fig. 15] Fig. 15 is similar to Fig. 14 and illustrates an implementation of a technique for detecting reading defects according to the present invention. [Fig. 16] Fig. 16 schematically illustrates a conventional mask set for a NOR flash memory cell. [Fig. 17] Fig. 17 schematically illustrates an example of a layout of mask sets for NOR flash memory cells that form a memory array. [Fig. 18] Fig. 18 schematically illustrates an example of a mask set for a NOR flash memory cell in the case of modified electrical connection of sources of floating gate transistors. [Fig. 19] Fig. 19 schematically illustrates the association of mask sets of multiple adjacent NOR flash memory cells in the case of modified electrical connection of sources of floating gate transistors. [Fig. 20] Fig. 20 schematically illustrates an EEPROM memory cell. [Fig. 21] Fig. 21 is similar to Fig. 6 in an EEPROM case. [Fig. 22] Fig. 22 is similar to Fig. 9 in the EEPROM case. [Fig. 23] Fig. 23 is similar to Fig. 22, but with an additional address decoder added. [Fig. 24] Fig. 24 is a schematic diagram of a ROM memory cell. [Fig. 25] Fig. 25 schematically illustrates the reading of a logical 0 in the memory cell exemplified in Fig. 24. [Fig. 26] Fig. 26 schematically illustrates the reading of logic 1 in the memory cell exemplified in Fig. 24. [Fig. 27] Fig. 27 is a drawing similar to Fig. 26, which models the injection of a defect by a laser attack. [Fig. 28] Fig. 28 is similar to Fig. 7 in the ROM case. [Fig. 29] Fig. 29 schematically illustrates the basic bit line of a ROM having modified electrical connections of the sources of transistors. [Fig. 30] Fig. 30 schematically illustrates a ROM architecture having modified electrical connections of the sources of transistors. [Fig. 31] Fig. 31 is similar to Fig. 30 and illustrates an implementation of a technique for detecting reading defects according to the present invention. [Fig. 32] Fig. 32 schematically illustrates a conventional mask set for a ROM memory cell. [Fig. 33] Fig. 33 schematically illustrates an example of a layout of mask sets for ROM memory cells that form a memory array. [Fig. 34] Fig. 34 schematically illustrates an example of a modified mask set for a ROM memory cell in the case of a modified electrical connection of the sources of the transistors. [Fig. 35] Fig. 35 schematically illustrates the association of mask sets of multiple adjacent ROM memory cells in the case of modified electrical connections of the sources of transistors. [Fig. 36] Fig. 36 is a flowchart illustrating the steps of a method for detecting and correcting defects during a reading operation according to the present invention. [Fig. 37] Fig. 37 schematically illustrates a NOR flash memory architecture having a column decoder modified according to the present invention to detect defects in a basic bit line adjacent to what is being programmed. [Fig. 38] Fig. 38 is similar to Fig. 37 and has divided word lines. [Fig. 39] Fig. 39 is similar to Fig. 37 and has a modified electrical connection of the sources of the floating gate transistors. [Fig. 40] Fig. 40 schematically illustrates an EEPROM architecture having a column decoder modified according to the present invention to detect defects in a basic bit line adjacent to that being programmed. [Fig. 41] Fig. 41 is a flowchart illustrating the steps of a method for detecting and correcting defects during a writing operation according to the present invention. Specific details for implementing the invention

[0074] Figure 1 is 2 in size M x 2 N A schematic example of a memory architecture (10) of a matrix array structure of bits is illustrated, which is referred to as columns 2 N Basic bit lines (BLE) (BLE1, BLE2, …, BLE2 N )), and 2 M Word lines (WL) (WL1, WL2, …, WL2 M Each memory cell (CM) is located at the intersection of line (BLE) and line (WL).

[0075] A sequence of M bits of binary address (ADR) controls an address decoder (200) for selecting word lines (WL).

[0076] The same sequences (ADR) are also 2 to be decoded NControls a column decoder (100) that takes N basic bit lines (BLE) as inputs and N bit lines (BL) as outputs. The decoder (100) selects a single basic bit line (BLE) and electrically connects it to a bit line (BL). The selection is achieved via an address (ADR).

[0077] N bit lines (BL) are input to a read circuit (101) that outputs a word (103) coded with N bits.

[0078] An example of a variation of such an architecture is shown in FIG. 2, where the read circuit (101) is located upstream of the column decoder (100).

[0079] The memory architectures (10) illustrated in FIGS. 1 and 2 are general and apply to various types of memories, including flash NOR memories, EEPROMs and ROMs.

[0080] FIG. 3 schematically illustrates a NOR flash memory cell (CM). Such a cell includes a floating gate transistor (Tg). The control gate (CG) of this transistor is connected to the word line (WL), its drain is connected to the basic bit line (BLE), and its source is connected to ground. The floating gate is denoted as FG, and, according to common convention, the transistor stores a binary value 0 when it is charged following its programming. In certain memories, a binary value 1 is stored.

[0081] For the sake of simplicity of explanation, it will be noted that in the examples of FIGS. 4, FIGS. 6 through 12, FIGS. 20 through 22, and FIGS. 24 through 27, all sources of the transistors are considered to be connected to ground. The sources may even be connected to common source lines, as described below.

[0082] FIG. 4 schematically illustrates the reading of a bit in a memory cell (CM) exemplified in FIG. 3.

[0083] WL p and BLE i The floating-gate transistor at the intersection of is read: a voltage higher than its threshold voltage (V lecture ) This WL p It is applied to the gate connected to it and turns it on. BLE i All transistors of the other memory cells (CM) connected in parallel are OFF because zero voltage is applied to their gates. Basic Bit Line (BLE i ) is connected to a detection circuit (105) or any other equivalent device. The detection circuit (105) includes a voltage comparator (107), the voltage comparator (107) is, for example, a non-inverting differential amplifier, and its non-inverting input terminal is a reference voltage (V REF It is connected to ), and its inverted input terminal is the bit line (BLE i supply voltage (V) through the resistor (R) and ) DD It connects to ).

[0084] Therefore, the read current (I lecture ) may also flow through the read transistor. The detection circuit (105) is the current (I lecture ) is converted into a voltage (V-), and this voltage is converted into a reference voltage (V) by a voltage comparator (107). REF Compares with ). The output of the comparator (107) provides the value of the read bit (BR).

[0085] The bit (BR) with a value of 0 is read when the floating-gate transistor is programmed in a manner known to itself. Then, this transistor, reference current (I REF Read current lower than ) (I lectureIt has a high threshold voltage that results in ). The current-to-voltage (I / V) conversion is the reference voltage (V REF It generates a voltage (V-) higher than )

[0086] FIG. 5 schematically illustrates the origin of a read defect that can affect memory, namely, the passage of ionized particles (Pi) through a floating-gate transistor. The floating-gate transistor is, for example, an NMOS transistor as shown in the figure. The particles (Pi) may be charged ionized radiation particles or may represent a beam of a laser that generates charge through the photoelectric effect. The charge is a transient current (I PH ) causes current to flow between the transistor's drain and the substrate, and thus, leads to a transient incorrect reading of the corresponding bit. This defect causes the current (I) between the source and drain to flow. PH It is modeled by sources that interfere with ).

[0087] As can be seen in Fig. 6, BLE i If the turned-off transistor located at the intersection of and WLq exists in the region of influence of interference effects that generate defects, the current (I lecture Current added to ) (I PH ) appears. The current received by the detection circuit (105) is now I PH + I lecture and, reference current (I REF It becomes higher than ). I / V conversion is the reference voltage (V REF It generates a voltage (V-) lower than ). Therefore, the output of the comparator (107) delivers a voltage corresponding to the bit (BR) of logic level 1, even if the binary value to be read in the absence of a fault is 0.

[0088] It should be noted that even if the value of a read bit is corrupted, the binary value stored by the read transistor is not modified. This is actually a problem of read defects, not a problem of altering the stored bit.

[0089] To detect a readout defect by implementing the method according to the present invention, the detection circuit (105) of FIGS. 4 and 6 may include an additional voltage comparator (107'), as schematically illustrated in FIG. 7, and its output takes a predefined state in the case of a readout defect.

[0090] The voltage comparator (107') may also be a non-inverting differential amplifier, and its non-inverting input terminal is the basic bit line (BLE i ) to the negative input terminal of the voltage comparator (107), and through the resistor (R) the supply voltage (V DD It is connected to the alarm reference voltage (V). The inverting input terminal is connected to the alarm reference voltage (V). REF, al It is connected to ). The voltage on the positive input terminal of the voltage comparator (107') is V test It is written as .

[0091] During a laser or radiation-induced defect-free logic 0 reading, I lecture = I lecture 0 and: I lecture 0 < I REF is. Therefore, V test, lecture 0 > V REF and BR = 0.

[0092] During a read of a fault-free logic 1, I lecture = I lecture 1 and: I alarm I lecture 1 I REF is. Therefore, V REF, al < V test, lecture 1 < V REF and BR = 1.

[0093] I lecture 0 < I REF< I lecture 1 < I alarm , V test, lecture 0 > V REF > V test, lecture 1 > V REF, al Given this and V test < V REF, al For this, the comparator (107') delivers an output (AL = 0) that triggers the alarm. In terms of current, this is the basic bit line (BLE i Alarm threshold current (I) at ) alarm Corresponds to an excess of ). Specifically, I PH + I lecture I alarm The alarm is triggered because of this.

[0094] The input terminals of the comparator (107') may be swapped. In this case, the state of the output (AL = 1) indicates the detection of a fault.

[0095] A detection circuit (105) having a comparator (107') for each of the N bits forming a word, i.e., bit lines (BL i It exists for each of ).

[0096] FIG. 8 schematically illustrates a block of a NOR flash memory architecture having a conventional column decoder (100). This block is associated in parallel with bit lines (BL) that provide bits of index (i) when a word of N bits is read. i Multiple basic bit lines (K BLE) connected to ) through a column decoder (100) (BLE i,1 , … , BLE i,K Includes ).

[0097] The column decoder (100) includes a select transistor (109) connected to each basic bit line.

[0098] The column decoder (100) is a single-line BLE (in this case, BLE i,jSelect ) and make this line (BL i Connect electrically to ).

[0099] A conventional detection circuit (105) is connected downstream of a column decoder (100) and has a read bit (BR) as its output.

[0100] Such a block is (BL i For each of the N read bits forming the word, it may be duplicated.

[0101] Figure 9 shows what is being read (BLE i,j Basic bit line (BLE) adjacent to ) i,j-1 in ) or BLE i,j A column decoder (100) according to the present invention configured to detect read defects is illustrated. For each basic bit line, an alarm transistor (111) is connected in parallel with a select transistor (109). All select transistors (109) are connected to a read line (l_r) connected to a detection circuit (105) having a read bit (BR) as an output. All alarm transistors (111) are connected to an alarm line (l_al) connected to a detection circuit (105) having an alarm bit (AL) as an output. The word line (WL) of index (p) (WL p ) is potential V lecture It is raised to. Only the select transistor (109) is the basic bit line (BLE i,j Regarding the ON state Because it exists (BLE i,j-1 The selection transistor (109) for is in the OFF state), only I lecturei,j Only cells that pass through are read.

[0102] An adjacent line (BLE) may be located directly above or below the line (BLE) being read (or close to it in the area of ​​influence of the fault generation effect).

[0103] Adjacent line (BLE) (BLE in Fig. 9) i,j-1 The alarm transistor (111) connected to ) has an alarm threshold current (I alarm It was turned on to detect an excess of ).

[0104] I PH, j-1 + I lecture, j-1 I alarm If this happens, the alarm bit (AL) is activated. If a fault is detected, the circuit may read this line again later.

[0105] FIG. 10 schematically illustrates a NOR flash memory block, wherein its column decoder (100) collects an alarm threshold current (I) from two lines (BLE) adjacent to a line (BLE) connected to a floating gate transistor being read. alarm It is configured to detect an excess of ). Adjacent lines (BLE) are located immediately above or below the line (BLE) being read (or close to it in the area of ​​interference effect). In this example, the adjacent lines (BLE) where faults are to be detected are the line (BLE) being read. i,j ) Lines located above and below respectively (BLE i,j-1 and BLE i,j+1 ) am.

[0106] The column decoder (100) has a current (I PH, j-1 + I PH, j+1 + I lecture, j-1 + I lecture, j+1 I alarm For the purpose of detecting ), lines (BLE i,j-1 and BLE i,j+1 ) is arranged to be connected to the detection circuit (105). When the alarm threshold current is exceeded, the alarm bit (AL) is activated. When a fault is detected, the reading may be repeated a certain number of times.

[0107] An example of a NOR flash memory architecture that enables read defects to be detected in lines (BLE) adjacent to a line (BLE) located at the block edge is illustrated in FIG. 11. A line (BLE) connected to the transistor being read and located at the block edge i,K For ), lines (belonging to the same block) (BLE i,K-1 Current flowing through ) and line (BLE i+1,1 ) Current flowing through the BLE of the block containing the bit lines (BLE) of index (i+1) is measured. For each of these currents, the detection circuit (105) is connected to the corresponding BLE.

[0108] Another example (not an example) is a line (BLE) connected to the transistor being read and located at the block edge. i,1 It concerns ); in this case, the line (BLE belonging to the same block) i,2 Current flowing through ) and line (BLE i-1,K The current flowing through the block containing the BLE of the bit of index (i-1) may also be measured.

[0109] FIG. 12 schematically illustrates a NOR flash memory architecture having a column decoder (100) including alarm transistors (111) in addition to select transistors (109), and paired split word lines (WL). In a pair of indices (p), the word lines (WL) of even indices (2k) p, 2k ) is a read potential (V) to activate the memory cells connected thereto. lecture Rising to ), and another word line of "odd" (2k+1) (WL p, 2k+1) is raised to a potential that disables the memory cells connected thereto. Given that for a given pair of word lines, the gates of these transistors are alternately connected to an even word line and an odd word line, the floating gate transistors of the read memory cells of all other lines (BLE) are enabled.

[0110] Therefore, the lines (BLE) adjacent to the line (BLE) containing the transistor being read do not have a path for electrical connection to ground. Therefore, they pass current only in the event that causes a fault effect.

[0111] Error detection may be performed through two adjacent lines next to what is being read or through other lines close to what is being read.

[0112] As shown in FIG. 12, (line being read (BLE i,j ) adjacent to) line (BLE i,j-1 All floating-gate transistors of ) are turned off with zero voltage applied to their control gates. Therefore, line (BLE i,j-1 Interference current (I) flowing through ) PH, j-1 It is possible to detect ). Therefore, the alarm current threshold (I alarm ) may be set lower than when the line adjacent to the one being read (BLE) can also pass the read current.

[0113] FIG. 13 schematically illustrates a NOR flash memory architecture having a conventional electrical connection of the sources of a column decoder (100) and floating gate transistors, including alarm transistors (111) in addition to select transistors (109). Transistors located on the same word line have their sources connected to a common line (SL) raised to a given potential (ground in this case). For example, their gates are connected to the word line (WL p The transistors connected to ) are SL p They have their sources connected to. Their gates are word lines (WL q The transistors connected to ) are SL q They have their sources connected to.

[0114] FIG. 14 illustrates the connection of the sources of the transistors of lines (BLE) to enable electrical isolation from ground of the sources of the floating gate transistors of a line (BLE) adjacent to a BLE (or two adjacent lines (BLE)), for example, including a floating gate transistor being read. The sources of the transistors of a given BLE are now connected to a common line (SL) raised to a given potential.

[0115] SL i,j-1 If this is high impedance (Hz), the line (BLE) containing the transistor being read, as shown in FIG. 15 i,j Basic bit line (BLE) adjacent to ) (used to detect fault currents) i,j-1 ) does not have a path for an electrical connection to ground. Therefore, the alarm current threshold (I) which may be set lower than when the line (BLE) can also pass the read current alarm ) line (BLE i, j-1 Interference current (I) flowing through ) PH, j-1It is possible to detect ).

[0116] FIG. 16 schematically illustrates a conventional mask set for a NOR flash memory cell, showing the layout of the connections of the control gate, floating gate, drain, and source of a transistor to the metal (M1) of level 1 of the basic bit line (BLE). The transistor's (drain and source) spreads have the same DIFF mask in the shape of T rotated 90° counterclockwise. The source is connected to the source line (SL). The floating gate has a mask (POLY1) in the shape of a rectangle. The control gate connected to the word line (WL) also has a mask (POLY2) in the shape of a rectangle. All these masks are superimposed as required by the electronic circuit manufacturing process used. The drain spread of the floating gate transistor is connected to the metal (M1) of the basic bit line (BLE) by a via "via1".

[0117] The juxtaposition of mask sets of memory cells (CM) forms a memory array in which source lines (SL) and word lines (WL) are parallel to each other and orthogonal to fundamental bit lines (BLE), as schematically illustrated in FIG. 13, for example. Contacts between the source diffusions of the transistors of the memory cells create source lines (SL). Contacts between the masks (POLY2) of the control gates (CG) of the transistors of the memory cells create word lines (WL). FIG. 17 illustrates this principle for a group of four transistors. Sharing elements of adjacent transistors reduces the memory footprint without adversely affecting functionality.

[0118] FIG. 18 schematically illustrates an example of a mask set for a NOR flash memory cell according to the present invention in the case of modified electrical connections of the sources of transistors. All masks are superimposed as required by the electronic circuit manufacturing process used. The source diffusion of the floating gate transistor is connected to the metal (M1) of the source line (SL) by a via "via1". The drain diffusion of the floating gate transistor is electrically connected to the metal (M2) of the basic bit line (BLE) by two vias "via1" and "via2". The control gate (CG) of POLY2 forms the word line (WL). This layout makes it possible to obtain basic bit lines (BLE) and source lines (SL) that are parallel to each other and orthogonal to WL, for example, as shown in FIG. 14 and FIG. 15.

[0119] FIG. 19 schematically illustrates the association of mask sets of multiple adjacent NOR flash memory cells in the case of modified electrical connections of the sources of transistors.

[0120] The method for detecting read defects according to the present invention is also applicable to EEPROM.

[0121] FIG. 20 schematically illustrates an EEPROM memory cell comprising two transistors in series: namely, a floating gate state transistor (Teg) and a select transistor (Tse), which may be a standard MOS transistor. Transistor (Teg) has its source connected to ground and its gate connected to the gate control line (CGL). Transistor (Tse) has its drain connected to the base bit line (BLE) and its gate connected to the word line (WL).

[0122] In read mode, the gate control line (CGL) is the supply voltage (V DD) or connected to another suitable reading voltage. As illustrated in FIG. 21, CGL p = V DD It turns on the floating gate transistor intended to be read, and WL p = V lecture is the read current (I lecture It is applied to the gate of the select transistor to allow ) to pass through.

[0123] Interference current of photoelectric or radiation origin (I PH ) is generated at the drain of the select transistor of the EEPROM memory cell.

[0124] The techniques for detecting read defects described above by referring to NOR flash memory are applied to the EEPROM case without major changes.

[0125] Specifically, it is sufficient to provide at least one alarm transistor (111) and at least one detection circuit (105) to detect an exceedance of an alarm current threshold, whether through the line being read (BLE) or through one or more adjacent lines (BLE), wherein the alarm transistor (111) is connected on one side to the line (BLE) where the read fault is to be detected and on the other side to the detection circuit (105). The remaining connections are similar to those of a NOR flash memory, and the control gates (CGL) of the transistors of the EEPROM need to be connected to appropriate biasing potentials.

[0126] Regarding the technique for detecting read defects by splitting word lines, the EEPROM case is simpler because there are already two distinct control voltages: namely, the voltage supplied by the word line (WL) for the select transistor and the voltage supplied by the gate control line (CGL) for the floating gate state transistor.

[0127] Detection of interference current in adjacent lines (BLE) is facilitated by modifying the bias connections of the gates of floating-gate transistors, as shown in FIG. 22, so that their state is controlled to be ON or OFF independently of the word line (WL). Thus, the line (BLE i,j During the reading of ), line (BLE i,j-1 The floating gate transistors of ) are turned off. In the absence of interference current, the current is on the line (BLE i,j-1 It does not flow through ).

[0128] This approach requires the addition of an additional address decoder (202), as illustrated in FIG. 23, the role of which is to transmit an accurate voltage to the control gate lines (CGL) of the floating gate transistors of the various lines (BLE).

[0129] The method for detecting read defects according to the present invention is also applied to ROM.

[0130] FIG. 24 is a schematic diagram of a ROM memory cell including a MOS transistor (Tn), in this case an NMOS transistor, the source of the MOS transistor is connected to ground, its gate is connected to the word line (WL), and its drain is connected to the line (BLE).

[0131] The contents of the ROM are fixed during the manufacture of the circuit. When an operating MOS is inserted between line (BLE) and line (WL), a logic 0 is conventionally stored in memory. When the MOS is not inserted (or when the inserted MOS is not operating), a logic 1 is stored. In certain memories, this convention is reversed.

[0132] FIG. 25 schematically illustrates the reading of a logic 0 in a ROM memory cell.

[0133] The basic bit line (BLE) to which the transistor being read is connected i ) (The gate of that transistor is WL p = V lecture (connected to) includes a read device (102). This read device (102) includes a PMOS pull-up transistor (112), its gate is connected to ground, and its source is V DD It is connected to, and his drain is the line (BLE i It connects to ).

[0134] The NMOS transistors of the ROM memory cells are dimensioned to have a low voltage across their terminals, whereas the PMOS transistor (112) is dimensioned to have a high voltage across its terminals when the NMOS transistor and PMOS transistor are carrying a read current. Thus, the output voltage is substantially equal to 0 V, i.e., read bit (BR) = 0.

[0135] FIG. 26 schematically illustrates the reading of a logic 1 in a ROM memory cell.

[0136] Read NMOS transistor (potential (V lecture In the line (WL p (connected to) does not operate. No current flows. This transistor does not allow current to pass through because it was built incompletely (by design) during the manufacture of the memory or became inoperable through proper injection (by design). Therefore, the pull-up transistor (112) of the read device (102) V DD It guarantees substantially the same output voltage as, that is, read bit (BR) = 1.

[0137] As exemplified in FIG. 27, an interference current (I) affecting adjacent memory cells PH ) causes logical 0 to be read instead of logical 1.

[0138] The techniques for detecting the read defects described above by referring to the NOR flash memory are applied to the ROM case.

[0139] These reading devices (102) need to be replaced with detection circuits (105), except that the detection technique involves modifying the connections of the sources of transistors so that a detection circuit does not need to be added (then, an alarm is triggered by the detection of current on an adjacent BLE), as will be described below.

[0140] FIG. 28 illustrates the replacement of the detection circuit (105) of the read device (102). As in the case of a NOR flash memory, I PH + I lecture I alarm The alarm is triggered in that case. Then, V test < V REF, al am.

[0141] Fig. 29 shows the basic bit line (BLE i,j Electrical connection of the sources of NMOS transistors of ) is illustrated, and a schematic diagram of the conventional electrical connection is shown, thereby, the sources of transistors connected to the same word line (WL) are connected to the same potential (as shown in FIG. 13 for the case of NOR flash memory) not illustrated for the ROM case line (BLE i,j The sources of the transistors of ) are the common line (SL i,j It is connected to the injected interference current (I PH Because of ), logical 0 is read instead of logical 1.

[0142] Adjacent lines (BLE) i,j-1 All sources of the transistors of ) are SL i,j-1 When connected to ground through, as shown in FIG. 30, the reading current can trigger the output of an alarm by the reading device (102), whether or not it is added to the interference current, so that AL = 0.

[0143] As shown in FIG. 31, SL i,j-1 Switching to high impedance (Hz) is I lecture Set = 0. Therefore, the interference current (I PH ) is BLE i,j-1 It is detected on the screen, and the alarm (AL = 0) is raised.

[0144] FIG. 32 schematically illustrates a conventional mask set for a ROM memory cell, showing the layout of the connections of the drain and source of the gate of a transistor to the metal (M1) of level 1 of the basic bit line (BLE). The transistor's (drain and source) diffusions have the same DIFF mask taking the shape of T rotated 90° counterclockwise. The source is connected to the source line (SL). The gate connected to the word line (WL) has a mask (POLY) taking the shape of a rectangle. These masks are superimposed as required by the electronic circuit manufacturing process used. The drain diffusion is connected to the metal (M1) of the basic bit line (BLE) by a via "via1".

[0145] FIG. 33 schematically illustrates an example of a layout of mask sets for ROM memory cells that form a memory array.

[0146] FIG. 34 schematically illustrates an example of a mask set according to the present invention for a ROM memory cell in the case of modified electrical connections of the sources of transistors. All masks are superimposed as required by the electronic circuit manufacturing process used. The source diffusion of the NMOS transistor is connected to the metal (M1) of the source line (SL) by a via "via1". The drain diffusion of the NMOS transistor is electrically connected to the metal (M2) of the basic bit line (BLE) by two vias "via1" and "via2". The gate of the POLY forms the word line (WL). This arrangement makes it possible to obtain basic bit lines (BLE) and source lines (SL) that are parallel to each other and orthogonal to the word lines (WL), for example, as illustrated in FIG. 30 and FIG. 31.

[0147] FIG. 35 schematically illustrates the association of mask sets of multiple adjacent ROM memory cells in the case of modified electrical connections of the sources of transistors.

[0148] FIG. 36 is a flowchart illustrating the steps of a method for detecting and correcting defects according to the present invention.

[0149] The method begins with step 301, which corresponds to reading a word from memory. Next, in step 302, the triggering of an alarm is tested. It should be noted that whether the alarm is triggered depends on the value of the alarm bit (AL). If the alarm is triggered (branch 303), step 301 is returned, and the same word is read again. Otherwise (branch 304), the final step 305, where the read word is correct, is reached, and the reading may continue.

[0150] Furthermore, defects may also be detected during programming of memory cells (CM).

[0151] FIG. 37 is associated with the memory cell (CM) being programmed (BLE i,j Basic bit line (BLE) adjacent to ) i,j-1 In (interference current (I PH, j-1 A column decoder (100) according to the present invention is illustrated, configured to detect defects (indicated by the presence of ).

[0152] An adjacent line (BLE) may be located immediately above or below the line (BLE) associated with the memory cell being programmed (or close to it in the area of ​​influence of the fault generation effect).

[0153] All select transistors (109) connected to the read line (l_r) are in the OFF state, and thus prevent any read.

[0154] Word line (WL) of index (p) (WL p ) is the potential (V programmation2 The basic bit line (BLE) associated with the memory cell (CM) being elevated and programmed. i,j ) is the potential (V programmation1 It rises to ).

[0155] Adjacent line (BLE) (in Fig. 37, BLE i,j-1 Only the alarm transistor (111) connected to ) has an alarm threshold current (I alarm It is turned on to detect an excess of ), and BLE i,j The alarm transistor (111) for is in the OFF state.

[0156] I PH, j-1 I alarm If so, the alarm beat (AL) is activated.

[0157] It may be noted that the detection circuit (105) is already present in the circuit and can be reused to detect defects or added for this purpose.

[0158] The detection circuit (105) is for each of the N bits forming a word, i.e., the bit lines (BL i It may exist for each of ).

[0159] FIG. 38 is similar to FIG. 37 but illustrates divided word lines, (lines associated with the memory cell (CM) being programmed (BLE i,j ) adjacent to) line (BLE i,j-1 All floating-gate transistors of ) are turned off, and zero voltage is applied to their control gates. Therefore, as described above with reference to FIG. 37, the line (BLE i,j-1 Interference current (I) flowing through ) PH, j-1 ) , alarm threshold current (I alarm It is possible to detect by comparing with ).

[0160] FIG. 39, similar to FIG. 37, illustrates the connection of the sources of the transistors of lines (BLE) to enable electrical isolation from ground of the sources of the floating-gate transistors of a line (BLE) adjacent to a BLE associated, for example, a memory cell (CM) being programmed. The sources of the transistors of a given BLE are now connected to a common line (SL) raised to a given potential.

[0161] SL i,j-1 If this is high impedance (Hz), the line (BLE) associated with the memory cell (CM) being programmed i,j (interference current (I) adjacent to ) PH, j-1 Basic bit line (BLE) used to detect ) i,j-1 ) does not have a path for an electrical connection to ground. Therefore, as described above with reference to FIG. 37, the line (BLE i, j-1 Interference current (I) flowing through ) PH, j-1 ) , alarm threshold current (I alarmIt is possible to detect by comparing with ).

[0162] FIG. 40 is associated with the memory cell (CM) being programmed (BLE i,j Basic bit line (BLE) adjacent to ) i, j-1 In (interference current (I PH, j-1 A schematic EEPROM memory architecture having a column decoder modified according to the present invention to detect defects (indicated by the presence of ) is illustrated.

[0163] An adjacent line (BLE) may be located immediately above or below the line (BLE) associated with the memory cell being programmed (or close to it in the area of ​​influence of the fault generation effect).

[0164] All select transistors (109) connected to the read line (l_r) are in the OFF state, and thus prevent any read.

[0165] Word line (WL) of index (p) (WL p ) is the potential (V programmation3 The basic bit line (BLE) associated with the memory cell (CM) being elevated and programmed. i,j ) is the potential (V programmation2 The gate control line (CGL) of the state transistor of the memory cell (CM) being raised and programmed i,j ) is the potential (V programmation1 It rises to ).

[0166] Adjacent line (BLE) (in Fig. 40, BLE i,j-1 Only the alarm transistor (111) connected to ) has an alarm threshold current (I alarm It is turned on to detect an excess of ), and BLE i,j The alarm transistor (111) for is in the OFF state.

[0167] Word line (WL) of index (q) (WL q) is, word line (WL p ) and adjacent basic bit lines (BLE i,j-1 The gate control line (CGL) of the state transistor of the memory cell located at the intersection of ) i,j-1 As with ), it rises to zero potential.

[0168] I PH, j-1 I alarm If so, the alarm beat (AL) is activated.

[0169] It may be noted that the detection circuit (105) is already present in the circuit and can be reused to detect defects or added for this purpose.

[0170] The detection circuit (105) is for each of the N bits forming a word, i.e., the bit lines (BL i It may exist for each of the. FIG. 41 is a flowchart illustrating the steps of a method for detecting and correcting defects affecting a circuit being programmed.

[0171] The method begins with step 401, which corresponds to programming a word in memory. Next, in step 402, the detection of excess current generated by a laser shot or the triggering of an alarm due to the passage of radiated particles is tested. It will be noted that whether the alarm is triggered depends on the value of the alarm bit (AL). If the alarm is triggered (branch 403), step 301 is returned to reprogram the same word. Otherwise (branch 404), the final step 405 is reached, where the programmed word is correct, and programming may continue.

[0172] This method is highly suitable for defects of natural origin. In an attack event, the attacker can repeat laser shots. Therefore, it is possible to propose other strategies that cause memory deletion or circuit resets after potentially multiple defects are detected in succession.

[0173] The present invention may also be used to detect attacks in security systems and to mitigate the effects of radiation on memory circuits.

[0174] The present invention is not limited to the examples of embodiments described above and may be extended to other types of memories if modifications allowing adaptation to their structures are made.

[0175] The MOS logic described in the above examples can be inverted, that is, it is possible to use PMOS transistors instead of NMOS transistors, and vice versa.

Claims

Claim 1 A method for detecting at least one defect caused by a photoelectric or radiation effect in a non-volatile semiconductor memory (10), wherein the memory comprises a plurality of memory cells (CM) including MOS transistors, each memory cell is located at the intersection of a base bit line (BLE) and a word line (WL), and in the method: - to detect the potential presence of at least one defect during a read of a memory cell, the binary content of the memory cell is such that a read current (I) flowing through the memory cell (CM) during a read after the memory cell is selected by the base bit line and the word line lecture The total current flowing through the basic bit line (BLE) to which the memory cell being read belongs, or through at least one basic bit line other than to which the memory cell being read belongs, which is read by detecting ), and a predefined threshold (I) indicating the presence of at least one defect in one or more memory cells other than the one being read. alarm A comparison is performed between ) and / or - to detect the potential presence of at least one defect during programming of at least one memory cell, at least one basic bit line (BLE) other than to which the memory cell being programmed belongs. i,j-1 Current (I) flowing through ) PH , I PH,j-1 ) and the above line (BLE i,j-1 A predefined threshold (I) indicating the presence of at least one defect in ) alarm A method for detecting at least one defect, wherein a comparison is performed between ). Claim 2 In claim 1, to detect the potential presence of at least one defect during reading of a memory cell, the binary content of the memory cell is such that the read current (I) flowing through the memory cell (CM) during reading after the memory cell is selected by the basic bit line and word line. lecture The total current flowing through the basic bit line (BLE) to which the memory cell being read belongs, or through at least one basic bit line other than to which the memory cell being read belongs, which is read by detecting ), and a predefined threshold (I) indicating the presence of at least one defect in one or more memory cells other than the one being read. alarm A method for detecting at least one defect, wherein a comparison is performed between ). Claim 3 In claim 1, to detect the potential presence of at least one defect during programming of at least one memory cell, at least one basic bit line (BLE) other than to which the memory cell being programmed belongs. i,j-1 Current (I) flowing through ) PH , I PH,j-1 ) and the above line (BLE i,j-1 A predefined threshold (I) indicating the presence of at least one defect in ) alarm A method for detecting at least one defect, wherein a comparison is performed between ). Claim 4 In claim 2, the at least one basic bit line (BLE) on which defect detection is performed i ) is a bit line (BLE) associated with the memory cell (CM) being read. i,j A method for detecting at least one defect, wherein ) Claim 5 In claim 4, the above-mentioned predefined threshold (I alarm ) is the read current (I) generally observed in the absence of a defect. lecture A method for detecting at least one defect substantially equal to twice the amplitude of ). Claim 6 In claim 1, the at least one basic bit line (BLE) on which defect detection is performed i ) is associated with the memory cell being read or programmed (BLE i,j Basic bit line (BLE) adjacent to ) i,j-1 ; BLE i,j+1 A method for detecting at least one defect, wherein ) Claim 7 In claim 6, defect detection is associated with the memory cell being read or programmed (BLE i,j A single line adjacent to ) (BLE i,j-1 ; BLE i,j+1 A method for detecting at least one defect, performed through ). Claim 8 In claim 6, defect detection is a basic bit line (BLE) associated with the memory cell being read or programmed. i,j A method for detecting at least one defect, performed through two lines next to ). Claim 9 In claim 6, the at least one basic bit line (BLE) on which defect detection is performed belongs to the same block as the memory cell being read or programmed (BLE i,j A method for detecting at least one defect, wherein ) Claim 10 In claim 6, the at least one basic bit line (BLE) on which defect detection is performed comprises the memory cell being read or programmed (BLE i,j A method for detecting at least one defect belonging to the next or previous block. Claim 11 In claim 1, the defect detection is associated with the memory cell being read or programmed (BLE i,j A method for detecting at least one defect, performed via one or more basic bit lines (BLE) that are not adjacent to ). Claim 12 In claim 6, the memory (10) comprises divided word lines (WL), and each pair of word lines (of index (p)) is a word line (W) of an even index (2k). p, 2k Word lines (W) of ) and odd index (2k+1) p, 2k+1 ) having, the gates of the transistors of the memory cells (CM) are alternately connected to the word lines of the even index and the corresponding word lines of the odd index, and at least one pair of word lines (2k, 2k+1) allows one of the lines to read a potential (V) to activate the connected memory cells. lecture ) to be raised to a write potential or to a potential that disables the connected memory cells, thereby enabling the read memory cells of all other basic bit lines (BLE) or programming all other basic bit lines (BLE), and at least one basic bit line (BLE) adjacent to that associated with the memory cell being read or programmed. i,j-1 ; BLE i,j+1 A method for detecting at least one defect, which enables defect detection in ). Claim 13 In Clause 6, each basic bit line (BLE i The sources of the transistors associated with ) are individual common lines (SL) raised to a given potential during at least the reading or programming of the corresponding memory cells. i Connected to ), and at least one adjacent basic bit line (BLE i,j-1 ; BLE i,j+1 A method for detecting at least one defect, wherein the sources of the transistors associated with ) are electrically insulated from the given potential at least during defect detection. Claim 14 In claim 12, the predetermined threshold (I alarm ) is the read current (I) generally observed in the absence of a defect. lecture A method for detecting at least one defect, set lower than twice the amplitude of ). Claim 15 A method for detecting at least one defect according to claim 1, wherein in the case of detecting a defect on a basic bit line, if a defect is still detected on the line, the reading of the line is repeated a predetermined number of times. Claim 16 A method for detecting at least one defect in claim 1, wherein, in the case of detecting a defect when programming a word in memory, if the defect is still detected, the programming of the line is repeated a predetermined number of times. Claim 17 A method for detecting at least one defect in claim 1, wherein the MOS transistors are floating gate MOS transistors. Claim 18 A non-volatile semiconductor memory circuit (10), wherein the memory circuit is configured to detect the potential presence of at least one defect caused by a photoelectric or radiation effect and comprises a plurality of memory cells (CM) including MOS transistors, each memory cell being located at the intersection of a basic bit line (BLE) and a word line (WL), the memory circuit comprises at least one alarm circuit (105; 102) whose input is connected to at least one basic bit line (BLE) where defect detection is performed, the alarm circuit having an output (AL), the state of the output indicating whether the at least one defect exists, and the alarm circuit, - a total current flowing through the at least one basic bit line (BLE) where defect detection is performed, and a predefined threshold (I) indicating the presence of at least one defect in one or more memory cells other than the one being read alarm ) by performing a comparison between ) to detect the potential presence of at least one defect during the reading of a memory cell, wherein the binary content of the memory cell is the read current (I) flowing through the memory cell (CM) during the reading after the memory cell is selected by the basic bit line and word line. lecture Detecting the potential presence of at least one defect during the reading of the memory cell, which is read by detecting ), and / or - at least one basic bit line (BLE) other than to which the memory cell being programmed belongs. i,j-1 Current (I) flowing through ) PH , I PH,j-1 ) and a predefined threshold (I) indicating the presence of at least one defect in the above line alarm A non-volatile semiconductor memory circuit configured to detect the potential presence of at least one defect during programming of at least one memory cell by performing a comparison between ). Claim 19 In claim 18, the memory circuit is a NOR flash memory circuit, and each memory cell (CM) includes a floating gate MOS transistor (Tg), the control gate (CG) of the floating gate MOS transistor is connected to a corresponding word line (WL), and the drain of the floating gate MOS transistor is connected to a corresponding basic bit line (BLE), a non-volatile semiconductor memory circuit. Claim 20 In claim 18, the memory circuit is an EEPROM memory circuit, and each memory cell (CM) comprises two transistors in series: namely, a MOS select transistor (Tse) and a floating gate state transistor (Teg), the gate of the select transistor (Tse) is connected to a word line (WL) associated with the cell, the drain of the select transistor (Tse) is connected to a basic bit line (BLE) associated with the cell, and the control gate (CG) of the state transistor is connected to a bias voltage (CGL), a non-volatile semiconductor memory circuit. Claim 21 A non-volatile semiconductor memory circuit according to claim 20, comprising an address decoder (202) that transmits the bias voltage (CGL) to the control gates (CG) of the state transistors (Teg) for each basic bit line (BLE). Claim 22 In claim 18, the memory circuit is a ROM memory circuit, and each memory cell (CM) includes a MOS transistor, the gate of the MOS transistor is connected to an associated word line (WL), and the drain of the MOS transistor is connected to an associated basic bit line (BLE), and the memory circuit includes a read device (102) connected to each basic bit line (BLE), and the read device (102) includes a MOS pull-up transistor (112), a non-volatile semiconductor memory circuit. Claim 23 In Clause 22, each basic bit line (BLE i The sources of the MOS transistors associated with ) are individual common lines (SL) raised to a given potential at least during the read of the corresponding memory cells. i Connected to ) and at least one adjacent basic bit line (BLE i,j-1 ; BLE i,j+1 Sources of transistors associated with ) are electrically insulated from the given potential, at least during defect detection, in a non-volatile semiconductor memory circuit. Claim 24 In Clause 18, for selection, each basic bit line (BLE i A non-volatile semiconductor memory circuit comprising a column decoder (100) including a select transistor (109) connected to ) and, for each basic bit line (BLE) where fault detection is performed, an alarm transistor (111) connected in parallel with the select transistor (109), wherein the alarm transistor is connected to at least one alarm circuit (105; 102). Claim 25 In claim 24, the alarm circuit (105; 102) comprises at least one detection circuit (105), and the detection circuit has a reference voltage (V REF The first input connected to ) and the basic bit line (BLE) where fault detection is performed i,j ; BLE i,j-1 ; BLE i,j+1 The apparatus includes a voltage comparator (107') having a second input connected to the alarm transistor (111) of the above, wherein the fault is a voltage (V on the second input) test A non-volatile semiconductor memory circuit in which the above is detected when it is lower than the reference voltage, and the alarm transistor is turned on during defect detection. Claim 26 In claim 25 combined with claim 22, the at least one detection circuit (105) is a non-volatile semiconductor memory circuit separated from the reading device (102). Claim 27 In claim 22, the at least one alarm circuit (105; 102) is a non-volatile semiconductor memory circuit comprising the read device (102). Claim 28 In claim 18, the non-volatile semiconductor memory circuit, wherein the MOS transistors are floating-gate MOS transistors.

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