Analog-to-digital converter

Abstract

An analog-to-digital converter according to an embodiment of the present disclosure converts a first input voltage and a second input voltage, which are analog signals, into a digital signal composed of a plurality of bits, and includes a first CDAC that outputs a first intermediate voltage from the first input voltage, a second CDAC that outputs a second intermediate voltage from the second input voltage, a comparator that compares the magnitudes of the first intermediate voltage and the second intermediate voltage, and a control logic circuit that sequentially outputs a plurality of bits from the most significant bit to the least significant bit based on a comparison result output from the comparator, wherein the control logic circuit controls the magnitudes of the first intermediate voltage and the second intermediate voltage through the first CDAC and the second CDAC to output each of the first bits adjacent to the most significant bit to the least significant bit, and controls the magnitude of the first intermediate voltage through the first CDAC to output the least significant bit.

Description

Technology Field

[0001] The present disclosure features a capacitive digital-to-analog converter (CDAC) that can be included in a subblock of a successive approximation analog-to-digital converter (SAR ADC), which is a high-speed analog-to-digital converter structure used in wired and wireless communication systems. Background Technology

[0002] Digital signal processing has higher processing speeds and is less sensitive to environmental noise compared to analog signal processing. However, since most natural signals are analog, it is necessary to first convert analog signals into digital signals to facilitate signal processing.

[0003] Analog-to-digital converters can be broadly classified into pipeline analog-to-digital converters, successive comparison analog-to-digital converters, flash analog-to-digital converters, and delta-sigma analog-to-digital converters.

[0004] Among these, the successive approximation analog-to-digital converter (SAR ADC) has the advantage of being able to be designed with a relatively small area and having low power consumption.

[0005] Successive comparison analog-to-digital converters can include CDACs as sub-blocks. Currently, numerous studies are underway to increase the switching speed during the sampling process of successive comparison analog-to-digital converters by reducing the total capacitance of the CDAC. Prior art literature

[0006] Republic of Korea Published Patent Application No. 10-2013-0015859 (2013-02-14) The problem to be solved

[0007] The analog-to-digital converter according to an embodiment of the present disclosure is intended to improve the sampling rate in the analog-to-digital conversion process by reducing capacitance.

[0008] The analog-to-digital converter according to an embodiment of the present disclosure aims to minimize the degradation of linearity of the analog-to-digital converter by monotonically controlling the switching operation of the CDAC in the conversion cycle for the least significant bit. means of solving the problem

[0009] An analog-to-digital converter according to an embodiment of the present disclosure converts a first input voltage and a second input voltage, which are analog signals, into a digital signal composed of a plurality of bits, and includes a first CDAC that outputs a first intermediate voltage from the first input voltage, a second CDAC that outputs a second intermediate voltage from the second input voltage, a comparator that compares the magnitudes of the first intermediate voltage and the second intermediate voltage, and a control logic circuit that sequentially outputs a plurality of bits from the most significant bit to the least significant bit based on a comparison result output from the comparator, wherein the control logic circuit controls the magnitudes of the first intermediate voltage and the second intermediate voltage through the first CDAC and the second CDAC to output each of the first bits adjacent to the most significant bit to the least significant bit, and controls the magnitude of the first intermediate voltage through the first CDAC to output the least significant bit. Effects of the invention

[0010] An analog-to-digital converter according to an embodiment of the present disclosure can improve the sampling rate in the analog-to-digital conversion process by reducing capacitance.

[0011] An analog-to-digital converter according to an embodiment of the present disclosure can minimize the degradation of linearity of the analog-to-digital converter by monotonically controlling the switching operation of the CDAC in the conversion cycle for the least significant bit. Brief explanation of the drawing

[0012] FIG. 1 is a block diagram of an analog-to-digital converter according to one embodiment of the present disclosure. FIG. 2 is a block diagram of a CDAC circuit according to one embodiment of the present disclosure. FIG. 3 is a circuit diagram of a CDAC circuit and a comparator according to one embodiment of the present disclosure. FIGS. 4a and 4b illustrate voltage changes of a CDAC circuit output according to one embodiment of the present disclosure. Figure 5 illustrates the control speed of the CDAC circuit in the conversion cycle for the most significant bit. Figures 6a, 6b, and 6c illustrate the output results of the CDAC circuit in the conversion cycle for the most significant bit. Figures 7a, 7b, and 7c illustrate the output results of the CDAC circuit in the conversion cycle for the least significant bit. Specific details for implementing the invention

[0013] In the following, embodiments of the present disclosure will be described clearly and in detail with reference to the accompanying drawings.

[0014] In the following, the terms “1” and “0” may also be expressed as logical high and logical low, etc., depending on the expression, for the convenience of explanation.

[0015] FIG. 1 is a block diagram of an analog-to-digital converter (10) according to one embodiment of the present disclosure.

[0016] The analog-to-digital converter (10) may include a CDAC circuit (100), a comparator (200), and a control logic circuit (300). In one embodiment, the control logic circuit (300) may be a successive approximation (SAR) type control logic circuit for quantizing analog signals (INP, INN) using a binary search method.

[0017] In one embodiment, the CDAC circuit (100) can sample analog signals (INP, INN) based on a control signal (CS1) of the control logic circuit (300). Additionally, the CDAC circuit (100) can output two intermediate voltages (MP, MN) based on the control signal (CS1). Here, the analog signals (INP, INN) received by the CDAC circuit (100) may be signal pairs that have a differential relationship.

[0018] In one embodiment, the comparator (200) may output a comparison result (CS2) from two intermediate voltages (MP, MN) output by the CDAC circuit (100). According to the embodiment, the comparison result (CS2) may include at least one bit.

[0019] For example, the comparator (200) compares the magnitudes of the first intermediate voltage (MP) and the second intermediate voltage (MN), and if the first intermediate voltage (MP) is larger, it outputs “1” as the comparison result (CS2), and if the first intermediate voltage (MP) is larger, it outputs “0” as the comparison result (CS2).

[0020] In another example, the comparator (200) can compare the magnitudes of the first intermediate voltage (MP) and the second intermediate voltage (MN), and output “10” as the comparison result (CS2) if the first intermediate voltage (MP) is larger, and output “01” as the comparison result (CS2) if the first intermediate voltage (MP) is smaller.

[0021] In one embodiment, the control logic circuit (300) can output a digital signal (OUT) based on the comparison result (CS2) of the comparator (200). Additionally, the control logic circuit (300) can generate a control signal (CS1) that controls the CDAC circuit (100).

[0022] In one embodiment of the present disclosure, the CDAC circuit (100) can monotonically control only the conversion cycle for the least significant bit during the process of converting an analog signal (INP, INN) into a digital signal (OUT) from the most significant bit to the least significant bit.

[0023] For convenience of explanation, the analog-to-digital converter (10) of the present disclosure is assumed to be a successive approximation analog-to-digital converter (SAR ADC) that outputs a 7-bit digital signal (OUT) from an analog signal (INP, INN).

[0024] The CDAC circuit (100) can decrease the intermediate voltage of the higher of the first intermediate voltage (MP) and the second intermediate voltage (MN) and increase the lower intermediate voltage based on the control signal (CS1) of the control logic circuit (300) from the conversion cycle for the first bit (or, most significant bit) to the conversion cycle for the least significant bit and the adjacent bit. Subsequently, the comparator (200) can output a comparison result (CS2) from the transformed first intermediate voltage (MP) and the second intermediate voltage (MN), respectively. The control logic circuit (300) can generate a digital signal (OUT) from the comparison result (CS2).

[0025] The CDAC circuit (100) can control the magnitude of only one of the first intermediate voltage (MP) and the second intermediate voltage (MN) based on the control signal (CS1) of the control logic circuit (300) in the conversion cycle for the last bit (or, least significant bit).

[0026] For example, after conversion for the least significant bit and adjacent bits, if the value of the first intermediate voltage (MP) is greater than the value of the second intermediate voltage (MN), the CDAC circuit (100) can reduce the magnitude of the first intermediate voltage (MP) based on the control signal (CS1) in the conversion cycle for the least significant bit.

[0027] As another example, after conversion for the least significant bit and adjacent bits, if the value of the first intermediate voltage (MP) is greater than the value of the second intermediate voltage (MN), the CDAC circuit (100) can increase the magnitude of the second intermediate voltage (MN) based on the control signal (CS1) in the conversion cycle for the least significant bit.

[0028] That is, the CDAC circuit (100) can monotonically control one of the first intermediate voltage (MP) and the second intermediate voltage (MN) in the conversion cycle for the least significant bit.

[0029] Furthermore, the comparator (200) can output a comparison result (CS2) from the first intermediate voltage (MP) and the second intermediate voltage (MN).

[0030] The control logic circuit (300) can generate a digital signal (OUT) from the comparison result (CS2).

[0031] For example, the control logic circuit (300) can output “1” to the output (OUT) when the value of the first intermediate voltage (MP) is greater than the value of the second intermediate voltage (MN).

[0032] As another example, the control logic circuit (300) can output “0” as an output (OUT) when the value of the first intermediate voltage (MP) is smaller than the value of the second intermediate voltage (MN).

[0033] If the CDAC circuit (100) monotonically controls the first intermediate voltage (MP) or the second intermediate voltage (MN) only in the conversion cycle for the least significant bit, compared to the case where the first intermediate voltage (MP) or the second intermediate voltage (MN) is monotonically controlled in all bit conversion cycles, the deterioration of linearity of the analog-to-digital converter (10) due to a change in the characteristics of the comparator (200) can be reduced relatively.

[0034] More specifically, if only the conversion cycle for the least significant bit is monotonically controlled, the change in the common mode voltage of the CDAC circuit (100) can be reduced in cycles excluding the conversion cycle for the least significant bit. The reduction in the change in the common mode voltage can minimize the change in the dynamic offset of the comparator (200). Furthermore, the reduction in the change in the common mode voltage can also minimize the change in the input-referred-noise characteristics of the comparator (200). Additionally, the reduction in the change in the common mode voltage can minimize the deterioration of the linearity of the analog-to-digital converter (10).

[0035] Additionally, if only the conversion cycle for the least significant bit in the analog-to-digital converter (10) is monotonically controlled, the capacitance of the CDAC circuit (100) can be reduced. If the capacitance of the CDAC circuit (100) is reduced, the speed of the switching operation of the CDAC circuit (100) can be improved.

[0036] Accordingly, the analog-to-digital converter (10) can improve the performance (e.g., operating speed) of the analog-to-digital converter (10) by monotonically controlling the first intermediate voltage (MP) or the second intermediate voltage (MN) only in the conversion cycle for the least significant bit, compared to the case where the first intermediate voltage (MP) or the second intermediate voltage (MN) is monotonically controlled in all the conversion cycles of the bits.

[0037] FIG. 2 is a block diagram of a CDAC circuit (100) according to one embodiment of the present disclosure. The same reference numerals are used for configurations that are identical or substantially identical to the configuration described in FIG. 1, and descriptions that overlap with the above content are omitted.

[0038] The CDAC circuit (100) may include a first CDAC (110) and a second CDAC (120).

[0039] Referring to FIG. 1 and FIG. 2, a first CDAC (110) and a second CDAC (120) according to one embodiment can each receive a differential pair of analog signals (INP, INN) to generate a first intermediate voltage (MP) and a second intermediate voltage (MN).

[0040] The first CDAC (110) and the second CDAC (120) can change the magnitude of the first intermediate voltage (MP) and the second intermediate voltage (MN) by operating for each cycle from the conversion cycle for the most significant bit to the conversion cycle for the bit adjacent to the least significant bit based on the control signal (CS1) of the control logic circuit (300).

[0041] Here, the bit adjacent to the least significant bit can be understood as the bit located to the left of the least significant bit. That is, the bit adjacent to the least significant bit can be understood as the bit at the lowest position among the bits excluding the least significant bit.

[0042] For example, the first CDAC (110) can control the magnitude of the first intermediate voltage (MP) in each conversion cycle from the conversion cycle for the most significant bit to the conversion cycle for the bit adjacent to the least significant bit, based on the control signal (CS1).

[0043] Additionally, the second CDAC (120) can control the magnitude of the second intermediate voltage (MN) in each conversion cycle from the conversion cycle for the most significant bit to the conversion cycle for the bit adjacent to the least significant bit, based on the control signal (CS1).

[0044] Subsequently, the comparator (200) can compare the magnitudes of the first intermediate voltage (MP) and the second intermediate voltage (MN) to output a comparison result (CS2). Additionally, the control logic circuit (300) can generate a digital signal (OUT) from the most significant bit to the bit adjacent to the least significant bit based on the comparison result (CS2).

[0045] One of the first CDAC (110) and the second CDAC (120) can change the magnitude of one of the first intermediate voltage (MP) and the second intermediate voltage (MN) in a conversion cycle for the least significant bit.

[0046] For example, the first CDAC (110) can control the magnitude of the first intermediate voltage (MP) in the conversion cycle for the least significant bit based on the control signal (CS1). Additionally, the second CDAC (120) can control the magnitude of the second intermediate voltage (MN) in the conversion cycle for the least significant bit based on the control signal (CS1).

[0047] Subsequently, the comparator (200) can compare the magnitudes of the first intermediate voltage (MP) and the second intermediate voltage (MN) to output a comparison result (CS2). The control logic circuit (300) can generate a digital signal (OUT) of the least significant bit based on the comparison result (CS2).

[0048] If the CDAC circuit (100) monotonically controls the first intermediate voltage (MP) or the second intermediate voltage (MN) only in the conversion cycle for the least significant bit, the deterioration of linearity of the analog-to-digital converter (10) due to a change in the characteristics of the comparator (200) can be minimized compared to the case where the first intermediate voltage (MP) or the second intermediate voltage (MN) is monotonically controlled in the conversion cycles of all bits.

[0049] More specifically, if only the conversion cycle for the least significant bit is monotonically controlled, the change in the common mode voltage of the CDAC circuit (100) can be reduced in cycles excluding the conversion cycle for the least significant bit. The reduction in the change in the common mode voltage can minimize the change in the dynamic offset of the comparator (200). Furthermore, the reduction in the change in the common mode voltage can also minimize the change in the input-referred-noise characteristics of the comparator (200). Additionally, the reduction in the change in the common mode voltage can minimize the deterioration of the linearity of the analog-to-digital converter (10).

[0050] Additionally, if only the conversion cycle for the least significant bit in the analog-to-digital converter (10) is monotonically controlled, the capacitance of the CDAC circuit (100) can be reduced. If the capacitance of the CDAC circuit (100) is reduced, the speed of the switching operation of the CDAC circuit (100) can be improved.

[0051] Accordingly, the analog-to-digital converter (10) can improve the performance of the analog-to-digital converter (10) by monotonically controlling the first intermediate voltage (MP) or the second intermediate voltage (MN) only in the conversion cycle for the least significant bit, compared to the case where the first intermediate voltage (MP) or the second intermediate voltage (MN) is monotonically controlled in all bit conversion cycles.

[0052] FIG. 3 is a circuit diagram of a CDAC circuit (100) and a comparator (200) according to one embodiment of the present disclosure. The same reference numerals are used for configurations that are identical or substantially identical to the configurations described above in FIG. 1 and FIG. 2, and descriptions that overlap with the above content are omitted.

[0053] Referring to FIG. 3, a CDAC circuit (100) for 8-bit conversion is shown for convenience of explanation. However, this is an example, and the number of capacitors and switches used may be determined differently depending on the resolution targeted in the analog-to-digital conversion.

[0054] In one embodiment, the CDAC circuit (100) may include 28 capacitors (CP1, CL1, C1-1 to C1-12, CP2, CL2, C2-1 to C2-12) and 26 switches (SL1, S1-1 to S1-12, SL2, S2-1 to S2-12). In this case, the CDAC circuit (100) may output an 8-bit digital signal (OUT) from an analog signal (INP, INN).

[0055] In another embodiment, the CDAC circuit (100) may include 24 capacitors and 22 switches. In this case, the CDAC circuit (100) may output a 7-bit digital signal (OUT) from an analog signal (INP, INN).

[0056] Referring to FIG. 3, the CDAC circuit (100) may include a first CDAC (110) and a second CDAC (120).

[0057] In one embodiment, the first CDAC (110) can receive a first input voltage (INP). The first CDAC (110) can selectively connect each of the plurality of capacitors (CL1, C1-1 to C1-12) to a first reference voltage node (N1) or a second reference voltage node (N2) by controlling at least some of the plurality of switches (SL1, S1-1 to S1-12) connected to the plurality of capacitors (CL1, C1-1 to C1-12) during each conversion cycle. Furthermore, the first CDAC (110) can generate a first intermediate voltage (MP) from the first input voltage (INP) based on the first reference voltage (VRP) or the second reference voltage (VRN).

[0058] The first CDAC (110) may include a first-1 conversion circuit (110a) for least bit conversion and a first-2 conversion circuit (110b) for remaining bit conversion.

[0059] The first-1 conversion circuit (110a) may include a first additional capacitor (CP1) connected between the terminal of the first input voltage (INP) and the second reference voltage node (N2), and a first least bit capacitor (CL1) connected from the terminal of the first input voltage (INP) to the first reference voltage node (N1) or the second reference voltage node (N2) by the first least bit switch (SL1).

[0060] The first-second conversion circuit (110b) may include a plurality of capacitors (C1-1 to C1-12) respectively connected from a node of the first input voltage (INP) to a first reference voltage node (N1) or a second reference voltage node (N2) by a plurality of switches (S1-1 to S1-12).

[0061] In one embodiment, the second CDAC (120) can receive a second input voltage (INN). The second CDAC (120) can selectively connect each of the plurality of capacitors (CL2, C2-1 to C2-12) to a first reference voltage node (N1) or a second reference voltage node (N2) by controlling a plurality of switches (SL2, S2-1 to S2-12) connected to a plurality of capacitors (CL2, C2-1 to C2-12) for each conversion cycle. Furthermore, the second CDAC (120) can generate a second intermediate voltage (MN) from the second input voltage (INN) based on the first reference voltage (VRP) or the second reference voltage (VRN).

[0062] The second CDAC (120) may include a second-1 conversion circuit (120a) for converting the least significant bit and a second-2 conversion circuit (120b) for converting the remaining bits.

[0063] The second-1 conversion circuit (120a) may include a second additional capacitor (CP2) connected between the terminal of the second input voltage (INN) and the second reference voltage node (N2), and a second least bit capacitor (CL2) connected from the terminal of the second input voltage (INN) to the first reference voltage node (N1) or the second reference voltage node (N2) by the second least bit switch (SL2).

[0064] The second-2 conversion circuit (120b) may include a plurality of capacitors (C2-1 to C2-12) respectively connected from the node of the second input voltage (INN) to the first reference voltage node (N1) or the second reference voltage node (N2) by a plurality of switches (S2-1 to S2-12).

[0065] The capacitance of the capacitors connected to the switches operating in every conversion cycle from the conversion cycle of the least significant bit and the adjacent bit to the conversion cycle of the most significant bit can be doubled.

[0066] For example, if the capacitance of the capacitors (CP1, CL1, CP2, CL2) for least bit conversion in the first CDAC (110) and the second CDAC (120) is 1C, the CDAC circuit (100) of the present disclosure can be designed so that the capacitance of the capacitor for most bit conversion increases by a factor of 2 starting from the bit adjacent to the least bit.

[0067] In one embodiment, if the capacitance of the capacitors (CP1, CL1, CP2, CL2) for converting the least significant bit is 1C, the capacitance of the capacitors (C1-1, C1-2, C2-1, C2-2) for converting the least significant bit and the adjacent bit may be 1C. The capacitance of the capacitors (C1-3, C1-4, C2-3, C2-4) for converting the next adjacent bit may be 2C. The capacitance of the capacitors (C1-5, C1-6, C2-5, C2-6) for converting the next adjacent bit may be 4C. The capacitance of the capacitors (C1-7, C1-8, C2-7, C2-8) for converting the next adjacent bit may be 8C. Next, the capacitance of the capacitors (C1-9, C1-10, C2-9, C2-10) for converting adjacent bits may be 16C. Finally, the capacitance of the capacitors (C1-11, C1-12, C2-11, C2-12) for converting the most significant bit may be 32C.

[0068] Ultimately, if the capacitance of the capacitors (CP1, CL1, CP2, CL2) for the least significant bit conversion is 1C, the capacitance of the 8-bit analog-to-digital converter (10) can be 128C.

[0069] However, unlike the present disclosure, the capacitance of an analog-to-digital converter in the case where all conversion cycles for bits from the most significant bit to the least significant bit are monotonically controlled may be 256C.

[0070] Accordingly, the analog-to-digital converter (10) of the present disclosure may have a relatively small capacitance, and by having a small capacitance, the switching speed of the analog-to-digital converter (10) may be improved. When the switching speed of the analog-to-digital converter (10) is improved, the performance of the analog-to-digital converter (10) may be improved.

[0071] The change in magnitude (VV1) of the first intermediate voltage (MP) for each conversion cycle can be calculated by dividing the magnitude (CV1) of the capacitance changing in the first CDAC circuit (110) for each cycle by the total capacitance (TC) of the CDAC circuit (100), and multiplying this by the value obtained by subtracting the second reference voltage (V2) from the magnitude (V1) of the first reference voltage. (Equation 1)

[0072] Additionally, the change in magnitude (VV2) of the second intermediate voltage (MN) for each conversion cycle can be calculated by dividing the magnitude (CV2) of the capacitance changing in the second CDAC circuit (120) for each cycle by the total capacitance (TC) of the CDAC circuit (100), and multiplying this by the value obtained by subtracting the second reference voltage (V2) from the magnitude of the first reference voltage (V1). (Equation 2)

[0073]

[0074]

[0075] For example, for convenience of explanation, it is assumed that the first reference voltage (VRP) is 1V and the second reference voltage (VRN) is 0V. Additionally, it is assumed that the switches (S1-1, S1-3, …, S1-11, S2-1, S2-3, …, S2-11) at the top of the first CDAC (110) and the second CDAC (120) are connected to the second reference voltage node (N2) in the reset state, and the switches (S1-2, S1-4, …, S1-12, S2-2, S2-4, …, S2-12) at the bottom of the first CDAC (110) and the second CDAC (120) are connected to the first reference voltage node (N1) in the reset state.

[0076] In the first cycle for converting the most significant bit in FIG. 3, the comparator (200) can compare the first intermediate voltage (MP) and the second intermediate voltage (MN). As a result of the comparison, the analog-to-digital converter (10) can output “1” to the output (OUT) if the first intermediate voltage (MP) is greater.

[0077] Next, in the second cycle, the first CDAC (110) can connect the first-12 switch (S1-12), which was connected to the first reference voltage node (N1), to the second reference voltage node (N2). That is, in the second cycle, the first CDAC (110) can control the first-12 switch (S1-12) to connect the first-12 capacitor (C1-12) to the second reference voltage node (N2). By connecting the first-12 capacitor (C1-12) to the second reference voltage node (N2), the first CDAC (110) can reduce the magnitude of the first intermediate voltage (MP).

[0078] Additionally, in the second cycle, the second CDAC (120) can connect the second-11 switch (S2-11), which was connected to the second reference voltage node (N2), to the first reference voltage node (N1). That is, in the second cycle, the second CDAC (120) can control the second-11 switch (S2-11) to connect the second-11 capacitor (C2-11) to the first reference voltage node (N1). By connecting the second-11 capacitor (C2-11) to the first reference voltage node (N1), the second CDAC (120) can increase the magnitude of the second intermediate voltage (MN).

[0079] Assuming that the capacitance of the capacitors (CP1, CL1, CP2, CL2) operating in the conversion cycle for the least significant bit is 1C, the total capacitance in the 8-bit analog-to-digital converter (10) is equal to 128C. Additionally, the capacitance of the capacitor connected to the switch that is switched to enter the second cycle is equal to 32C. Considering the aforementioned equations for the magnitude change of intermediate voltages (MP, MN) (Equation 1, Equation 2), the amount of change of each intermediate voltage (MP, MN) can be calculated as (32 / 128)*(1-0) and is equal to 1 / 4V. Therefore, in the second cycle, the first intermediate voltage (MP) decreases by 1 / 4V compared to the first cycle, and the second intermediate voltage (MN) increases by 1 / 4V.

[0080] Next, the analog-to-digital converter (10) again compares the magnitudes of the first intermediate voltage (MP) and the second intermediate voltage (MN) to generate a digital output signal for the second cycle. Then, for the third cycle, switches connected to capacitors with a capacitance of 16C are operated. Then, in the third cycle, according to Equation 1, the larger intermediate voltage is reduced by 1 / 8V and the smaller intermediate voltage is increased by 1 / 8V.

[0081] The analog-to-digital converter (10) can generate a digital signal (OUT) from an analog signal (INP, INN) by repeating the above method up to the cycle immediately preceding the conversion cycle for the least significant bit.

[0082] In the process of generating the least significant bit, the first CDAC (110) and the second CDAC (120) can control the least significant bit switches (SL1, SL2) that operate in the least significant bit conversion cycle. Additionally, in the process of generating the least significant bit, one of the first CDAC (110) and the second CDAC (120) can control the magnitude of only one of the first intermediate voltage (MP) and the second intermediate voltage (MN).

[0083] For example, after conversion for the least significant bit and adjacent bits, if the value of the first intermediate voltage (MP) is greater than the value of the second intermediate voltage (MN), the first CDAC (110) can reduce the magnitude of the first intermediate voltage (MP) based on the control signal (CS1) in the conversion cycle for the least significant bit.

[0084] In another example, after conversion for the least significant bit and adjacent bits, if the value of the first intermediate voltage (MP) is greater than the value of the second intermediate voltage (MN), the second CDAC (120) can increase the magnitude of the second intermediate voltage (MN) based on the control signal (CS1) in the conversion cycle for the least significant bit.

[0085] To explain one embodiment of the least significant bit conversion cycle, it is assumed that the second intermediate voltage (MN) is smaller than the first intermediate voltage (MP).

[0086] Then, the second least significant bit switch (SL2) can be switched from the second reference voltage node (N2) to the first reference voltage node (N1) to increase the second intermediate voltage (MN) of a small magnitude. Subsequently, the comparator (200) can compare the magnitudes of the first intermediate voltage (MP) and the second intermediate voltage (MN) and output a comparison result (CS2). The control logic circuit (300) outputs the least significant bit from the comparison result (CS2).

[0087] As described above in FIG. 1, an analog-to-digital converter (10) that monotonically controls only the least significant bit conversion cycle using the CDAC circuit (100) of FIG. 3 can reduce the deterioration of linearity of the analog-to-digital converter (10) due to a change in the characteristics of the comparator (200) relatively compared to the case where the CDAC circuit is monotonically controlled in all bit conversion cycles.

[0088] FIGS. 4a and 4b illustrate a voltage change of the output of a CDAC circuit (100) according to one embodiment of the present disclosure. FIGS. 4a and 4b illustrate the result of an analog-to-digital converter (10) outputting a 7-bit digital signal.

[0089] Referring to FIG. 4a, the control logic circuit (300) (or analog-to-digital converter (10)) of the present disclosure can change the voltage of each differential signal during the conversion cycle for the most significant bit, from the 1st bit to the 6th bit. Here, when the voltage of the differential signal changes, the common mode voltage of the CDAC circuit (100) can be maintained. That is, by maintaining the common mode voltage of the CDAC circuit (100), the analog-to-digital converter (10) can minimize changes in the dynamic offset of the comparator (200) or changes in the input-referred-noise characteristics.

[0090] Referring to FIG. 4b, in the conversion cycle for the 7th bit of the present disclosure, only one of the two voltages of the differential signal may change monotonically. FIG. 4b illustrates a small differential signal voltage increasing monotonically, but according to an embodiment, the present disclosure may have a large differential signal voltage decreasing monotonically in the conversion cycle for the least significant bit.

[0091] When the conversion cycle for the least significant bit is controlled monotonically, the change in the common mode voltage of the CDAC circuit (100) may be smaller compared to when all bit conversion cycles are controlled monotonically. When the change in the common mode voltage of the CDAC circuit (100) is small, the linearity of the analog-to-digital converter (10) can be improved. Therefore, when the conversion cycle for the least significant bit is controlled monotonically, the linearity of the analog-to-digital converter (10) can be improved.

[0092] Additionally, the present disclosure designs the capacitance of capacitors for the least significant bit conversion and the capacitance of capacitors for bit conversion adjacent to the least significant bit to be equal, so that the total capacitance of the analog-to-digital converter (10) may be smaller than that of an analog-to-digital converter that does not monotonically control all bit conversion cycles. When the total capacitance is small, the switching speed of the CDAC circuit (100) may be increased. As the switching speed of the CDAC circuit (100) increases, the performance of the analog-to-digital converter (10) may be improved as a result.

[0093] Figure 5 illustrates the control speed of the CDAC circuit (100) in the conversion cycle for the most significant bit.

[0094] Referring to FIG. 5, an analog-to-digital converter (V) that changes the voltage of the differential signal in all conversion cycles for every bit CDAC,conv ), an analog-to-digital converter that monotonicly controls the voltage of the differential signal in the conversion cycle for every bit (V CDAC,monotonic ), and an analog-to-digital converter (V) that monotonically controls only the conversion cycle for the least significant bit. CDAC,proposed , 10) may have a speed difference in the voltage change of the CDAC output during the conversion cycle for the most significant bit.

[0095] The analog-to-digital converter of the present disclosure (V) monotonically controls only the conversion cycle for the least significant bit. CDAC,proposed , 10) has the smallest capacitance of the CDAC circuit (100) among the three types of analog-to-digital converters. When the capacitance of the CDAC circuit (100) is small, the control speed of the CDAC circuit (100) can be improved.

[0096] Accordingly, referring to FIG. 5, the analog-to-digital converter (V) of the present disclosure CDAC,proposed The graph waveform of , 10) changes the fastest.

[0097] That is, the analog-to-digital converter (V) of the present disclosure CDAC,proposed , 10) is the case where the voltage of the differential signal is changed entirely in the conversion cycle for every bit (V CDAC,conv ) and in the case where the voltage of the differential signal is monotonicly controlled in the conversion cycle for all bits (V CDAC,monotonic Compared to ), the output speed of the CDAC circuit (100) can be adjusted within a relatively short time.

[0098] FIGS. 6a, FIGS. 6b, and FIGS. 6c illustrate the output results of the CDAC circuit (100) in a conversion cycle for the most significant bit. Descriptions that overlap with FIG. 5 are omitted.

[0099] Referring to FIG. 6c, the analog-to-digital converter (10) of the present disclosure can control both the first intermediate voltage (MP) and the second intermediate voltage (MN) when generating bits adjacent to the least significant bit from the most significant bit. Accordingly, the analog-to-digital converter (10) of the present disclosure differs in waveform from the analog-to-digital converter of FIG. 6b which monotonically controls the conversion cycle for all bits.

[0100] Additionally, referring to FIG. 6c, the output of the CDAC circuit (100) of the present disclosure may be a differential output. That is, the analog-to-digital converter (10) of the present disclosure may have the same differential voltage change in cycles excluding the last cycle as the analog-to-digital converter that changes the voltage of the differential signal in all bit conversion cycles of FIG. 6a. Additionally, the common mode voltage of the CDAC output of the analog-to-digital converter (10) of the present disclosure may be maintained in cycles excluding the last cycle.

[0101] As described above in FIG. 1, when the common mode voltage is maintained, the linearity of the analog-to-digital converter (10) can be improved.

[0102] FIGS. 7a, 7b, and 7c illustrate the output results of the CDAC circuit (100) in a conversion cycle for the least significant bit. Descriptions that overlap with FIGS. 5 and 6 are omitted. The output results of the CDAC circuit (100) shown in FIG. 7 can be referenced as an example of the analog-to-digital converter (10) shown in FIG. 1.

[0103] Referring to FIG. 7a, the analog-to-digital converter (10) of the present disclosure can change the voltage of each differential signal in a conversion cycle from the most significant bit to the least significant bit and adjacent bits. Here, when the voltage of the differential signal changes, the common mode voltage of the CDAC circuit (100) can be maintained. That is, by maintaining the common mode voltage of the CDAC circuit (100), the analog-to-digital converter (10) can minimize changes in the dynamic offset of the comparator (200) or changes in the input-referred-noise characteristics.

[0104] Referring to FIG. 7b according to one embodiment, the analog-to-digital converter (10) of the present disclosure can reduce any one of the voltages of the differential signal by monotonically controlling the CDAC circuit (100) in the conversion cycle for the least significant bit.

[0105] Referring to FIG. 7c according to another embodiment, the analog-to-digital converter (10) of the present disclosure can increase any one of the voltages of the differential signal by monotonically controlling the CDAC circuit (100) in the conversion cycle for the least significant bit.

[0106] The foregoing describes specific embodiments for implementing the present disclosure. In addition to the embodiments described above, the present disclosure may also include embodiments that are simply modified or can be easily modified. Furthermore, the present disclosure may also include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present disclosure should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of this application.

Claims

Claim 1 An analog-to-digital converter that converts a first input voltage and a second input voltage, which are analog signals, into a digital signal composed of a plurality of bits, comprising: a first CDAC (capacitive digital-to-analog converter) that outputs a first intermediate voltage from the first input voltage; a second CDAC that outputs a second intermediate voltage from the second input voltage; a comparator that compares the magnitudes of the first intermediate voltage and the second intermediate voltage; and a control logic circuit that sequentially outputs the plurality of bits from the most significant bit to the least significant bit based on a comparison result output from the comparator, wherein the control logic circuit controls the magnitudes of the first intermediate voltage and the second intermediate voltage through the first CDAC and the second CDAC to output each of the first bits adjacent to the most significant bit to the least significant bit, and controls the magnitude of the first intermediate voltage through the first CDAC to output the least significant bit. Claim 2 An analog-to-digital converter according to claim 1, further comprising: a first reference voltage terminal receiving a first reference voltage; and a second reference voltage terminal receiving a second reference voltage smaller than the first reference voltage; wherein the first CDAC comprises a plurality of first capacitors selectively connected between each of the first reference voltage terminal and the second reference voltage terminal and a first node where the first intermediate voltage is output; and a first additional capacitor connected between the second reference voltage terminal and the first node; and wherein the second CDAC comprises a plurality of second capacitors selectively connected between each of the first reference voltage terminal and the second reference voltage terminal and a second node where the second intermediate voltage is output; and a second additional capacitor connected between the second reference voltage terminal and the second node. Claim 3 In claim 2, the first CDAC comprises a plurality of first switches connected to each of the plurality of first capacitors, and the second CDAC comprises a plurality of second switches connected to each of the plurality of second capacitors, an analog-to-digital converter. Claim 4 In claim 1, the control logic circuit outputs a bit with a value of "1" when the magnitude of the first intermediate voltage is greater than the magnitude of the second intermediate voltage, and outputs a bit with a value of "0" when the magnitude of the first intermediate voltage is less than the magnitude of the second intermediate voltage. Claim 5 In claim 3, among the plurality of first switches, the first least bit switch used for analog-to-digital conversion of the least bit is connected to the first least bit capacitor among the plurality of first capacitors, and among the plurality of second switches, the second least bit switch used for analog-to-digital conversion of the least bit is connected to the second least bit capacitor among the plurality of second capacitors, and the control logic circuit, in response to the output of each bit from the most significant bit to the second bit adjacent to the first bit, when the magnitude of the first intermediate voltage is greater than the second intermediate voltage, controls the first-7 switch among the plurality of first switches to connect the first-7 capacitor among the plurality of first capacitors connected to the first-7 switch to the second reference voltage terminal, and controls the second-7 switch among the plurality of second switches to connect the second-7 capacitor among the plurality of second capacitors connected to the second-7 switch to the first reference voltage terminal, and the first adjacent to the least bit An analog-to-digital converter that, in response to a bit being output, controls the second least significant bit switch to connect the second least significant bit capacitor to the first reference voltage terminal when the magnitude of the first intermediate voltage is greater than the second intermediate voltage. Claim 6 An analog-to-digital converter according to claim 3, wherein the plurality of first capacitors include a first least bit capacitor having the same capacitance as the first additional capacitor, and the plurality of second capacitors include a second least bit capacitor having the same capacitance as the second additional capacitor. Claim 7 An analog-to-digital converter according to claim 6, wherein among the plurality of first capacitors, the first-1 capacitor and the first-2 capacitor among the plurality of first capacitors have the same capacitance as the first additional capacitor, among the plurality of second capacitors, the second-1 capacitor and the second-2 capacitor among the plurality of second capacitors have the same capacitance as the second additional capacitor, each of the first-3 capacitor among the plurality of first capacitors and the first-4 capacitor among the plurality of first capacitors has twice the capacitance of the first-1 capacitor, and each of the second-3 capacitor among the plurality of second capacitors and the second-4 capacitor among the plurality of second capacitors has twice the capacitance of the second-1 capacitor. Claim 8 In claim 7, the control logic circuit, in an operation of outputting each of the first bits adjacent to the most significant bit to the least significant bit, when the magnitude of the first intermediate voltage is greater than the magnitude of the second intermediate voltage, controls the first-6 switch among the plurality of first switches connected to the first-6 capacitor among the plurality of first capacitors to connect the first-6 capacitor connected to the first reference voltage terminal to the second reference voltage terminal, and controls the second-5 switch among the plurality of second switches connected to the second-5 capacitor among the plurality of second capacitors to connect the second-5 capacitor connected to the second reference voltage terminal to the first reference voltage terminal, and when the magnitude of the first intermediate voltage is smaller than the magnitude of the second intermediate voltage, controls the first-5 switch among the plurality of first switches connected to the first-5 capacitor among the plurality of first capacitors to connect the first-5 capacitor connected to the second reference voltage terminal to the first reference voltage terminal, and among the plurality of second capacitors An analog-to-digital converter that controls the 2-6 switch among the plurality of 2 switches connected to the 2-6 capacitor to connect the 2-6 capacitor, which is connected to the 1 reference voltage terminal, to the 2 reference voltage terminal. Claim 9 In claim 8, the first least bit switch used for analog-to-digital conversion of the least bit among the plurality of first switches is connected to the first least bit capacitor among the plurality of first capacitors, and the second least bit switch used for analog-to-digital conversion of the least bit among the plurality of second switches is connected to the second least bit capacitor among the plurality of second capacitors, and the control logic circuit, in an operation of outputting the least bit, connects the first least bit switch from the first reference voltage terminal to the second reference voltage terminal when the magnitude of the first intermediate voltage is greater than the magnitude of the second intermediate voltage, and connects the second least bit switch from the first reference voltage terminal to the second reference voltage terminal when the magnitude of the first intermediate voltage is smaller than the magnitude of the second intermediate voltage, an analog-to-digital converter. Claim 10 An analog-to-digital converter according to claim 2, wherein the first reference voltage is 1V and the second reference voltage is 0V.

Images