Data recovery circuit that acquires data using clock signal

Abstract

The present invention relates to a data recovery circuit for acquiring continuous data in response to a rising edge of a clock signal, comprising: a first circuit for acquiring second data continuous with respect to a first data based on a first external signal, a second external signal having a differential relationship, and a previously acquired first data; and a second circuit for acquiring an integral value between the second data and a third data continuous with respect to the second data from the first external signal and the second external signal, and acquiring the third data by subtracting the second data from the integral value. The first circuit further comprises a high-band filter for outputting a first slope signal of the first external signal and a second slope signal of the second external signal, a comparator for outputting a comparison result between the first slope signal and the second slope signal, and a decoding circuit for acquiring the second data based on the comparison result and the first data.

Description

Technology Field

[0001] The present invention relates to a data recovery circuit, and more specifically, to a data recovery circuit that operates by a clock signal having a speed of half the data transmission speed. Background Technology

[0002] Conventionally, when transmitting data, a clock signal required for data extraction was transmitted along with the data signal, and after receiving it at the receiving circuit, the data signal was acquired based on the clock signal to extract the data. However, as systems become faster and operating voltages decrease, this method causes various problems. For example, as the data speed of the memory interface increases, the frequency of the required clock signal has also steadily increased; however, there is a disadvantage in that the Bit Error Rate (BER) deteriorates due to clock jitter, which increases as the frequency of the clock signal increases.

[0003] To solve this problem, memory interfaces have utilized a method of using clock signals with a speed of half or one-fourth of the data transfer speed. However, using low-speed clock signals requires clocks with multiple phases, and additional circuits such as QPGs (Quadrature Phase Generators) are used to generate them, which increases power consumption. The problem to be solved

[0004] The present invention aims to provide a data recovery circuit that uses a clock at a speed lower than the data transmission speed and does not require a circuit for generating clocks of multiple phases or an additional reference voltage. means of solving the problem

[0005] The present invention relates to a data recovery circuit for acquiring continuous data in response to a rising edge of a clock signal, comprising: a first circuit for acquiring second data continuous to the first data based on a first external signal, a second external signal, and previously acquired first data that are in a differential relationship; and a second circuit for acquiring an integral value between the second data and third data continuous to the second data from the first external signal and the second external signal, and acquiring third data by subtracting the second data from the integral value.

[0006] In addition, a first circuit according to one embodiment is characterized by including a high-band filter that outputs a first slope signal of a first external signal and a second slope signal of a second external signal, a comparator that outputs a comparison result between the first slope signal and the second slope signal, and a decoding circuit that acquires second data based on the comparison result and the first data.

[0007] In addition, the first comparison signal and the second comparison signal output from the comparator according to one embodiment are characterized in that they have different values ​​when the difference between the first slope signal and the second slope signal exceeds a threshold value, and have the same value when the difference between the first slope signal and the second slope signal is less than or equal to the threshold value.

[0008] Additionally, a decoding circuit according to one embodiment further includes a NAND gate that receives a first comparison signal and a second comparison signal, and a multiplexer that selectively outputs the first comparison signal and the second comparison signal, or the first data, as the second data based on a control signal output from the NAND gate. The circuit is characterized in that if the comparison result has a value less than or equal to a threshold value from a reference value, the first data is output as the second data; if the comparison result has a positive value exceeding the threshold value from the reference value, “1” is output as the second data; and if the comparison result has a negative value exceeding the threshold value from the reference value, “0” is output as the second data.

[0009] In addition, the flip-flop of the first circuit according to one embodiment is connected between a NAND gate and a multiplexer, and outputs the control signal output from the NAND gate in response to the rising edge of an external clock signal, and the comparator is characterized in that when the difference between the first slope signal and the second slope signal is less than or equal to the threshold value, the rising edge of the external clock signal subsequently outputs a comparison result.

[0010] In addition, the first circuit according to one embodiment is characterized by including an amplifier circuit that amplifies and outputs a first external signal and a second external signal.

[0011] In addition, a second circuit according to one embodiment is characterized by including an integration circuit that obtains an integral value by performing an integration operation between second data and third data from a first external signal and a second external signal, and a circuit that outputs third data by subtracting a value obtained by multiplying the second data by a specified weight from the integral value.

[0012] In addition, a data recovery circuit for acquiring continuous data in response to a rising edge of a clock signal according to one embodiment is characterized by comprising: a first circuit for acquiring second data continuous with said first data based on the slopes of each of a first external signal and a second external signal having a differential relationship and a first data already acquired; and a second circuit for acquiring third data continuous with said second data based on the first external signal, the second external signal, and the second data.

[0013] In addition, the second circuit according to one embodiment is characterized by further including an integration circuit that performs an integration operation between second data and third data from a first external signal and a second external signal, and an output circuit that outputs third data by subtracting a value obtained by multiplying the second data by a specified weight from an integration value output from the integration circuit.

[0014] In addition, the output circuit according to one embodiment is characterized by including a circuit that outputs the result of subtracting the value obtained by multiplying the integral value output by the integration circuit by a weight specified for the second data.

[0015] In addition, the second circuit according to one embodiment is characterized by further including a latch circuit that outputs third data while a reset signal is applied to the output circuit. Effects of the invention

[0016] The data recovery circuit of the present invention can improve the performance of data communication by receiving data using a clock signal having a speed lower than the data transmission speed.

[0017] In addition, the data recovery circuit of the present invention can reduce the power required for phase control of the clock signal by receiving data using a clock signal having a speed lower than the data transmission speed and a signal having an inverse phase of the clock signal. Brief explanation of the drawing

[0018] The drawings attached below are intended to aid in understanding various examples of the present disclosure and provide various examples of the present disclosure together with a detailed description. However, the technical features of the various examples of the present disclosure are not limited to specific drawings, and the features disclosed in each drawing may be combined with one another to form new embodiments. Reference numerals in each drawing denote structural elements. FIG. 1 is a block diagram illustrating the configuration of a data recovery circuit according to one embodiment of the present disclosure. FIG. 2 is a diagram illustrating a data acquisition operation using an embodiment of the present disclosure. FIG. 3 is a circuit diagram of a first circuit among data recovery circuits according to one embodiment of the present disclosure. FIG. 4 is a circuit diagram of a decoding circuit in a first circuit according to one embodiment of the present disclosure. FIG. 5 is a circuit diagram of a second circuit among data recovery circuits according to one embodiment of the present disclosure. FIG. 6 is a circuit diagram of a data recovery circuit according to one embodiment of the present disclosure. Specific details for implementing the invention

[0019] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

[0020] The detailed description set forth below, together with the accompanying drawings, is intended to describe exemplary embodiments of the invention and is not intended to represent the only embodiment in which the invention may be practiced. The following detailed description includes specific details to provide a complete understanding of the invention. However, those skilled in the art will know that the present disclosure may be practiced without such specific details.

[0021] In some cases, to avoid obscuring the concept of the present disclosure, known structures and devices may be omitted or illustrated in the form of block diagrams focusing on the core functions of each structure and device. Additionally, throughout the entire disclosure, the same components are described using the same reference numerals.

[0022] Various examples according to the concept of the present invention may be subject to various modifications and may take various forms; therefore, various examples are illustrated in the drawings and described in detail in this disclosure. However, this is not intended to limit the various examples according to the concept of the present invention to specific disclosed forms, and includes modifications, equivalents, or substitutions that fall within the spirit and scope of the present invention.

[0023] Terms such as "first" or "second" may be used to describe various components, but said components should not be limited by said terms. For the sole purpose of distinguishing one component from another, for example, without departing from the scope of rights according to the concept of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component.

[0024] The terms used in this disclosure are used merely to describe specific various examples and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this disclosure, terms such as “comprising” or “having” are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0025] In the following, embodiments of the present invention will be described clearly and in detail with reference to the accompanying drawings.

[0026] FIG. 1 is a block diagram illustrating the configuration of a data recovery circuit according to one embodiment of the present disclosure. FIG. 2 is a diagram showing a data acquisition operation using one embodiment of the present disclosure.

[0027] Referring to FIG. 1, a data recovery circuit (10) according to an embodiment of the present disclosure may include an amplifier circuit (100), a first circuit (200), and a second circuit (300).

[0028] Here, the first external signal (OS1) and the second external signal (OS2) may have a differential relationship.

[0029] The amplifier circuit (100) can amplify the first external signal (OS1) and the second external signal (OS2).

[0030] For example, the amplifier circuit (100) may be composed of an S2D amplifier (Single-to-Differential Amplifier) ​​and a CTLE (Continuous Time Linear Equalizer), but is not limited thereto.

[0031] Referring to FIG. 1 and FIG. 2 together, the data recovery circuit (10) can acquire consecutive second data (D2) and third data (D3) in response to the rising edge of the odd clock signal (CK_ODD).

[0032] More specifically, the data recovery circuit (10) may include a first circuit (200) that outputs a second data (D2) from a first external signal (OS1), a second external signal (OS2), and previously acquired first data (D1) in response to the rising edge of an odd clock signal (CK_ODD).

[0033] Here, the first data (D1) can be understood as data previously acquired in response to the rising edge of an even clock signal (CK_EVEN) having an inverse phase with an odd clock signal (CK_ODD).

[0034] Also, here, for example, the speed (or frequency) of the odd clock signal (CK_ODD) may have a value equal to 1 / 4 of the speed (or frequency) of the first external signal (OS1) and the second external signal (OS2).

[0035] The first circuit (200) can receive the amplified first external signal (OS1) and the second external signal (OS2).

[0036] Additionally, the first circuit (200) can output a second data (D2) that is continuous with the first data (D1) based on a first external signal (OS1), a second external signal (OS2), and the first data (D1).

[0037] More specifically, the first circuit (200) can output a second data (D2) that is continuous with the first data (D1) based on the result of comparison between the slopes of each of the first external signal (OS1) and the second external signal (OS2), and the first data (D1) that has already been acquired.

[0038] For example, the first circuit (200) can output the value of the second data (D2) as “1” if the result of comparing the slope of the first external signal (OS1) and the slope of the second external signal (OS2) is positive.

[0039] In another example, the first circuit (200) can output a second data (D2) having the same value as the first data (D1) when the result of comparing the slope of the first external signal (OS1) and the slope of the second external signal (OS2) has a difference less than a threshold value from “0”.

[0040] As another example, the first circuit (200) can output the value of the second data (D2) as “0” when the result of comparing the slope of the first external signal (OS1) and the slope of the second external signal (OS2) is negative.

[0041] Additionally, the data recovery circuit (10) may include a second circuit (300) that outputs a third data (D3) that is continuous with the second data (D2) based on a first external signal (OS1), a second external signal (OS2), and second data (D2).

[0042] More specifically, the second circuit (300) can obtain an integral value between the second data (D2) and the third data (D3) that is continuous with the second data (D2).

[0043] Additionally, the second circuit (300) can output the third data (D3) by subtracting the second data (D2) from the integral value.

[0044] For example, the second circuit (300) can output the third data (D3) by subtracting the value obtained by multiplying the second data (D2) by a pre-set weight from the integral value between the second data (D2) and the third data (D3).

[0045] Referring to the configurations described above, a data recovery circuit (10) according to one embodiment can acquire two consecutive data in response to the rising edge of a clock signal having a speed smaller than the data transmission speed.

[0046] For example, the data recovery circuit (10) can acquire consecutive second data (D2) and third data (D3) in response to the rising edge of an odd clock signal (CK_ODD) having a speed equal to 1 / 4 of the speed of the first external signal (OS1) and the second external signal (OS2).

[0047] The data recovery circuit (10) according to the embodiment of the present disclosure acquires data using a clock signal having a speed smaller than the data transmission speed, thereby minimizing the decrease in performance of data communication due to the increase in the speed of the clock signal.

[0048] Through this, the data recovery circuit (10) can improve the performance of data communication.

[0049] In addition, the data recovery circuit (10) according to the embodiment of the present disclosure can reduce the power required for phase control of the clock signal by receiving data using an odd clock signal (CK_ODD) and an even clock signal (CK_EVEN) having opposite phases to each other.

[0050] One embodiment of the present disclosure can restore data by using two phases of an odd clock signal (CK_ODD) and an even clock signal (CK_EVEN), each having a speed equal to 1 / 4 of the data transmission speed.

[0051] FIG. 3 is a circuit diagram of a first circuit (200) among data recovery circuits according to one embodiment of the present disclosure.

[0052] Referring to FIG. 3, a first circuit (200) according to an embodiment of the present disclosure may include a high-band filter (210), a comparator (220), and a decoding circuit (230).

[0053] The first circuit (200) may include a high-band filter (210) that outputs a slope signal of each of the first external signal (OS1) and the second external signal (OS2).

[0054] The high-band filter (210) can receive a first external signal (OS1) and output a first slope signal (HPP).

[0055] A high-band filter (210) according to one embodiment can output a first slope signal (HPP) corresponding to the slope of the first external signal (OS1) from the first external signal (OS1).

[0056] Additionally, the high-band filter (210) can output a second slope signal (HPN) corresponding to the slope of the second external signal (OS2) from the second external signal (OS2).

[0057] The comparator (220) can compare the first slope signal (HPP) and the second slope signal (HPN) to output the first comparison signal (CPP) and the second comparison signal (CPN).

[0058] For example, if the difference between the first slope signal (HPP) and the second slope signal (HPN) exceeds a threshold value, the first comparison signal (CPP) may have a value of “1” and the second comparison signal (CPN) may have a value of “0”.

[0059] The comparison signal output from the comparator (220) may have the same value when the difference between the first slope signal (HPP) and the second slope signal (HPN) is less than or equal to a threshold value.

[0060] For example, if the difference between the first slope signal (HPP) and the second slope signal (HPN) is less than or equal to a threshold value, the first comparison signal (CPP) may have a value of “1” and the second comparison signal (CPN) may have a value of “1”.

[0061] The decoding circuit (230) can output second data (D2) based on the first comparison signal (CPP), the second comparison signal (CPN), and the first data (D1).

[0062] More specifically, the decoding circuit (230) can determine the value of the second data (D2) based on whether the result of comparison between the first comparison signal (CPP) and the second comparison signal (CPN) exceeds a preset threshold value from a reference value (e.g., “0”).

[0063] For example, the decoding circuit (230) can output the first data (D1) as the second data (D2) when the result of comparison between the first comparison signal (CPP) and the second comparison signal (CPN) has a value less than or equal to a threshold value from a reference value.

[0064] In another example, the decoding circuit (230) can output “1” as the second data (D2) when the result of comparison between the first comparison signal (CPP) and the second comparison signal (CPN) has a positive value exceeding a threshold value from the reference value.

[0065] In another example, the decoding circuit (230) can output “0” as the second data (D2) if the result of comparison between the first comparison signal (CPP) and the second comparison signal (CPN) exceeds a threshold value from the reference value and has a negative value.

[0066] That is, the decoding circuit (230) can determine the value of the second data (D2) based on the sign of the comparison result when the comparison result between the first comparison signal (CPP) and the second comparison signal (CPN) has a difference greater than or equal to a threshold value from a reference value.

[0067] FIG. 4 is a circuit diagram of a decoding circuit (230) in a first circuit (200) according to one embodiment of the present disclosure.

[0068] Referring to FIG. 4, the first external signal (OS1) and the second external signal (OS2) can be input to a high-band filter (210).

[0069] Referring to FIG. 4, the high-band filter (210) can output a first slope signal (HPP) and a second slope signal (HPN).

[0070] The comparator (220) can output a first comparison signal (CPP) and a second comparison signal (CPN).

[0071] Furthermore, the comparator (220) can receive the first slope signal (HPP) and the second slope signal (HPN) output from the high-band filter (210).

[0072] Additionally, the comparator (220) can output a first comparison signal (CPP) and a second comparison signal (CPN) based on the first slope signal (HPP) and the second slope signal (HPN).

[0073] The NAND gate (240) can receive a first comparison signal (CPP) and a second comparison signal (CPN) output from the comparator (220).

[0074] For example, the NAND gate (240) can output “1” if the value of the product of the first comparison signal (CPP) and the second comparison signal (CPN) is “0”.

[0075] For example, the NAND gate (240) can output “0” if the value of the product of the first comparison signal (CPP) and the second comparison signal (CPN) is “1”.

[0076] The multiplexer (270) can selectively output one of the first comparison signal (CPP), the second comparison signal (CPN), or the first data (D1) as the second data based on the control signal output from the NAND gate (240).

[0077] The flip-flop (250) can be connected between the NAND gate (240) and the multiplexer (270).

[0078] The flip-flop (250) can output a control signal output from the NAND gate (240) in response to the rising edge of the external clock signal (CK_O).

[0079] The decoding circuit (230) may include a first latch (260) that receives a first comparison signal (CCP) and a second comparison signal (CPN) and outputs them to a multiplexer (270).

[0080] The first latch (260) can receive the first comparison signal (CPP) and the second comparison signal (CPN) output from the comparator (220).

[0081] According to one embodiment, the first latch (260) can output the values ​​of the first comparison signal (CPP) and the second comparison signal (CPN) to the multiplexer (270) while a reset signal is input to the decoding circuit (230).

[0082] FIG. 5 is a circuit diagram of a second circuit (300) of a data recovery circuit (10) according to one embodiment of the present disclosure.

[0083] Referring to FIG. 5, the second circuit (300) can receive a first external signal (OS1) and a second external signal (OS2).

[0084] The second circuit (300) may include an integration circuit (310) that outputs a first integration signal (INP) and a second integration signal (INN).

[0085] More specifically, the integration circuit (310) can output a first integration signal (INP) and a second integration signal (INN) based on a first external signal (OS1) and a second external signal (OS2).

[0086] Here, the first integral signal (INP) and the second integral signal (INN) may be signals corresponding to the integral value obtained through the integral operation between the second data (D2) and the third data (D3) from the first external signal (OS1) and the second external signal (OS2).

[0087] The second circuit (300) may include an output circuit (320) that subtracts the value obtained by multiplying the first integral signal (INP) and the second integral signal (INN) by a weight specified in the second data (D2).

[0088] According to one embodiment, the output circuit (320) can output a first output signal (OUTP) and a second output signal (OUTN). Additionally, the second circuit (300) may include a weighting circuit (330) that receives second data (D2) and multiplies it by a specified weight.

[0089] The second circuit (300) may include a weighting circuit (330) that receives the second data (D2) and multiplies it by a specified weight.

[0090] The second circuit (300) may include a second latch (340) that receives a first output signal (OUTP) and a second output signal (OUTN) and outputs third data.

[0091] The second latch (340) can receive the first output signal (OUTP) and the second output signal (OUTN) output from the output circuit (320).

[0092] FIG. 6 is a circuit diagram of a data recovery circuit (10) according to one embodiment of the present disclosure.

[0093] Here, the data recovery circuit (10) illustrated in FIG. 6 can be understood to include a configuration substantially identical to that of the first circuit (200) illustrated in FIG. 3 and the second circuit (300) illustrated in FIG. 5.

[0094] Accordingly, the same reference numerals have been used for configurations that are identical or substantially identical to the aforementioned configurations, and descriptions that overlap with the aforementioned content are omitted.

[0095] The data recovery circuit (10) can output a continuous second data (D2) based on the slopes of the first external signal (OS1) and the second external signal (OS2), respectively, and the first data (D1) that has already been acquired, in response to the rising edge of the odd clock signal (CK_ODD).

[0096] More specifically, the data recovery circuit (10) can output a continuous second data (D2) based on the result of comparison between the slopes of each of the first external signal (OS1) and the second external signal (OS2), and the first data (D1) that has already been acquired.

[0097] For example, the data recovery circuit (10) can output the value of the second data (D2) as “1” if the result of comparing the slope of the first external signal (OS1) and the slope of the second external signal (OS2) is positive.

[0098] In another example, the data recovery circuit (10) can output a second data (D2) having the same value as the first data (D1) when the result of comparing the slope of the first external signal (OS1) and the slope of the second external signal (OS2) has a difference less than a threshold value from “0”.

[0099] Additionally, the data recovery circuit (10) can output a third data (D3) that is continuous with the second data (D2) based on a first external signal (OS1), a second external signal (OS2), and second data (D2).

[0100] More specifically, the data recovery circuit (10) can obtain an integral value between the second data (D2) and the third data (D3) that is consecutive to the second data (D2). Additionally, the data recovery circuit (10) can output the third data (D3) by subtracting a value obtained by multiplying the second data (D2) by a predetermined weight from the integral value.

[0101] That is, the data recovery circuit (10) according to the embodiment of the present disclosure can output two consecutive data in response to the rising edge of a single clock signal.

[0102] For example, the data recovery circuit (10) can acquire consecutive second data (D2) and third data (D3) in response to the rising edge of an odd clock signal (CK_ODD) having a speed equal to 1 / 4 of the speed of the first external signal (OS1) and the second external signal (OS2).

[0103] The data recovery circuit (10) according to the embodiment of the present disclosure acquires data using a clock signal having a speed smaller than the data transmission speed, thereby minimizing the decrease in performance of data communication due to the increase in the speed of the clock signal.

[0104] Through this, the data recovery circuit (10) can improve the performance of data communication.

[0105] In addition, the data recovery circuit (10) according to the embodiment of the present disclosure can reduce the power required for phase control of the clock signal by receiving data using an odd clock signal (CK_ODD) and an even clock signal (CK_EVEN) having opposite phases to each other.

[0106] The foregoing describes specific embodiments for carrying out the present disclosure. In addition to the embodiments described above, the present disclosure may also include embodiments that are simply modified or can be easily modified.

[0107] In addition, the present disclosure will also include techniques that can be easily modified and implemented using the embodiments.

[0108] Accordingly, the scope of the present disclosure should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of this disclosure. Explanation of the symbols

[0109] 10: Data recovery circuit 100: Amplifier circuit 200: First circuit 210: High-band filter 220: Comparator 230: Decoding circuit 240: NAND circuit 250: Flip-flop 260: 1st latch 270: Multiplexer 300: Second circuit 310: Integration circuit 320: Output circuit 330: Weighting circuit 340: Second latch

Claims

Claim 1 A data recovery circuit for acquiring continuous data in response to a rising edge of a clock signal, comprising: a first circuit for acquiring second data continuous to said first data based on a first external signal, a second external signal and a previously acquired first data having a differential relationship; and a second circuit for acquiring an integral value between said second data and a third data continuous to said second data from said first external signal and said second external signal, and acquiring said third data by subtracting said second data from said integral value, wherein the first circuit further comprises: a high-band filter for outputting a first slope signal of said first external signal and a second slope signal of said second external signal, a comparator for outputting a comparison result between said first slope signal and said second slope signal, and a decoding circuit for acquiring said second data based on said comparison result and said first data. Claim 2 A data recovery circuit according to claim 1, wherein the first comparison signal and the second comparison signal output from the comparator have different values ​​when the difference between the first slope signal and the second slope signal exceeds a threshold value, and have the same value when the difference between the first slope signal and the second slope signal is less than or equal to a threshold value. Claim 3 In paragraph 2, the decoding circuit further comprises: a NAND gate receiving the first comparison signal and the second comparison signal, and a multiplexer that selectively outputs the first comparison signal and the second comparison signal, or the first data, as the second data based on a control signal output from the NAND gate. Claim 4 In paragraph 3, the decoding circuit is a data recovery circuit that: outputs the first data as the second data when the comparison result has a value less than or equal to the threshold value from the reference value; outputs "1" as the second data when the comparison result has a positive value exceeding the threshold value from the reference value; and outputs "0" as the second data when the comparison result has a negative value exceeding the threshold value from the reference value. Claim 5 In paragraph 3, the data recovery circuit further comprises a flip-flop connected between the NAND gate and the multiplexer and outputting the control signal output from the NAND gate in response to the rising edge of an external clock signal, and the comparator outputs a comparison result after the rising edge of the external clock signal when the difference between the first slope signal and the second slope signal is less than or equal to the threshold value. Claim 6 A data recovery circuit according to claim 1, further comprising an amplifier circuit that amplifies and outputs the first external signal and the second external signal. Claim 7 A data recovery circuit according to claim 1, wherein the second circuit further comprises: an integration circuit that obtains the integral value by performing an integration operation between the second data and the third data from the first external signal and the second external signal, and a weighting circuit that outputs the third data by subtracting a value obtained by multiplying the second data by a specified weight from the integral value. Claim 8 A data recovery circuit for acquiring continuous data in response to a rising edge of a clock signal, comprising: a first circuit for acquiring second data continuous to said first data based on the slopes of each of a first external signal and a second external signal having a differential relationship and a first data already acquired; and a second circuit for acquiring third data continuous to said second data based on the first external signal, the second external signal and the second data, wherein the second circuit further comprises: an integration circuit for performing an integration operation between said second data and said third data from said first external signal and said second external signal; and an output circuit for outputting said third data by subtracting a value obtained by multiplying said second data by a specified weight from an integration value output from said integration circuit. Claim 9 In claim 8, the output circuit comprises a circuit that outputs the result of subtracting the value obtained by multiplying the integral value output by the integration circuit by a weight specified for the second data. Claim 10 In claim 8, the second circuit further comprises a data recovery circuit that outputs the third data while a reset signal is applied to the output circuit.

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