Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device comprises a substrate including a first surface and a second surface opposite to the first surface, an active pattern extending in a first direction on the first surface of the substrate, a first portion connected to a source / drain region of the active pattern, and a first source / drain contact including a second portion extending from the first portion in a first direction or in a second direction intersecting the first direction, a power rail providing voltage on the second surface of the substrate, a through electrode connected to the power rail and penetrating the substrate, and a landing pad connecting the through electrode and the second portion of the source / drain contact.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0002] As the electronics industry develops to a high degree, demands regarding the characteristics of semiconductor devices are steadily increasing. For example, there is a growing demand for high reliability, high speed, and / or multifunctionality in semiconductor devices. To meet these required characteristics, the structures within semiconductor devices are becoming increasingly complex and highly integrated. The problem to be solved

[0003] The technical problem that the present invention aims to solve is to provide a semiconductor device with improved Power, Performance, and Area (PPA).

[0004] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises a substrate including a first surface and a second surface opposite to the first surface, an active pattern extending in a first direction on the first surface of the substrate, a first portion connected to a source / drain region of the active pattern, and a first source / drain contact including a second portion extending from the first portion in a first direction or in a second direction intersecting the first direction, a power rail providing voltage on the second surface of the substrate, a through electrode connected to the power rail and penetrating the substrate on the second surface of the substrate, and a landing pad connecting the through electrode and the second portion of the source / drain contact.

[0006] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises: a substrate including a first surface and a second surface opposite to the first surface; a first active pattern extending in a first direction on the first surface of the substrate; a second active pattern extending in a first direction and spaced apart from the first active pattern in a second direction intersecting the first active pattern and the first direction on the first surface of the substrate; a third active pattern extending in a first direction and spaced apart from the first active pattern in a first direction on the first surface of the substrate; a gate electrode extending in a second direction on the first active pattern and the second active pattern; a source / drain contact connected to a source / drain region disposed on one side of the gate electrode of the first active pattern in the first direction; a power rail providing voltage on the second surface of the substrate; a through electrode connected to the power rail and penetrating the substrate; and a landing pad in contact with the source / drain contact and the through electrode between the first active pattern and the second active pattern or between the second active pattern and the third active pattern, wherein the source / drain contact comprises a source / drain region and It includes a first part in contact and a second part extending from the first part in a first direction or a second direction and in contact with a landing pad.

[0007] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises: a substrate including a first surface and a second surface opposite to the first surface; an active pattern extending in a first direction on the first surface of the substrate; a field insulating film covering at least a portion of the sidewall of the active pattern; a gate electrode extending in a second direction intersecting the first direction on the active pattern; a source / drain contact including a first portion connected to a source / drain region of the active pattern and a second portion extending from the first portion in a first direction or a second direction; a silicide film between the source / drain region and the source / drain contact; a power rail providing voltage on the second surface of the substrate; a back wiring connected to the power rail on the second surface of the substrate; a through electrode connected to the power rail and penetrating the substrate and the field insulating film; a landing pad on the field insulating film that contacts the through electrode and the second portion of the source / drain contact and comprises the same material as the gate electrode; and a front wiring connected to the source / drain contact on the first surface of the substrate.

[0008] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0009] FIG. 1 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. Figure 2 is a cross-sectional view taken along A-A' of Figure 1. Figure 3 is a cross-sectional view taken along B-B' of Figure 1. Figure 4 is a cross-sectional view taken along C-C' of Figure 1. Figure 5 is a cross-sectional view taken along B-B' of Figure 1. FIG. 6 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 7 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. Figure 8 is a cross-sectional view taken along D-D' of Figure 7. FIG. 9 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. Figure 10 is a cross-sectional view taken along E-E' of Figure 9. FIG. 11 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 12 is a cross-sectional view taken along F-F' of FIG. 11. FIG. 13 is a cross-sectional view taken along A-A' of FIG. 1. FIG. 14 is a cross-sectional view taken along C-C' of FIG. 1. FIGS. 15 to 21 are intermediate drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. Specific details for implementing the invention

[0010] FIG. 1 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 2 is a cross-sectional view taken along A-A' of FIG. 1. FIG. 3 is a cross-sectional view taken along B-B' of FIG. 1. FIG. 4 is a cross-sectional view taken along C-C' of FIG. 1.

[0011] Referring to FIG. 1, a semiconductor device according to some embodiments may include a substrate (100), an active pattern (F1, F2), gate electrodes (G1 to G3), first and second source / drain contacts (180, 280), a gate contact (190), first and second front vias (222, 242), first and second front wiring (232, 252), first and second power rails (312, 314), first and second through vias (400, 500), first and second landing pads (530, 630), first and second back vias (322, 342), and first and second back wiring (332, 352).

[0012] The substrate (100) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (100) may be a silicon substrate or may include other materials, such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0013] The substrate (100) may include a first surface (100a) and a second surface (100b) that are opposite to each other. In the embodiments described below, the first surface (100a) may be referred to as the front side of the substrate (100), and the second surface (100b) may be referred to as the back side of the substrate (100).

[0014] The substrate (100) may include a first active region (AR1), a second active region (AR2), and a field region between the first active region (AR1) and the second active region (AR2). The field region may form a boundary with the first active region (AR1) and the second active region (AR2). The first active region (AR1) and the second active region (AR2) may be spaced apart from each other. The first active region (AR1) and the second active region (AR2) may be separated by the field region.

[0015] The field region may be defined by a substrate trench (DT) formed within the substrate (100). The substrate trench (DT) may be a trench deeper than the pin-cut trench (FCT). The substrate trench (DT) may extend in a first direction (X) to separate a first active region (AR1) and a second active region (AR2).

[0016] Semiconductor devices (e.g., transistors) of different conductivity types may be formed on the first active region (AR1) and the second active region (AR2). For example, an NMOS transistor may be formed on the first active region (AR1) and a PMOS transistor may be formed on the second active region (AR2). As another example, a PMOS transistor may be formed on the first active region (AR1) and an NMOS transistor may be formed on the second active region (AR2).

[0017] Active patterns (F1, F2) may be formed on the substrate (100). For example, a first active pattern (F1) may be formed on a first active region (AR1), and a second active pattern (F2) may be formed on a second active region (AR2). The active patterns (F1, F2) may extend in a first direction (X). The active patterns (F1, F2) may be defined by a pin-cut trench (FCT). The pin-cut trench (FCT) may define the sidewalls of the active patterns (F1, F2). The active patterns (F1, F2) may be spaced apart from each other in a second direction (Y) that intersects the first direction (X). In some embodiments, the active patterns (F1, F2) may each include a pin-shaped pattern protruding from a first surface (100a) of the substrate (100).

[0018] The active pattern (F1, F2) may be part of the substrate (100) or may include an epitaxial layer grown from the substrate (100). The active pattern (F1, F2) may include, for example, an elemental semiconductor material such as silicon or germanium. Additionally, the active pattern (F1, F2) may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0019] A group IV-IV compound semiconductor may be, for example, a binary compound, a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound doped with a group IV element. A group III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb). In one example, the first active pattern (F1) may include the same material as the second active pattern (F2). In another example, the first active pattern (F1) may include a different material from the second active pattern (F2).

[0020] The number and arrangement of the first active pattern (F1) placed in the first active area (AR1), and the number and arrangement of the second active pattern (F2) placed in the second active area (AR2) are merely exemplary and are not limited to those illustrated.

[0021] A field insulating film (105) may be formed on a first surface (100a) of a substrate (100). The field insulating film (105) may be formed on a portion of the sidewall of a first active pattern (F1) and a portion of the sidewall of a second active pattern (F2). The field insulating film (105) may surround at least a portion of the sidewall of the first active pattern (F1) and at least a portion of the sidewall of the second active pattern (F2). The field insulating film (105) may fill a substrate trench (DT). The field insulating film (105) may fill a portion of a pin-cut trench (FCT). The active patterns (F1, F2) may protrude above the upper surface of the field insulating film (105). The field insulating film (105) may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0022] Gate electrodes (G1 to G3) can be formed on active patterns (F1, F2). Gate electrodes (G1 to G3) can intersect with active patterns (F1, F2). Gate electrodes (G1 to G3) can extend in a second direction (Y). Gate electrodes (G1 to G3) can be spaced apart from each other in a first direction (X). A second gate electrode (G2) can be placed between the first gate electrode (G1) and the third gate electrode (G3).

[0023] Each of the gate electrodes (G1 to G3) may include a gate conductive film (130). The gate conductive film (130) may include, for example, at least one of Ti, Ta, W, Al, Co, and combinations thereof, but is not limited thereto. The gate conductive film (130) may include, for example, silicon or silicon germanium, which are not metals.

[0024] Although the gate conductive film (130) is depicted as a single film, the technical concept of the present invention is not limited thereto. Unlike what is depicted, the gate conductive film (130) may be formed by stacking a plurality of conductive materials. For example, the gate conductive film (130) may include a work function control film that controls the work function and a filling conductive film that fills the space formed by the work function control film. The work function control film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive film may include, for example, W or Al. Such a gate conductive film (130) may be formed, for example, through a replacement process, but is not limited thereto.

[0025] A gate dielectric film (120) may be interposed between the active patterns (F1, F2) and the gate conductive film (130). For example, the gate dielectric film (120) may extend along the sidewalls and bottom surface of the gate conductive film (130). However, the technical concept of the present invention is not limited thereto, and the gate dielectric film (120) may extend along the bottom surface of the gate conductive film (130) but not along the sidewalls of the gate conductive film (130).

[0026] A gate dielectric film (120) may be interposed between a field insulating film (105) and a gate conductive film (130). The gate dielectric film (120) may be formed along the profile of an active pattern (F1, F2) protruding above the field insulating film (105) and along the upper surface of the field insulating film (105).

[0027] The gate dielectric film (120) may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include, for example, hafnium oxide, but is not limited thereto.

[0028] A gate spacer (140) may be formed on a substrate (100) and a field insulating film (105). The gate spacer (140) may extend along the side walls of the gate conductive film (130). The gate spacer (140) may be placed on the long side wall of the gate conductive film (130). For example, the gate spacer (140) may extend in a second direction (Y).

[0029] The gate spacer (140) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride and combinations thereof, but is not limited thereto.

[0030] The gate capping pattern (150) may extend along the upper surface of the gate conductive film (130). For example, the gate capping pattern (150) may extend in a second direction (Y) to cover the upper surface of the gate conductive film (130). However, the technical concept of the present invention is not limited thereto, and the gate capping pattern (150) may be further disposed on the upper surface of the gate spacer (140).

[0031] The gate capping pattern (150) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride and combinations thereof, but is not limited thereto.

[0032] A first source / drain region (160) may be disposed on a first active pattern (F1). The first source / drain region (160) may be formed within the first active pattern (F1) on both sides of a gate conductive film (130). The first source / drain region (160) may be disposed between adjacent gate conductive films (130). The first source / drain region (160) may be spaced apart from the gate conductive film (130) by a gate spacer (140).

[0033] The first source / drain region (160) may include an epitaxial layer formed within the first active pattern (F1). In some embodiments, the first active pattern (F1) may share the first source / drain region (160). For example, the first source / drain region (160) may be a merged epitaxial layer.

[0034] When the semiconductor device formed within the first active region (AR1) is an NFET, the first source / drain region (160) may include n-type impurities or impurities to prevent the diffusion of n-type impurities. For example, the first source / drain region (160) may include at least one of P, Sb, As, or a combination thereof.

[0035] A second source / drain region (260) may be disposed on a second active pattern (F2). The second source / drain region (260) may be formed within active patterns (F1, F2) on both sides of the gate conductive film (130). The second source / drain region (260) may be disposed between adjacent gate conductive films (130). The second source / drain region (260) may be spaced apart from the gate conductive film (130) by a gate spacer (140).

[0036] The second source / drain region (260) may include an epitaxial layer formed within the second active pattern (F2). In some embodiments, the second active pattern (F2) may share the second source / drain region (260). For example, the second source / drain region (260) may be a merged epitaxial layer.

[0037] In the case where the semiconductor device formed within the second active region (AR2) is a PFET, the second source / drain region (260) may include p-type impurities or impurities to prevent the diffusion of p-type impurities. For example, the second source / drain region (260) may include at least one of B, C, In, Ga, and Al or a combination thereof.

[0038] Although the first source / drain region (160) and the second source / drain region (260) are each depicted as single membranes, the technical concept of the present invention is not limited thereto. For example, the first source / drain region (160) and the second source / drain region (260) may each be formed as multiple membranes containing impurities of different concentrations.

[0039] First to sixth front interlayer insulating films (110, 210, 220, 230, 240, 250) may be formed on the first surface (100a) of the substrate (100). The first to sixth front interlayer insulating films (110, 210, 220, 230, 240, 250) may be stacked sequentially on the first surface (100a) of the substrate (100). The first to sixth front interlayer insulating films (110, 210, 220, 230, 240, 250) may include, for example, at least one of silicon oxide, silicon oxynitride, and a low-dielectric (low-k) material having a dielectric constant lower than that of silicon oxide, but are not limited thereto.

[0040] The first front interlayer insulating film (110) and the second front interlayer insulating film (210) may be formed to cover the field insulating film (105), the first source / drain region (160), the second source / drain region (260), the gate spacer (140), and the gate capping pattern (150). For example, the first front interlayer insulating film (110) may be formed on the field insulating film (105) to cover the sidewall of the gate spacer (140). The second front interlayer insulating film (210) may be formed on the first front interlayer insulating film (110) to cover the upper surface of the gate capping pattern (150).

[0041] A first source / drain contact (180) may be disposed on both sides of the gate electrodes (G1 to G3). The first source / drain contact (180) may be electrically connected to a first active region (AR1). The first source / drain contact (180) may be disposed on a first source / drain region (160) of a first active pattern (F1). The first source / drain contact (180) may be electrically connected to the first source / drain region (160) by penetrating the first front interlayer insulating film (110) and the second front interlayer insulating film (210). A first silicide film (165) may be formed between the first source / drain contact (180) and the first source / drain region (160).

[0042] In some embodiments, the first source / drain contact (180) may include a first portion (180a) connected to the first source / drain region (160) and a second portion (180b) extending from the first portion (180a) in a second direction (Y). The first portion (180a) may contact the first source / drain region (160). The second portion (180b) may contact the first landing pad (530), which will be described later.

[0043] A second source / drain contact (280) may be disposed on both sides of the gate electrodes (G1 to G3). The second source / drain contact (280) may be electrically connected to the second active region (AR2). The second source / drain contact (280) may be disposed on the second source / drain region (260) of the second active pattern (F2). The second source / drain contact (280) may be electrically connected to the second source / drain region (260) by penetrating the first front interlayer insulating film (110) and the second front interlayer insulating film (210). A second silicide film (265) may be formed between the second source / drain contact (280) and the second source / drain region (260).

[0044] In some embodiments, the second source / drain contact (280) may include a first portion (280a) connected to the second source / drain area (260) and a second portion (280b) extending from the first portion (280a) in a second direction (Y). The first portion (280a) may contact the second source / drain area (260). The second portion (280b) may contact the second landing pad (630), which will be described later.

[0045] The first and second source / drain contacts (180, 280) may each include a source / drain barrier film (182) and a source / drain filling film (184). The source / drain barrier film (182) may be interposed between the first and second front interlayer insulating films (110, 210) and the source / drain filling film (184).

[0046] The gate contact (190) may be placed, for example, on the second gate electrode (G2). The gate contact (190) may be connected to the gate conductive film (130) by penetrating the gate capping pattern (150). The gate contact (190) may also be placed on the first gate electrode (G1) and the third gate electrode (G3).

[0047] The gate contact (190) may include a gate barrier film (192) and a gate filling film (194). The gate barrier film (192) may be interposed between the gate capping pattern (150), the second and third front interlayer insulating films (210, 220), and the gate filling film (194).

[0048] For example, the source / drain barrier film (182) and the gate barrier film (192) may comprise at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof and nitrides thereof, but are not limited thereto. For example, the source / drain filling film (184) and the gate filling film (194) may comprise at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co) and alloys thereof, but are not limited thereto.

[0049] A first front via (222) may be provided within the third front interlayer insulating film (220). The first front via (222) may be placed in the first and second source / drain contacts (180, 280). The first front via (222) may be connected to the first and second source / drain contacts (180, 280). A first front wiring (232) may be provided within the fourth front interlayer insulating film (230). The first front wiring (232) may be connected to the first front via (222). A second front via (242) may be provided within the fifth front interlayer insulating film (240). The second front via (242) may be connected to the first front wiring (232). A second front wiring (252) may be provided within the sixth front interlayer insulating film (250). The second front wiring (252) can be connected to the second front via (242).

[0050] The first and second front vias (222, 242) and the first and second front wiring (232, 252) may include a front barrier film (202) and a front filling film (204). The front barrier film (202) may be interposed between the third to sixth front interlayer insulating films (220, 230, 240, 250) and the front filling film (204).

[0051] First to fifth rear interlayer insulating films (310, 320, 330, 340, 350) may be formed on the second surface (100b) of the substrate (100). The first to fifth rear interlayer insulating films (310, 320, 330, 340, 350) may be stacked sequentially on the second surface (100b). The first to fifth rear interlayer insulating films (310, 320, 330, 340, 350) may include, for example, at least one of silicon oxide, silicon oxynitride, and a low-dielectric (low-k) material having a dielectric constant lower than that of silicon oxide, but are not limited thereto.

[0052] A first power rail (312) and a second power rail (314) may be provided within the first rear interlayer insulating film (310). The first power rail (312) and the second power rail (314) may be disposed on the second surface (100b) of the substrate (100).

[0053] The first power rail (312) and the second power rail (314) may be extended, for example, in a first direction (X). The first power rail (312) may be spaced apart from the second power rail (314) in a second direction (Y). The first power rail (312) has a first voltage (V DD ) can provide. The second power rail (314) provides the second voltage (V SS ) can provide. For example, the first power rail (312) can provide a power voltage (V DD ) provides, and the second power rail (314) provides ground voltage (V SS It can provide ).

[0054] At least a portion of the first power rail (312) may overlap with the first landing pad (530) in a third direction (Z). The third direction (Z) may be a direction perpendicular to the first surface (100a) of the substrate (100). At least a portion of the second power rail (314) may overlap with the second landing pad (630) in a third direction (Z). For example, the first and second power rails (312, 314) may not overlap with the first and second active patterns (F1, F2) in a third direction (Z). Or the first and second power rails (312, 314) may overlap with at least a portion of the first and second active patterns (F1, F2) in a third direction (Z).

[0055] When a first power rail (312) and a second power rail (314) are formed on a first surface (100a) of a substrate (100) or within a field insulating film (105), there may be a risk of contamination of the first and second power rails (312, 314) during the process of forming a first source / drain region (160), etc., on the first surface (100a) of the substrate (100). However, in a semiconductor device according to some embodiments, the first and second power rails (312, 314) are formed on the second surface (100b) of the substrate (100), so the risk of contamination of the first and second power rails (312, 314) as described above may be reduced. In addition, the process of forming the first and second power rails (312, 314) is carried out separately from the process of forming the first source / drain region (160), etc. on the first surface (100a) of the substrate (100), so the process can be simplified.

[0056] A first rear via (322) may be provided within the second rear interlayer insulating film (320). The first rear via (322) may be placed on the first and second power rails (312, 314). The first rear via (322) may be connected to the first and second power rails (312, 314). A first rear wiring (332) may be provided within the third rear interlayer insulating film (330). The first rear wiring (332) may be connected to the first rear via (322). A second rear via (342) may be provided within the fourth rear interlayer insulating film (340). The second rear via (342) may be connected to the first rear wiring (332). A second rear wiring (352) may be provided within the fifth rear interlayer insulating film (350). The second rear wiring (352) can be connected to the second rear via (342).

[0057] The first and second power rails (312, 314), the first and second rear vias (322, 342), and the first and second rear wiring (332, 352) may be relatively larger than the first and second front vias (222, 242) and the first and second front wiring (232, 252).

[0058] The first and second power rails (312, 314), the first and second rear vias (322, 342), and the first and second rear wiring (332, 352) may include a rear barrier film (302) and a rear filling film (304). The rear barrier film (302) may be interposed between the first to fifth rear interlayer insulating films (310, 320, 330, 340, 350) and the rear filling film (304).

[0059] The first and second front vias (222, 242), the first and second front wiring (232, 252), the first and second power rails (312, 314), the first and second rear vias (322, 342), and the first and second rear wiring (332, 352) are shown only as being formed by a dual damascene process, but this is merely illustrative, and they may, of course, be formed by a single damascene process or other wiring processes.

[0060] The first and second rear vias (322, 342) and the first and second rear wiring (332, 352) can form a power delivery network (PDN) of a semiconductor device according to some embodiments. For example, the first and second rear vias (322, 342) and the first and second rear wiring (332, 352) can be connected to pads, etc. of a semiconductor device according to some embodiments to receive power from the outside and deliver it. Accordingly, since the semiconductor device according to some embodiments includes first and second power rails (312, 314) and a power delivery network formed on the second surface (100b) of the substrate (100), the Power, Performance, Area (PPA) can be improved or enhanced compared to a semiconductor device in which the first and second power rails (312, 314) and / or power delivery network are formed on the first surface (100a) of the substrate (100).

[0061] The arrangement, number, etc. of the first and second front vias (222, 242), first and second front wires (232, 252), first and second rear vias (322, 342), and first and second rear wires (332, 352) are merely exemplary and are not limited thereto.

[0062] For example, the front barrier film (202) and the rear barrier film (302) may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and nitrides thereof, but are not limited thereto. For example, the front filling film (204) and the rear filling film (304) may include at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), and alloys thereof, but are not limited thereto.

[0063] The first and second landing pads (530, 630) may be placed on a substrate (100) where the first and second active patterns (F1, F2) are not placed. The first and second landing pads (530, 630) may be placed on a field insulating film (105). For example, the first and second landing pads (530, 630) may be placed in an area where dummy pins have been removed. Accordingly, the Power, Performance, Area (PPA) of a semiconductor device according to some embodiments may be improved or enhanced.

[0064] In some embodiments, the first and second landing pads (530, 630) may be placed between two adjacent gate electrodes among the gate electrodes (G1 to G3) arranged at regular intervals. The first landing pad (530) and the second landing pad (630) may be placed between the same gate electrodes. For example, the first landing pad (530) may be placed between the first gate electrode (G1) and the second gate electrode (G2), and the second landing pad (630) may be placed between the first gate electrode (G1) and the second gate electrode (G2). It may be overlapped with the first power rail (312) in the third direction (Z). The second landing pad (630) may be placed between the first gate electrode (G1) and the second gate electrode (G2) and overlapped with the second power rail (314) in the third direction (Z).

[0065] For example, the width (W11) of the first landing pad (530) in the first direction (X) and the width (W12) of the second landing pad (630) in the first direction (X) may be substantially the same as the width (W13) of the gate electrodes (G1 to G3) in the first direction (X).

[0066] The first and second landing pads (530, 630) can penetrate the first front interlayer insulating film (110). The first landing pad (530) can connect the first source / drain contact (180) and the first through-via (400). The first landing pad (530) can contact the second portion (180b) of the first source / drain contact (180) and the first through-via (400). The second landing pad (630) can connect the second source / drain contact (280) and the second through-via (500). The second landing pad (630) can contact the second portion (280b) of the second source / drain contact (280) and the second through-via (500).

[0067] The first and second landing pads (530, 630) can be formed by a process of forming gate electrodes (G1 to G3). The upper surfaces of the first and second landing pads (530, 630) can be placed on the same plane as the upper surface of the gate capping pattern (150). A first spacer (540) can be placed on the side walls of the first landing pad (530), and a second spacer (640) can be placed on the side walls of the second landing pad (630). The first spacer (540) and the second spacer (640) can be placed on the uppermost surface (105US) of the field insulating film.

[0068] In some embodiments, a first dielectric film (520) may be disposed between the first landing pad (530) and the first spacer (540). The first dielectric film (520) may be formed along both side walls of the first landing pad (530). A second dielectric film (620) may be disposed between the second landing pad (630) and the second spacer (640). The second dielectric film (620) may be formed along both side walls of the second landing pad (630).

[0069] The first and second landing pads (530, 630) may include the same material as the gate conductive film (130). The first and second spacers (540, 640) may include the same material as the gate spacer (140). The first and second dielectric films (520, 620) may include the same material as the gate dielectric film (120).

[0070] In a semiconductor device according to some embodiments, the first and second through-vias (400, 500) and the first and second source / drain contacts (180, 280) are connected by the first and second landing pads (530, 630), so a separate process is not required to form power vias to connect the first and second through-vias (400, 500) and the first and second source / drain contacts (180, 280). In addition, since the first and second landing pads (530, 630) are formed by the same process as the gate electrodes (G1 to G3), a separate process is not required to form the first and second landing pads (530, 630). Thus, the process can be simplified.

[0071] The first and second through-vias (400, 500) can penetrate the substrate (100) and the field insulating film (105). The first through-via (400) can penetrate the substrate (100) and the field insulating film (105) to connect the first power rail (312) and the first landing pad (530). The second through-via (500) can penetrate the substrate (100) and the field insulating film (105) to connect the second power rail (314) and the second landing pad (630). Accordingly, the first source / drain region (160) receives the first voltage (V) from the first power rail (312) through the first through-via (400), the first landing pad (530), and the first source / drain contact (180). DD) can be provided. The second source / drain region (260) receives a second voltage (V) from the second power rail (314) through the second through-via (500), the second landing pad (630), and the second source / drain contact (280). SS You can receive ).

[0072] In some embodiments, the upper surface (400US) of the first through-via (400) and the upper surface (500US) of the second through-via (500) may be positioned above the uppermost surface (105US) of the field insulating film (105).

[0073] In some embodiments, the width of the first through-via (400) may decrease as it extends from the first power rail (312) toward the first landing pad (530). The width of the second through-via (500) may decrease as it extends from the second power rail (314) toward the second landing pad (630). This may be attributed to the characteristics of the etching process for forming the first and second through-vias (400, 500). For example, the first and second through-vias (400, 500) may be formed from an etching process performed on the second surface (100b) of the substrate (100).

[0074] Figure 5 is a cross-sectional view taken along B-B' of Figure 1. For the convenience of explanation, the explanation will focus on the differences from the explanation using Figures 1 to 4.

[0075] Referring to FIG. 5, in a semiconductor device according to some embodiments, a first spacer (540) may be formed on both side walls of a first landing pad (530), and a second spacer (640) may be formed on both side walls of a second landing pad (630). The first dielectric film (520) of FIG. 3 is not formed between the first landing pad (530) and the first spacer (540), and the second dielectric film (620) of FIG. 3 is not formed between the second landing pad (630) and the second spacer (640).

[0076] FIG. 6 is a schematic layout diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 to 4.

[0077] Referring to FIG. 6, in a semiconductor device according to some embodiments, a first landing pad (530) and a second landing pad (630) may be placed between different gate electrodes. For example, the first landing pad (530) may be placed between a first gate electrode (G1) and a second gate electrode (G2), and the second landing pad (630) may be placed between a second gate electrode (G2) and a third gate electrode (G3).

[0078] FIG. 7 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 8 is a cross-sectional view taken along D-D' of FIG. 7. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 to 4.

[0079] Referring to FIGS. 7 and FIGS. 8, in a semiconductor device according to some embodiments, a first active region (AR1) may include a first active pattern (F11, F12, F13), and a second active region (AR2) may include a second active pattern (F21, F22).

[0080] The first-1 active pattern (F11) may be spaced apart from the first-2 active pattern (F12) in a first direction (X). The first-1 active pattern (F11) and the first-2 active pattern (F12) may be separated by a pin-cut trench (FCT). The sidewall of the first active pattern (F11) and the sidewall of the first-2 active pattern (F12) may face each other in the first direction (X). The first-3 active pattern (F13) may be spaced apart from the first-1 and first-2 active patterns (F11, F12) in a second direction (Y). The second-1 active pattern (F21) may be spaced apart from the second-2 active pattern (F22) in a first direction (X). The second-1 active pattern (F21) and the second-2 active pattern (F22) may be separated by a pin-cut trench (FCT). The sidewall of the 2-1 active pattern (F21) and the sidewall of the 2-2 active pattern (F22) may face each other in the first direction (X). The 2-1 and 2-2 active patterns (F21, F22) may be spaced apart from the 1-3 active pattern (F13) in the second direction (Y).

[0081] A first gate electrode (G1) may be formed on a first-1 active pattern (F11), a first-3 active pattern (F13), and a second-1 active pattern (F21). The first gate electrode (G1) may be disposed on an end including a sidewall of the first-1 active pattern (F11) and an end including a sidewall of the second-1 active pattern (F21). The first gate electrode (G1) may wrap around the end of the first-1 active pattern (F11) and the end of the second-1 active pattern (F21). A second gate electrode (G2) may be formed on a first-2 active pattern (F12), a first-3 active pattern (F13), and a second-2 active pattern (F22). The second gate electrode (G2) may be disposed at the end including the sidewall of the first-2 active pattern (F12) and the end including the sidewall of the second-2 active pattern (F22). The second gate electrode (G2) may wrap around the end of the first-2 active pattern (F12) and the end of the second-2 active pattern (F22). The third gate electrode (G3) may be formed on the first-2 active pattern (F12), the first-3 active pattern (F13), and the second-2 active pattern (F22).

[0082] At the point where the first-1 active pattern (F11) and the second-1 active pattern (F21) intersect with the first gate electrode (G1), a source / drain region is not disposed on one or both sides of the first gate electrode (G1). At the point where the first-1 active pattern (F11) and the second-1 active pattern (F21) intersect with the first gate electrode (G1), a portion of the first gate electrode (G1) may be formed on the first-1 active pattern (F11) and the second-1 active pattern (F21), and the remaining portion of the first gate electrode (G1) may be formed on the field insulating film (105). At the point where the first-2 active pattern (F12) and the second-2 active pattern (F22) intersect with the second gate electrode (G2), a source / drain region is not disposed on one or both sides of the second gate electrode (G2). At the point where the first-2 active pattern (F12) and the second-2 active pattern (F22) intersect with the second gate electrode (G2), a portion of the second gate electrode (G2) is formed on the first-2 active pattern (F12) and the second-2 active pattern (F22), and the remaining portion of the second gate electrode (G2) can be formed on the field insulating film (105).

[0083] The first and second power rails (312, 314) may overlap in the third direction (Z) with at least a portion of the active patterns (F11, F12, F13, F22) that are spaced apart from each other in the first direction (X), for example. For example, the first power rail (312) may overlap in the third direction (Z) with the first-1 and first-2 active patterns (F11, F12), and the second power rail (314) may overlap in the third direction (Z) with the second-1 and second-2 active patterns (F21, F22).

[0084] In some embodiments, the first and second landing pads (530, 630) may be placed in an area where the first and second active patterns (F11, F12, F13, F22) are cut. The first and second landing pads (530, 630) may be placed between the first and second active patterns (F11, F12, F21, F22) that are spaced apart from each other in a first direction (X). That is, the first and second landing pads (530, 630) may be placed between the first and second active patterns (F11, F12, F21, F22) that have their sidewalls facing each other. The first and second landing pads (530, 630) may be placed on the field insulating film (105).

[0085] For example, the first landing pad (530) may be positioned between the first-1 active pattern (F11) and the first-2 active pattern (F12). The first landing pad (530) may be positioned between the side wall of the first-1 active pattern (F11) and the side wall of the first-2 active pattern (F12). The second landing pad (630) may be positioned between the second-1 active pattern (F21) and the second-2 active pattern (F22). The second landing pad (630) may be positioned between the side wall of the second-1 active pattern (F21) and the side wall of the second-2 active pattern (F22).

[0086] In some embodiments, the gap between the first gate electrode (G1) and the second gate electrode (G2) may be larger than the gap between the second gate electrode (G2) and the third gate electrode (G3). The first gate electrode (G1) and the second gate electrode (G2) may be spaced apart so that one additional gate electrode can be placed between them. The first and second landing pads (530, 630) may be placed between the first gate electrode (G1) and the second gate electrode (G2).

[0087] For example, the gap between the first gate electrode (G1) and the first landing pad (530) or the second landing pad (630) may be the same as the gap between the second gate electrode (G2) and the first landing pad (530) or the second landing pad (630) and the gap between the second gate electrode (G2) and the third gate electrode (G3). That is, the first and second landing pads (530, 630) may be placed at a position corresponding to the gate electrode omitted between the first gate electrode (G1) and the second gate electrode (G2).

[0088] The first and second landing pads (530, 630) are positioned between the first gate electrode (G1) and the second gate electrode (G2), but the distance between the first and second landing pads (530, 630) and the first gate electrode (G1) does not have to be the same as the distance between the first and second landing pads (530, 630) and the second gate electrode (G2). Additionally, a gate electrode crossing the first-third active pattern (F13) may be further positioned between the first gate electrode (G1) and the second gate electrode (G2) and between the first landing pad (530) and the second landing pad (630). The first gate electrode (G1), the gate electrode crossing the first-third active pattern (F13), and the second gate electrode (G2) may be arranged along the first direction (X) at regular intervals.

[0089] FIG. 9 is a schematic layout diagram illustrating a semiconductor device according to some embodiments. FIG. 10 is a cross-sectional view taken along E-E' of FIG. 9. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 7 and FIG. 8.

[0090] Referring to FIGS. 9 and 10, in a semiconductor device according to some embodiments, gate electrodes (G1 to G3) may be arranged in a first direction (X) at regular intervals. A first gate electrode (G1) may be formed on a first-1 active pattern (F11), a first-3 active pattern (F13), and a second-1 active pattern (F21). A second gate electrode (G2) may be formed on a first-2 active pattern (F12), a first-3 active pattern (F13), and a second-2 active pattern (F22). A third gate electrode (G3) may be formed on a first-2 active pattern (F12), a first-3 active pattern (F13), and a second-2 active pattern (F22).

[0091] The first and second landing pads (530, 630) may be placed in an area where the first and second active patterns (F11, F12, F13, F22) are cut between adjacent gate electrodes (G1 to G3). Accordingly, the Power, Performance, Area (PPA) of a semiconductor device according to some embodiments may be improved or enhanced. For example, the first landing pad (530) may be placed between the first-1 active pattern (F11) and the first-2 active pattern (F12) between the first gate electrode (G1) and the second gate electrode (G2). The second landing pad (630) may be placed between the second-1 active pattern (F21) and the second-2 active pattern (F22) between the first gate electrode (G1) and the second gate electrode (G2).

[0092] For example, the width (W21) of the first landing pad (530) in the first direction (X) and the width (W22) of the second landing pad (630) in the first direction (X) may be smaller than the width (W23) of the gate electrodes (G1 to G3) in the first direction (X).

[0093] FIG. 11 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 12 is a cross-sectional view taken along F-F' of FIG. 11. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 to 4.

[0094] Referring to FIGS. 11 and 12, in a semiconductor device according to some embodiments, a first active region (AR1) may include a first active pattern (F11, F12, F13), and a second active region (AR2) may include a second active pattern (F21, F22).

[0095] The first-1 active pattern (F11) may be separated from the first-2 active pattern (F12) in a first direction (X). The first-1 active pattern (F11) and the first-2 active pattern (F12) may be separated by a device isolation structure (DB). The sidewall of the first active pattern (F11) and the sidewall of the first-2 active pattern (F12) may face each other in the first direction (X). The first-3 active pattern (F13) may be separated from the first-1 and first-2 active patterns (F11, F12) in a second direction (Y). The second-1 active pattern (F21) may be separated from the second-2 active pattern (F22) in a first direction (X). The second-1 active pattern (F21) and the second-2 active pattern (F22) may be separated by a device isolation structure (DB). The sidewall of the 2-1 active pattern (F21) and the sidewall of the 2-2 active pattern (F22) may face each other in the first direction (X). The 2-1 and 2-2 active patterns (F21, F22) may be spaced apart from the 1-3 active pattern (F13) in the second direction (Y).

[0096] The device isolation structure (DB) may be disposed between a first source / drain region (160) and a second source / drain region (260) adjacent in a first direction (X). The device isolation structure (DB) may extend in a second direction (Y). The device isolation structure (DB) may include, for example, at least one of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonide, silicon oxynitride and silicon oxycarbonitride, and aluminum oxide. The device isolation structure (DB) may be composed of a plurality of films.

[0097] A first gate electrode (G1) may be formed on a first-1 active pattern (F11), a first-3 active pattern (F13), and a second-1 active pattern (F21). A second gate electrode (G2) may be formed on a first-2 active pattern (F12), a first-3 active pattern (F13), and a second-2 active pattern (F22).

[0098] In some embodiments, the first and second landing pads (530, 630) may be placed in an area where the first and second active patterns (F11, F12, F13, F22) are cut. The first and second landing pads (530, 630) may be placed between the first and second active patterns (F11, F12, F21, F22) that are spaced apart from each other in a first direction (X). That is, the first and second landing pads (530, 630) may be placed between the first and second active patterns (F11, F12, F21, F22) that have one sidewalls facing each other. The first and second landing pads (530, 630) may be placed on a device isolation structure (DB).

[0099] In some embodiments, a first through-via (400) may be formed on a device isolation structure (DB). The first through-via (400) may penetrate the substrate (100) and the device isolation structure (DB). The first through-via (400) may connect the first power rail (312) and the first landing pad (530). A second through-via may be formed on a device isolation structure (DB). The second through-via may penetrate the substrate (100) and the device isolation structure (DB) to connect the second power rail (314) and the second landing pad (630).

[0100] In some embodiments, the first-1 active pattern (F11) and the first-2 active pattern (F12) included in the first active region (AR1) may be separated by a pin-cut trench (FCT) as in FIG. 7 or FIG. 9, and the second active region (AR2) may be separated by a device isolation structure (DB) as in FIG. 11. In this case, the first landing pad (530) may be placed on the field insulating film (105) as in FIG. 7 or FIG. 9, and the second landing pad (630) may be placed on the device isolation structure (DB).

[0101] FIG. 13 is a cross-sectional view taken along A-A' of FIG. 1. FIG. 14 is a cross-sectional view taken along C-C' of FIG. 1. For the convenience of explanation, the explanation will focus on the differences from the explanation using FIG. 1 to 4.

[0102] Referring to FIG. 13 and FIG. 14, in a semiconductor device according to some embodiments, each first and second active pattern (F1, F2) may include a pin-shaped pattern (112) protruding from a first surface (100a) of a substrate (100) and a plurality of wire patterns (114, 116, 118). The first and second active patterns (F1, F2) may extend in a first direction (X).

[0103] For example, a plurality of wire patterns (114, 116, 118) may be stacked sequentially on a first surface (100a) of a substrate (100) and may be spaced apart from each other in a third direction (Z). The first wire pattern (114) may be spaced apart from the pin-shaped pattern (112) in a third direction (Z), the second wire pattern (116) may be spaced apart from the first wire pattern (114) in a third direction (Z), and the third wire pattern (118) may be spaced apart from the second wire pattern (116) in a third direction (Z).

[0104] The first to third wire patterns (114, 116, 118) can penetrate the first to third gate electrodes (G1 to G3). The first to third gate electrodes (G1 to G3) can surround the outer surface of the first to third wire patterns (114, 116, 118).

[0105] In the drawings, the cross-sections of the first to third wire patterns (114, 116, 118) are each depicted as rectangular, but this is merely illustrative. For example, the cross-sections of the first to third wire patterns (114, 116, 118) may each be different polygons or circles. In some embodiments, unlike what is depicted, the width of the first to third wire patterns (114, 116, 118) may decrease as it moves away from the first surface (100a) of the substrate (100).

[0106] Although only FinFETs (Fin-type transistors) and transistors having a channel region of a wire pattern (nanowire or nanosheet) have been described as semiconductor devices according to some embodiments, these are merely exemplary. As other examples, semiconductor devices according to some embodiments may include tunneling FETs, VFETs (Vertical FETs), CFETs (Complementary FETs), or three-dimensional (3D) transistors. Alternatively, semiconductor devices according to some embodiments may include bipolar junction transistors, horizontal diffusion transistors (LDMOS), etc.

[0107] FIGS. 15 to 21 are intermediate drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIGS. 15 and 17 are cross-sectional views taken along A-A' of FIG. 1, and FIGS. 16 and FIGS. 18 to 21 are cross-sectional views taken along B-B' of FIG. 1.

[0108] Referring to FIGS. 15 and 16, a pin-cut trench (FCT) extending in a first direction (X) may be formed in the substrate (100). First and second active patterns (F1, F2) may be defined by the pin-cut trench (FCT). Accordingly, first and second active patterns (F1, F2) protruding from the first surface (100a) of the substrate (100) may be formed. The first and second active patterns (F1, F2) may be arranged in a second direction (Y).

[0109] A substrate trench (DT) defining a first active region (AR1) and a second active region (AR2) may be formed on the substrate (100). Accordingly, the active pattern within the area where the substrate trench (DT) is formed may be removed. The substrate trench (DT) may be formed to a depth greater than or equal to the depth of the pin-cut trench (FCT).

[0110] A field insulating film (105) may be formed on a first surface (100a) of a substrate (100). The field insulating film (105) may fill the substrate trench (DT) and the pin-cut trench (FCT). The field insulating film (105) may cover at least a portion of the first and second active patterns (F1, F2).

[0111] Referring to FIGS. 17 and 18, first to third gate electrodes (G1 to G3) and first and second landing pads (530, 630) may be formed on the first and second active patterns (F1, F2) and the field insulating film (105). A gate spacer (140) and first and second spacers (540, 640) may be formed, a gate dielectric film (120) and first and second dielectric films (520, 620) may be formed, a gate conductive film (130) and first and second landing pads (530, 630) may be formed, and a gate capping pattern (150) may be formed. The upper surface of the first and second landing pads (530, 630) may be placed on the same plane as the upper surface of the gate capping pattern (150). That is, the first and second landing pads (530, 630) can be formed by a process of forming the first to third gate electrodes (G1 to G3). The first and second landing pads (530, 630) can be formed by a process of patterning the gate electrodes (G1 to G3). The gate conductive film (130) and the first and second landing pads (530, 630) can be formed, for example, through a replacement process, but are not limited thereto.

[0112] First and second source / drain regions (160, 260) may be formed in the first and second active patterns (F1, F2). Each of the first and second source / drain regions (160, 260) may be formed within each of the first and second active patterns (F1, F2).

[0113] A first front interlayer insulating film (110) covering the field insulating film (105) and the first and second source / drain regions (160, 260) may be formed. The upper surface of the first front interlayer insulating film (110) may be placed on the same plane as the upper surface of the first to third gate electrodes (G1 to G3) and the upper surface of the first and second landing pads (530, 630).

[0114] Referring to FIG. 19, a second front interlayer insulating film (210) may be formed on a first front interlayer insulating film (110). A first source / drain contact (180) comprising a first portion (180a) and a second portion (180b) and a second source / drain contact (280) comprising a first portion (280a) and a second portion (280b) may be formed. The first portion (180a) of the first source / drain contact (180) may be connected to a first source / drain region (160), and the first portion (280a) of the second source / drain contact (280) may be connected to a second source / drain region (260). A second portion (180b) of the first source / drain contact (180) may be connected to the first landing pad (530), and a second portion (280b) of the second source / drain contact (280) may be connected to the second landing pad (630). A first silicide film (165) may be formed at the interface between the first source / drain region (160) and the first source / drain contact (180). A second silicide film (265) may be formed at the interface between the second source / drain region (260) and the second source / drain contact (280).

[0115] Referring to FIG. 20, third to sixth front interlayer insulating films (220, 230, 240, 250), first and second front vias (222, 242), and first and second front wiring (232, 252) may be formed on the second front interlayer insulating film (210).

[0116] Referring to FIG. 21, first and second through-vias (400, 500) may be formed from the second surface (100b) of the substrate (100) toward the first surface (100a). The first and second through-vias (400, 500) may penetrate the substrate (100) and the field insulating film (105). The first through-via (400) may penetrate at least a portion of the first landing pad (530), the first dielectric film (520), and the first spacer (540). Accordingly, the first through-via (400) may be connected to the first landing pad (530). The second through-via (500) may penetrate at least a portion of the second landing pad (630), the second dielectric film (620), and the second spacer (640). Accordingly, the second through via (500) can be connected to the second landing pad (630).

[0117] In the process of forming the first through-via (400), at least a portion of the first dielectric film (520) placed on the bottom surface of the first landing pad (530) may be removed. Also, at least a portion of the first spacer (540) may be removed. That is, unlike what is shown in the drawing, a portion of the first spacer (540) may be removed, or a portion of the first dielectric film (520) placed on the bottom surface of the first landing pad (530) may remain. In the process of forming the second through-via (500), at least a portion of the second dielectric film (620) placed on the bottom surface of the second landing pad (630) may be removed. Also, at least a portion of the second spacer (640) may be removed. That is, unlike what is shown in the drawing, a portion of the second spacer (640) may be removed, or a portion of the second dielectric film (620) placed on the bottom surface of the second landing pad (630) may remain.

[0118] Referring to FIG. 3, a first rear interlayer insulating film (310) and first and second power rails (312, 314) may be formed on the second surface (100b) of the substrate (100). Second to fifth rear interlayer insulating films (320, 330, 340, 350), first and second rear vias (322, 342), and first and second rear wiring (332, 352) may be formed on the first rear interlayer insulating film (310). Accordingly, the first and second power rails (312, 314) and a power supply network may be formed on the second surface (100b) of the substrate (100).

[0119] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0120] 100: Substrate 105: Field insulating film 110, 210, 220, 230, 240, 250: 1st to 6th front interlayer insulating films 120: Gate Dielectric Membrane 130: Gate Conductive Membrane 140: Gate spacer 150: Gate capping pattern 160, 260: 1st and 2nd source / drain regions 165: 265: 1st and 2nd silicide membranes 180, 280: 1st and 2nd source / drain contacts 222, 242: 1st and 2nd front vias 232, 252: 1st and 2nd front wiring 310, 320, 330, 340, 350: 1st to 5th rear interlayer insulating films 312, 314: 1st and 2nd Power Rails 322, 342: 1st and 2nd rear vias 332, 352: 1st and 2nd rear patterns 400, 500: 1st and 2nd penetrating vias 530, 630: 1st and 2nd landing pads

Claims

Claim 1 A semiconductor device comprising: a substrate including a first surface and a second surface opposite to the first surface; an active pattern extending in a first direction on the first surface of the substrate; a first source / drain contact including a first portion connected to a source / drain region of the active pattern and a second portion extending from the first portion in the first direction or in a second direction intersecting the first direction; a power rail providing voltage on the second surface of the substrate; a through electrode connected to the power rail and penetrating the substrate; and a landing pad connecting the through electrode and the second portion of the source / drain contact, wherein the second portion of the source / drain contact overlaps with the landing pad in a third direction perpendicular to the first surface of the substrate, and in the third direction, the lowest surface of the second portion of the source / drain contact is lower than the lowest surface of the first portion of the source / drain contact. Claim 2 A semiconductor device according to claim 1, further comprising a gate electrode extending in the second direction on the active pattern, wherein the landing pad comprises the same material as the gate electrode. Claim 3 A semiconductor device according to claim 1, further comprising a gate electrode extending in the second direction on the active pattern and a gate capping pattern disposed on the gate electrode, wherein the upper surface of the landing pad is disposed on the same plane as the upper surface of the gate capping pattern. Claim 4 A semiconductor device according to claim 1, further comprising a dielectric film covering the side wall of the landing pad. Claim 5 A semiconductor device according to claim 1, further comprising a spacer disposed on the side wall of the landing pad. Claim 6 A semiconductor device according to claim 1, further comprising a field insulating film on the first surface of the substrate that surrounds at least a portion of the sidewall of the active pattern, wherein the penetrating electrode penetrates the substrate and the field insulating film, and the landing pad is disposed on the field insulating film. Claim 7 A semiconductor device according to claim 6, wherein the upper surface of the through electrode is positioned above the uppermost surface of the field insulating film. Claim 8 A semiconductor device according to claim 1, wherein the substrate further comprises an active region defined by a substrate trench, the active pattern is disposed on the active region, and the landing pad overlaps in the third direction with a field insulating film filling the substrate trench. Claim 9 In claim 1, the active pattern comprises a first active pattern and a second active pattern spaced apart from each other in the first direction, the first active pattern and the second active pattern are separated by a pin-cut trench, and the landing pad is a semiconductor device that overlaps in the third direction with a field insulating film filling the pin-cut trench. Claim 10 A substrate comprising a first surface and a second surface opposite to the first surface; an active pattern extending in a first direction on the first surface of the substrate; a field insulating film covering at least a portion of the sidewall of the active pattern; a gate electrode extending in a second direction intersecting the first direction on the active pattern; a source / drain contact comprising a first portion connected to a source / drain region of the active pattern and a second portion extending from the first portion in a first direction or a second direction; a silicide film between the source / drain region and the source / drain contact; a power rail providing voltage on the second surface of the substrate; a back wiring connected to the power rail on the second surface of the substrate; a through electrode connected to the power rail and penetrating the substrate and the field insulating film; a landing pad on the field insulating film in contact with the through electrode and the second portion of the source / drain contact, and comprising the same material as the gate electrode. A semiconductor device comprising a front wiring connected to the source / drain contact on the first surface of the substrate, wherein, in a third direction perpendicular to the first surface of the substrate, the upper surface of the through electrode is above the uppermost surface of the field insulating film.

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