Memory device with tunable threshold voltage and fabrication method thereof

Abstract

A memory device capable of controlling a threshold voltage and a method for manufacturing the same are disclosed. According to one embodiment, the memory device comprises a substrate, an inert electrode formed on the substrate, a ferroelectric layer formed on the inert electrode, an active layer formed on the ferroelectric layer, and an active electrode formed on the active layer.

Description

Technology Field

[0001] The present invention relates to a memory device, and more particularly to a memory device in which a two-dimensional ferroelectric layer is inserted in an ion-conducting filament-based memory device to control filament characteristics by controlling the oxidation / reduction reaction of ions according to the direction of the internal electric field, thereby allowing the switching threshold voltage and resistance state to be selectively used. Background Technology

[0002] Next-generation semiconductor memory devices are rapidly transitioning from a two-dimensional planar structure to a three-dimensional stacked structure to achieve both high integration and low power consumption simultaneously. Consequently, reducing cell area and ensuring uniformity of switching characteristics for individual memory devices are emerging as important challenges.

[0003] In particular, conductive filament-based memory (CBRAM, ECM / VCM RRAM) devices are suitable for 3D stacking implementation due to advantages such as a simple MIM (Metal Insulator Metal) structure, low power consumption, and high speed; however, due to the non-uniformity of filament length and thickness and the randomness of formation locations, the critical voltage (V SET , V RESET There is a problem where the width of the distribution of fluctuations and resistance states increases.

[0004] This variability issue makes it difficult to accurately set target resistance values ​​when implementing Multi-Level Cells (MLCs), requiring the repetitive Program & Verify process, which results in reduced speed and increased energy consumption.

[0005] Previously, research was conducted to control filament formation pathways through active electrode alloying, electrolyte doping, and nanostructure insertion, but there were still limitations in the complete reproducibility of filament nucleation sites and the control of critical voltage.

[0006] The present invention proposes a technology that inserts a two-dimensional ferroelectric material into the interface between an intermediate layer (active layer) and an inert electrode, thereby actively controlling the internal electric field of a memory device according to the polarization direction within the two-dimensional ferroelectric material to control the position and speed of formation and extinction of conductive filaments, and thereby precisely control the critical voltage and resistance state. Prior art literature

[0007] Republic of Korea Published Patent No. 2025-0101287 (Published July 4, 2025) Republic of Korea Registered Patent No. 2359393 (Announced February 8, 2022) Republic of Korea Registered Patent No. 1531154 (Announced June 25, 2015) Republic of Korea Published Patent No. 2014-0046613 (Published April 21, 2014) The problem to be solved

[0008] The technical problem that the present invention aims to solve is to provide a memory device capable of controlling threshold voltage and a method for manufacturing the same. means of solving the problem

[0009] A memory device according to one embodiment of the present invention comprises a substrate, an inert electrode formed on the substrate, a ferroelectric layer formed on the inert electrode, an active layer formed on the ferroelectric layer, and an active electrode formed on the active layer.

[0010] A memory device according to another embodiment of the present invention comprises a substrate, a ferroelectric layer formed on the substrate, an active layer formed in a portion of the ferroelectric layer, an inert electrode formed in a portion of the substrate where the active layer is not formed, and an active electrode formed on the active layer. Effects of the invention

[0011] 1) Active control of filament formation and extinction

[0012] Depending on the polarization direction of the ferroelectric layer, the electric field within the active layer and the positive charge of the ferroelectric material reinforce or cancel each other out, allowing for the active control of filament formation and extinction rates. Consequently, the (switching) threshold voltage can be adjusted, improving the accuracy of the target resistance value during MLC implementation.

[0013] 2) Power drive

[0014] When the polarization direction of the ferroelectric material aligns with the filament formation direction, the drift velocity of polar ions forming filaments within the active layer increases, enabling memory switching to a low-resistance state at a lower voltage. When the polarization direction of the ferroelectric material is opposite to the filament formation direction, an oxidation reaction is induced at the interface between the filament and the ferroelectric material, accelerating filament breakdown, and the internal electric field enables memory switching to a high-resistance state at a higher voltage.

[0015] 3. Improvement of Retention and Reliability

[0016] When the polarization direction coincides with the filament growth direction, the memory retention characteristics in a low-resistance state are improved due to the induction of reduction reactions of conductive filaments within the active layer and the stabilization of the conductive path. In addition, due to the inertness and layered structure of the two-dimensional ferroelectric material, excessive filament formation can be prevented, thereby enabling stable repetitive operation characteristics. Brief explanation of the drawing

[0017] Detailed descriptions of each drawing are provided to help to more fully understand the drawings cited in the detailed description of the present invention. FIG. 1 is a schematic diagram of a conductive filament-based memory device according to one embodiment of the present invention. Figure 2 illustrates the structure of a conductive filament-based memory device shown in Figure 1 (left: vertical MIFeM, right: planar MIFeM). Figure 3 is a diagram illustrating the change in switching threshold voltage of a memory device according to the polarization state of the ferroelectric layer. Figure 4 illustrates the results of a comparison of CBRAM operating characteristics according to the polarization state (up / down) of the two-dimensional ferroelectric layer. Specific details for implementing the invention

[0018] Specific structural or functional descriptions of embodiments according to the concept of the present invention disclosed herein are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and are not limited to the embodiments described herein.

[0019] Since embodiments according to the concept of the present invention may be subject to various modifications and may take various forms, embodiments are illustrated in the drawings and described in detail in this specification. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosed forms, and includes all modifications, equivalents, or substitutions that fall within the spirit and scope of the present invention.

[0020] Terms such as "first" or "second" may be used to describe various components, but said components should not be limited by said terms. For the sole purpose of distinguishing one component from another, for example, without departing from the scope of rights according to the concept of the present invention, the first component may be named the second component and similarly the second component may be named the first component.

[0021] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. Conversely, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between. Other expressions describing the relationships between components, such as "between" and "exactly between," or "adjacent to" and "directly adjacent to," should be interpreted in the same way.

[0022] The terms used herein are used merely to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “comprising” or “having” are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described herein, and should not be understood as precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0023] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification.

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings attached to this specification. However, the scope of the patent application is not limited or restricted by these embodiments. Identical reference numerals in each drawing indicate identical components.

[0025] Next-generation semiconductor memory devices are rapidly transitioning from a two-dimensional planar structure to a three-dimensional stacked structure to achieve both high integration and low power consumption simultaneously. Consequently, reducing cell area and ensuring uniformity of switching characteristics for individual memory devices are emerging as important challenges.

[0026] In particular, conductive filament-based memory (CBRAM, ECM / VCM RRAM) devices are suitable for 3D stacking implementation due to advantages such as a simple MIM (Metal Insulator Metal) structure, low power consumption, and high speed; however, due to the non-uniformity of filament length and thickness and the randomness of formation locations, the critical voltage (V SET , V RESET There is a problem where the width of the distribution of fluctuations and resistance states increases.

[0027] This variability issue makes it difficult to accurately set target resistance values ​​when implementing MLC (Multi-Level Cell), requiring the repetitive Program & Verify process, which results in reduced speed and increased energy consumption.

[0028] Previously, research was conducted to control filament formation pathways through active electrode alloying, electrolyte doping, and nanostructure insertion, but there were still limitations in the complete reproducibility of filament nucleation sites and the control of critical voltage.

[0029] The present invention proposes a technology that inserts a two-dimensional ferroelectric material into the interface between an intermediate layer and an inert electrode, thereby actively controlling the internal electric field of a memory device according to the polarization direction within the two-dimensional ferroelectric material to control the position and speed of formation and extinction of conductive filaments, and thereby precisely control the critical voltage and resistance state.

[0030] FIG. 1 is a schematic diagram of a conductive filament-based memory device according to one embodiment of the present invention, and FIG. 2 shows the structure of the conductive filament-based memory device shown in FIG. 1 (left; vertical MIFeM, right; planar MIFeM).

[0031] A conductive filament-based memory device according to one embodiment of the present invention has 1) a structure in which a two-dimensional ferroelectric layer is inserted into a vertical structure of a Metal Insulator Metal (MIM) (first structure) or 2) a structure in which an inert electrode is formed in an extra region of the two-dimensional ferroelectric layer (second structure). Exemplary memory devices may be CBRAM (Conductive-Bridge RAM), ECM RRAM (Electrochemical Metallization RRAM), VCM RRAM (Valence Change Mechanism RRAM), etc.

[0032] The ferroelectric layer can be an insulating / semiconductor material having switchable residual polarization characteristics as a two-dimensional ferroelectric material, and may be composed of any one of In2Se3, CuInP2S6, GeS, GeSe, SnS, SnSe, SnTe, MoTe2, Bi2O2Te, Bi2O2Se, and Al2Se3, or a combination (or alloy) of at least two of these.

[0033] In the first structure of the memory device (vertical MIFeM structure), the ferroelectric layer can be inserted between the active layer and the inert electrode. In the second structure of the memory device (planar MIFeM structure), the ferroelectric layer can serve as an inert electrode. At this time, the active layer may be formed in a portion of the ferroelectric layer, and the inert electrode may be formed in a portion of the ferroelectric layer where the active layer is not formed. According to the embodiment, the active layer and the inert electrode formed on the ferroelectric layer may be formed spaced apart from each other. Of course, the inert electrode of the first structure and the ferroelectric layer of the second structure may be formed on a substrate.

[0034] The ferroelectric layer can be transferred (or formed) onto an inert electrode (in the case of the first structure) or on top of a substrate (in the case of the second structure) using processes such as chemical vapor deposition (CVD), mechanical exfoliation, and / or wet / dry transfer.

[0035] To control the threshold voltage of the memory device, a polarization alignment process is involved through separate electrical poling (E-field poling) of the ferroelectric layer, which can utilize active and inert electrodes or separately formed electrodes. That is, according to the embodiment, a separate pair of electrodes to induce polarization of the ferroelectric layer can be connected to the ferroelectric layer.

[0036] The formation and / or removal of conductive filaments can be achieved using an electrochemical metallization (ECM) method based on active metal cations such as Ag, Cu, Ni, Te, Ti, and Co, or a valence change mechanism (VCM) method based on oxygen vacancies. That is, the active electrode may be any one of Ag, Cu, Ni, Te, Ti, and Co, which are capable of forming metal cation conductive filaments, or may include at least two of these. Examples of the active layer may be an insulator that is any one of MgO, SiO2, HfO2, Al2O3, Ta2O5, ZrO2, GST, TiO2, and Si3N4, or includes at least two of these.

[0037] The inert electrode may be a metal composed of any one of Pt, Au, W, TiN, Mo, Ta, and TaN, or a combination of at least two of these.

[0038] Figure 3 is a diagram illustrating the change in switching threshold voltage of a memory device according to the polarization state of the ferroelectric layer.

[0039] Based on a cation-based conductive filament, during electrical poling of the ferroelectric layer, upwardly aligned polarization forms an internal electric field that enhances filament formation, while downwardly aligned polarization forms an internal electric field that inhibits it, thereby providing a reinforcing or canceling effect on the electric field for conductive filament formation. In this case, the reinforcing and canceling effects on the internal electric field can be determined by the polarity of the ions constituting the conductive filament.

[0040] After the polarization direction is aligned, the internal electric field due to the ferroelectric layer is almost never lost unless a voltage greater than the coercive electric field is applied, and subsequently, the threshold voltage in the switching operation of the memory device is actively controlled according to the polarization state.

[0041] Figure 4 illustrates the results of a comparison of CBRAM operating characteristics according to the polarization state (up / down) of the two-dimensional ferroelectric layer.

[0042] Figure 4 shows the switching operation of a second structure (vertical MIFeM) memory device based on an In2Se3 ferroelectric layer, an MgO active layer, an Ag active electrode, and a Pt inert electrode, and it can be observed that the change in threshold voltage is clearly visible depending on the polarization state (up / down) of the ferroelectric layer. In this case, up (down) indicates the alignment (opposite) of the filament formation direction and the electric field direction due to polarization.

[0043] The critical voltage for each polarization state was verified through iterative operation, and the degree of change in critical voltage can be controlled by the thickness of the active layer and ferroelectric layer, the type of ions forming the conductive filament, the maximum allowable current level, etc.

[0044] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

Claim 1 A memory device comprising: a substrate; an inert electrode formed on the substrate; a ferroelectric layer formed on the inert electrode; an active layer formed on the ferroelectric layer; and an active electrode formed on the active layer, wherein, during operation of the memory device, filament formation in the active layer is enhanced or suppressed according to the polarization direction of the ferroelectric layer. Claim 2 A memory device according to claim 1, wherein the inert electrode and the active electrode comprise at least one of Pt, Au, W, TiN, Mo, Ta, and TaN. Claim 3 A memory device according to claim 1, wherein the ferroelectric layer comprises at least one of In2Se3, CuInP2S6, GeS, GeSe, SnS, SnSe, SnTe, MoTe2, Bi2O2Te, Bi2O2Se, and Al2Se3. Claim 4 A memory device according to claim 1, wherein the active layer comprises at least one of MgO, SiO2, HfO2, Al2O3, Ta2O5, ZrO2, GST, TiO2, and Si3N4. Claim 5 A memory device according to claim 1, wherein the active electrode comprises Ag, the active layer comprises MgO, the ferroelectric layer comprises In2Se3, the inert electrode comprises Pt, and the memory device is a CBRAM (Conductive-Bridge RAM). Claim 6 delete Claim 7 A memory device according to claim 1, wherein, during operation of the memory device, filament formation in the active layer is enhanced due to polarization of the ferroelectric layer, thereby lowering the switching threshold voltage of the memory device. Claim 8 A memory device according to claim 1, wherein, during operation of the memory device, filament formation in the active layer is suppressed due to polarization of the ferroelectric layer, thereby increasing the switching threshold voltage of the memory device. Claim 9 A memory device comprising: a substrate; a ferroelectric layer formed on the substrate; an active layer formed in a portion of the ferroelectric layer; an inert electrode formed in a portion of the substrate where the active layer is not formed; and an active electrode formed on the active layer, wherein, during operation of the memory device, filament formation in the active layer is enhanced or suppressed according to the polarization direction of the ferroelectric layer.

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