Two-dimensional semiconductor device forming multiple edge contacts and manufacturing method thereof

Abstract

The present invention relates to a semiconductor device comprising: a substrate; a two-dimensional semiconductor material layer including a pattern having a predetermined shape formed on the substrate; and a source electrode and a drain electrode disposed on the two-dimensional semiconductor material layer at a predetermined interval, wherein the source electrode and the drain electrode are each formed in a shape corresponding to the pattern to form a plurality of edge contacts.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device that reduces contact resistance by forming a plurality of edge contacts using a two-dimensional semiconductor material, and a method for manufacturing the same. Background Technology

[0002] In semiconductor device fabrication, contact resistance between the semiconductor material and the metal electrode is one of the critical factors determining device performance. In particular, while contact resistance in silicon (Si) can be reduced relatively easily through doping and interface processes, two-dimensional semiconductor materials face fundamental structural difficulties in improving contact resistance due to the characteristics of their atomic layer structure, such as doping limitations, Fermi level pinning, and weakened interfacial bonding.

[0003] However, while silicon materials experience a significant decline in mobility and difficulty in channel control as their thickness decreases, two-dimensional semiconductor materials have the advantage of maintaining high mobility and excellent channel control characteristics even at very thin atomic layer thicknesses. Therefore, as the thickness scaling of semiconductor devices continues to advance, the importance of channel materials that possess excellent semiconductor properties even at thin thicknesses is increasing, and research on two-dimensional materials is actively underway as next-generation semiconductor materials to replace silicon.

[0004] In multilayer devices of two-dimensional semiconductor materials, when top contact between the semiconductor material and the metal electrode is used, the interface between each layer acts as a tunneling barrier, which degrades device performance. To solve this, edge contact has been proposed. In the case of edge contact, all layers come into direct contact with the metal electrode and contact through the cross-section, allowing carriers to be injected directly into the channel, thereby improving contact resistance.

[0005] However, existing edge contact methods have limitations, such as being single contact structures where contact is formed on only one side, splitting effects and tapering effects occurring during the formation process, and potentially degrading device characteristics due to unstable contact.

[0006] Furthermore, existing research on edge contact formation has primarily focused on flake-shaped materials. However, these flake-shaped semiconductor materials are very small, and top-down methods such as mechanical exfoliation present a problem in that it is difficult to precisely control their thickness to the desired level. While thin-film semiconductor materials produced via Chemical Vapor Deposition (CVD) offer the advantage of enabling large-area synthesis, synthesizing thin films with high performance and uniformity while accurately controlling the desired thickness during the formation of multilayer structures remains a technical challenge.

[0007] Therefore, there is a need for a new approach that can effectively solve the contact resistance problem while utilizing the excellent properties of two-dimensional semiconductor materials.

[0008] Korean Published Patent No. 10-2022-0107576, which is the technical background of the present invention, relates to a semiconductor device comprising a two-dimensional material. The problem to be solved

[0009] The present invention aims to solve the problems of the aforementioned prior art by providing a two-dimensional semiconductor device having improved electrical characteristics and effectively reducing contact resistance by forming multiple edge contacts.

[0010] In addition, a method for manufacturing a two-dimensional semiconductor device having multiple edge contacts is provided by repeatedly transferring a single-layer two-dimensional semiconductor material to form a uniform multilayer structure and patterning it.

[0011] In addition, a transistor having excellent performance including the above-mentioned two-dimensional semiconductor device is provided.

[0012] In addition, a memory device having enhanced characteristics including the above-mentioned two-dimensional semiconductor device is provided.

[0013] In addition, a sensor having high sensitivity characteristics including the above-mentioned two-dimensional semiconductor device is provided.

[0014] In addition, an efficient optoelectronic device including the above-mentioned two-dimensional semiconductor device is provided.

[0015] In addition, a high-performance integrated circuit including the above-mentioned two-dimensional semiconductor device is provided.

[0016] However, the technical problems that the embodiments of the present invention aim to solve are not limited to the technical problems described above, and other technical problems may exist. means of solving the problem

[0017] As a technical means for achieving the above-mentioned technical problem, the first aspect of the present invention provides a semiconductor device comprising: a substrate; a two-dimensional semiconductor material layer including a pattern having a predetermined shape formed on the substrate; and a source electrode and a drain electrode disposed on the two-dimensional semiconductor material layer at a predetermined interval, wherein the source electrode and the drain electrode are each formed in a shape corresponding to the pattern to form a plurality of edge contacts.

[0018] According to one embodiment of the present invention, the source electrode and the drain electrode may each be formed to surround a portion of the upper surface and the entire side surface of the two-dimensional semiconductor material layer, but are not limited thereto.

[0019] According to one embodiment of the present invention, the pattern may include a first region and a second region having different thicknesses, and the source electrode and the drain electrode may be formed to individually wrap the upper surface and the side surface of the first region and the second region, respectively, to increase the contact area with the two-dimensional semiconductor material layer, but are not limited thereto.

[0020] According to one embodiment of the present invention, the predetermined shape may include, but is not limited to, a shape selected from the group consisting of a line, a hole, a zigzag, a matrix, a honeycomb, and combinations thereof.

[0021] According to one embodiment of the present invention, the two-dimensional semiconductor material may include, but is not limited to, a material selected from the group consisting of MoS2, WS2, MoSe2, WSe2, MoTe2, WTe2, TiS2, TiSe2, TiTe2, HfS2, HfSe2, HfTe2, ZrS2, ZrSe2, ZrTe2, TcS2, TcSe2, TcTe2, ReS2, ReSe2, ReTe2, PdS2, PdSe2, PtS2, PtSe2, black phosphorus, and combinations thereof.

[0022] According to one embodiment of the present invention, the source electrode and the drain electrode may each simultaneously contact the two-dimensional semiconductor material layer and the substrate, but are not limited thereto.

[0023] According to one embodiment of the present invention, the two-dimensional semiconductor material layer may include an electrode contact region formed at both ends and in contact with the source electrode and the drain electrode, respectively; and a channel region formed between the electrode contact regions and not in contact with the source electrode and the drain electrode, but is not limited thereto.

[0024] According to one embodiment of the present invention, the contact resistance may be reduced by the plurality of edge contacts, but is not limited thereto.

[0025] In addition, a second aspect of the present invention provides a method for manufacturing a semiconductor device comprising the steps of: repeatedly transferring a single-layer two-dimensional semiconductor material formed on a transfer substrate to form a multilayer two-dimensional semiconductor material; patterning the multilayer two-dimensional semiconductor material to form a two-dimensional semiconductor material layer including a pattern having a predetermined shape; and forming a source electrode and a drain electrode on the two-dimensional semiconductor material layer at a predetermined interval, wherein the source electrode and the drain electrode are each formed in a shape corresponding to the pattern to form a plurality of edge contacts.

[0026] According to one embodiment of the present invention, the source electrode and the drain electrode may each be formed to surround a portion of the upper surface and the entire side surface of the two-dimensional semiconductor material layer, but are not limited thereto.

[0027] According to one embodiment of the present invention, the pattern may include a first region and a second region having different thicknesses, and the source electrode and the drain electrode may be formed to individually wrap the upper surface and the side surface of the first region and the second region, respectively, to increase the contact area with the two-dimensional semiconductor material layer, but are not limited thereto.

[0028] According to one embodiment of the present invention, the step of forming the multilayer two-dimensional semiconductor material may include, but is not limited to, the step of forming a stacked structure by sequentially forming a polymer layer and a thermal release tape on a single-layer two-dimensional semiconductor material formed on a transfer substrate; the step of fixing the stacked structure using a vacuum chuck and then separating the transfer substrate; the step of contacting a single-layer two-dimensional semiconductor material located at the bottom of the stacked structure with a single-layer two-dimensional semiconductor material formed on another transfer substrate and then separating the substrate to stack an additional single-layer two-dimensional semiconductor material on the bottom of the stacked structure; the step of repeating the stacking step to form a plurality of single-layer two-dimensional semiconductor materials stacked on the bottom of the stacked structure; and the step of contacting the bottom of the stacked structure with a target substrate and then removing the thermal release tape and the polymer layer.

[0029] According to one embodiment of the present invention, the step of separating the transfer substrate may be performed by immersing the entire structure including the transfer substrate, a single-layer two-dimensional semiconductor material, a polymer layer, a thermal release tape, and a vacuum chuck in distilled water, but is not limited thereto.

[0030] According to one embodiment of the present invention, the step of forming the two-dimensional semiconductor material layer may utilize either a partial etching method in which only a portion of the upper layer of the multilayer two-dimensional semiconductor material is selectively etched and patterned while a portion of the lower layer is retained; or a total etching and transfer method in which the entire layer of the multilayer two-dimensional semiconductor material is etched and patterned, and then transferred onto a separate two-dimensional semiconductor material, but is not limited thereto.

[0031] According to one embodiment of the present invention, the etching may be performed by a method selected from the group consisting of sputtering, reactive ion beam, atomic layer etching, laser irradiation, electron beam irradiation, thermal etching, wet etching, and combinations thereof, but is not limited thereto.

[0032] In addition, a third aspect of the present invention provides a transistor comprising a semiconductor device according to a first aspect of the present invention.

[0033] In addition, the fourth aspect of the present invention provides a memory device comprising a semiconductor device according to the first aspect of the present invention.

[0034] In addition, the fifth aspect of the present invention provides a sensor comprising a semiconductor device according to the first aspect of the present invention.

[0035] In addition, the sixth aspect of the present invention provides an optoelectronic device comprising a semiconductor device according to the first aspect of the present invention.

[0036] Additionally, the seventh aspect of the present invention provides an integrated circuit comprising a semiconductor device according to the first aspect of the present invention.

[0037] The means for solving the problem described above are merely exemplary and should not be interpreted as intended to limit the present invention. In addition to the exemplary embodiments described above, additional embodiments may exist in the drawings and the detailed description of the invention. Effects of the invention

[0038] A two-dimensional semiconductor device forming multiple edge contacts according to the present invention provides significantly reduced contact resistance compared to the conventional top contact method through a multiple edge contact structure. Specifically, the contact resistance can be effectively improved by greatly increasing the contact area through an electrode structure that simultaneously wraps the top surface and the side surface of a patterned two-dimensional semiconductor material layer.

[0039] In addition, the method for manufacturing a two-dimensional semiconductor device according to the present invention can form a large-area CVD multilayer structure with uniform thickness and precise thickness control through a repetitive transfer process using a vacuum chuck. Specifically, it can stably form a layered structure with excellent crystallinity by resolving the problems of thin film damage and interlayer residue generation, which are issues of conventional transfer methods. On the other hand, conventional mechanical peeling methods or general transfer methods had limitations in controlling the desired thickness and ensuring high uniformity.

[0040] Furthermore, the method according to the present invention can freely realize various pattern shapes and thickness structures by selectively utilizing partial etching, total etching, and transfer methods. This implies that precise structural control is possible while maintaining high process flexibility, as it is compatible with various etching techniques such as sputtering, reactive ion beam etching, and atomic layer etching.

[0041] The two-dimensional semiconductor device according to the present invention includes a first region and a second region having different thicknesses, thereby effectively utilizing the unique characteristics of each region. Specifically, the thin region has excellent light absorption and charge separation efficiency, which is advantageous for high-sensitivity photodetection, while the thick region provides mechanical stability, efficient current flow, and heat dissipation characteristics.

[0042] The semiconductor device according to the present invention can be applied to various two-dimensional semiconductor materials such as MoS2, WS2, MoSe2, WSe2, MoTe2, WTe2, TiS2, TiSe2, TiTe2, HfS2, HfSe2, HfTe2, ZrS2, ZrSe2, ZrTe2, TcS2, TcSe2, TcTe2, ReS2, ReSe2, ReTe2, PdS2, PdSe2, PtS2, PtSe2, and black phosphorus, and can significantly contribute to the development of next-generation nanoscale electronic devices that require high mobility and excellent channel control characteristics even at the atomic layer level of thin thickness. Through this, research on performance improvement and miniaturization of various electronic devices such as transistors, memory devices, sensors, optoelectronic devices, and integrated circuits can be promoted.

[0043] However, the effects obtainable from this invention are not limited to those described above, and other effects may exist. Brief explanation of the drawing

[0044] Figure 1a is a conceptual diagram showing a structure for forming multiple edge contacts. Figure 1b is a conceptual diagram showing the structure of a semiconductor device in which multiple edge contacts are formed. FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 3 is a process diagram showing the steps of forming a multilayer two-dimensional semiconductor material by repeatedly transferring a single-layer two-dimensional semiconductor material. Figure 4 is a process diagram showing the steps of forming a two-dimensional semiconductor material layer through a partial etching method. Figure 5 is a process diagram showing the steps of forming a two-dimensional semiconductor material layer through a total etching and transfer method. Figure 6a is a photograph showing TEM images of a multilayer structure manufactured according to the method of the present invention (top) and a multilayer structure manufactured through a conventional transfer method (bottom). Figure 6b is a graph showing the change in the Raman spectrum as the number of layers increases. Figure 6c is a graph showing the change in device characteristics according to the increase in the number of layers. Figure 7a is a graph showing the characteristics of a device having a structure in which only the channel region has different thicknesses. Figure 7b is a graph showing the characteristics of a device having a structure in which both the channel region and the electrode contact region have different thicknesses. Figure 8a is a graph showing the characteristics of a device having the same number of layers. FIG. 8b is a graph showing the characteristics of devices (10 μm) having different numbers of layers. FIG. 8c is a graph showing the characteristics of a device (1 μm) having different numbers of layers. Specific details for implementing the invention

[0045] Embodiments of the present invention are described below with reference to the attached drawings to enable those skilled in the art to easily implement the invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0046] Throughout this specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected," but also cases where they are "electrically connected" with other elements interposed between them.

[0047] Throughout the entire specification, when a component is described as being located "on," "on top," "on top," "under," "on bottom," or "on bottom" of another component, this includes not only cases where the component is in contact with the other component but also cases where another component exists between the two components.

[0048] Throughout this specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0049] As used herein, terms of degree such as “about,” “substantially,” etc., are used to mean at or near the stated value when inherent manufacturing and material tolerances are presented in the stated meaning, and are used to prevent unscrupulous infringers from unfairly exploiting the disclosure in which precise or absolute values ​​are mentioned to aid in understanding the invention. Furthermore, throughout this specification, “a step of” or “a step of” does not mean “a step for”.

[0050] Throughout this specification, the term “combination thereof” included in the Markush-type expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-type expression, and means including one or more selected from the group consisting of said components.

[0051] Throughout the entire specification, the description "A and / or B" means "A, B, or A and B".

[0052] Hereinafter, the semiconductor device and the method for manufacturing the same according to the present invention will be described in detail with reference to the embodiments, examples, and drawings. However, the present invention is not limited to these embodiments, examples, and drawings.

[0054] As a technical means for achieving the above-mentioned technical problem, the first aspect of the present invention provides a semiconductor device comprising: a substrate (100); a two-dimensional semiconductor material layer (200) formed on the substrate (100) and having a pattern having a predetermined shape; and a source electrode and a drain electrode (300) disposed on the two-dimensional semiconductor material layer (200) at a predetermined interval, wherein the source electrode and the drain electrode (300) are each formed in a shape corresponding to the pattern to form a plurality of edge contacts.

[0055] The semiconductor device according to the present invention is configured to effectively solve the existing contact resistance problem while utilizing the excellent properties of a two-dimensional semiconductor material. The substrate (100) is the final substrate on which the semiconductor device is formed and can be formed from various materials such as silicon, quartz, sapphire, and a flexible substrate. The two-dimensional semiconductor material layer (200) is composed of a semiconductor material with a layered structure that exhibits excellent electrical properties while having a thin thickness at the atomic layer level, and includes a specially designed pattern to allow multiple edge contacts to be formed. The source electrode and drain electrode (300) are formed in a shape corresponding to the pattern for efficient charge exchange with the two-dimensional semiconductor material layer (200), thereby providing a three-dimensional contact structure that goes beyond the existing planar contact method.

[0056] According to one embodiment of the present invention, the pattern includes a first region (210) and a second region (220) having different thicknesses, and the source electrode and drain electrode (300) may be formed to individually wrap the upper surface and side surface of the first region (210) and the second region (220), respectively, to increase the contact area with the two-dimensional semiconductor material layer (200), but are not limited thereto.

[0057] Figure 1a is a conceptual diagram showing a structure for forming multiple edge contacts.

[0058] The first region (210) and the second region (220) can each perform unique functions by having different thicknesses. The first region (210) has a relatively thin thickness, which provides excellent light absorption and charge separation efficiency, and acts as a photoactive layer near the electrode contact area, which is advantageous for high-sensitivity photodetection. The second region (220) has a relatively thick thickness, which is advantageous for ensuring mechanical stability, allows current to flow efficiently, and can effectively dissipate heat generated at the contact area. Additionally, edge contact can be formed on the side portion of the thick region.

[0059] According to one embodiment of the present invention, the source electrode and the drain electrode (300) may each be formed to cover a portion of the upper surface and the entire side surface of the two-dimensional semiconductor material layer (200), but are not limited thereto.

[0060] Figure 1b is a conceptual diagram showing the structure of a semiconductor device in which multiple edge contacts are formed.

[0061] In this structure, the source electrode and drain electrode (300) do not simply contact the upper surface of the two-dimensional semiconductor material layer (200), but form a three-dimensional contact structure that wraps around the sides as well. This solves the problem of interlayer tunneling barriers that occurs in conventional top contact methods and provides a path through which carriers can be directly injected into the channel. In particular, through a structure that wraps around the entire side, each atomic layer can individually contact the metal electrode, thereby significantly reducing contact resistance. As electrode materials, metals such as gold, silver, copper, aluminum, titanium, and chromium, or alloys thereof, may be used, and to further reduce contact resistance, a metal having an appropriate work function may be selected or an intermediate layer may be inserted.

[0062] According to one embodiment of the present invention, the predetermined shape may include, but is not limited to, a shape selected from the group consisting of a line, a hole, a zigzag, a matrix, a honeycomb, and combinations thereof.

[0063] The shape of the pattern can be optimized according to the device's application and required performance. Line shapes provide efficient unidirectional current flow, while hole shapes enable localized electric field concentration through point contact. Zigzag shapes can maximize contact area by increasing contact length, and matrix shapes can provide uniform current distribution. Honeycomb shapes can simultaneously ensure structural stability and efficient charge transfer. The size of these patterns can generally be adjusted in the sub-micrometer to millimeter range.

[0064] According to one embodiment of the present invention, the two-dimensional semiconductor material may include, but is not limited to, a material selected from the group consisting of MoS2, WS2, MoSe2, WSe2, MoTe2, WTe2, TiS2, TiSe2, TiTe2, HfS2, HfSe2, HfTe2, ZrS2, ZrSe2, ZrTe2, TcS2, TcSe2, TcTe2, ReS2, ReSe2, ReTe2, PdS2, PdSe2, PtS2, PtSe2, black phosphorus, and combinations thereof.

[0065] These two-dimensional semiconductor materials each exhibit unique electrical and optical properties. MoS2 and WS2 display excellent n-type semiconductor characteristics, providing high mobility and stability. MoSe2 and WSe2 have relatively small band gaps, resulting in excellent photoresponsiveness in the near-infrared region. Black phosphorus exhibits anisotropic electrical conductivity along with direct band gap characteristics, making it suitable for specialized applications. These materials are characterized by high mobility and excellent channel control even at very thin atomic layer thicknesses; as thickness scaling progresses, their importance as channel materials possessing excellent semiconductor properties even at thin thicknesses is increasing.

[0066] According to one embodiment of the present invention, the source electrode and the drain electrode (300) may each simultaneously contact the two-dimensional semiconductor material layer (200) and the substrate (100), but are not limited thereto.

[0067] This structure provides a more stable electrical connection by having the electrode contact not only the two-dimensional semiconductor material layer (200) but also a portion of the substrate (100). This is particularly advantageous for ensuring stability in high-current operation or high-temperature environments, and can improve the mechanical stability of the device.

[0068] According to one embodiment of the present invention, the two-dimensional semiconductor material layer (200) may include an electrode contact region formed at both ends and in contact with the source electrode and drain electrode (300), respectively; and a channel region formed between the electrode contact regions and not in contact with the source electrode and drain electrode (300), but is not limited thereto.

[0069] The electrode contact region is a site where efficient charge exchange with the source electrode and drain electrode (300) takes place, and minimizes contact resistance through multiple edge contacts. In this region, increasing the contact area plays an important role in reducing contact resistance in very small device sizes or specific device structures. The channel region serves as a charge transfer path between the source and drain and is a major active region whose conductivity is controlled by the gate voltage.

[0070] According to one embodiment of the present invention, the contact resistance may be reduced by the plurality of edge contacts, but is not limited thereto.

[0071] Multiple edge contacts significantly increase the actual contact area between the electrode and the two-dimensional semiconductor material, thereby drastically reducing contact resistance. This resolves the splitting and tapering effects that occur in conventional single top contact or single edge contact methods, and prevents performance degradation caused by unstable contact. In edge contact, all layers contact the metal electrode and make contact in a single section, allowing carriers to be injected directly into the channel, thus improving contact resistance.

[0072] Additionally, a second aspect of the present invention provides a method for manufacturing a semiconductor device comprising the steps of: repeatedly transferring a single-layer two-dimensional semiconductor material (120) formed on a transfer substrate (110) to form a multilayer two-dimensional semiconductor material (160); patterning the multilayer two-dimensional semiconductor material (160) to form a two-dimensional semiconductor material layer (200) having a pattern having a predetermined shape; and forming a source electrode and a drain electrode (300) on the two-dimensional semiconductor material layer (200) at a predetermined interval, wherein the source electrode and the drain electrode (300) are each formed in a shape corresponding to the pattern to form a plurality of edge contacts.

[0073] Regarding the method for manufacturing a semiconductor device according to the second aspect of the present invention, detailed descriptions of parts that overlap with the first aspect of the present invention have been omitted, but even if such descriptions are omitted, the contents described in the first aspect of the present invention can be applied equally to the second aspect of the present invention.

[0074] The manufacturing method according to the present invention is designed to overcome the limitations of existing flake-based methods or general CVD multilayer synthesis methods and to form a uniform and controllable large-area multilayer structure. The transfer substrate (110) is an initial substrate on which a single-layer two-dimensional semiconductor material (120) is formed, and materials such as sapphire, silicon / silicon dioxide, and quartz used as growth substrates may be used. The single-layer two-dimensional semiconductor material (120) is formed through chemical vapor deposition, and the number of layers can be precisely controlled through a repetitive transfer process. By utilizing a large-area CVD thin film through this method, it becomes possible to form a large number of multiple edge contacts over a large area, which not only contributes to improving device characteristics but also enhances applicability in various fields.

[0075] FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0076] First, a single-layer two-dimensional semiconductor material (120) formed on a transfer substrate (110) is repeatedly transferred to form a multilayer two-dimensional semiconductor material (160). (S100)

[0077] In this step, a vacuum chuck (150) is used to transfer a thin film to form a multilayer structure of a desired thickness, thereby solving the problem of thin film damage and interlayer residue generation, which is one of the problems of the conventional transfer method. The multilayer two-dimensional semiconductor material (160) formed through repeated transfer is a structure in which a plurality of single-layer two-dimensional materials are stacked, and the number of layers can be adjusted according to the application.

[0078] According to one embodiment of the present invention, the step of forming the multilayer two-dimensional semiconductor material (160) comprises: a step of forming a laminated structure by sequentially forming a polymer layer (130) and a thermal release tape (140) on a single-layer two-dimensional semiconductor material (120) formed on a transfer substrate (110); a step of fixing the laminated structure using a vacuum chuck (150) and then separating the transfer substrate (110); a step of bringing a single-layer two-dimensional semiconductor material (120) located at the bottom of the laminated structure into contact with a single-layer two-dimensional semiconductor material (120) formed on another transfer substrate (110) and then separating the substrate to laminate an additional single-layer two-dimensional semiconductor material (120) at the bottom of the laminated structure; and a step of repeating the lamination step to form a plurality of single-layer two-dimensional semiconductor materials (120) laminated at the bottom of the laminated structure. The method may include the step of removing the thermal peel tape (140) and the polymer layer (130) after contacting the lower part of the laminated structure with the target substrate (100), but is not limited thereto.

[0079] In this process, the polymer layer (130) is generally coated with a polymer material such as PMMA (polymethyl methacrylate) and serves to provide mechanical support and protection for the thin film. The heat release tape (140) has the characteristic of having its adhesive strength reduced by heat and is used for adhesion to the vacuum chuck (150). The size of the adsorption hole of the vacuum chuck (150) can generally be adjusted in the range of 0.1 μm to 1000 μm, specifically in the range of 0.5 μm to 500 μm, and more specifically in the range of 1 μm to 100 μm. The pressure range is generally controlled between 0.1 bar and 2 bar, specifically between 0.2 bar and 1.5 bar, and more specifically between 0.3 bar and 1 bar.

[0080] FIG. 3 is a process diagram showing the step of forming a multilayer two-dimensional semiconductor material (160) by repeatedly transferring a single-layer two-dimensional semiconductor material (120).

[0081] First, a polymer layer (130) and a thermal release tape (140) are sequentially formed on a single-layer two-dimensional semiconductor material (120) formed on a transfer substrate (110) to form a laminated structure. (S110)

[0082] The polymer layer (130) can be formed by methods such as spin coating, dip coating, or spray coating, and the heat release tape (140) must have the characteristic of having appropriate adhesion while being easily separated through heat treatment.

[0083] Next, the laminated structure is fixed using a vacuum chuck (150), and then the transfer substrate (110) is separated. (S120)

[0084] Fixing using a vacuum chuck (150) is essential for stable support of the laminated structure. The vacuum pressure must be adjusted to ensure sufficient adhesion while preventing damage to the thin film. Separation of the transfer substrate (110) is performed using weak van der Waals bonds between the thin film and the substrate, and it is important to minimize damage to the thin film during this process.

[0085] According to one embodiment of the present invention, the step of separating the transfer substrate (110) may be performed by immersing the entire structure including the transfer substrate (110), a single-layer two-dimensional semiconductor material (120), a polymer layer (130), a thermal release tape (140), and a vacuum chuck (150) in distilled water, but is not limited thereto.

[0086] In the underwater separation process, the weak van der Waals bonds between the substrate and the thin film can be effectively separated by utilizing the surface tension of water and capillary action. This method enables uniform separation while minimizing damage to the thin film compared to mechanical peeling. The water temperature and separation time can be appropriately adjusted according to the size, thickness, and adhesion state of the thin film, and the stability of the laminated structure can be maintained through the adsorption force of the vacuum chuck (150) during the separation process.

[0087] Next, a single-layer two-dimensional semiconductor material (120) located at the bottom of the stacked structure is brought into contact with a single-layer two-dimensional semiconductor material (120) formed on another transfer substrate (110), and then the substrate is separated to stack an additional single-layer two-dimensional semiconductor material (120) at the bottom of the stacked structure. (S130)

[0088] At this stage, contact must be made under precise alignment and controlled pressure. Contact between the two single-layer two-dimensional semiconductor materials (120) is made by van der Waals forces, and an interlayer bond can be formed through appropriate contact pressure and time. During the contact process, the intervention of bubbles or foreign substances must be prevented, and environmental conditions such as temperature and humidity must also be considered to ensure uniform contact. After the substrate is separated, the new single layer is stably bonded to the existing stacked structure.

[0089] Next, the stacking step is repeated to form a plurality of single-layer two-dimensional semiconductor materials (120) stacked on the lower part of the stacked structure. (S140)

[0090] The number of layers is determined by the target final thickness and the required characteristics of the device. Uniformity and reproducibility must be ensured at each layering step by maintaining the same conditions and procedures as the previous step. During the iterative process, the alignment and adhesion status between layers are continuously monitored, and layering conditions can be fine-tuned as needed. As layering progresses, the mechanical stability and electrical properties of the entire structure gradually improve, ultimately enabling the attainment of a high-quality multilayer structure with the desired number of layers.

[0091] Finally, after bringing the lower part of the laminated structure into contact with the target substrate (100), the thermal release tape (140) and the polymer layer (130) are removed. (S150)

[0092] Contact with the target substrate (100) is an important step for stably transferring the multilayer structure onto the substrate on which the final device is to be formed. After contact, the thermal release tape (140) is removed, which reduces the adhesive strength of the tape through heat treatment so that it can be easily separated. The removal of the polymer layer (130) is performed by methods such as dissolution using a suitable solvent or plasma ashing, and this process must be carried out under mild conditions so as not to damage the underlying two-dimensional semiconductor material. Finally, a uniform and high-quality multilayer two-dimensional semiconductor material (160) is stably formed on the target substrate (100).

[0093] Next, the multilayer two-dimensional semiconductor material (160) is patterned to form a two-dimensional semiconductor material layer (200) including a pattern having a predetermined shape. (S200)

[0094] In the patterning process, methods such as photolithography, electron beam lithography, or nanoimprint lithography may be used. Since the precision of the patterning directly affects the performance of the final device, precise control at the nanometer level is required. The minimum line width of the pattern can generally be adjusted in the range of 0.1 μm to 100 μm, specifically in the range of 0.5 μm to 50 μm, more specifically in the range of 0.8 μm to 20 μm, and most specifically in the range of 1 μm to 10 μm.

[0095] According to one embodiment of the present invention, the step of forming the two-dimensional semiconductor material layer (200) may be performed using either a partial etching method in which only a portion of the upper layer of the multilayer two-dimensional semiconductor material (160) is selectively etched and patterned while a portion of the lower layer is retained; or a total etching and transfer method in which the entire layer of the multilayer two-dimensional semiconductor material (160) is etched and patterned, and then transferred onto a separate two-dimensional semiconductor material, but is not limited thereto.

[0096] Figure 4 is a process diagram showing the steps of forming a two-dimensional semiconductor material layer through a partial etching method.

[0097] In the partial etching method, a thin film with a multilayer structure is patterned into a desired electrode contact shape through mask patterning and etching processes, and then the contact area is removed to a desired thickness. Through precise control of the etching depth, a desired thickness difference between the first region (210) and the second region (220) can be formed.

[0098] Figure 5 is a process diagram showing the steps of forming a two-dimensional semiconductor material layer through a total etching and transfer method.

[0099] In the total etching and transfer method, it is possible to form a thin film with a second thickness difference by forming a thin film with different thicknesses or a thin film with all contact regions removed, and then transferring it to the same material having a desired layer. In addition, it is possible to form a bond by transferring it to a different material having a desired layer or a different material having a desired thickness difference.

[0100] According to one embodiment of the present invention, the etching may be performed by a method selected from the group consisting of sputtering, reactive ion beam, atomic layer etching, laser irradiation, electron beam irradiation, thermal etching, wet etching, and combinations thereof, but is not limited thereto.

[0101] Each etching method has unique characteristics and advantages and disadvantages. Sputtering is a physical etching method with excellent directionality, while reactive ion beams can achieve both chemical selectivity and physical directionality simultaneously. Atomic layer etching enables precise thickness control at the atomic level, and laser irradiation allows for selective etching through localized heating. Electron beam irradiation enables direct patterning without a mask, and thermal etching can minimize damage under mild conditions. Wet etching allows for large-area processing and is cost-effective. In terms of removal methods, materials ranging from single layers to multilayers or all layers can be removed to the desired thickness.

[0102] Finally, a source electrode and a drain electrode (300) are formed on the two-dimensional semiconductor material layer (200) at a predetermined interval. (S300)

[0103] In the electrode formation process, a metal electrode is formed on the electrode contact area after the electrode contact area is formed. For electrode formation, patterning through photolithography and metal film deposition through physical or chemical deposition are performed. The source electrode and drain electrode (300) are formed in a shape corresponding to the pattern to form multiple edge contacts, and in particular, special processes such as isotropic etching or oblique deposition may be applied to form a three-dimensional structure that wraps around the sides.

[0104] In addition, a third aspect of the present invention provides a transistor comprising a semiconductor device according to a first aspect of the present invention.

[0105] Regarding the transistor according to the third aspect of the present invention, detailed descriptions of parts that overlap with the first aspect of the present invention have been omitted, but even if such descriptions are omitted, the contents described in the first aspect of the present invention may be applied equally to the third aspect of the present invention.

[0106] The transistor according to the present invention exhibits enhanced electrical characteristics through multiple edge contacts. In particular, an increase in on-current, an improvement in the on-off ratio, and a reduction in subthreshold swing are achieved, enabling the realization of a high-performance transistor. Such a transistor can be utilized in low-power logic devices, high-frequency devices, or flexible electronic devices, and is particularly suitable for next-generation nanoscale electronic devices as it can maintain excellent electrical characteristics even at thin thicknesses.

[0107] In addition, the fourth aspect of the present invention provides a memory device comprising a semiconductor device according to the first aspect of the present invention.

[0108] Regarding the memory device according to the fourth aspect of the present invention, detailed descriptions of parts that overlap with the first aspect of the present invention have been omitted, but even if such descriptions are omitted, the contents described in the first aspect of the present invention can be applied equally to the fourth aspect of the present invention.

[0109] The memory device according to the present invention exhibits improved read / write speeds and data retention characteristics due to reduced contact resistance. Combined with the unique properties of two-dimensional semiconductor materials, it can be utilized as a next-generation memory device of various forms, such as non-volatile memory, phase change memory, or resistive change memory. In particular, since the desired thickness can be controlled, the properties of two-dimensional semiconductor materials, in which the bandgap changes depending on the thickness, can be utilized for desired purposes.

[0110] In addition, the fifth aspect of the present invention provides a sensor comprising a semiconductor device according to the first aspect of the present invention.

[0111] Regarding the sensor according to the fifth aspect of the present invention, detailed descriptions of parts that overlap with the first aspect of the present invention have been omitted, but even if such descriptions are omitted, the contents described in the first aspect of the present invention may be applied equally to the fifth aspect of the present invention.

[0112] The sensor according to the present invention provides high sensitivity and a fast response speed through the excellent light absorption characteristics and reduced contact resistance of the first region (210). This can be utilized for various sensing applications such as optical sensors, gas sensors, biosensors, and pressure sensors, and can exhibit excellent performance, especially in applications requiring high sensitivity. The overall performance of the sensor can be improved by optimizing the characteristics of each region through the thickness difference between the first region (210) and the second region (220).

[0113] In addition, the sixth aspect of the present invention provides an optoelectronic device comprising a semiconductor device according to the first aspect of the present invention.

[0114] Regarding the optoelectronic device according to the sixth aspect of the present invention, detailed descriptions of parts that overlap with the first aspect of the present invention have been omitted, but even if such descriptions are omitted, the contents described in the first aspect of the present invention can be applied equally to the sixth aspect of the present invention.

[0115] The optoelectronic device according to the present invention provides high performance by combining the excellent photoelectric properties of a two-dimensional semiconductor material with efficient charge collection through multiple edge contacts. The thin thickness of the first region (210) improves light absorption and charge separation efficiency, while the thick thickness of the second region (220) provides mechanical stability and efficient charge transfer. This structure can be applied to various optoelectronic devices such as solar cells, photodetectors, and light-emitting diodes.

[0116] Additionally, the seventh aspect of the present invention provides an integrated circuit comprising a semiconductor device according to the first aspect of the present invention.

[0117] Regarding the integrated circuit according to the seventh aspect of the present invention, detailed descriptions of parts that overlap with the first aspect of the present invention have been omitted, but even if such descriptions are omitted, the contents described in the first aspect of the present invention may be applied equally to the seventh aspect of the present invention.

[0118] The integrated circuit according to the present invention enables the implementation of high-density, high-performance circuits by using two-dimensional semiconductor devices having multiple edge contacts as basic components. Through reduced contact resistance and improved electrical characteristics, low-power operation and high integration density can be achieved simultaneously, which can contribute to the development of high-performance integrated circuits such as next-generation microprocessors, memory chips, or system-on-chip (SoC). By utilizing large-area CVD thin films, a large number of devices can be fabricated simultaneously over a large area, thereby ensuring manufacturing efficiency and economic viability.

[0119] The present invention is to be explained in more detail through the following examples, but the following examples are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0121] [Example 1-1] Manufacturing of a semiconductor device using a partial etching method

[0122] In this embodiment, a semiconductor device was manufactured using a partial etching method.

[0123] First, a four-layer CVD MoS2 thin film was transferred onto a target substrate by repeatedly transferring a one-layer CVD MoS2 thin film. For thin film transfer, PMMA was spin-coated onto the one-layer CVD MoS2 thin film at 500 rpm for 5 seconds and at 4000 rpm for 25 seconds, after which a thermal release tape was attached to the PMMA. Subsequently, the thin film with the thermal release tape and PMMA was fixed using a vacuum chuck, and the film and substrate were separated by immersing it in distilled water at room temperature for approximately 30 seconds. This process was repeated to form a four-layer CVD MoS2 thin film, which was then transferred onto the target substrate.

[0124] Next, the heat release tape attached to the thin film was removed by heating it at a temperature of 100°C for 5 minutes, and then the PMMA thin film was removed using an acetone solution.

[0125] Subsequently, PR line patterning was performed through a photolithography process, and then an etching process was selectively carried out only on the exposed areas. For the atomic layer etching process, treatment was performed for 2 minutes in a remote plasma system under conditions of chlorine (Cl2) 80 sccm and 200 W, followed by treatment for 2 minutes in a 3-grid ion beam system under conditions of argon (Ar) 60 sccm, 200 W, 1st grid 25 V, and 2nd grid -125 V.

[0126] After removing PR, the electrode region was patterned, and then an electrode (Cr 5 nm / Au 50 nm) was deposited to fabricate the device.

[0127] [Example 1-2] Manufacturing of semiconductor devices through total etching and transfer method

[0128] In this embodiment, a semiconductor device was manufactured using a total etching and transfer method.

[0129] First, a 3-layer CVD MoS2 thin film was transferred onto a target substrate by repeatedly transferring a 1-layer CVD MoS2 thin film in the same manner as in Example 1-1 above.

[0130] Next, the exposed area after PR line patterning through a photolithography process was treated in a reactive ion beam etcher with argon (Ar) at 100 sccm and 25 W for 5 minutes.

[0131] After removing the PR, the three layers of CVD MoS2 thin film were transferred onto the one layer of CVD MoS2 thin film formed on the target substrate, and then an electrode (Cr 5 nm / Au 50 nm) was formed.

[0132] [Comparative Example 1]

[0133] In this comparative example, as shown in FIG. 7a, electrodes were first formed on a 4-layer CVD MoS2 thin film, and then selective etching was performed on the channel region.

[0134] Specifically, after performing PR line patterning through a photolithography process, only the exposed area was selectively etched. The etching process was performed by applying the same etching process as in Example 1-1.

[0135] Accordingly, the channel region had a structure with different layers of 4 layers and 1 layer, and the region where the electrode was formed maintained an electrode contact region with an unetched 4-layer structure.

[0136] [Experimental Example 1] Analysis of the Multilayer Structure Formation Process

[0137] Figure 6a shows TEM images of a multilayer structure manufactured according to the method of the present invention (top) and a multilayer structure manufactured through a conventional transfer method (bottom).

[0138] Referring to Fig. 6a, as a result of forming a multilayer structure using a vacuum chuck, CVD MoS2 was used for the thin film, and MoS2 structures ranging from 1L to 5L were formed by repeatedly transferring 1L to the target thickness. As can be seen in the TEM image, a crystalline layered structure was formed, and the absence of interlayer residues confirmed that the residue problem, which is one of the issues of conventional transfer methods, did not occur. In contrast, conventional transfer methods have low crystallinity and generate interlayer residues.

[0139] According to Figures 6b and 6c, it was possible to confirm the trend of increasing peak spacing of the Raman spectrum and changes in device characteristics (increase in on-current) with increasing number of layers in the structures of 1L, 3L, and 5L, respectively.

[0140] [Experimental Example 2] Improvement of device characteristics through edge contact formation

[0141] A device having a structure in which both the channel region and the electrode contact region have different thicknesses (Example 1) and a device having a structure in which only the channel region has a different thickness (Comparative Example 1) were fabricated and a comparative evaluation was conducted.

[0142] Referring to Figures 7a and 7b, it was confirmed that in a device (Example 1) having structures with different thicknesses formed in the electrode contact area, the resistance was reduced by the formation of edge contacts, and the device characteristics were improved (increase in on-current, increase in on / off ratio, decrease in subthreshold swing).

[0143] [Experimental Example 3] Analysis of characteristics according to the number of edge contact surfaces

[0144] A comparative evaluation of device characteristics was conducted according to the number of edge contact surfaces. Specifically, the characteristics were compared after fabricating the device by adjusting the pattern line width differently (0, 10 μm, 1 μm).

[0145] It was confirmed that electrical characteristics were improved in devices with different numbers of layers (Figs. 8b and 8c) compared to a device with the same number of layers (0 μm) (Fig. 8a), and that electrical characteristics were superior in a device with shorter lengths of different layers, that is, a device with more different layers formed (Fig. 8c). This result indicates that electrical characteristics were improved as the edge contact area increased as the number of edge contact surfaces increased.

[0146] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.

[0147] The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and the concept of equivalents thereof should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0148] 100: Substrate (Target Substrate) 110: Transfer board 120: Monolayer 2D semiconductor material 130: Polymer layer 140: Heat release tape 150: Vacuum Chuck 160: Multilayer 2D semiconductor materials 200: 2D semiconductor material layer 210: Zone 1 220: Second Zone 300: Source electrode and drain electrode

Claims

Claim 1 A semiconductor device comprising: a substrate; a two-dimensional semiconductor material layer including a pattern having a predetermined shape formed on the substrate; and a source electrode and a drain electrode disposed on the two-dimensional semiconductor material layer at a predetermined interval, wherein the source electrode and the drain electrode are each formed to surround a portion of the upper surface and the entire side surface of the two-dimensional semiconductor material layer, and are each formed in a shape corresponding to the pattern to form a plurality of edge contacts. Claim 2 delete Claim 3 A semiconductor device according to claim 1, wherein the pattern includes a first region and a second region having different thicknesses, and the source electrode and the drain electrode are formed to individually wrap the upper surface and the side surface of the first region and the second region, respectively, thereby increasing the contact area with the two-dimensional semiconductor material layer. Claim 4 A semiconductor device according to claim 1, wherein the predetermined shape comprises a line, a hole, a zigzag, a matrix, a honeycomb, and combinations thereof, selected from the group consisting of a line, a hole, a zigzag, a matrix, a honeycomb, and combinations thereof. Claim 5 A semiconductor device according to claim 1, wherein the two-dimensional semiconductor material comprises a material selected from the group consisting of MoS2, WS2, MoSe2, WSe2, MoTe2, WTe2, TiS2, TiSe2, TiTe2, HfS2, HfSe2, HfTe2, ZrS2, ZrSe2, ZrTe2, TcS2, TcSe2, TcTe2, ReS2, ReSe2, ReTe2, PdS2, PdSe2, PtS2, PtSe2, black phosphorus, and combinations thereof. Claim 6 A semiconductor device according to claim 1, wherein the source electrode and the drain electrode each simultaneously contact the two-dimensional semiconductor material layer and the substrate. Claim 7 A semiconductor device according to claim 1, wherein the two-dimensional semiconductor material layer comprises: electrode contact regions formed at both ends and contacting the source electrode and drain electrode, respectively; and channel regions formed between the electrode contact regions and not contacting the source electrode and drain electrode. Claim 8 A semiconductor device according to claim 1, wherein the contact resistance is reduced by the plurality of edge contacts. Claim 9 A method for manufacturing a semiconductor device comprising: a step of repeatedly transferring a single-layer two-dimensional semiconductor material formed on a transfer substrate to form a multilayer two-dimensional semiconductor material; a step of patterning the multilayer two-dimensional semiconductor material to form a two-dimensional semiconductor material layer including a pattern having a predetermined shape; and a step of forming a source electrode and a drain electrode at a predetermined interval on the two-dimensional semiconductor material layer; wherein the source electrode and the drain electrode are each formed to surround a part of the upper surface and the entire side surface of the two-dimensional semiconductor material layer, and are each formed in a shape corresponding to the pattern to form a plurality of edge contacts. Claim 10 delete Claim 11 A method for manufacturing a semiconductor device according to claim 9, wherein the pattern comprises a first region and a second region having different thicknesses, and the source electrode and the drain electrode are formed to individually wrap the upper surface and the side surface of the first region and the second region, respectively, thereby increasing the contact area with the two-dimensional semiconductor material layer. Claim 12 A method for manufacturing a semiconductor device according to claim 9, wherein the step of forming the multilayer two-dimensional semiconductor material comprises: a step of sequentially forming a polymer layer and a thermal release tape on a single-layer two-dimensional semiconductor material formed on a transfer substrate to form a stacked structure; a step of fixing the stacked structure using a vacuum chuck and then separating the transfer substrate; a step of contacting a single-layer two-dimensional semiconductor material located at the bottom of the stacked structure with a single-layer two-dimensional semiconductor material formed on another transfer substrate and then separating the substrate to stack an additional single-layer two-dimensional semiconductor material on the bottom of the stacked structure; a step of repeating the stacking step to form a plurality of single-layer two-dimensional semiconductor materials stacked on the bottom of the stacked structure; and a step of contacting the bottom of the stacked structure with a target substrate and then removing the thermal release tape and the polymer layer. Claim 13 A method for manufacturing a semiconductor device according to claim 12, wherein the step of separating the transfer substrate is performed by immersing the entire structure including the transfer substrate, a single-layer two-dimensional semiconductor material, a polymer layer, a thermal release tape, and a vacuum chuck in distilled water. Claim 14 A method for manufacturing a semiconductor device according to claim 9, wherein the step of forming the two-dimensional semiconductor material layer utilizes either a partial etching method in which only a portion of the upper layer of the multilayer two-dimensional semiconductor material is selectively etched and patterned while a portion of the lower layer is retained; or a total etching and transfer method in which the entire layer of the multilayer two-dimensional semiconductor material is etched and patterned, and then transferred onto a separate two-dimensional semiconductor material. Claim 15 A method for manufacturing a semiconductor device according to claim 14, wherein the etching is performed by a method selected from the group consisting of sputtering, reactive ion beam, atomic layer etching, laser irradiation, electron beam irradiation, thermal etching, wet etching, and combinations thereof. Claim 16 A transistor comprising a semiconductor element according to claim 1. Claim 17 A memory device comprising a semiconductor device according to claim 1. Claim 18 A sensor comprising a semiconductor element according to claim 1. Claim 19 An optoelectronic device comprising a semiconductor device according to claim 1. Claim 20 An integrated circuit comprising a semiconductor element according to claim 1.

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