Serial peripheral interface integrated circuit and operation method thereof

Abstract

A Serial Peripheral Interface (SPI) integrated circuit (IC) and a method of operating the same are provided. An SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and transmits the first command information and the first debugging information to the slave IC via an SPI channel. When the SPI IC is a slave IC, the SPI IC receives the second command information and the second debugging information transmitted by the master IC via the SPI channel, and verifies the second command information using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC verifies the second command information and executes the second command information under the condition that it is accurate.

Description

Technology Field

[0001] The present invention relates to an integrated circuit, and more particularly to a serial peripheral interface integrated circuit and a method of operating the same. Background Technology

[0002] In some product applications, multiple integrated circuits (ICs) may be required to work together. For example, in Large Touch Display IC (LTDI) applications, multiple (e.g., 30) driver ICs work together to drive the same large touch display panel. The Serial Peripheral Interface (SPI) architecture can provide a multi-drop driver architecture. In an SPI multi-drop driver architecture, a master IC can connect to and drive multiple slave ICs through the same wiring (channel). When different ICs pass through the SPI channel, the transmitted signal of the SPI channel may be distorted due to external influences. The problem to be solved

[0003] The present disclosure provides a Serial Peripheral Interface (SPI) integrated circuit (IC) and a method of operating the same that can protect data transmitted through an SPI channel and / or ensure the accuracy of data received through an SPI channel. means of solving the problem

[0004] In an embodiment of the present disclosure, the SPI IC includes a core circuit and a debugging circuit. The debugging circuit is coupled to the core circuit. When the SPI IC is a master IC of the SPI architecture, the core circuit generates first command information for a slave IC of the SPI architecture, and the debugging circuit generates first debugging information corresponding to the first command information, and the SPI IC transmits the first command information and the first debugging information to the slave IC in the SPI architecture via an SPI channel. When the SPI IC is a slave IC in the SPI architecture, the debugging circuit receives second command information and second debugging information transmitted by the master IC via the SPI channel, and the debugging circuit verifies the second command information using the second debugging information. When the above SPI IC is a slave IC of the above SPI architecture and the above SPI IC is a target slave circuit selected by the master IC of the above SPI architecture, the core circuit executes the second command information transmitted by the master IC under the condition that the second command information is verified by the debugging circuit and is accurate.

[0005] In one embodiment of the present invention, the operation method comprises the following steps. When the SPI IC is a master IC of the SPI architecture, first command information for a slave IC in the SPI architecture is generated, first debugging information corresponding to the first command information is generated, and the first command information and the first debugging information are transmitted to the slave IC in the SPI architecture via an SPI channel. When the SPI IC is a slave IC of the SPI architecture, the second command information and the second debugging information transmitted by the master IC are received via the SPI channel, and the second command information is verified using the second debugging information. Additionally, when the SPI IC is a slave IC of the SPI architecture and the SPI IC is a target slave circuit selected by the master IC of the SPI architecture, the second command information transmitted by the master IC is executed under the condition that the second command information is verified and is accurate.

[0006] In summary, according to actual application scenarios, the SPI IC provided by the embodiment of the present disclosure can operate as a master IC or a slave IC of an SPI architecture. When the SPI IC is a master IC, the SPI IC can generate debugging information corresponding to the command information and transmit the command information and debugging information to a slave IC via an SPI channel. When the SPI IC is a slave IC, if the SPI IC is a target slave circuit selected by the master IC of the SPI architecture, the SPI IC can receive the command information and debugging information transmitted by the master IC via an SPI channel, and the SPI IC can verify the command information using the debugging information. When the command information is verified and is accurate, the SPI IC can execute the command information sent by the master IC. Therefore, the SPI IC can protect data transmitted via an SPI channel and / or guarantee the accuracy of data received via an SPI channel.

[0007] To make the above-described content easier to understand, various embodiments are described in detail as follows, together with the drawings. Brief explanation of the drawing

[0008] The accompanying drawings are incorporated into this specification and constitute part of it, in order to provide further understanding of the content of this disclosure. The drawings illustrate exemplary embodiments of the invention and serve to explain the principles of the invention together with the description. FIG. 1 is a schematic diagram of a circuit block of a Serial Peripheral Interface (SPI) architecture according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram of a circuit block of an SPI architecture according to another embodiment of the present disclosure. FIG. 3 is a schematic diagram of a circuit block of an SPI integrated circuit according to an embodiment of the present disclosure. FIG. 4 is a schematic flowchart of an operation method of an SPI integrated circuit according to one embodiment of the present invention. FIG. 5 is a schematic flowchart of a method of operation of an SPI integrated circuit according to another embodiment of the present disclosure. Specific details for implementing the invention

[0009] The term “combined (or connected)” as used in the entire disclosure (including the claims) refers to direct or indirect means of connection. For example, if the disclosure describes a first device being combined (or connected) to a second device, this should be described as the first device being directly connected to the second device, or being indirectly connected to the second device through the first device being connected to another device or by using specific means of connection. Furthermore, throughout the specification (including the claims), terms such as “first” and “second” are used merely to name elements or to distinguish different embodiments or scopes, and should not be interpreted as an upper or lower limit on the number of any elements, nor as limiting the order of the elements. Moreover, elements / components / steps having the same reference number represent the same or similar parts in the drawings and embodiments where appropriate. Descriptions of elements / components / steps having the same reference number or term in different embodiments may refer to one another.

[0010] FIG. 1 is a schematic diagram of circuit blocks of a Serial Peripheral Interface (SPI) architecture (100) according to an embodiment of the present disclosure. In the embodiment illustrated in FIG. 1, the SPI architecture (100) may be a multi-drop driving architecture. The SPI architecture (100) includes a plurality of integrated circuits (ICs), such as a master IC (M11) and slave ICs (S11, ..., S1n). The number n of slave ICs (S11 to S1n) may be determined by design. In the SPI architecture (100), the slave ICs (S11 to S1n) are connected together to the master IC (M11). The master IC (M11) and the slave ICs (S11 to S1n) are assigned / defined by different dedicated identification codes.

[0011] The master IC (M11) can transmit commands (or data) and clock signals according to SPI specifications to slave ICs (S11 to S1n) through an SPI channel / interface. The master IC (M11) can select any one of the slave ICs (S11 to S1n) as a target slave circuit through an SPI channel / interface, and the target slave circuit can execute (process) the commands (or data) sent by the master IC (M11). When any of the slave ICs (S11 to S1n) determines that it is not the target slave circuit selected by the master IC (M11), the unselected slave IC may ignore (not process) the commands (data) of the master IC (M11).

[0012] FIG. 2 is a schematic diagram of circuit blocks of an SPI architecture (200) according to another embodiment of the present disclosure. In the embodiment illustrated in FIG. 2, the SPI architecture (200) may be a daisy-chain architecture. The SPI architecture (200) includes a plurality of ICs connected in series, such as a master IC (M21) and slave ICs (S21, ..., S2n). The number n of slave ICs (S21 to S1n) may be determined according to the design. In the daisy-chain SPI architecture (200), the slave ICs (S21 to S2n) are connected in series to form a daisy chain, and the master IC (M21) is connected to the first slave IC (S21) in the daisy chain. The master IC (M21) and the slave ICs (S21 to S2n) are assigned / defined by different dedicated identification codes. The master IC (M21) can send commands (or data) and clock signals according to the SPI standard to the daisy chain through an SPI channel / interface, and any slave ICs (S21~S2n) in the daisy chain can transmit commands (or data) and clock signals from the previous IC to the next IC.

[0013] The master IC (M21) can select any one of the slave ICs (S21 to S2n) as a target slave circuit via an SPI channel / interface. That is, each of the slave ICs (S21 to S2n) can determine whether the previous IC is the target slave circuit selected by the master IC (M21) by decoding a command (or data) from the previous IC. The target slave circuit can further execute (process) the command (data) transmitted by the master IC (M21). When any of the slave ICs (S21 to S2n) determines that it is not the target slave circuit selected by the master IC (M21), the unselected slave IC may ignore (not process) the command (data) of the master IC (M21).

[0014] FIG. 3 is a schematic diagram of circuit blocks of SPI ICs according to an embodiment of the present disclosure. FIG. 3 illustrates an SPI IC (310) and a SPI IC (320). Here, the SPI IC (310) operates as a master IC (e.g., the master IC (M11) of FIG. 1 or the master IC (M21) of FIG. 2) in an SPI architecture, and the SPI IC (320) can operate as a slave IC (e.g., one of the slave ICs S11 to S1n shown in FIG. 1 or one of the slave ICs S21 to S2n shown in FIG. 2) in an SPI architecture. The SPI IC (310) can be coupled to the SPI IC (320) through an SPI channel (SPI interface). The SPI IC (310) can transmit commands (or data) and clock signals according to the SPI specification to the slave SPI IC (320) through the SPI channel. The SPI IC (320) can return the data to the SPI IC (310) through the SPI channel based on the result of executing the command and / or the result of processing the data.

[0015] FIG. 4 is a schematic flowchart of a method of operating an SPI IC according to an embodiment of the present invention. Referring to FIG. 3 and FIG. 4, an SPI IC (310) acting as a master IC includes a core circuit (311) and a debugging circuit (312). The debugging circuit (312) is connected to the core circuit (311). In step S410, the core circuit (311) can generate command information for the SPI IC (320) (a slave IC within the SPI architecture, i.e., a target slave circuit), and this command information (first command information) may include a command (data) that complies with the SPI specification. In some actual designs, this command information may include a dedicated identification code (chip identification code) of the target slave circuit. In some other actual designs, this command information may include a chip identification code and a command code that complies with the SPI specification.

[0016] In some other actual designs, this command information may include a data error correction flag, a chip identification code, and a command code that comply with the SPI specification. The data error correction flag is used to notify the SPI IC (320) whether to enable an error correction operation for the data information provided by the SPI IC (310) (detailed description is provided in the following paragraphs). For example, the core circuit (311) may notify the SPI IC (320) (slave IC) to enable an error correction operation for the data information by setting the data error correction flag. Alternatively, the core circuit (311) may reset the data error correction flag to notify the SPI IC (320) to disable the error correction operation for the data information.

[0017] In step S420, the debugging circuit (312) may generate debugging information (first debugging information) corresponding to the command information. The specific implementation of the generation of debugging information by the debugging circuit (312) is not limited in this embodiment. For example, in some actual designs, the debugging information may include an error-correcting code (ECC), that is, the debugging circuit (312) may perform an ECC algorithm on the command information to generate the debugging information. In some other actual designs, the debugging circuit (312) may perform a checksum algorithm or other debugging algorithm on the command information to generate the debugging information.

[0018] In step S430, the debugging circuit (312) (or core circuit (311)) can transmit the command information and debugging information to the SPI IC (320) via the SPI channel. After the transmission of the command information and debugging information is completed, the core circuit (311) can further generate data information (first data information) corresponding to the command information (first command information) and transmit the data information to the SPI IC (320) via the SPI channel. According to the actual design, the data information may include an address field, a data field, and / or other fields compliant with the SPI specification.

[0019] According to the actual design, in some embodiments, the debugging circuit (312) may further generate debugging information (third debugging information) corresponding to the data information. The debugging circuit (312) (or core circuit (311)) may transmit the data information and the third debugging information to the SPI IC (320) via an SPI channel. The specific implementation of the generation of the third debugging information by the debugging circuit (312) is not limited in this embodiment. For example, in some actual designs, the third debugging information may include a cyclic redundancy check (CRC) code, that is, the debugging circuit (312) may generate the third debugging information by performing a CRC algorithm on the data information. In some other actual designs, the debugging circuit (312) may perform a checksum algorithm or other debugging algorithm on the data information to generate the third debugging information.

[0020] FIG. 5 is a schematic flowchart of a method of operation of an SPI IC according to another embodiment of the present disclosure. Referring to FIG. 3 and FIG. 5, an SPI IC (320) acting as a slave IC in an SPI architecture may include a core circuit (321) and a debugging circuit (322). The debugging circuit (322) is coupled to the core circuit (321). In step S510, the debugging circuit (322) may receive command information (second command information) and debugging information (second debugging information) transmitted by the SPI IC (310) (master IC) through an SPI channel. In some practical designs, this command information may include a chip identification code (proprietary identification code), a data error correction flag, an SPI command code, and / or other data. In some practical designs, the debugging information includes an error correction code (ECC), a checksum code, or other debugging information. In step S520, the debugging circuit (322) may verify the command information using the debugging information.

[0021] The SPI IC (320) (slave IC) can determine whether the SPI IC (320) itself is the target slave circuit selected by the SPI IC (310) by decoding command information from the SPI IC (310). When the SPI IC (320) is not the target slave circuit selected by the SPI IC (310) (determined as "No" in step S530), the core circuit (321) can perform step S540. That is, the core circuit (321) can ignore (not process) the command information from the SPI IC (310). When the SPI IC (320) is the target slave circuit selected by the SPI IC (310) (determined as "Yes" in step S530), the core circuit (321) can perform step S550, which is to determine whether the command information from the SPI IC (310) has been verified and is accurate.

[0022] Based on the inspection performed in step S520, when the debugging circuit (32) inspects that the command information is incorrect (determined as "No" in step S550), the debugging circuit (322) may perform step S560. In step S560, the debugging circuit (322) may notify / request the SPI IC (310) to retransmit the command information through the SPI channel by returning error information (e.g., an error flag) to the SPI IC (310). When the SPI IC (320) notifies that the command information is incorrect, the core circuit (311) of the SPI IC (310) may retransmit the command information to the SPI IC (320) through the SPI channel.

[0023] When the debugging circuit (322) confirms that the above command information is accurate (determined as "Yes" in step S550), the core circuit (321) can execute the command information transmitted by the SPI IC (310) (master IC) by performing step S570. In the process of executing the above command information, the debugging circuit (322) can receive data information (second data information) corresponding to the command information transmitted by the SPI IC (310) through the SPI channel. According to the actual design, the data information may include an address field, a data field, and / or other fields compliant with the SPI specification.

[0024] When the data error correction flag is set, the debugging circuit (322) may receive additional debugging information (fourth debugging information) corresponding to the data information through the SPI channel. In some actual designs, the fourth debugging information may include a CRC code, a checksum algorithm, or other debugging information. The debugging circuit (322) may verify the command information using the fourth debugging information. When the debugging circuit (322) verifies whether the data information is accurate, the core circuit (321) may process the data information transmitted by the SPI IC (310) (master IC). When the debugging circuit (322) verifies that one bit (or multiple bits) of the data information is incorrect, the debugging circuit (322) may recover the data information using the fourth debugging information.

[0025] When the debugging circuit (322) determines that the use of the above-mentioned fourth debugging information is insufficient to recover the erroneous data information, the debugging circuit (322) may return the error information (e.g., an error flag) to the SPI IC (310) (master IC) and notify / request the SPI IC (310) to retransmit the data information through the SPI channel. When the SPI IC (320) notifies that the data information is incorrect, the core circuit (311) of the SPI IC (310) may retransmit the data information to the SPI IC (320) through the SPI channel.

[0026] In another actual design, command information from the SPI IC (310) may include a data error correction flag. The SPI IC (320) may determine whether to enable an error correction operation for the data information provided by the SPI IC (310) based on the data error correction flag from the SPI IC (310). For example, when the data error correction flag is enabled, the debugging circuit (322) may check the data information from the SPI IC (310) using the fourth debugging information. When the data error correction flag is disabled, the debugging circuit (322) may not check the data information.

[0027] Referring to the foregoing, in a system comprising multiple chips connected in series, the master IC can select one chip (slave IC) using a chip identification code and issue commands for reading and writing to the selected chip. In some embodiments, the master IC and the slave IC can protect the chip identification code and commands using ECC. If an error occurs in the transmission of the chip identification code and commands, the slave IC can request the master IC to retransmit the chip identification code and commands to restore them. Thus, the master IC and the slave IC can guarantee the accuracy of the chip identification code and commands. After confirming that the chip identification code and commands have been successfully transmitted, the master IC can transmit an address and data to the slave IC. The master IC and the slave IC can verify the accuracy of the address and data using CRC. If an error occurs in the transmission of the address and data, the slave IC recovers the address and data in a timely manner or returns an error signal to the master IC to retransmit the address and data.

[0028] Depending on different design needs, the core circuit (311), debugging circuit (312), core circuit (321), and / or debugging circuit (322) may be implemented in the form of hardware, firmware, software (i.e., programs), or a combination of most of the three above. In the form of hardware, the core circuit (311), debugging circuit (312), core circuit (321), and / or debugging circuit (322) may be implemented as logic circuits on an IC. The related functions of the core circuit (311), debugging circuit (312), core circuit (321), and / or debugging circuit (322) may be implemented in hardware using a hardware description language (e.g., Verilog HDL or VHDL) or other suitable programming language. For example, the related functions of the core circuit (311), the debugging circuit (312), the core circuit (321) and / or the debugging circuit (322) may be implemented in circuits within one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs) and / or various logic blocks, modules and other processing units.

[0029] In the form of software and / or firmware, the related functions of the core circuit (311), the debugging circuit (312), the core circuit (321), and / or the debugging circuit (322) may be implemented as programming code. For example, the core circuit (311), the debugging circuit (312), the core circuit (321), and / or the debugging circuit (322) may be implemented using a general-purpose programming language (e.g., C, C++, or assembly language) or other suitable programming language. The programming code may be written / stored on a "non-transient computer-readable medium." In some embodiments, the non-transient computer-readable medium includes, for example, ROM (Ready Only Memory), semiconductor memory, programmable logic circuits, and / or storage devices. The storage devices include hard disk drives (HDDs), solid-state drives (SSDs), or other storage devices. A central processing unit (CPU), controller, microcontroller, or microprocessor reads and executes programming code from the above non-transient computer-readable medium to achieve the related functions of the core circuit (311), debugging circuit (312), core circuit (321), and / or debugging circuit (322).

[0030] It will be apparent to those skilled in the art that various modifications and variations may be made to the embodiments disclosed above without departing from the scope or spirit of the present disclosure. With the foregoing in mind, the above disclosure is intended to include cases where such modifications and variations fall within the scope of the following claims and their equivalents.

Claims

Claim 1 As a serial peripheral interface (SPI) integrated circuit (IC), the SPI IC comprises: a core circuit; The system includes a debugging circuit coupled to the core circuit, wherein, in response to the SPI IC being a master IC of the SPI architecture, the core circuit generates first command information for a slave IC of the SPI architecture, and the debugging circuit generates first debugging information corresponding to the first command information, and the first command information and the first debugging information are transmitted to the slave IC within the SPI architecture via an SPI channel, and the first command information includes a first data error correction flag; wherein, in response to the SPI IC being a slave IC of the SPI architecture, the debugging circuit receives second command information and second debugging information transmitted by the master IC via the SPI channel, and the debugging circuit verifies the second command information using the second debugging information; wherein, in response to the SPI IC being a slave IC of the SPI architecture and the SPI IC being a target slave circuit selected by the master IC of the SPI architecture, the core circuit receives the second command information transmitted by the master IC under the condition that the second command information is verified by the debugging circuit and is accurate Executing the second command information; in response to the fact that the SPI IC is the master IC of the SPI architecture, the core circuit generates first data information corresponding to the first command information, and the debugging circuit generates third debugging information corresponding to the first data information, and the first data information and the third debugging information are transmitted to the slave IC of the SPI architecture through the SPI channel;In response to the fact that the above SPI IC is a master IC of the SPI architecture, the core circuit is configured to generate a reset flag formed by resetting the first data error correction flag included in the first command information, and the reset flag serves to notify the slave IC of the SPI architecture to disable the error correction operation for the first data information. Claim 2 In claim 1, the SPI IC is a master IC of the SPI architecture, and in response to a slave IC of the SPI architecture notifying that the first command information received by the slave IC is incorrect, the core circuit retransmits the same first command information to the slave IC through the SPI channel. Claim 3 In claim 1, the SPI IC is a slave IC of the SPI architecture, and the second command information is verified by the debugging circuit, and in response to an error, the debugging circuit notifies the master IC of the SPI architecture to retransmit the second command information through the SPI channel. Claim 4 In claim 1, the SPI IC, wherein the first debugging information includes a first error correction code and the second debugging information includes a second error correction code. Claim 5 In claim 1, the first command information includes a first chip identification code and a first command code, and the second command information includes a second chip identification code and a second command code, SPI IC. Claim 6 In paragraph 5, the above second command information further includes a second data error correction flag, an SPI IC. Claim 7 In claim 1, in response to the fact that the SPI IC is a slave IC of the SPI architecture and the SPI IC is a target slave circuit selected by the master IC of the SPI architecture, the debugging circuit receives second data information corresponding to the second command information transmitted by the master IC and fourth debugging information corresponding to the second data information, the debugging circuit verifies the second data information using the fourth debugging information, and the core circuit processes the second data information transmitted by the master IC under the condition that the second data information is verified by the debugging circuit and is accurate. Claim 8 In claim 7, the SPI IC is the master IC of the SPI architecture, and in response to the slave IC of the SPI architecture notifying that the first data information received by the slave IC is incorrect, the core circuit retransmits the same first data information to the slave IC through the SPI channel. Claim 9 In claim 7, the SPI IC is a slave IC of the SPI architecture, and in response to the debugging circuit confirming that one bit of the second data information is incorrect, the debugging circuit recovers the second data information using the fourth debugging information. Claim 10 In claim 9, the SPI IC is a slave IC of the SPI architecture, and in response to the debugging circuit determining that the use of the fourth debugging information is insufficient to recover the second data information that has errors, the debugging circuit notifies the master IC of the SPI architecture to retransmit the second data information through the SPI channel. Claim 11 In claim 7, the SPI IC, wherein the third debugging information includes a first cyclic redundancy check code and the fourth debugging information includes a second cyclic redundancy check code. Claim 12 In claim 7, the SPI IC, wherein the first data information includes a first address field and a first data field, and the second data information includes a second address field and a second data field. Claim 13 In claim 7, the second command information includes a second data error correction flag, the SPI IC is a slave IC of the SPI architecture, the SPI IC is a target slave circuit selected by a master IC of the SPI architecture, and in response to the second data error correction flag being active, the debugging circuit checks the second data information using the fourth debugging information, and the SPI IC is a slave IC of the SPI architecture, the SPI IC is a target slave circuit selected by a master IC of the SPI architecture, and in response to the second data error correction flag being inactive, the debugging circuit does not check the second data information, SPI IC. Claim 14 A method of operation of a Serial Peripheral Interface (SPI) integrated circuit (IC), wherein the method of operation comprises: generating first command information for a slave IC in the SPI architecture in response to the fact that the SPI IC is a master IC of the SPI architecture, generating first debugging information corresponding to the first command information, and transmitting the first command information and the first debugging information to the slave IC of the SPI architecture via an SPI channel, wherein the first command information includes a first data error correction flag; receiving second command information and second debugging information transmitted by the master IC via the SPI channel in response to the fact that the SPI IC is a slave IC of the SPI architecture, and verifying the second command information using the second debugging information; executing the second command information transmitted by the master IC in response to the fact that the SPI IC is a slave IC of the SPI architecture and the SPI IC is a target slave circuit selected by the master IC of the SPI architecture, under the condition that the second command information is verified and accurate; wherein the SPI IC is the A method of operation comprising: generating first data information corresponding to the first command information and generating third debugging information corresponding to the first data information in response to the SPI architecture being a master IC; transmitting the first data information and the third debugging information to a slave IC of the SPI architecture through the SPI channel; generating a reset flag formed by resetting the first data error correction flag included in the first command information in response to the SPI IC being a master IC of the SPI architecture; and notifying the slave IC of the SPI architecture to disable error correction operations for the first data information using the reset flag. Claim 15 A method of operation according to claim 14, wherein the SPI IC is a master IC of the SPI architecture and the slave IC within the SPI architecture is notified that the first command information received by the slave IC is incorrect, and the same first command information is retransmitted to the slave IC through the SPI channel. Claim 16 A method of operation according to claim 14, further comprising the step of the SPI IC being a slave IC of the SPI architecture, the second command information being verified, and in response to an error, notifying the master IC of the SPI architecture to retransmit the second command information through the SPI channel. Claim 17 A method of operation according to claim 14, wherein the first debugging information includes a first error correction code and the second debugging information includes a second error correction code. Claim 18 A method of operation according to claim 14, wherein the first command information includes a first chip identification code and a first command code, and the second command information includes a second chip identification code and a second command code. Claim 19 In paragraph 18, the method of operation further comprising the second command information including a second data error correction flag. Claim 20 A method of operation according to claim 14, further comprising the step of receiving second data information corresponding to second command information transmitted by the master IC and fourth debugging information corresponding to second data information in response to the fact that the SPI IC is a slave IC of the SPI architecture and the SPI IC is a target slave circuit selected by the master IC of the SPI architecture, verifying the second data information using the fourth debugging information, and processing the second data information transmitted by the master IC under the condition that the second data information is verified and accurate. Claim 21 A method of operation according to claim 20, wherein the SPI IC is a master IC of the SPI architecture and the slave IC within the SPI architecture is notified that the first data information received by the slave IC is incorrect, and the same first data information is retransmitted to the slave IC through the SPI channel. Claim 22 A method of operation according to claim 20, further comprising the step of recovering the second data information using the fourth debugging information in response to one bit of the second data information being incorrect, wherein the SPI IC is a slave IC of the SPI architecture. Claim 23 A method of operation according to claim 22, further comprising the step of notifying the master IC of the SPI architecture to retransmit the second data information through the SPI channel in response to the fact that the SPI IC is a slave IC of the SPI architecture and the fourth debugging information is insufficient to recover the second data information that has errors. Claim 24 A method of operation according to claim 20, wherein the third debugging information includes a first cyclic redundancy check code, and the fourth debugging information includes a second cyclic redundancy check code. Claim 25 A method of operation according to claim 20, wherein the first data information includes a first address field and a first data field, and the second data information includes a second address field and a second data field. Claim 26 In claim 20, the second command information includes a second data error correction flag, and the operating method comprises: a step of checking the second data information using the fourth debugging information in response to the second data error correction flag being active, wherein the SPI IC is a slave IC of the SPI architecture and the SPI IC is a target slave circuit selected by the master IC of the SPI architecture; and a step of not checking the second data information in response to the second data error correction flag being inactive.

Images