Semiconductor package

Abstract

According to embodiments of the present invention, a semiconductor package may include a first semiconductor chip; and a second semiconductor chip provided on an upper surface of the first semiconductor chip. The first semiconductor chip may include: a first bonding pad provided on an upper surface of a first semiconductor substrate; and a first through-via provided on a lower surface of the first bonding pad that penetrates the first semiconductor substrate. The second semiconductor chip may include: a second wiring pattern on a lower surface of a second semiconductor substrate; and a second bonding pad provided on a lower surface of the second wiring pattern and connected to the second wiring pattern, wherein the second bonding pad is directly bonded to the first bonding pad, the width of the first through-via may be smaller than the width of the first bonding pad, and the width of the second wiring pattern may be larger than the width of the second bonding pad.

Description

Technology Field

[0001] The present invention relates to a semiconductor package, specifically a semiconductor package comprising directly bonded bonding pads. Background Technology

[0002] A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips on a printed circuit board and electrically connecting them using bonding wires or bumps. With the advancement of the electronics industry, various studies are underway to improve the reliability and durability of semiconductor packages. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor package with improved reliability, durability, and electrical characteristics. means of solving the problem

[0004] According to embodiments of the present invention, a semiconductor package may include a first semiconductor chip; and a second semiconductor chip provided on an upper surface of the first semiconductor chip. The first semiconductor chip may include: a first semiconductor substrate; a first bonding pad provided on an upper surface of the first semiconductor substrate; and a first through-via provided on a lower surface of the first bonding pad that penetrates the first semiconductor substrate. The second semiconductor chip may include: a second semiconductor substrate; a second wiring pattern on a lower surface of the second semiconductor substrate; and a second bonding pad provided on a lower surface of the second wiring pattern and connected to the second wiring pattern, wherein the second bonding pad is directly bonded to the first bonding pad, the width of the first through-via may be smaller than the width of the first bonding pad, and the width of the second wiring pattern may be larger than the width of the second bonding pad.

[0005] According to embodiments of the present invention, a semiconductor package may include a first substrate; a first pad provided on an upper surface of the first substrate; a first conductive pattern in contact with a lower surface of the first pad; and a semiconductor chip provided on the upper surface of the first substrate. The semiconductor chip comprises: a semiconductor substrate; a wiring layer provided on a lower surface of the semiconductor substrate and including a wiring pattern; and a bonding pad connected to a lower surface of the wiring pattern, wherein the bonding pad is directly bonded to the first pad, and the width of the wiring pattern may be greater than the width of the bonding pad and the width of the first conductive pattern may be smaller than the width of the first pad.

[0006] According to embodiments of the present invention, a semiconductor package comprises a first semiconductor chip; and a second semiconductor chip on an upper surface of the first semiconductor chip, wherein the first semiconductor chip comprises: a first semiconductor substrate; first integrated circuits provided on a lower surface of the first semiconductor substrate; a first wiring layer provided on the lower surface of the first semiconductor substrate and comprising a first insulating layer and a first wiring structure; a first back insulating layer provided on an upper surface of the first semiconductor substrate; a first through-via provided within the first semiconductor substrate and electrically connected to the first wiring structure; and a first bonding pad provided on an upper surface of the first through-via and within the first back insulating layer and connected to the first through-via. The second semiconductor chip comprises: a second semiconductor substrate; second integrated circuits provided on a lower surface of the second semiconductor substrate; and a second wiring layer provided on the lower surface of the second semiconductor substrate and comprising a second insulating layer, a second wiring structure, and a second wiring pattern. and includes a second bonding pad in contact with the lower surface of the second wiring pattern, wherein the second bonding pad is directly bonded to the first bonding pad, the second insulating layer is directly bonded to the first rear insulating layer, the width of the lower surface of the second wiring pattern is greater than the width of the lower surface of the second bonding pad, and the width of the upper surface of the first bonding pad may be greater than the width of the first through-via. Effects of the invention

[0007] According to the present invention, a first semiconductor chip may include a first bonding pad on its upper surface. A second semiconductor chip may be provided on the first semiconductor chip. The second semiconductor chip may include a second wiring pattern and a second bonding pad. The second bonding pad may be directly bonded to the first bonding pad. The second wiring pattern may be provided on the upper surface of the second bonding pad. During the direct bonding process of the first bonding pad and the second bonding pad, the second wiring pattern may apply force to the first bonding pad and the second bonding pad. Accordingly, direct bonding between the first and second bonding pads can be formed well. Electrical characteristics between the first semiconductor chip and the second semiconductor chip can be improved, and the reliability of the semiconductor package can be improved. Brief explanation of the drawing

[0008] FIG. 1a is a drawing illustrating a semiconductor package according to embodiments. FIG. 1b is a drawing for explaining a first semiconductor chip according to embodiments. FIG. 1c is a drawing for explaining a second semiconductor chip according to embodiments. FIG. 1d is an enlarged view of area I of FIG. 1a. FIG. 1e is an enlarged view of region II of FIG. 1a. FIG. 1f is an enlarged view of region III of FIG. 1a. Figure 1g is an enlarged view of region IV of Figure 1a. FIG. 2a is a diagram illustrating direct bonding between a first semiconductor chip and a second semiconductor chip according to embodiments. FIG. 2b is a diagram illustrating direct bonding between a first semiconductor chip and a second semiconductor chip according to embodiments. FIG. 2c is a diagram illustrating direct bonding between second semiconductor chips according to embodiments. FIG. 2d is a drawing for explaining direct bonding between a second semiconductor chip and a third semiconductor chip according to embodiments. FIG. 3a is a diagram illustrating direct bonding between a first semiconductor chip and a second semiconductor chip according to embodiments. FIG. 3b is a diagram illustrating direct bonding between second semiconductor chips according to embodiments. FIG. 3c is a diagram illustrating direct bonding between a second semiconductor chip and a third semiconductor chip according to embodiments. FIG. 4a is a diagram illustrating the direct bonding of a first semiconductor chip and a second semiconductor chip according to embodiments. FIG. 4b is a diagram illustrating direct bonding between second semiconductor chips according to embodiments. FIG. 5a is a drawing for illustrating a semiconductor package according to embodiments. Figure 5b is an enlarged view of area V of Figure 5a. FIG. 6a is a drawing for illustrating a semiconductor package according to embodiments. Figure 6b is an enlarged view of the V' area of ​​Figure 6a. FIG. 6c is a diagram illustrating direct bonding between a first semiconductor chip and an interposer substrate according to embodiments. FIG. 7 is a drawing for illustrating a semiconductor package according to embodiments. Specific details for implementing the invention

[0009] In this specification, the same reference numerals throughout the text may refer to the same components. A semiconductor package according to the concept of the present invention and a method for manufacturing the same are described.

[0011] FIG. 1a is a drawing illustrating a semiconductor package according to embodiments.

[0012] Referring to FIG. 1a, the semiconductor package may be a chip stack (10). The chip stack (10) may include a first semiconductor chip (100) and a second semiconductor chip (200).

[0013] The first semiconductor chip (100) may be, for example, a logic chip or a buffer chip. The first semiconductor chip (100) may control the second semiconductor chip (200). The first semiconductor chip (100) may include a first substrate, a first wiring layer (120), first conductive pads (150), first through-vias (170), a first back insulating layer (130), and first bonding pads (155). The first substrate may be a first semiconductor substrate (110). The first wiring layer (120) may include a first insulating layer (121), first wiring structures (123), and first wiring patterns (125). The first through-vias (170) may be first conductive patterns.

[0014] A second semiconductor chip (200) may be provided on a first semiconductor chip (100). The second semiconductor chip (200) may have a different size from the first semiconductor chip (100). For example, the width of the second semiconductor chip (200) may be smaller than the width of the first semiconductor chip (100). The second semiconductor chip (200) may be a different type of semiconductor chip from the first semiconductor chip (100). For example, the second semiconductor chip (200) may be a memory chip. The memory chip may include a High Bandwidth Memory (HBM) chip. The second semiconductor chip (200) may include a plurality of stacked second semiconductor chips (200). For example, the second semiconductor chips (200) may include a stacked second lower semiconductor chip (200A), a second intermediate semiconductor chip (200B), and a second upper semiconductor chip (200C). The second semiconductor chips (200) may have the same size as each other. The second semiconductor chips (200) may be of the same type. Each of the second semiconductor chips (200) may include a second semiconductor substrate (210), a second wiring layer (220), second bonding pads (250), second through-vias (270), a second back insulating layer (230), and second upper bonding pads (255). The second wiring layer (220) may include a second insulating layer (221) and second wiring patterns (225). The number of second semiconductor chips (200) is not limited to that illustrated and can be varied in many ways. For example, the chip stack (10) may include a single second semiconductor chip (200). Hereinafter, for the sake of simplicity of description, a single second semiconductor chip (200) is described.

[0015] The chip stack (10) may further include a third semiconductor chip (300). The third semiconductor chip (300) may be provided on the second semiconductor chip (200). For example, the third semiconductor chip (300) may be provided on the second upper semiconductor chip (200C). The third semiconductor chip (300) may be the uppermost semiconductor chip. The third semiconductor chip (300) may have substantially the same width as the second semiconductor chip (200). The height of the third semiconductor chip (300) may be greater than the height of the second semiconductor chip (200). The third semiconductor chip (300) may be a chip of the same type as the second semiconductor chip (200). For example, the third semiconductor chip (300) may be a High Bandwidth Memory (HBM) chip. The third semiconductor chip (300) may include a third semiconductor substrate (310), a third wiring layer (320), and third bonding pads (350). The third semiconductor chip (300) may not include a third through-via, a third back insulating layer, and a third top bonding pad. The third wiring layer (320) may include a third insulating layer (321) and third wiring patterns (325).

[0016] The chip stack (10) may further include a first molding film (400). The first molding film (400) may be provided on the upper surface of the first semiconductor chip (100). The first molding film (400) may cover the upper surface of the first semiconductor chip (100), the sidewall of the second semiconductor chip (200), and the sidewall of the third semiconductor chip (300). The first molding film (400) may expose the upper surface of the third semiconductor chip (300). The first molding film (400) may include an insulating polymer such as an epoxy-based molding compound.

[0018] Below, the first semiconductor chip will be described in more detail.

[0019] FIG. 1b is a drawing for explaining a first semiconductor chip according to embodiments.

[0020] Referring to FIGS. 1a and 1b, the first semiconductor chip (100) may include a first semiconductor substrate (110), a first wiring layer (120), first conductive pads (150), first integrated circuits (115), first through-vias (170), a first back insulating layer (130), and first bonding pads (155).

[0021] The first semiconductor substrate (110) may include a semiconductor material such as, for example, silicon, germanium, or silicon-germanium. The lower surface of the first semiconductor substrate (110) may be the front surface, and the upper surface of the first semiconductor substrate (110) may be the rear surface. The first integrated circuits (115) may be provided on the lower surface of the first semiconductor substrate (110). The first integrated circuits (115) may include, for example, transistors. The first wiring layer (120) may be provided on the lower surface of the first semiconductor substrate (110). The first wiring layer (120) may include a front-end of line (FEOL) layer and a back-end of line (BEOL) layer. The front-end layer of the first wiring layer (120) may be provided between the first semiconductor substrate (110) and the back-end layer of the first wiring layer (120). A first insulating layer (121) is provided on the lower surface of the first semiconductor substrate (110) and may cover the first integrated circuits (115). The first insulating layer (121) may be multilayer. The first insulating layer (121) may include a silicon-containing insulating material. The silicon-containing insulating material may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and / or tetraethyl orthosilicate. First wiring structures (123) may be provided within the first insulating layer (121). The first wiring structures (123) may be electrically connected to the first integrated circuits (115). Being electrically connected to a semiconductor chip may mean being electrically connected to the integrated circuits of the semiconductor chip. Being electrically connected to two components includes being connected directly or indirectly through other conductive components. The first wiring structures (123) may include first wirings and first vias connected to the first wirings. The first vias may be provided between the first wirings.The first wirings and the first vias may include a metallic material.

[0022] First conductive pads (150) may be provided on the lower surface of the first wiring layer (120). For example, the first conductive pads (150) may be provided within the first wiring layer (120), and the lower surfaces of the first conductive pads (150) may be exposed by the first insulating layer (121). The lower surface of the first semiconductor chip (100) may include the lower surface of the first wiring layer (120) and the lower surfaces of the first conductive pads (150). The first conductive pads (150) may each be provided on the lower surfaces of the first wiring patterns (125).

[0023] Each of the first conductive pads (150) may have inclined side walls. The angle (θ10) between the lower surfaces and the side walls of the first conductive pads (150) may be acute. The angle between the side walls and the upper surfaces of the first conductive pads (150) may be obtuse. The width (W10) of the lower surface of each of the first conductive pads (150) may be greater than the width of the upper surface. The width (W10) of the lower surface of each of the first conductive pads (150) may be 1 μm to 6 μm. The width of each of the first conductive pads (150) may increase from the upper surface to the lower surface.

[0024] Each of the first conductive pads (150) may include a lower metal pad (150M) and a lower barrier pad (150B). The lower barrier pad (150B) may be provided on the lower surface and side walls of the lower metal pad (150M). The lower barrier pad (150B) may include titanium, tantalum, and / or an alloy thereof. The lower metal pad (150M) may include, for example, copper. The coefficient of thermal expansion of the lower metal pad (150M) may be 5 ppm / K to 18 ppm / K.

[0025] First wiring patterns (125) may be provided on the upper surfaces of the first conductive pads (150). The first wiring patterns (125) may be in direct contact with the upper surfaces of the first conductive pads (150). The first wiring patterns (125) may be provided between the first conductive pads (150) and the first wiring structures (123) and may be electrically connected to the first conductive pads (150) and the first wiring structures (123). The first wiring patterns (125) may correspond to the lowest wirings of the first insulating layer (121). For example, the first wiring patterns (125) may correspond to the lowest wirings of the back-end layer. The first wiring patterns (125) may be spaced apart laterally from each other. Any components spaced apart laterally from each other may be spaced apart horizontally from each other. Horizontal may mean parallel to the upper surface of the first semiconductor substrate (110). Each of the first wiring patterns (125) may have an inclined sidewall. For example, the angle (θ1) between the lower surface and the sidewall of each of the first wiring patterns (125) may be obtuse. The angle between the sidewall and the upper surface of each of the first wiring patterns (125) may be acute. The lower surface of each of the first wiring patterns (125) may have a first width (W1). The width of the upper surface of each of the first wiring patterns (125) may be greater than the first width (W1). For example, the width of each of the first wiring patterns (125) may increase from the lower surface to the upper surface. The width of the first wiring patterns (125) may be greater than the widths of the lower surfaces of the first conductive pads (150). For example, the first width (W1) may be larger than the width of the corresponding lower surface of the first conductive pads (150). Accordingly, the lower surface of the first conductive pads (150) may overlap vertically with the first wiring patterns (125). Vertical may mean perpendicular to the upper surface of the first semiconductor substrate (110).

[0026] Each of the first wiring patterns (125) may have a first thickness (T1). The first thickness (T1) may be 0.5 to 1.5 times the thickness (T10) of the first conductive pads (150). The first thickness (T1) may be greater than the thicknesses of the first wirings of the first wiring structures (123). The first thickness (T1) may be, for example, 1 μm to 5 μm.

[0027] Each of the first wiring patterns (125) may include a first barrier layer (125B) and a first metal wiring (125M). The first barrier layer (125B) may be provided on the upper surface of the first metal wiring (125M). The first barrier layer (125B) may include titanium, tantalum, and / or an alloy thereof. The thickness of the first barrier layer (125B) may be smaller than the thickness of the first metal wiring (125M). The first metal wiring (125M) may include aluminum, tin, and / or zinc.

[0028] The first wiring patterns (125) may have a greater coefficient of thermal expansion than the first conductive pads (150). For example, the coefficient of thermal expansion of the first metal wiring (125M) may be greater than the coefficient of thermal expansion of the lower metal pad (150M). The coefficient of thermal expansion of the first metal wiring (125M) may be greater than 18 ppm / K and less than or equal to 50 ppm / K.

[0029] Conductive patterns may be provided within the first semiconductor substrate (110). The conductive patterns may be first through-vias (170). For example, the first through-vias (170) may penetrate the upper and lower surfaces of the first semiconductor substrate (110). The first through-vias (170) may further penetrate the upper surface of the first insulating layer (121). For example, the first insulating layer (121) may comprise a plurality of layers, and the first through-vias (170) may further penetrate at least one of the plurality of layers. The first through-vias (170) may be connected to the first wiring structures (123). The first through-vias (170) may be electrically connected to the first integrated circuits (115) through the first wiring structures (123). The first through vias (170) can be electrically connected to the first wiring patterns (125) and the first conductive pads (150).

[0030] Each of the first through vias (170) may include a first via barrier film (170B) and a first conductive via (170M). The first conductive via (170M) may be disposed on the inner wall of the first via barrier film (170B). The first conductive via (170M) may include a metal such as copper or tungsten. The first via barrier film (170B) may be provided along the side wall of the first conductive via (170M). For example, the first via barrier film (170B) may be provided between the first conductive via (170M) and the first semiconductor substrate (110), between the first conductive via (170M) and the first back insulating layer (130), and between the first conductive via (170M) and the first insulating layer (121). The first via barrier film (170B) may not cover the upper and lower surfaces of the first conductive via (170M). The first via barrier film (170B) may comprise titanium, tantalum, and / or an alloy thereof. The first via barrier film (170B) may prevent the diffusion of material contained in the first conductive via (170M). The first via barrier film (170B) may further function as a seed film in the formation process of the first conductive via (170M).

[0031] The first semiconductor chip (100) may further include a first liner film (117). The first liner film (117) may be provided between the first via barrier film (170B) and the first semiconductor substrate (110). The first liner film (117) may be further extended between the first via barrier film (170B) and the first back insulating layer (130) and between the first via barrier film (170B) and the first insulating layer (121).

[0032] A first rear insulating layer (130) may be provided on the upper surface of the first semiconductor substrate (110). The first rear wiring layer may be a single layer or a multilayer. The first rear insulating layer (130) may include a silicon-based insulating material. First through-vias (170) may be further provided within the lower portion of the first rear insulating layer (130).

[0033] First bonding pads (155) may be provided on the upper surface of the first semiconductor chip (100). The upper surface of the first semiconductor chip (100) may include the upper surfaces of the first bonding pads (155) and the upper surface of the first rear insulating layer (130). The first bonding pads (155) may be provided on the first through-vias (170) and within the first rear insulating layer (130). The first bonding pads (155) may be electrically connected to the first through-vias (170). The first bonding pads (155) may be in direct contact with the first through-vias (170). Accordingly, the manufacturing process of the first semiconductor chip (100) is simplified, and the first semiconductor chip (100) can be miniaturized. The width of the first bonding pads (155) may be greater than the widths of the first through-vias (170). For example, the width (W11) of the upper surface of each of the first bonding pads (155) may be greater than the width (W12) of the upper surface of the first through-via (170) electrically connected thereto. Each of the first bonding pads (155) may have an inclined sidewall. For example, the angle (θ15) between the lower surface and the sidewall of each of the first bonding pads (155) may be obtuse. The angle between the sidewall and the upper surface of each of the first bonding pads (155) may be acute. The width (W11) of the upper surface of each of the first bonding pads (155) may be greater than the width of the lower surface. The width (W11) of the upper surface of each of the first bonding pads (155) may be, for example, 5 μm to 20 μm.

[0034] Each of the first bonding pads (155) may include a first metal pad (155M) and a first barrier pad (155B). The first barrier pad (155B) may cover the bottom surface and side wall of the first metal pad (155M). The first barrier pad (155B) may include titanium, tantalum, and / or an alloy thereof. The first metal pad (155M) may include, for example, copper. As an example, the first metal pad (155M) may include the same metal as the first conductive via (170M), but is not limited thereto. The coefficient of thermal expansion of the first metal pad (155M) may be 5 ppm / K to 18 ppm / K.

[0036] The second semiconductor chip is described below. For the sake of simplicity, a single second semiconductor chip is described.

[0037] FIG. 1c is a drawing for explaining a second semiconductor chip according to embodiments.

[0038] Referring to FIG. 1c, the second semiconductor chip (200) may include a second semiconductor substrate (210), second integrated circuits (215), a second wiring layer (220), second bonding pads (250), second through-vias (270), a second back insulating layer (230), and second upper bonding pads (255). The second semiconductor chip (200) may be the second lower semiconductor chip (200A), the second intermediate semiconductor chip (200B), or the second upper semiconductor chip (200C) described above in FIG. 1a. The second semiconductor substrate (210) may include a semiconductor material such as, for example, silicon, germanium, or silicon-germanium. The lower surface of the second semiconductor substrate (210) may be the front surface, and the upper surface of the second semiconductor substrate (210) may be the back surface. The second integrated circuits (215) may be provided on the lower surface of the second semiconductor substrate (210). The second integrated circuits (215) may include, for example, transistors.

[0039] A second wiring layer (220) may be provided on the lower surface of the second semiconductor substrate (210). The second wiring layer (220) may include a front-end layer and a back-end layer. The front-end layer of the second wiring layer (220) may be provided between the second semiconductor substrate (210) and the back-end layer of the second wiring layer (220). The second wiring layer (220) may include a second insulating layer (221), second wiring patterns (225), and second wiring structures (223). The second insulating layer (221) is provided on the lower surface of the second semiconductor substrate (210) and may cover the second integrated circuits (215). The second insulating layer (221) may be a multilayer. The second insulating layer (221) may include a silicon-containing insulating material. The second wiring structures (223) may be provided within the second insulating layer (221). The second wiring structures (223) may be electrically connected to the second integrated circuits (215). The second wiring structures (223) may include second wires and second vias. The second vias are provided between the second wires and may be connected to the second wires. The second wires and second vias may include a metallic material.

[0040] The second wiring patterns (225) may correspond to the lowest wirings of the second insulation layer (221). For example, the second wiring patterns (225) may correspond to the lowest wirings of the back-end layer. The second wiring patterns (225) may be spaced apart from each other. Each of the second wiring patterns (225) may have a slanted side wall. For example, the angle (θ2) between the bottom surface and the side wall of each of the second wiring patterns (225) may be obtuse. The angle between the side wall and the top surface of each of the second wiring patterns (225) may be acute. The bottom surface of each of the second wiring patterns (225) may have a second width (W2). The width of the top surface of each of the second wiring patterns (225) may be greater than the second width (W2). For example, the width of each of the second wiring patterns (225) may increase from the bottom surface to the top surface. The second thickness (T2) of the second wiring patterns (225) may be relatively thick. For example, the second thickness (T2) may be greater than the thicknesses of the second wirings of the second wiring structures (223). The second thickness (T2) may be, for example, 1 μm to 5 μm.

[0041] Each of the second wiring patterns (225) may include a second barrier layer (225B) and a second metal wiring (225M). The second barrier layer (225B) may be provided on the upper surface of the second metal wiring (225M). The second barrier layer (225B) may include titanium, tantalum, and / or an alloy thereof. The thickness of the second barrier layer (225B) may be smaller than the thickness of the second metal wiring (225M). The second metal wiring (225M) may include aluminum, tin, and / or zinc. The coefficient of thermal expansion of the second metal wiring (225M) may be greater than 18 ppm / K and less than or equal to 50 ppm / K.

[0042] The second bonding pads (250) may be provided on the lower surface of the second wiring layer (220). For example, the second bonding pads (250) may be provided within the second wiring layer (220). The lower surfaces of the second bonding pads (250) may not be covered by the second insulating layer (221). The lower surface of the second semiconductor chip (200) may include the lower surface of the second wiring layer (220) and the lower surfaces of the second bonding pads (250). The lower surface of the second wiring layer (220) may include the lower surface of the second insulating layer (221). The second wiring patterns (225) may be provided on the upper surfaces of the second bonding pads (250). For example, the second wiring patterns (225) may be in direct contact with the upper surfaces of the second bonding pads (250). The second bonding pads (250) can be electrically connected to the second integrated circuits (215) through the second wiring patterns (225) and the second wiring structures (223).

[0043] The angle (θ20) between the lower surfaces and side walls of the second bonding pads (250) may be acute. The angle between the side walls and upper surfaces of the first bonding pads (155) may be obtuse. The width (W20) of the lower surface of each of the second bonding pads (250) may be greater than the width of the upper surface. For example, the width of each of the second bonding pads (250) may increase from the upper surface to the lower surface. The widths of the second bonding pads (250) may be smaller than the second width (W2). For example, the width (W20) of the lower surface of each of the second bonding pads (250) may be smaller than the second width (W2). The width (W20) of the lower surface of each of the second bonding pads (250) may be 1 μm to 6 μm. Accordingly, the lower surface of each of the second bonding pads (250) can be vertically overlapped with the second wiring patterns (225) connected thereto.

[0044] Each of the second bonding pads (250) may include a second metal pad (250M) and a second barrier pad (250B). The second barrier pad (250B) may be provided on the lower surface and side walls of the second metal pad (250M). The second barrier pad (250B) may include titanium, tantalum, and / or an alloy thereof. The second metal pad (250M) may include a metal different from the second metal wiring (225M). The second metal pad (250M) may include, for example, copper.

[0045] The coefficient of thermal expansion of the second wiring patterns (225) may be greater than the coefficient of thermal expansion of the second bonding pads (250). The coefficient of thermal expansion of the second metal wiring (225M) may be greater than the coefficient of thermal expansion of the second metal pad (250M). For example, the coefficient of thermal expansion of the second metal pad (250M) may be 5 ppm / K to 18 ppm / K.

[0046] The second thickness (T2) may be 0.5 to 1.5 times the thickness (T20) of the second bonding pad (250).

[0047] Second through-vias (270) may be provided within the second semiconductor substrate (210). For example, the second through-vias (270) may penetrate the upper and lower surfaces of the second semiconductor substrate (210). The second through-vias (270) may further penetrate the upper surface of the second insulating layer (221). For example, the second insulating layer (221) may comprise a plurality of layers, and the second through-vias (270) may further penetrate at least one of the plurality of layers. The second through-vias (270) may be connected to the second wiring patterns (225) through the second wiring structures (223). Accordingly, the second through-vias (270) may be electrically connected to at least one of the second integrated circuits (215) and the second bonding pads (250).

[0048] Each of the second through-vias (270) may include a second via barrier film (270B) and a second conductive via (270M). The second conductive via (270M) may be disposed on the inner wall of the second via barrier film (270B). The second conductive via (270M) may include a metal such as copper or tungsten. The second via barrier film (270B) may be provided along the side wall of the second conductive via (270M). For example, the second via barrier film (270B) may be provided between the second conductive via (270M) and the second semiconductor substrate (210), between the second conductive via (270M) and the second back insulating layer (230), and between the second conductive via (270M) and the second insulating layer (221). The second via barrier film (270B) may not cover the upper and lower surfaces of the second conductive via (270M). The second via barrier film (270B) may comprise at least one of titanium, tantalum, and alloys thereof. The second via barrier film (270B) may further function as a seed film in the formation process of the second conductive via (270M).

[0049] The second semiconductor chip (200) may further include a second liner film (217). The second liner film (217) may be provided between the second via barrier film (270B) and the second semiconductor substrate (210). The second liner film (217) may be further extended between the second via barrier film (270B) and the second back insulating layer (230) and between the second via barrier film (270B) and the second insulating layer (221). Alternatively, the second liner film (217) may not be provided between the second via barrier film (270B) and the second back insulating layer (230) or between the second via barrier film (270B) and the second insulating layer (221).

[0050] A second rear insulating layer (230) may be provided on the upper surface of the second semiconductor substrate (210). The second rear wiring layer may be a single layer or a multilayer. The second rear insulating layer (230) may include a silicon-based insulating material. The second through-vias (270) may extend further into the second rear insulating layer (230).

[0051] Second upper bonding pads (255) may be provided on the second through-vias (270) and within the second back insulating layer (230). The second upper bonding pads (255) may be electrically connected to the second through-vias (270). If separate conductive components, such as separate wiring, are interposed between the second upper bonding pads (255) and the second through-vias (270), the manufacturing process of the second semiconductor chip (200) may become complicated. According to embodiments, the second upper bonding pads (255) may be in direct contact with the second through-vias (270). Accordingly, the manufacturing process of the second semiconductor chip (200) is simplified, and the second semiconductor chip (200) may be miniaturized. The width of the second upper bonding pads (255) may be greater than the widths of the second through-vias (270). For example, the width (W21) of the upper surface of each of the second bonding pads (250) may be larger than the width (W22) of the upper surface of the second through-via (270) connected thereto. The width (W21) of the upper surface of each of the second bonding pads (250) may be, for example, 5 μm to 20 μm.

[0052] The shape and material of the second upper bonding pads (255) may be the same or similar as described in the example of the first bonding pads (155) of FIG. 1B. For example, each of the second bonding pads (250) may have an inclined side wall. For example, the angle (θ25) between the bottom surface and the side wall of each of the second bonding pads (250) may be obtuse. The angle between the side wall and the top surface of each of the second bonding pads (250) may be acute. The width (W21) of the top surface of each of the second bonding pads (250) may be greater than the width of the bottom surface.

[0053] Each of the second upper bonding pads (255) may include a second metal pad (250M) and a second upper barrier pad (255B). The second upper barrier pad (255B) may cover the lower surface and side wall of the second upper metal pad (255M). The second upper barrier pad (255B) may include titanium, tantalum, and / or an alloy thereof. The second upper metal pad (255M) may include, for example, copper. As an example, the second upper metal pad (255M) may include the same metal as the second conductive via (270M), but is not limited thereto. The coefficient of thermal expansion of the second upper metal pad (255M) may be 5 ppm / K to 18 ppm / K.

[0055] The bonding of the first semiconductor chip and the second semiconductor chip is described below. For the sake of simplicity, a single first bonding pad, a single second bonding pad, and a single second wiring pattern are described.

[0056] FIG. 1d is an enlarged view of region I of FIG. 1a. FIG. 1e is an enlarged view of region II of FIG. 1a.

[0057] Referring to FIGS. 1a and 1d, a second semiconductor chip (200) may be provided on the upper surface of a first semiconductor chip (100). The second semiconductor chip (200) may be connected to the first semiconductor chip (100) by direct bonding. For example, a second lower semiconductor chip (200A) may be directly bonded to the first semiconductor chip (100). Connecting any two chips by direct bonding may include directly bonding conductive components at mutually facing positions of the two chips and directly bonding insulating components at mutually facing positions of the two chips. Direct bonding of insulating components may include the formation of chemical bonds between the insulating components. Direct bonding of any two chips may include hybrid bonding. For example, the second bonding pad (250) of the second sub-semiconductor chip (200A) can be directly bonded to the first bonding pad (155) of the first semiconductor chip (100). During the direct bonding process, metal atoms within the first bonding pad (155) can diffuse into the second bonding pad (250), and metal atoms within the second bonding pad (250) can diffuse into the first bonding pad (155). Therefore, the interface between the first bonding pad (155) and the second bonding pad (250) may not be distinguishable.

[0058] The second insulating layer (221) of the second lower semiconductor chip (200A) may be in direct contact with the first rear insulating layer (130) of the first semiconductor chip (100) and connected by direct bonding. For example, a chemical bond may be provided between the second insulating layer (221) and the first rear insulating layer (130). The chemical bond may be a covalent bond. The interface between the first rear insulating layer (130) and the second insulating layer (221) may not be distinct.

[0059] Direct bonding the first semiconductor chip (100) and the second lower semiconductor chip (200A) may include applying heat and pressure to the first semiconductor chip (100) and the second lower semiconductor chip (200A). The second wiring pattern (225) may have a greater coefficient of thermal expansion than the first and second bonding pads (155, 250). For example, the coefficient of thermal expansion of the second metal wiring (225M) may be greater than the coefficient of thermal expansion of the second metal pad (250M) and the coefficient of thermal expansion of the first metal pad (155M). During the direct bonding process, the second wiring pattern (225) may apply force to the second bonding pad (250) due to the difference in the coefficients of thermal expansion. The force may include pressure. Since the coefficient of thermal expansion of the second metal wiring (225M) is greater than 18 ppm / K, the second wiring pattern (225) can apply sufficient force to the first bonding pad (155) and the second bonding pad (250) during the direct bonding. Accordingly, the second bonding pad (250) can be bonded more easily and firmly with the first bonding pad (155).

[0060] The second wiring pattern (225) may overlap with the lower surface of the second bonding pad (250). The lower surface of the second bonding pad (250) may be the bonding surface of the first bonding pad (155) and the second bonding pad (250). Accordingly, direct bonding between the first bonding pad (155) and the second bonding pad (250) may be better.

[0061] Since the second thickness (T2) of the second wiring pattern (225) is at least 0.5 times the thickness (T20) of the second bonding pad (250), the second wiring pattern (225) can apply sufficient force to the second bonding pad (250) during the direct bonding process. Accordingly, the first bonding pad (155) and the second bonding pad (250) can be bonded more firmly.

[0062] If the second thickness (T2) is greater than 1.5 times the thickness (T20) of the second bonding pad (250), the second insulating layer (221) may peel off from the second wiring pattern (225) due to the difference in the coefficient of thermal expansion between the second wiring pattern (225) and the second insulating layer (221). In this case, defects such as a void may occur between the second insulating layer (221) and the second wiring pattern (225). According to the embodiments, since the thickness of the second wiring pattern (225) is greater than 1.5 times the thickness of the first bonding pad (155), the second insulating layer (221) can cover the second wiring pattern (225) well. Accordingly, the phenomenon of the second insulating layer (221) peeling off from the second wiring pattern (225) can be prevented. The width of the first bonding pad (155) may be greater than the width of the second bonding pad (250). For example, the width (W11) of the upper surface of the first bonding pad (155) may be greater than the width (W20) of the lower surface of the second bonding pad (250). Accordingly, even if a process error occurs during the placement process of the second semiconductor chip (200), the lower surface of the second bonding pad (250) can make good contact with the first bonding pad (155). For example, the lower surface of the second bonding pad (250) may completely overlap with the first bonding pad (155). The first bonding pad (155) may have a first upper surface and a second upper surface. The first upper surface of the first bonding pad (155) contacts the second bonding pad (250) and can be connected to the second bonding pad (250) by direct bonding. The second upper surface of the first bonding pad (155) is spaced apart from the second bonding pad (250) and can come into contact with the first insulating layer (121).

[0063] The thickness (T11) of the first bonding pad (155) may be smaller than the thickness (T21) of the second bonding pad (250).

[0064] Referring to FIG. 1a and FIG. 1e, a plurality of second wiring patterns (225) may be horizontally spaced apart from each other. The second insulating layer (221) may have a first lower surface (221u1) that overlaps vertically with the second wiring patterns (225) and a second lower surface (221u2) that does not overlap vertically with the second wiring patterns (225). During the direct bonding process of the first semiconductor chip (100) and the second lower semiconductor chip (200A), a force may be applied between the first lower surface (221u1) of the second insulating layer (221) and the first rear insulating layer (130) by the second wiring patterns (225). The force may be pressure. Accordingly, a chemical bond may be easily formed between the first lower surface (221u1) of the second insulating layer (221) and the upper surface of the second rear insulating layer (230). The first lower surface (221u1) of the second insulating layer (221) can be directly bonded well with the second rear insulating layer (230). During the direct bonding process, the force applied by the second wiring patterns (225) may be difficult to transmit to the second lower surface (221u2) of the second insulating layer (221). Direct bonding may not be formed between the second lower surface (221u2) of the second insulating layer (221) and the first rear insulating layer (130). For example, the second lower surface (221u2) of the second insulating layer (221) may be spaced apart from the upper surface of the first rear insulating layer (130). A void or air gap may be provided between the second lower surface (221u2) of the second insulating layer (221) and the first rear insulating layer (130). As another example, the second lower surface (221u2) of the second insulating layer (221) may be in contact with the upper surface of the first rear insulating layer (130), but may not be chemically bonded with the upper surface of the first rear insulating layer (130).

[0066] Below, the bonding between the second semiconductor chips is described.

[0067] FIG. 1f is an enlarged view of region III of FIG. 1a.

[0068] Referring to FIGS. 1a and 1f, a plurality of second semiconductor chips (200) may be vertically stacked on a first semiconductor chip (100). The second semiconductor chips (200) may be connected to each other by direct bonding. For example, a second lower semiconductor chip (200A) and a second intermediate semiconductor chip (200B) may be connected to each other by direct bonding. Each of the second lower semiconductor chip (200A) and the second intermediate semiconductor chip (200B) may be substantially the same as described above in the second semiconductor chip (200) of FIG. 1b. The second upper bonding pad (255) of the second lower semiconductor chip (200A) and the second bonding pad (250) of the second intermediate semiconductor chip (200B) may be in direct contact with each other and connected to each other by direct bonding. The interface between the second upper bonding pad (255) of the second lower semiconductor chip (200A) and the second bonding pad (250) of the second intermediate semiconductor chip (200B) may not be distinguishable.

[0069] Since the second thickness (T2) of the second wiring pattern (225) of the second intermediate semiconductor chip (200B) is at least 0.5 times the thickness (T21) of the second upper bonding pad (255) of the second intermediate semiconductor chip (200B), the second upper bonding pad (255) of the second lower semiconductor chip (200A) and the second bonding pad (250) of the second intermediate semiconductor chip (200B) can be directly bonded well.

[0070] The thickness (T21) of the second upper bonding pad (255) of the second lower semiconductor chip (200A) may be smaller than the thickness (T20) of the second bonding pad (250) of the second intermediate semiconductor chip (200B). The width of the second upper bonding pad (255) of the second lower semiconductor chip (200A) may be larger than the width of the second bonding pad (250) of the second intermediate semiconductor chip (200B). Specifically, the width (W21) of the upper surface of the second upper bonding pad (255) of the second lower semiconductor chip (200A) may be larger than the width (W20) of the lower surface of the second bonding pad (250) of the second intermediate semiconductor chip (200B). Even if a process error occurs during the placement process of the second intermediate semiconductor chip (200B), the second bonding pad (250) of the second intermediate semiconductor chip (200B) can make good contact with the second upper bonding pad (255) of the second lower semiconductor chip (200A). For example, the width (W21) of the upper surface of the second upper bonding pad (255) of the second lower semiconductor chip (200A) may be greater than 1 time and less than or equal to 2 times the width (W20) of the lower surface of the second bonding pad (250) of the second intermediate semiconductor chip (200B).

[0071] The second rear insulating layer (230) of the second lower semiconductor chip (200A) and the second insulating layer (221) of the second intermediate semiconductor chip (200B) can be connected to each other by direct bonding. A chemical bond may be provided between the second rear insulating layer (230) of the second lower semiconductor chip (200A) and the second insulating layer (221) of the second intermediate semiconductor chip (200B). The interface between the second rear insulating layer (230) of the second lower semiconductor chip (200A) and the second insulating layer (221) of the second intermediate semiconductor chip (200B) may not be distinguishable.

[0072] Referring to FIG. 1a, a plurality of second wiring patterns (225) may be horizontally spaced apart from each other. The second insulating layer (221) of the second intermediate semiconductor chip (200B) may have a first lower surface and a second lower surface. The first lower surface and the second lower surface of the second insulating layer (221) of the second intermediate semiconductor chip (200B) may be substantially the same as those previously described in the example of the first lower surface and the second lower surface (221u2) of the second insulating layer (221) of the second lower semiconductor chip (200A) of FIG. 1e. For example, the first lower surface of the second insulating layer (221) of the second intermediate semiconductor chip (200B) may overlap vertically with the second wiring patterns (225) of the second intermediate semiconductor chip (200B) and may be well directly bonded to the upper surface of the second rear insulating layer (230) of the second lower semiconductor chip (200A). The second lower surface of the second insulating layer (221) of the second intermediate semiconductor chip (200B) may not vertically overlap with the second wiring patterns (225) of the second intermediate semiconductor chip (200B). The second lower surface of the second insulating layer (221) of the second intermediate semiconductor chip (200B) may be spaced apart from the second rear insulating layer (230) of the second lower semiconductor chip (200A). As another example, the second lower surface of the second insulating layer (221) of the second intermediate semiconductor chip (200B) may be in contact with the second rear insulating layer (230) of the second lower semiconductor chip (200A), but may not be chemically bonded.

[0073] The second upper semiconductor chip (200C) may be connected to the second intermediate semiconductor chip (200B) by direct bonding. The direct bonding between the second upper semiconductor chip (200C) and the second intermediate semiconductor chip (200B) may be substantially the same as described in the example of direct bonding between the second intermediate semiconductor chip (200B) and the second lower semiconductor chip (200A) of FIG. 1f. For example, the second upper bonding pad (255) of the second intermediate semiconductor chip (200B) and the second bonding pad (250) of the second upper semiconductor chip (200C) may be in direct contact with each other and connected by direct bonding. The interface between the second upper bonding pad (255) of the second intermediate semiconductor chip (200B) and the second bonding pad (250) of the second upper semiconductor chip (200C) may not be distinct. The second rear insulating layer (230) of the second intermediate semiconductor chip (200B) and the second insulating layer (221) of the second upper semiconductor chip (200C) can be connected to each other by direct bonding. A chemical bond may be provided between the second rear insulating layer (230) of the second intermediate semiconductor chip (200B) and the second insulating layer (221) of the second upper semiconductor chip (200C). The interface between the second rear insulating layer (230) of the second intermediate semiconductor chip (200B) and the second insulating layer (221) of the second upper semiconductor chip (200C) may not be distinguishable.

[0075] Hereinafter, the bonding between the third semiconductor chip (300) and the second semiconductor chip (200) and the third semiconductor chip (300) will be described.

[0076] FIG. 1g is an enlarged view of region IV of FIG. 1a. For simplification, a single second semiconductor chip will be described below.

[0077] Referring to FIG. 1a and FIG. 1g, a third semiconductor chip (300) may be provided on a second semiconductor chip (200). The third semiconductor chip (300) may include a third semiconductor substrate (310), third integrated circuits (315), a third wiring layer (320), and a third bonding pad (350). The upper surface of the third semiconductor substrate (310) may be the upper surface of the third semiconductor chip (300). The third semiconductor substrate (310) may include, for example, silicon, germanium, or silicon-germanium. The third integrated circuits (315) may be provided on the lower surface of the third semiconductor substrate (310). The third integrated circuits (315) may include transistors. The third wiring layer (320) may be provided on the lower surface of the third semiconductor substrate (310). The third wiring layer (320) may include a front-end layer and a back-end layer. The third wiring layer (320) may include a third insulating layer (321), a plurality of third wiring patterns (325), and third wiring structures (323). The third insulating layer (321) is provided on the lower surface of the third semiconductor substrate (310) and may cover the third integrated circuits (315). The third insulating layer (321) may be multilayer. The third insulating layer (321) may include a silicon-containing insulating material. The third wiring structures (323) may be provided within the third insulating layer (321). The third wiring structures (323) may be electrically connected to the third integrated circuits (315). The third wiring structures (323) may include third wirings and third vias connected to the third wirings. The third wirings and third vias may include metallic material.

[0078] The third wiring patterns (325) may correspond to the lowest wirings of the third insulation layer (321). For example, the third wiring patterns (325) may correspond to the lowest wirings of the back-end layer. Each of the third wiring patterns (325) may have a slanted sidewall. For example, the angle between the bottom surface and the sidewall of each of the third wiring patterns (325) may be obtuse. The angle between the sidewall and the top surface of each of the third wiring patterns (325) may be acute. The bottom surface of each of the third wiring patterns (325) may have a third width (W3). The width of the top surface of each of the third wiring patterns (325) may be greater than the third width (W3). For example, the width of the third wiring patterns (325) may increase from the bottom surface to the top surface. The third thickness (T3) of the third wiring pattern (325) may be greater than the thicknesses of the third wirings of the third wiring structures (323). For example, the third thickness (T3) may be 1 μm to 5 μm.

[0079] Each of the third wiring patterns (325) may include a third barrier layer (325B) and a third metal wiring (325M). The third barrier layer (325B) may be provided on the upper surface of the third metal wiring (325M). The third barrier layer (325B) may include titanium, tantalum, and / or an alloy thereof. The thickness of the third barrier layer (325B) may be smaller than the thickness of the third metal wiring (325M). The third metal wiring (325M) may include aluminum, tin, and / or zinc.

[0080] Third bonding pads (350) may be provided on the lower surface of the third wiring layer (320). For example, the third bonding pads (350) may be provided within the third wiring layer (320), and the lower surfaces of the third bonding pads (350) may not be covered by the third insulating layer (321). The lower surface of the third semiconductor chip (300) may include the lower surface of the third wiring layer (320) and the lower surfaces of the third bonding pads (350). The upper surfaces of the third bonding pads (350) may be in direct contact with the third wiring patterns (325). The third bonding pads (350) may be electrically connected to the third integrated circuits (315) through the third wiring structures (323). The angle between the lower surfaces and the side walls of the third bonding pads (350) may be an acute angle. The angle between the side walls and the top surfaces of the first bonding pads (155) may be obtuse. The width (W30) of the bottom surface of each of the third bonding pads (350) may be greater than the width of the top surface. The width (W30) of the bottom surface of each of the third bonding pads (350) may be 1 μm to 6 μm.

[0081] Each of the third bonding pads (350) may include a third metal pad (350M) and a third barrier pad (350B). The third barrier pad (350B) may be provided on the lower surface and side walls of the third metal pad (350M). The third barrier pad (350B) may include titanium, tantalum, and / or an alloy thereof. The third metal pad (350M) may include a metal different from the third metal wiring (325M). The third metal pad (350M) may include, for example, copper.

[0082] The third wiring patterns (325) may have a greater coefficient of thermal expansion than the third bonding pads (350). The third metal wiring (325M) may have a greater coefficient of thermal expansion than the third metal pad (350M). For example, the coefficient of thermal expansion of the third metal wiring (325M) may be greater than 18 ppm / K and less than or equal to 50 ppm / K. The coefficient of thermal expansion of the third metal pad (350M) may be between 5 ppm / K and 18 ppm / K. Hereinafter, for convenience of explanation, a single second upper bonding pad (255), a single third bonding pad (350), and a single third wiring pattern (325) will be described.

[0083] The third semiconductor chip (300) can be connected to the second upper semiconductor chip (200C) by direct bonding. For example, the second upper bonding pad (255) of the second upper semiconductor chip (200C) and the third bonding pad (350) of the third semiconductor chip (300) can be connected to each other by direct bonding. The interface between the second upper bonding pad (255) of the second upper semiconductor chip (200C) and the third bonding pad (350) of the third semiconductor chip (300) may not be distinguishable.

[0084] The third thickness (T3) may be 0.5 to 1.5 times the thickness (T30) of the third bonding pad (350). Since the third thickness (T3) is 0.5 times or more the thickness (T30) of the third bonding pad (350) of the third semiconductor chip (300), the third wiring pattern (325) can apply sufficient force to the third bonding pad (350) and the second bonding pad (250) of the second upper semiconductor chip (200C) during the direct bonding process. Since the third thickness (T3) is 1.5 times or less the thickness of the third bonding pad (350) of the third semiconductor chip (300), the third insulating layer (321) may not be peeled off from the third wiring pattern (325).

[0085] The third width (W3) may be larger than the width (W30) of the lower surface of the third bonding pad (350). Accordingly, the lower surface of the third bonding pad (350) may be vertically overlapped with the corresponding third wiring pattern (325).

[0086] The width of the second upper bonding pad (255) of the second upper semiconductor chip (200C) may be equal to or greater than the width of the third bonding pad (350). For example, the width (W21) of the upper surface of the second upper bonding pad (255) of the second upper semiconductor chip (200C) may be greater than the width (W30) of the lower surface of the third bonding pad (350). Accordingly, in the placement process of the third semiconductor chip (300), the third bonding pad (350) can be well connected to the second upper bonding pad (255) of the second upper semiconductor chip (200C).

[0087] The width (W21) of the upper surface of the second upper bonding pad (255) of the second upper semiconductor chip (200C) may be greater than 1 time and less than or equal to 2 times the width (W30) of the lower surface of the third bonding pad (350).

[0088] The thickness (T31) of the second upper bonding pad (255) of the second upper semiconductor chip (200C) may be smaller than the thickness (T31) of the third bonding pad (350).

[0089] The second rear insulating layer (230) of the second upper semiconductor chip (200C) and the third insulating layer (321) of the third semiconductor chip (300) can be connected to each other by direct bonding. A chemical bond can be provided between the second rear insulating layer (230) of the second upper semiconductor chip (200C) and the third insulating layer (321) of the third semiconductor chip (300).

[0090] As shown in FIG. 1a, a plurality of third wiring patterns (325) may be horizontally spaced apart from each other. The third insulating layer (321) may have a first lower surface (221u1) and a second lower surface. The first lower surface (221u1) and the second lower surface of the third insulating layer (321) may be similar to those previously described in the example of the first lower surface (221u1) and the second lower surface of the first insulating layer (121) in FIG. 1e. For example, the first lower surface (221u1) of the third insulating layer (321) may overlap vertically with the third wiring patterns (325) and may be well directly bonded to the second rear insulating layer (230) of the second upper semiconductor chip (200C). The second lower surface of the third insulating layer (321) may not overlap vertically with the third wiring patterns (325). The third lower surface of the third semiconductor chip (300) may be spaced apart from the second rear insulating layer (230) of the second upper semiconductor chip (200C). As another example, the third lower surface may be in contact with the second rear insulating layer (230) of the second upper semiconductor chip (200C) but may not be chemically bonded.

[0092] FIG. 2a is a drawing for explaining direct bonding between a first semiconductor chip and a second semiconductor chip according to embodiments, and corresponds to an enlarged view of Region I of FIG. 1a. FIG. 2b is a drawing for explaining direct bonding between a first semiconductor chip and a second semiconductor chip according to embodiments, and corresponds to an enlarged view of Region I of FIG. 1a. Hereinafter, in the description of FIG. 2a and FIG. 2b, FIG. 1a is referred to together with FIG. 1a, and a single first through-via is described.

[0093] Referring to FIGS. 2a and 2b, the second semiconductor chip (200) can be connected to the first semiconductor chip (100) by direct bonding. For example, the second bonding pad (250) of the second lower semiconductor chip (200A) can be directly bonded to the first bonding pad (155) of the first semiconductor chip (100). However, the second bonding pad (250) may protrude into the second wiring pattern (225). For example, the upper surface of the second bonding pad (250) may be provided at a higher level than the lower surface of the second wiring pattern (225). At this time, the lower surface of the second wiring pattern (225) may be a surface covered by the second insulating layer (221).

[0094] The first through-via (170) may protrude into the first bonding pad (155). For example, the upper surface of the first through-via (170) may be provided at a level that is more swollen than the bottom surface of the first bonding pad (155). The bottom surface of the first bonding pad (155) may be provided on the first rear insulating layer (130).

[0095] Referring to FIG. 2b, the second wiring pattern (225) may further include a second lower barrier layer (225BB) in addition to the second metal wiring (225M) and the second barrier layer (225B). The second lower barrier layer (225BB) may be provided on the lower surface of the second metal wiring (225M). The thickness of the second lower barrier layer (225BB) may be smaller than the thickness of the second metal wiring (225M). The second lower barrier layer (225BB) may include titanium, tantalum, and / or an alloy thereof.

[0097] FIG. 2c is a drawing for explaining direct bonding between second semiconductor chips according to embodiments, and corresponds to an enlarged view of region III of FIG. 1a. Hereinafter, in the description of FIG. 2c, FIG. 1a is referenced together with FIG. 1a, and a number of second through-vias are described.

[0098] Referring to FIG. 2c, the second bonding pad (250) of the second intermediate semiconductor chip (200B) can be directly bonded to the second upper bonding pad (255) of the second lower semiconductor chip (200A). However, the second bonding pad (250) of the second intermediate semiconductor chip (200B) may protrude into the second wiring pattern (225) of the second intermediate semiconductor chip (200B). For example, the upper surface of the second bonding pad (250) may be provided at a higher level than the lower surface of the second wiring pattern (225).

[0099] The second through-via (270) of the second lower semiconductor chip (200A) may protrude into the second upper bonding pad (255) of the second lower semiconductor chip (200A). For example, the upper surface of the second through-via (270) may be provided at a level that is more swollen than the bottom surface of the second upper bonding pad (255).

[0100] Although not illustrated, the second wiring pattern (225) of the second intermediate semiconductor chip (200B) may further include a second lower barrier layer (225BB in FIG. 2b) in addition to the second metal wiring (225M) and the second barrier layer (225B).

[0102] FIG. 2d is a drawing for explaining direct bonding between a second semiconductor chip and a third semiconductor chip according to embodiments, and corresponds to an enlarged view of region IV of FIG. 1a.

[0103] Referring to FIG. 2d, the third bonding pad (350) of the third semiconductor chip (300) can be directly bonded to the second upper bonding pad (255) of the second upper semiconductor chip (200C). The third bonding pad (350) of the third semiconductor chip (300) can protrude into the third wiring pattern (325). For example, the upper surface of the third bonding pad (350) can be provided at a higher level than the lower surface of the third wiring pattern (325). At this time, the lower surface of the third wiring pattern (325) may be a surface covered by the second insulating layer (221).

[0104] The second through-via (270) of the second intermediate semiconductor chip (200B) may protrude into the second upper bonding pad (255) of the second intermediate semiconductor chip (200B). For example, the upper surface of the second through-via (270) may be provided at a level that is more swollen than the bottom surface of the second upper bonding pad (255).

[0105] Although not illustrated, the third wiring pattern (325) may further include a third lower barrier layer in addition to the third metal wiring (325M) and the third barrier layer (325B). The third lower barrier layer may be provided on the lower surface of the third wiring pattern (325). The third lower barrier layer may be substantially the same as described in the examples of the second lower barrier layer (225BB) of FIG. 2B.

[0107] FIG. 3a is a drawing for explaining direct bonding between a first semiconductor chip and a second semiconductor chip according to embodiments, and corresponds to an enlarged view of Region I of FIG. 1a. Hereinafter, FIG. 1a will be referenced together with FIG. 3a in the description.

[0108] Referring to FIG. 3a, the second semiconductor chip (200) may be connected to the first semiconductor chip (100) by direct bonding. For example, the second lower semiconductor chip (200A) may be directly bonded to the first semiconductor chip (100). The direct bonding between the second lower semiconductor chip (200A) and the first semiconductor chip (100) may be substantially the same as described in the examples of FIG. 1d and FIG. 1e above. For example, the second bonding pad (250) of the second lower semiconductor chip (200A) may be directly bonded to the first bonding pad (155) of the first semiconductor chip (100). However, the width (W20) of the lower surface of the second bonding pad (250) may be substantially the same as the width (W11) of the upper surface of the first bonding pad (155). The thickness (T21) of the second bonding pad (250) may be the same as or different from the thickness (T11) of the first bonding pad (155).

[0110] FIG. 3b is a drawing for explaining direct bonding between second semiconductor chips according to embodiments, and corresponds to an enlarged view of region III of FIG. 1a. FIG. 1a will be referenced together with FIG. 3b in the following description.

[0111] Referring to FIG. 3b, the second intermediate semiconductor chip (200B) may be connected to the second lower semiconductor chip (200A) by direct bonding. The direct bonding between the second lower semiconductor chip (200A) and the second intermediate semiconductor chip (200B) may be the same or similar as described in the example of FIG. 1f above. For example, the second bonding pad (250) of the second intermediate semiconductor chip (200B) may be directly bonded to the second upper bonding pad (255) of the second lower semiconductor chip (200A). However, the width (W20) of the lower surface of the second bonding pad (250) of the second intermediate semiconductor chip (200B) may be substantially the same as the width (W21) of the upper surface of the second upper bonding pad (255) of the second lower semiconductor chip (200A).

[0112] Referring again to FIG. 1a, the direct bonding between the second upper semiconductor chip (200C) and the second intermediate semiconductor chip (200B) may be similar to the direct bonding between the second intermediate semiconductor chip (200B) and the second lower semiconductor chip (200A) described in the example of FIG. 3b. For example, unlike as shown in the example of FIG. 3a, the width of the lower surface of the second bonding pad (250) of the second upper semiconductor chip (200C) may be substantially the same as the width of the upper surface of the second upper bonding pad (255) of the second intermediate semiconductor chip (200B).

[0114] FIG. 3c is a drawing for explaining direct bonding between a second semiconductor chip and a third semiconductor chip according to embodiments, and corresponds to an enlarged view of region IV of FIG. 1a. FIG. 1a will be referenced together with FIG. 3c in the following description.

[0115] Referring to FIG. 3c, the third semiconductor chip (300) may be connected to the second upper semiconductor chip (200C) by direct bonding. The direct bonding between the second upper semiconductor chip (200C) and the third semiconductor chip (300) may be the same or similar as described in the example of FIG. 1f above. For example, the third bonding pad (350) of the third semiconductor chip (300) may be directly bonded to the second upper bonding pad (255) of the second upper semiconductor chip (200C). However, the width (W30) of the lower surface of the third bonding pad (350) of the third semiconductor chip (300) may be substantially the same as the width (W21) of the upper surface of the second upper bonding pad (255) of the second upper semiconductor chip (200C).

[0117] FIG. 4a is a drawing for explaining the direct bonding of a first semiconductor chip and a second semiconductor chip according to embodiments, and corresponds to an enlarged view of Region I of FIG. 1a. FIG. 1a will be referenced together with FIG. 4a in the following description.

[0118] Referring to FIG. 4a, the second semiconductor chip (200) can be connected to the first semiconductor chip (100) by direct bonding. For example, the second lower semiconductor chip (200A) can be directly bonded to the first semiconductor chip (100). The direct bonding between the second lower semiconductor chip (200A) and the first semiconductor chip (100) may be substantially the same as described in the example of FIG. 3a above. For example, the lower surface of the second bonding pad (250) of the second lower semiconductor chip (200A) may be directly bonded to the upper surface of the first bonding pad (155) of the first semiconductor chip (100). The width (W20) of the lower surface of the second bonding pad (250) may be substantially the same as the width (W11) of the upper surface of the first bonding pad (155). However, the central axis of the second bonding pad (250) may not be vertically aligned with the central axis of the first bonding pad (155). A portion of the lower surface of the second bonding pad (250) may further contact the first rear insulating layer (130). A portion of the upper surface of the first bonding pad (155) may further contact the second insulating layer (221).

[0120] FIG. 4b is a drawing for explaining direct bonding between second semiconductor chips according to embodiments, and corresponds to an enlarged view of region III of FIG. 1a. FIG. 1a will be referenced together with FIG. 3b in the following description.

[0121] Referring to FIG. 4b, the second intermediate semiconductor chip (200B) may be connected to the second lower semiconductor chip (200A) by direct bonding. The direct bonding between the second lower semiconductor chip (200A) and the second intermediate semiconductor chip (200B) may be the same or similar as described in the example of FIG. 3b above. For example, the second bonding pad (250) of the second intermediate semiconductor chip (200B) may be directly bonded to the second upper bonding pad (255) of the second lower semiconductor chip (200A). The width (W20) of the lower surface of the second bonding pad (250) of the second intermediate semiconductor chip (200B) may be substantially the same as the width (W21) of the upper surface of the second upper bonding pad (255) of the second lower semiconductor chip (200A). However, the central axis of the second bonding pad (250) of the second intermediate semiconductor chip (200B) may not be vertically aligned with the central axis of the second upper bonding pad (255) of the second lower semiconductor chip (200A). A portion of the lower surface of the second bonding pad (250) of the second intermediate semiconductor chip (200B) may further contact the first rear insulating layer (130) of the second lower semiconductor chip (200A). A portion of the upper surface of the second upper bonding pad (255) of the second lower semiconductor chip (200A) may further contact the second insulating layer (221).

[0122] The direct bonding between the second intermediate semiconductor chip (200B) and the second upper semiconductor chip (200C) shown in FIG. 1a can be modified as described in the example of direct bonding between the second lower semiconductor chip (200A) and the second intermediate semiconductor chip (200B) in FIG. 4b.

[0123] The direct bonding between the second upper semiconductor chip (200C) and the third semiconductor chip (300) shown in FIG. 1a can be modified as described in the example of direct bonding between the second lower semiconductor chip (200A) and the second intermediate semiconductor chip (200B) in FIG. 4b.

[0125] FIG. 5a is a drawing for illustrating a semiconductor package according to embodiments. FIG. 5b is an enlarged view of region V of FIG. 5a.

[0126] Referring to FIGS. 5a and 5b, the semiconductor package may be a chip stack (10A). The chip stack (10A) may include a first semiconductor chip (100), a second semiconductor chip (200), a third semiconductor chip (300), and a first molding film (400). The first semiconductor chip (100), the second semiconductor chip (200), the third semiconductor chip (300), and the first molding film (400) may be substantially the same as those described above in the examples of FIGS. 1a through 1g. For example, the first semiconductor chip (100) may include a first semiconductor substrate (110), a first wiring layer (120), first conductive pads (150), first integrated circuits (115), first through-vias (170), a first back insulating layer (130), and first bonding pads (155). The first wiring layer (120) may include a first insulating layer (121) and first wiring structures (123).

[0127] However, the first wiring layer (120) may not include the first wiring patterns (125) described in the examples of FIG. 1a and FIG. 1b. The first conductive pads (150) may be directly connected to the first wiring structures (123).

[0129] FIG. 6a is a drawing for illustrating a semiconductor package according to embodiments. FIG. 6b is an enlarged view of region V' of FIG. 6a.

[0130] FIGS. 6A and 6B show that the semiconductor package (1) may include a substrate, solder balls (500), a chip stack (10), and a fourth semiconductor chip (600). The substrate may be an interposer substrate (900). The interposer substrate (900) may include an interposer die (910), metal vias (970), an interposer wiring layer (920), and bonding pads. The bonding pads may be interposer bonding pads (950). The interposer substrate (900) may not include integrated circuits such as transistors. For example, integrated circuits may not be provided on the interposer die (910). The interposer die (910) may be a first substrate. The interposer die (910) may include a semiconductor die such as a silicon die, a germanium die, or a silicon-germanium die.

[0131] Metal vias (970) may be provided within the interposer die (910). The metal vias (970) may be spaced apart from each other. The metal vias (970) may penetrate the upper and lower surfaces of the interposer die (910).

[0132] An interposer wiring layer (920) may be provided on the upper surface of an interposer die (910). The interposer wiring layer (920) may include a dielectric layer (921) and conductive structures (923). The dielectric layer (921) may include a plurality of layers. The dielectric layer (921) may include a silicon-based insulating material. Conductive structures (923) may be provided within the dielectric layer (921). The conductive structures (923) may include wiring portions and via portions. The via portions may be connected to the wiring portions. The conductive structures (923) may include a metal such as, for example, copper, tungsten, titanium, and / or an alloy thereof.

[0133] Interposer bonding pads (950) may be provided on the upper surface of an interposer substrate (900). For example, the interposer bonding pads (950) may be provided on conductive structures (923) and may be connected to the conductive structures (923). The conductive structures (923) may include a first conductive structure and a second conductive structure. The second conductive structure may be electrically isolated from the first conductive structure. Any two interposer bonding pads (950) may be electrically connected to each other through the first conductive structure. The other of the interposer bonding pads (950) may be electrically connected to any one of the metal vias (970) through the second conductive structure. Being electrically connected to the interposer substrate (900) may mean being electrically connected to at least one of the conductive structures (923).

[0134] A chip stack (10) may be disposed on the upper surface of an interposer substrate (900). The chip stack (10) may be substantially the same as the chip stack (10) described in the example of FIG. 1a. A plurality of chip stacks (10) may be provided, and the chip stacks (10) may be spaced apart from each other. The number of chip stacks (10) may vary. For example, a semiconductor package (1) may include a single chip stack (10). A chip stack (10) may include a first semiconductor chip (100), a second semiconductor chip (200), a third semiconductor chip (300), and a first molding film (400).

[0135] The chip stack (10) can be connected to the interposer substrate (900) by direct bonding. For example, the first semiconductor chip (100) can be connected to the interposer substrate (900) by direct bonding. The first conductive pads (150) and the interposer bonding pads (950) can be connected to each other by direct bonding. The interface between the first conductive pads (150) and the interposer bonding pads (950) may not be distinct. The coefficient of thermal expansion of the first wiring patterns (125) may be greater than the coefficient of thermal expansion of the first conductive pads (150) and the coefficient of thermal expansion of the interposer bonding pads (950). Since the first wiring patterns (125) are provided on the first conductive pads (150), direct bonding between the first conductive pads (150) and the interposer bonding pads (950) can be formed well. Hereinafter, for the sake of simplicity of explanation, a single first conductive pad (150), a single interposer bonding pad (950), and a single first wiring pad are described.

[0136] As shown in FIG. 1b, the first thickness (T1) is at least 0.5 times the thickness (T10) of the first conductive pad (150), so that the first wiring pattern (125) can apply sufficient force to the first conductive pad (150) during the direct bonding process. Since the first thickness (T1) is 1.5 times or less the thickness (T10) of the first conductive pad (150), the first insulating layer (121) may not be peeled off from the first wiring patterns (125). The first width (W1) may be larger than the width (W10) of the lower surface of the first conductive pad (150). Accordingly, the lower surface of the first conductive pad (150) may overlap vertically with the third wiring pattern (325).

[0137] The width of the interposer bonding pad (950) may be greater than the width of the first conductive pad (150). For example, the width of the upper surface of the interposer bonding pad (950) may be greater than the width (W10) of the lower surface of the first conductive pad (150). Accordingly, in the process of placing the chip stack (10), the first conductive pad (150) can be well connected to the interposer bonding pad (950). The thickness (T10) of the first conductive pad (150) may be smaller than the thickness (T40) of the interposer bonding pad (950).

[0138] The dielectric layer (921) and the first insulating layer (121) can be connected to each other by direct bonding. A chemical bond can be provided between the dielectric layer (921) and the first insulating layer (121).

[0139] The bonding pads (950) may include a fourth barrier pad (950B) and a fourth metal pad (950M). The fourth barrier pad (950B) may cover the lower surface and side wall of the fourth metal pad (950M). The fourth barrier pad (950B) may include tantalum and / or an alloy thereof. The fourth metal pad (950M) may include, for example, copper. The coefficient of thermal expansion of the fourth metal pad (950M) may be 5 ppm / K to 18 ppm / K.

[0140] Each of the conductive structures (923) may further include a conductive pattern (922). The conductive pattern (922) may come into contact with the lower surface of an interposer bonding pad (950) electrically connected thereto. The width of the conductive pattern (922) may be smaller than the width of the interposer bonding pad (950) electrically connected thereto.

[0141] As shown in FIG. 6a, solder balls (500) may be provided on the lower surface of an interposer substrate (900) and electrically connected to metal vias (970). The solder balls (500) may be spaced apart from each other and electrically separated. The solder balls (500) may include a solder material such as, for example, tin, silver, zinc, and / or an alloy thereof. The semiconductor package (1) may further include solder pads (905). Solder pads (905) may be interposed between the solder balls (500) and the metal vias (970). The solder pads (905) may include a material different from the solder balls. The solder pads (905) may include a metal such as, for example, copper, gold, or nickel.

[0142] The chip stack (10) can be electrically connected to the solder balls (500) and the fourth semiconductor chip (600) through the interposer substrate (900).

[0143] A fourth semiconductor chip (600) may be mounted on an interposer substrate (900). The fourth semiconductor chip (600) may be spaced apart from the chip stack (10). For example, the fourth semiconductor chip (600) may be placed between a plurality of chip stacks (10). The fourth semiconductor chip (600) may be a different type of semiconductor chip from the first to third semiconductor chips (100, 200, 300). For example, the fourth semiconductor chip (600) may include a logic chip or a system-on-chip (SOC). As an example, the fourth semiconductor chip (600) may be a logic chip that performs a different function from the first semiconductor chip (100). The fourth semiconductor chip (600) may be an ASIC chip or an application processor (AP) chip. The fourth semiconductor chip (600) may include a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU).

[0144] The fourth semiconductor chip (600) may include a fourth insulating layer (621), a fourth wiring pattern (615), and a fourth bonding pad (650). The fourth insulating layer (621), the fourth wiring pattern (615), and the fourth bonding pad (650) may each be similar to the first insulating layer (121), the first wiring pattern (125), and the first bonding pad (155) of FIG. 1b and FIG. 6b. For example, the lower surface of the fourth semiconductor chip (600) may include the lower surface of the fourth insulating layer (621) and the lower surface of the fourth bonding pad (650). The fourth insulating layer (621) may be provided on the lower surface of the fourth semiconductor chip (600). The fourth insulating layer (621) may include a silicon-based insulating material. The fourth bonding pad (650) may be provided on the lower surface of the fourth semiconductor chip (600). The fourth bonding pad (650) may be a chip pad. The fourth bonding pad (650) may include copper, for example.

[0145] The fourth wiring pattern (615) may be provided within the fourth insulating layer (621). The fourth wiring pattern (615) may be provided on the fourth bonding pad (650) and may be in contact with the fourth bonding pad (650). The fourth bonding pad (650) may be electrically connected to the integrated circuits of the fourth semiconductor chip (600) through the fourth wiring pattern (615). The thickness of the fourth wiring pattern (615) may be 0.5 to 1.5 times the thickness of the fourth bonding pad (650). The width of the fourth wiring pattern (615) may be greater than the width of the fourth bonding pad (650). The coefficient of thermal expansion of the fourth wiring pattern (615) may be greater than the coefficient of thermal expansion of the fourth bonding pad (650). For example, the coefficient of thermal expansion of the fourth wiring pattern (615) may be greater than 18 ppm / K and less than or equal to 50 ppm / K. The coefficient of thermal expansion of the second metal pad (250M) may be between 5 ppm / K and 18 ppm / K.

[0146] The fourth semiconductor chip (600) can be connected to the interposer substrate (900) by direct bonding. For example, the fourth bonding pad (650) and the corresponding interposer bonding pad (950) can be connected to each other by direct bonding. The interface between the fourth bonding pad (650) and the interposer bonding pad (950) may not be distinct. Since the fourth wiring pattern (615) is provided on the fourth bonding pad (650), direct bonding between the fourth bonding pad (650) and the interposer bonding pad (950) can be formed well. The dielectric layer (921) and the fourth insulating layer (621) can be connected to each other by direct bonding. A chemical bond can be provided between the dielectric layer (921) and the fourth insulating layer (621).

[0147] The fourth semiconductor chip (600) can be electrically connected to the solder balls (500) through the interposer substrate (900).

[0148] The semiconductor package (1) may further include a second molding film (420). The second molding film (420) is provided on an interposer substrate (900) and may cover the sidewalls of the chip stack (10) and the sidewalls of the fourth semiconductor chip (600). The second molding film (420) may expose the upper surface of the chip stack (10) and the upper surface of the fourth semiconductor chip (600). The second molding film (420) may include an insulating polymer such as an epoxy-based molding compound.

[0150] FIG. 6c is a drawing for explaining direct bonding between a first semiconductor chip and an interposer substrate according to embodiments, and corresponds to an enlarged view of region V' of FIG. 6a. Hereinafter, FIG. 6a will be referenced together with FIG. 6c in the description.

[0151] Referring to FIG. 6c, the first conductive pad (150) and the interposer bonding pad (950) can be connected to each other by direct bonding. However, the first conductive pad (150) may protrude into the first wiring pattern (125). The upper surface of the first conductive pad (150) may be provided at a higher level than the lower surface of the first wiring pattern (125). At this time, the lower surface of the first wiring pattern (125) may be covered by the first insulating layer (121).

[0153] FIG. 7 is a drawing for illustrating a semiconductor package according to embodiments. Hereinafter, content that overlaps with what has been previously described is omitted.

[0154] Referring to FIG. 7, the semiconductor package (1A) may include an interposer substrate (900), solder balls (500), a chip stack (10A), and a fourth semiconductor chip (600). The chip stack (10A) may be the same as described in the examples of FIG. 5a and 5b. For example, the first semiconductor chip (100) may not include a first wiring pattern (125).

[0155] The semiconductor package (1A) may further include first bumps (810), second bumps (820), and an underfill film (430). The first bumps (810) may be interposed between an interposer substrate (900) and a first semiconductor chip (100). The first bumps (810) may be connected to interposer bonding pads (950) and first bonding pads (155). The first bumps (810) may include at least one of solder balls and metal pillars.

[0156] The second bumps (820) may be interposed between the interposer substrate (900) and the fourth semiconductor chip (600). The fourth semiconductor chip (600) may include a plurality of fourth bonding pads (650). The second bumps (820) may be connected to the fourth bonding pads (650) and the corresponding interposer bonding pads (950). The second bumps (820) may include at least one of solder balls and metal pillars.

[0157] The underfill film (430) is interposed between the interposer substrate (900) and the fourth semiconductor chip (600) to seal the first bumps (810). The underfill film (430) may be further extended into the gap region between the interposer substrate (900) and the first semiconductor chip (100) to seal the second bumps (820). The underfill film (430) may include an insulating polymer.

[0159] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments and may be used in various other combinations, modifications, and environments without departing from the essence of the invention.

Claims

Claim 1 A first semiconductor chip; and a second semiconductor chip provided on an upper surface of the first semiconductor chip, wherein the first semiconductor chip comprises: a first semiconductor substrate; a first bonding pad provided on an upper surface of the first semiconductor substrate; and a first through-via penetrating the first semiconductor substrate and provided on a lower surface of the first bonding pad, and the second semiconductor chip comprises: a second semiconductor substrate; and a second wiring pattern on a lower surface of the second semiconductor substrate. A semiconductor package comprising a second bonding pad provided on the lower surface of the second wiring pattern and connected to the second wiring pattern, wherein the second bonding pad is directly bonded to the first bonding pad, the width of the first through-via is smaller than the width of the first bonding pad, the width of the second wiring pattern is larger than the width of the second bonding pad, the second wiring pattern has a width that increases from its lower surface to its upper surface, the second bonding pad has a width that increases from its upper surface to its lower surface, and the coefficient of thermal expansion of the second wiring pattern is greater than the coefficient of thermal expansion of the second bonding pad. Claim 2 A semiconductor package according to claim 1, wherein the second wiring pattern contacts the upper surface of the second bonding pad and the first through-via contacts the lower surface of the first bonding pad. Claim 3 In claim 1, the first bonding pad comprises: a first upper surface in contact with the second bonding pad; and a second upper surface spaced apart from the second bonding pad, in a semiconductor package. Claim 4 A semiconductor package according to claim 1, wherein the width of the first bonding pad is greater than the width of the second bonding pad, and the thickness of the first bonding pad is smaller than the thickness of the second bonding pad. Claim 5 A semiconductor package according to claim 1, wherein the angle between the lower surface and the side wall of the second bonding pad is acute, and the angle between the lower surface and the side wall of the second wiring pattern is obtuse. Claim 6 A semiconductor package according to claim 1, wherein the thickness of the second wiring pattern is 0.5 to 1.5 times the thickness of the second bonding pad. Claim 7 delete Claim 8 A semiconductor package according to claim 1, wherein the second wiring pattern comprises: metal wiring; and a barrier pattern on the upper surface of the metal wiring, and the second bonding pad comprises: a metal pad; and a barrier pad covering the lower surface and sidewall of the metal pad, wherein the metal wiring comprises a metal element different from that of the metal pad. Claim 9 In claim 8, the metal pad comprises copper, and the metal wiring comprises aluminum, tin, and / or zinc in a semiconductor package. Claim 10 A semiconductor package according to claim 1, further comprising a third semiconductor chip provided on an upper surface of the second semiconductor chip, wherein the second semiconductor chip comprises: a second through-via penetrating the second semiconductor substrate; and a second upper bonding pad on an upper surface of the second through-via, and the third semiconductor chip comprises: a third semiconductor substrate; a third wiring pattern on a lower surface of the third semiconductor substrate; and a third bonding pad provided on a lower surface of the third wiring pattern and connected to the third wiring pattern, wherein the third bonding pad is directly bonded to the second upper bonding pad, and the width of the third wiring pattern is greater than the width of the third bonding pad. Claim 11 In claim 10, the width of the second through-via is smaller than the width of the second upper bonding pad in the semiconductor package. Claim 12 A semiconductor package comprising: a first substrate; a first pad provided on an upper surface of the first substrate; a first conductive pattern in contact with a lower surface of the first pad; and a semiconductor chip provided on the upper surface of the first substrate, wherein the semiconductor chip comprises: a semiconductor substrate; a wiring layer provided on a lower surface of the semiconductor substrate and including a wiring pattern; and a bonding pad connected to a lower surface of the wiring pattern, wherein the bonding pad is directly bonded to the first pad, the width of the wiring pattern is greater than the width of the bonding pad and the width of the first conductive pattern is smaller than the width of the first pad, the coefficient of thermal expansion of the wiring pattern is greater than the coefficient of thermal expansion of the bonding pad, the wiring pattern has a width that increases from its lower surface to its upper surface, and the bonding pad has a width that increases from its upper surface to its lower surface. Claim 13 In claim 12, the wiring layer further comprises an insulating layer, and the upper surface of the first pad comprises: a first upper surface in contact with the bonding pad; and a second upper surface in contact with the insulating layer, forming a semiconductor package. Claim 14 A semiconductor package according to claim 12, wherein the angle between the lower surface and the side wall of the bonding pad is acute, and the angle between the lower surface and the side wall of the wiring pattern is obtuse. Claim 15 In claim 12, the first substrate comprises an interposer die, and the first pad comprises an interposer pad, forming a semiconductor package. Claim 16 A semiconductor package according to claim 12, further comprising integrated circuits provided on the lower surface of the first substrate, wherein the first conductive pattern comprises a first through-via penetrating the first substrate. Claim 17 A first semiconductor chip; and a second semiconductor chip on an upper surface of the first semiconductor chip, wherein the first semiconductor chip comprises: a first semiconductor substrate; first integrated circuits provided on a lower surface of the first semiconductor substrate; a first wiring layer provided on the lower surface of the first semiconductor substrate and comprising a first insulating layer and a first wiring structure; a first back insulating layer provided on an upper surface of the first semiconductor substrate; a first through-via provided within the first semiconductor substrate and electrically connected to the first wiring structure; and a first bonding pad provided on an upper surface of the first through-via and within the first back insulating layer and connected to the first through-via, wherein the second semiconductor chip comprises: a second semiconductor substrate; second integrated circuits provided on a lower surface of the second semiconductor substrate; and a second wiring layer provided on the lower surface of the second semiconductor substrate and comprising a second insulating layer, a second wiring structure, and a second wiring pattern. A semiconductor package comprising a second bonding pad in contact with the lower surface of the second wiring pattern, wherein the second bonding pad is directly bonded to the first bonding pad, the second insulating layer is directly bonded to the first rear insulating layer, the width of the lower surface of the second wiring pattern is greater than the width of the lower surface of the second bonding pad, the width of the upper surface of the first bonding pad is greater than the width of the first through-via, the width of the lower surface of the second bonding pad is greater than the width of the upper surface of the second bonding pad, the width of the lower surface of the second wiring pattern is smaller than the width of the upper surface of the second wiring pattern, and the second wiring pattern has a coefficient of thermal expansion greater than that of the second bonding pad. Claim 18 A semiconductor package according to claim 17, wherein the width of the upper surface of the first bonding pad is greater than the width of the lower surface of the second bonding pad, and the thickness of the first bonding pad is smaller than the thickness of the second bonding pad. Claim 19 delete Claim 20 A semiconductor package according to claim 17, wherein the thickness of the second wiring pattern is 0.5 to 1.5 times the thickness of the second bonding pad.

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