Semiconductor package including underfill and method of forming the same

Abstract

A semiconductor package includes a first semiconductor chip on a substructure. A first underfill is disposed between the first semiconductor chip and the substructure. The first underfill includes a first portion adjacent to the center of the first semiconductor chip and a second portion adjacent to the edge of the first semiconductor chip. The second portion has a higher degree of hardening than the first portion. A plurality of internal connection terminals are disposed between the first semiconductor chip and the substructure. The plurality of internal connection terminals extend within the first underfill.

Description

Technology Field

[0001] The invention relates to a semiconductor package having an underfill and a method for forming the same. Background Technology

[0002] In response to the demand for high integration of semiconductor packages, technologies for mounting multiple semiconductor chips within a single package are being attempted. Underfill may be applied between the multiple semiconductor chips. The underfill may protrude outward from the multiple semiconductor chips. Excessive lateral expansion of the underfill causes various problems. The problem to be solved

[0003] The objective according to embodiments of the technical concept of the present invention is to provide a semiconductor package capable of controlling excessive lateral expansion of the underfill and a method for forming the same. means of solving the problem

[0004] A semiconductor package according to embodiments of the technical concept of the present invention comprises a first semiconductor chip on a substructure. A first underfill is disposed between the first semiconductor chip and the substructure. The first underfill includes a first portion adjacent to the center of the first semiconductor chip and a second portion adjacent to the edge of the first semiconductor chip. The second portion has a higher degree of hardening than the first portion. A plurality of internal connection terminals are provided disposed between the first semiconductor chip and the substructure and extending within the first underfill.

[0005] A method for forming a semiconductor package according to embodiments of the technical concept of the present invention comprises forming a plurality of internal connection terminals and a preliminary underfill covering the plurality of internal connection terminals on a first semiconductor chip. The first semiconductor chip is laminated on a substructure. The preliminary underfill is bonded between the first semiconductor chip and the substructure. The preliminary underfill is cured using a laser bonding process to form a first underfill. While curing the preliminary underfill to form the first underfill, the plurality of internal connection terminals are reflowed.

[0006] A semiconductor package according to embodiments of the technical concept of the present invention comprises a plurality of semiconductor chips stacked sequentially on a substructure. A plurality of underfills are disposed between the plurality of semiconductor chips and the substructure and between the plurality of semiconductor chips. Each of the plurality of underfills includes a first portion adjacent to the center of one adjacent semiconductor chip and a second portion adjacent to the edge of one adjacent semiconductor chip. The second portion has a higher degree of curing than the first portion. A plurality of internal connection terminals are provided, disposed between the plurality of semiconductor chips and the substructure and between the plurality of semiconductor chips, and extending within the plurality of underfills. Effects of the invention

[0007] According to embodiments of the technical concept of the present invention, a plurality of semiconductor chips are stacked on a substructure. A plurality of underfills are disposed between the substructure and the plurality of semiconductor chips. A first underfill between the substructure and a first semiconductor chip includes a first portion adjacent to the center of the first semiconductor chip and a second portion adjacent to the edge of the first semiconductor chip. The second portion has a higher degree of curing than the first portion. The second portion may serve to prevent excessive lateral expansion of the first underfill. A semiconductor package capable of controlling the lateral expansion of the underfill and a method for forming the same may be provided. Brief explanation of the drawing

[0008] FIG. 1 is a cross-sectional view illustrating semiconductor packages according to embodiments of the technical concept of the present invention. Figure 2 is a partial view showing a part of Figure 1. FIGS. 3 to 13 are cross-sectional views for illustrating semiconductor packages according to embodiments of the technical concept of the present invention. FIGS. 14 to 30 are cross-sectional and schematic diagrams for explaining methods of forming a semiconductor package according to embodiments of the technical concept of the present invention. Specific details for implementing the invention

[0009] FIG. 1 is a cross-sectional view illustrating semiconductor packages according to embodiments of the technical concept of the present invention, and FIG. 2 is a partial view showing a part of FIG. 1.

[0010] Referring to FIGS. 1 and 2, semiconductor packages according to embodiments of the technical concept of the present invention may include a lower structure (11), a plurality of external connection terminals (13), a first semiconductor chip (21), a second semiconductor chip (22), a third semiconductor chip (23), an upper semiconductor chip (28), a first underfill (35), a plurality of second underfills (39), a plurality of internal connection terminals (42), and a sealing material (47).

[0011] Each of the first semiconductor chip (21), the second semiconductor chip (22), and the third semiconductor chip (23) may include a plurality of through electrodes (56), a plurality of first pads (57), and a plurality of second pads (58). The upper semiconductor chip (28) may include the plurality of first pads (57). The lower structure (11) may include the plurality of through electrodes (56), the plurality of first pads (57), and the plurality of second pads (58). The first underfill (35) may include a first portion (35C) and a second portion (35F).

[0012] The lower structure (11) may include a buffer chip, a logic chip, a memory chip, an interposer, a printed circuit board, a ceramic substrate, or a combination thereof. In one embodiment, the lower structure (11) may include internal wiring such as the plurality of through electrodes (56). The plurality of first pads (57) may be disposed adjacent to the lower surface of the lower structure (11). The plurality of second pads (58) may be disposed adjacent to the upper surface of the lower structure (11). The plurality of first pads (57) and the plurality of second pads (58) may be connected to the plurality of through electrodes (56).

[0013] The plurality of external connection terminals (13) may be disposed on the lower surface of the lower structure (11). The plurality of external connection terminals (13) may be in contact with the plurality of first pads (57). Each of the plurality of external connection terminals (13) may include Sn, Ag, Cu, Al, AlN, Au, Be, Bi, Co, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, TaN, Te, Ti, TiN, W, WN, Zn, Zr, or a combination thereof. Each of the plurality of external connection terminals (13) may include a conductive bump, a conductive ball, a conductive pin, a conductive lead, a conductive pillar, or a combination thereof. For example, each of the plurality of external connection terminals (13) may include UBM (Under Bump Metal) and a conductive bump. The plurality of external connection terminals (13) may be omitted.

[0014] The first semiconductor chip (21) may be disposed on the lower structure (11). The first underfill (35) may be adhered between the lower structure (11) and the first semiconductor chip (21). The plurality of internal connection terminals (42) penetrating the first underfill (35) may be disposed between the lower structure (11) and the first semiconductor chip (21).

[0015] The first semiconductor chip (21) may include volatile memory, non-volatile memory, a microprocessor, a buffer chip, an application processor, a logic chip, or a combination thereof. In one embodiment, the first semiconductor chip (21) may include Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Flash Memory, EEPROM, Phase-change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), or a combination thereof. For example, the first semiconductor chip (21) may include volatile memory such as DRAM.

[0016] The plurality of through electrodes (56) may extend within the first semiconductor chip (21). The plurality of through electrodes (56) may penetrate the first semiconductor chip (21). The plurality of first pads (57) may be disposed on the lower surface of the first semiconductor chip (21). The plurality of first pads (57) may be in contact with the plurality of through electrodes (56). The plurality of second pads (58) may be disposed on the upper surface of the first semiconductor chip (21). The plurality of second pads (58) may be in contact with the plurality of through electrodes (56). The first semiconductor chip (21) may include a plurality of active / passive elements (not shown). The plurality of first pads (57) may be connected to a plurality of active / passive elements (not shown) within the first semiconductor chip (21). Each of the plurality of through electrodes (56), the plurality of first pads (57), and the plurality of second pads (58) may include Cu, Al, Ag, AlN, Au, Be, Bi, Co, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Sn, Ta, TaN, Te, Ti, TiN, W, WN, Zn, Zr, or a combination thereof.

[0017] The first underfill (35) may comprise a non-conductive film (NCF) having laser-sensitive additives. In one embodiment, the content of the laser-sensitive additives in the first underfill (35) may be 0.01 wt% to 10 wt%. The laser-sensitive additives may comprise polyimide (PI), such as polybenzoxazole (PBO) or photosensitive polyimides (PSPI), benzocyclobutene (BCB), or a combination thereof.

[0018] In one embodiment, the first underfill (35) may comprise a filler, a first epoxy, a second epoxy, a first polymer, a second polymer, a flux, and the laser-sensitive additive. The filler may comprise SiO, TiO, AlO, SiC, BN, or a combination thereof. For example, the filler may comprise SiO2. The first epoxy may comprise a liquid-type material for controlling adhesive properties. The first epoxy may comprise bisphenol A, phenol novolak, bisphenol F, or a combination thereof. The second epoxy may comprise a solid-type material for controlling adhesive properties. The second epoxy may comprise naphthalene-based epoxy, cresol novolak epoxy, bisphenol A, or a combination thereof. The first polymer may comprise a hardener. The first polymer may include novolak phenol resin, polyamine, polyamide, or a combination thereof. The second polymer may include a thermoplastic resin for film formation. The second polymer may include phenoxy resin, PVB resin, or a combination thereof.

[0019] The second portion (35F) of the first underfill (35) may have a relatively higher degree of curing than the first portion (35C). In one embodiment, the first portion (35C) of the first underfill (35) may have a degree of curing of 10% to 35%. The second portion (35F) of the first underfill (35) may have a degree of curing of 50% to 80%. The degree of curing of the first underfill (35) can be verified using a measuring device such as FT-IR (Fourier-Transform Infrared Spectroscopy). The second portion (35F) of the first underfill (35) may have a relatively lower flowability than the first portion (35C).

[0020] The second portion (35F) of the first underfill (35) may be in continuity with the outside of the first portion (35C). The first portion (35C) of the first underfill (35) may be limited between the first semiconductor chip (21) and the substructure (11). The first portion (35C) of the first underfill (35) may be aligned adjacent to the center of the first semiconductor chip (21). The second portion (35F) of the first underfill (35) may be aligned adjacent to the edge of the first semiconductor chip (21). The second portion (35F) of the first underfill (35) may extend between the first semiconductor chip (21) and the substructure (11). The second portion (35F) of the first underfill (35) may protrude outside the first semiconductor chip (21). The second portion (35F) of the first underfill (35) may extend onto the sides of the first semiconductor chip (21). The second portion (35F) of the first underfill (35) may come into contact with the sides of the first semiconductor chip (21).

[0021] The plurality of internal connection terminals (42) may penetrate the first underfill (35) and contact the plurality of first pads (57) of the first semiconductor chip (21). The plurality of internal connection terminals (42) may penetrate the first underfill (35) and contact the plurality of second pads (58) of the lower structure (11). Each of the plurality of internal connection terminals (42) may include Sn, Ag, Cu, Al, AlN, Au, Be, Bi, Co, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, TaN, Te, Ti, TiN, W, WN, Zn, Zr, or a combination thereof. Each of the plurality of internal connection terminals (42) may include a conductive bump, a conductive ball, a conductive pin, a conductive lead, a conductive pillar, or a combination thereof. For example, each of the plurality of internal connection terminals (42) may include a conductive bump.

[0022] The second semiconductor chip (22) and the third semiconductor chip (23) may be vertically stacked in sequence on the first semiconductor chip (21). The upper semiconductor chip (28) may be vertically stacked on the third semiconductor chip (23). One or more other semiconductor chips may be additionally stacked between the third semiconductor chip (23) and the upper semiconductor chip (28). The plurality of second underfills (39) may be disposed between the first semiconductor chip (21), the second semiconductor chip (22), the third semiconductor chip (23), and the upper semiconductor chip (28). The plurality of internal connection terminals (42) penetrating the plurality of second underfills (39) may be disposed between the first semiconductor chip (21), the second semiconductor chip (22), the third semiconductor chip (23), and the upper semiconductor chip (28).

[0023] Each of the second semiconductor chip (22) and the third semiconductor chip (23) may include a configuration similar to the first semiconductor chip (21). The upper semiconductor chip (28) may include a configuration similar to the first semiconductor chip (21). A plurality of first pads (57) may be disposed on the lower surface of the upper semiconductor chip (28). The upper semiconductor chip (28) may have a different thickness from the first semiconductor chip (21). The upper semiconductor chip (28) may be thicker than the first semiconductor chip (21). In one embodiment, each of the first semiconductor chip (21), the second semiconductor chip (22), the third semiconductor chip (23), and the upper semiconductor chip (28) may include a volatile memory such as DRAM.

[0024] Each of the plurality of second underfills (39) may comprise a non-conductive film (NCF) having a laser-sensitive additive or a non-conductive film (NCF) not having a laser-sensitive additive. In one embodiment, each of the plurality of second underfills (39) may comprise the filler, the first epoxy, the second epoxy, the first polymer, the second polymer, the flux, and the laser-sensitive additive. In one embodiment, each of the plurality of second underfills (39) may comprise the filler, the first epoxy, the second epoxy, the first polymer, the second polymer, and the flux.

[0025] Each of the plurality of second underfills (39) may have a substantially uniform degree of curing. In each of the plurality of second underfills (39), the degree of curing of the portion adjacent to the center of a corresponding one of the second semiconductor chip (22), the third semiconductor chip (23), and the upper semiconductor chip (28) and the degree of curing of the portion adjacent to the edge may be substantially the same. Each of the plurality of second underfills (39) may protrude to the outside of the second semiconductor chip (22), the third semiconductor chip (23), and the upper semiconductor chip (28). Each of the plurality of second underfills (39) may be in contact with the side of the first semiconductor chip (21), the second semiconductor chip (22), the third semiconductor chip (23), and the upper semiconductor chip (28).

[0026] The encapsulating material (47) covering the first semiconductor chip (21), the second semiconductor chip (22), the third semiconductor chip (23), the upper semiconductor chip (28), the first underfill (35), and the plurality of second underfills (39) may be disposed on the lower structure (11). The encapsulating material (47) may include an epoxy molding compound (EMC).

[0027] According to embodiments of the technical concept of the present invention, the second part (35F), having a relatively higher degree of hardening than the first part (35C), can serve to prevent excessive lateral expansion of the first underfill (35). The size and shape of the first underfill (35) and the plurality of second underfills (39) can be controlled.

[0028] FIGS. 3 to 13 are cross-sectional views for illustrating semiconductor packages according to embodiments of the technical concept of the present invention.

[0029] Referring to FIG. 3, semiconductor packages according to embodiments of the technical concept of the present invention may include a lower structure (11), a plurality of external connection terminals (13), a first semiconductor chip (21), a second semiconductor chip (22), a third semiconductor chip (23), an upper semiconductor chip (28), a plurality of first underfills (35), a plurality of internal connection terminals (42), and a sealing material (47).

[0030] The plurality of first underfills (35) may be disposed between the lower structure (11), the first semiconductor chip (21), the second semiconductor chip (22), the third semiconductor chip (23), and the upper semiconductor chip (28). Each of the plurality of first underfills (35) may comprise a non-conductive film (NCF) having a laser-sensitive additive. Each of the plurality of first underfills (35) may comprise a first portion (35C) and a second portion (35F) in continuity with the outside of the first portion (35C). The second portion (35F) may have a relatively higher degree of curing than the first portion (35C).

[0031] Referring to FIG. 4, a plurality of first underfills (35) can be in contact with each other.

[0032] Referring to FIG. 5, a first underfill (35) and a plurality of second underfills (39) can be in contact with each other. The first underfill (35) can be in contact with one of the adjacent second underfills (39).

[0033] Referring to FIG. 6, the upper semiconductor chip (28) may include a configuration similar to the first semiconductor chip (21). For example, the upper semiconductor chip (28) may have substantially the same thickness as the first semiconductor chip (21). The upper semiconductor chip (28) may include a plurality of through electrodes (56), a plurality of first pads (57), and a plurality of second pads (58).

[0034] Referring to FIG. 7, semiconductor packages according to embodiments of the technical concept of the present invention may include a lower structure (11), a plurality of external connection terminals (13), a first sub-package (121), a second sub-package (122), a third sub-package (123), an upper sub-package (128), a plurality of first underfills (35), a plurality of internal connection terminals (42), and a sealing material (47).

[0035] The first sub-package (121), the second sub-package (122), the third sub-package (123), and the upper sub-package (128) may be vertically stacked in sequence on the lower structure (11). The plurality of first underfills (35) may be disposed between the lower structure (11), the first sub-package (121), the second sub-package (122), the third sub-package (123), and the upper sub-package (128).

[0036] Each of the first sub-package (121), the second sub-package (122), the third sub-package (123), and the upper sub-package (128) may include a semiconductor chip (125), a plurality of chip pads (127), an inner encapsulation material (147), a plurality of redistribution layers (155), a plurality of through electrodes (156), a plurality of first pads (157), and a plurality of second pads (158).

[0037] The semiconductor chip (125) may include a configuration similar to the first semiconductor chip (21 in FIG. 1). The chip pad (127) may be disposed adjacent to one side of the semiconductor chip (125). For example, the plurality of chip pads (127) may be disposed adjacent to the lower surface of the semiconductor chip (125). The inner encapsulation material (147) may cover the side of the semiconductor chip (125). In one embodiment, the inner encapsulation material (147) may cover the side and upper surface of the semiconductor chip (125). The inner encapsulation material (147) may include an epoxy molding compound (EMC), a printed circuit board, a ceramic substrate, a semiconductor substrate, or a combination thereof.

[0038] The plurality of through electrodes (156) may penetrate the inner encapsulation material (147). The plurality of first pads (157) may be disposed on the lower surface of the inner encapsulation material (147). The plurality of first pads (157) may be in contact with the plurality of through electrodes (156). The plurality of redistribution layers (155) may be in contact with the plurality of first pads (157) and the plurality of chip pads (127). The plurality of second pads (158) may be disposed on the upper surface of the inner encapsulation material (147). The plurality of second pads (158) may be in contact with the plurality of through electrodes (156).

[0039] Each of the plurality of chip pads (127), the plurality of redistribution layers (155), the plurality of through electrodes (156), the plurality of first pads (157), and the plurality of second pads (158) may include Cu, Ag, Al, AlN, Au, Be, Bi, Co, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Sn, Ta, TaN, Te, Ti, TiN, W, WN, Zn, Zr, or a combination thereof.

[0040] Referring to FIG. 8, semiconductor packages according to embodiments of the technical concept of the present invention may include a lower structure (11), a plurality of external connection terminals (13), a first sub-package (121), a second sub-package (122), a third sub-package (123), an upper sub-package (128), a first underfill (35), a plurality of second underfills (39), a plurality of internal connection terminals (42), and a sealing material (47). The first underfill (35) may be disposed between the lower structure (11) and the first sub-package (121). The plurality of second underfills (39) may be disposed between the first sub-package (121), the second sub-package (122), the third sub-package (123), and the upper sub-package (128).

[0041] Referring to FIG. 9, semiconductor packages according to embodiments of the technical concept of the present invention may include a substructure (11), a plurality of external connection terminals (13), a first semiconductor chip (21), a second semiconductor chip (22), a third semiconductor chip (23), an upper semiconductor chip (28), a first underfill (35), a plurality of second underfills (39), a plurality of internal connection terminals (42), and a sealing material (47). The sealing material (47) may extend over the sides of the substructure (11). The sealing material (47) may cover the sides of the substructure (11).

[0042] Referring to FIG. 10, semiconductor packages according to embodiments of the technical concept of the present invention may include a substructure (11), a plurality of external connection terminals (13), a first semiconductor chip (21), a second semiconductor chip (22), a third semiconductor chip (23), an upper semiconductor chip (28), a plurality of first underfills (35), a plurality of internal connection terminals (42), and a sealing material (47). The sealing material (47) may extend over the sides of the substructure (11). The sealing material (47) may cover the sides of the substructure (11).

[0043] Referring to FIG. 11, semiconductor packages according to embodiments of the technical concept of the present invention may include a substructure (11), a plurality of external connection terminals (13), a plurality of first underfills (35), a plurality of internal connection terminals (42), a sealing material (47), a first semiconductor chip (221), and a second semiconductor chip (222). The second semiconductor chip (222) may be disposed adjacent to the first semiconductor chip (221). The second semiconductor chip (222) may be disposed at substantially the same horizontal level as the first semiconductor chip (221). The plurality of first underfills (35) may be disposed between the first semiconductor chip (221) and the substructure (11), and between the second semiconductor chip (222) and the substructure (11).

[0044] Each of the plurality of first underfills (35) may include a first portion (35C) and a second portion (35F). The second portion (35F), having a relatively higher degree of hardening than the first portion (35C), may serve to prevent excessive lateral expansion of the plurality of first underfills (35). The gap between the first semiconductor chip (221) and the second semiconductor chip (222) may be minimized.

[0045] Referring to FIG. 12, semiconductor packages according to embodiments of the technical concept of the present invention may include a substructure (11), a plurality of external connection terminals (13), a plurality of first underfills (35), a plurality of second underfills (39), a plurality of internal connection terminals (42), a sealing material (47), a first semiconductor chip (321), a second semiconductor chip (322), a third semiconductor chip (323), a first upper semiconductor chip (328), a fourth semiconductor chip (421), a fifth semiconductor chip (422), a sixth semiconductor chip (423), and a second upper semiconductor chip (428).

[0046] The first semiconductor chip (321), the second semiconductor chip (322), the third semiconductor chip (323), and the first upper semiconductor chip (328) can be vertically stacked in sequence on the lower structure (11). The first semiconductor chip (321), the second semiconductor chip (322), the third semiconductor chip (323), and the first upper semiconductor chip (328) can form a first tower. The fourth semiconductor chip (421), the fifth semiconductor chip (422), the sixth semiconductor chip (423), and the second upper semiconductor chip (428) can be vertically stacked in sequence on the lower structure (11). The fourth semiconductor chip (421), the fifth semiconductor chip (422), the sixth semiconductor chip (423), and the second upper semiconductor chip (428) can form a second tower. The second tower can be placed adjacent to the first tower.

[0047] A plurality of first underfills (35) may be disposed between the first semiconductor chip (321) and the lower structure (11), and between the fourth semiconductor chip (421) and the lower structure (11). A plurality of second underfills (39) may be disposed between the first semiconductor chip (321), the second semiconductor chip (322), the third semiconductor chip (323), and the first upper semiconductor chip (328), and between the fourth semiconductor chip (421), the fifth semiconductor chip (422), the sixth semiconductor chip (423), and the second upper semiconductor chip (428). Each of the plurality of first underfills (35) may include a first portion (35C) and a second portion (35F). The second portion (35F), having a relatively higher degree of hardening than the first portion (35C), may serve to prevent excessive lateral expansion of the plurality of first underfills (35). The gap between the first tower and the second tower can be minimized.

[0048] Referring to FIG. 13, semiconductor packages according to embodiments of the technical concept of the present invention may include a substructure (11), a plurality of external connection terminals (13), a plurality of first underfills (35), a plurality of internal connection terminals (42), a sealing material (47), a first semiconductor chip (321), a second semiconductor chip (322), a third semiconductor chip (323), a first upper semiconductor chip (328), a fourth semiconductor chip (421), a fifth semiconductor chip (422), a sixth semiconductor chip (423), and a second upper semiconductor chip (428). The first semiconductor chip (321), the second semiconductor chip (322), the third semiconductor chip (323), and the first upper semiconductor chip (328) may form a first tower. The fourth semiconductor chip (421), the fifth semiconductor chip (422), the sixth semiconductor chip (423), and the second upper semiconductor chip (428) may form a second tower.

[0049] A plurality of first underfills (35) may be disposed between the lower structure (11), the first semiconductor chip (321), the second semiconductor chip (322), the third semiconductor chip (323), and the first upper semiconductor chip (328), and between the lower structure (11), the fourth semiconductor chip (421), the fifth semiconductor chip (422), the sixth semiconductor chip (423), and the second upper semiconductor chip (428). Each of the plurality of first underfills (35) may include a first portion (35C) and a second portion (35F). The second portion (35F), having a relatively higher degree of hardening than the first portion (35C), may serve to prevent excessive lateral expansion of the plurality of first underfills (35). The gap between the first tower and the second tower may be minimized.

[0050] FIGS. 14 to 30 are cross-sectional and schematic diagrams for explaining methods of forming a semiconductor package according to embodiments of the technical concept of the present invention. FIG. 20 is a partial view showing a part of FIG. 19.

[0051] Referring to FIGS. 14 and 15, a first semiconductor chip (21) may be provided. The first semiconductor chip (21) may include a plurality of through electrodes (56), a plurality of first pads (57), and a plurality of second pads (58). A plurality of internal connection terminals (42) may be formed on the plurality of first pads (57). A preliminary underfill (35PRE) covering the plurality of internal connection terminals (42) may be formed on the first semiconductor chip (21). The surface of the preliminary underfill (35PRE) may include a plurality of irregularities. The convex surfaces of the preliminary underfill (35PRE) may be aligned with the plurality of internal connection terminals (42).

[0052] In one embodiment, forming the preliminary underfill (35PRE) on the first semiconductor chip (21) may include forming a film (F) on a wafer (W) and separating it using a sawing process, as shown in FIG. 14. The first semiconductor chip (21) may be separated from the wafer (W), and the preliminary underfill (35PRE) may be separated from the film (F). The sides of the first semiconductor chip (21) and the preliminary underfill (35PRE) may form substantially the same plane.

[0053] The above preliminary underfill (35PRE) may include a non-conductive film (NCF) having laser-sensitive additives. In one embodiment, the content of the laser-sensitive additives in the preliminary underfill (35PRE) may be 0.01 wt% to 10 wt%.

[0054] In one embodiment, the pre-underfill (35PRE) may comprise a filler, a first epoxy, a second epoxy, a first polymer, a second polymer, a flux, and laser-sensitive additives. The filler may comprise SiO, TiO, AlO, SiC, BN, or a combination thereof. For example, the filler may comprise SiO2. The first epoxy may comprise a liquid-type material for controlling adhesive properties. The first epoxy may comprise bisphenol A, phenol novolak, bisphenol F, or a combination thereof. The second epoxy may comprise a solid-type material for controlling adhesive properties. The second epoxy may comprise a naphthalene-based epoxy, cresol novolak epoxy, bisphenol A, or a combination thereof. The first polymer may include a hardener. The first polymer may include novolak phenol resin, polyamine, polyamide, or a combination thereof. The second polymer may include a thermoplastic resin for film formation. The second polymer may include phenoxy resin, PVB resin, or a combination thereof.

[0055] The laser-sensitive additives may include polyimide (PI), such as polybenzoxazole (PBO) and photosensitive polyimides (PSPI), benzocyclobutene (BCB), or a combination thereof. For example, the laser-sensitive additives may include polybenzoxazole (PBO).

[0056] In one embodiment, the preliminary underfill (35PRE) may comprise a non-conductive film (NCF) that does not have a laser-sensitive additive. The preliminary underfill (35PRE) may comprise the filler, the first epoxy, the second epoxy, the first polymer, the second polymer, and the flux.

[0057] Referring to FIG. 16, in one embodiment, the surface of the preliminary underfill (35PRE) may be flat.

[0058] Referring to FIG. 17, an upper semiconductor chip (28) may be provided. Providing the upper semiconductor chip (28) may involve a process similar to providing the first semiconductor chip (21). The upper semiconductor chip (28) may include a plurality of first pads (57). A plurality of internal connection terminals (42) may be formed on the plurality of first pads (57). A preliminary underfill (35PRE) covering the plurality of internal connection terminals (42) may be formed on the upper semiconductor chip (28).

[0059] Referring to FIG. 18, in one embodiment, the preliminary underfill (35PRE) may have a horizontal width narrower than the first semiconductor chip (21). The side of the preliminary underfill (35PRE) may be offset from the side of the first semiconductor chip (21).

[0060] Referring to FIG. 19, a substructure (11) may be provided. The first semiconductor chip (21) may be attached to the substructure (11). The preliminary underfill (35PRE) may be adhered between the substructure (11) and the first semiconductor chip (21).

[0061] In one embodiment, attaching the first semiconductor chip (21) to the substructure (11) may include applying pressure toward the substructure (11) to the first semiconductor chip (21) using a handling device (582). While applying pressure toward the substructure (11) to the first semiconductor chip (21) using the handling device (582), the pre-underfill (35PRE) may be heated to a first temperature. The first temperature may be 70°C to 150°C. Heating the pre-underfill (35PRE) to the first temperature may be performed using a contact heating device, a non-contact heating device, or a combination thereof. For example, the contact heating device may include a heater block. The non-contact heating device may include IR reflow, hot air reflow, or laser reflow.

[0062] Referring to FIG. 20, the plurality of internal connection terminals (42) can penetrate the preliminary underfill (35PRE) and come into contact with the plurality of second pads (58) of the lower structure (11).

[0063] Referring to FIGS. 21 and 22, the first underfill (35) can be formed by curing the preliminary underfill (35PRE) using a laser bonding process.

[0064] Forming the first underfill (35) using the laser bonding process described above may include irradiating a laser beam (LB) toward the first semiconductor chip (21) and the preliminary underfill (35PRE) using a laser generator (586) and a beam splitter (584). In one embodiment, irradiating the laser beam (LB) toward the first semiconductor chip (21) and the preliminary underfill (35PRE) may be performed for 0.1 seconds to 5 seconds. While irradiating the laser beam (LB), pressure may be applied toward the first semiconductor chip (21) toward the substructure (11) using the handling device (582). The handling device (582) may include a material that transmits the laser beam (LB), such as quartz or reinforced glass. The beam splitter (584) may be positioned between the laser generator (586) and the handling device (582). The laser beam (LB) generated using the laser generator (586) and the beam splitter (584) may pass through the handling device (582) and be irradiated toward the first semiconductor chip (21) and the preliminary underfill (35PRE).

[0065] The laser beam (LB) may include a plurality of first laser beams (LB1) and a plurality of second laser beams (LB2). Each of the plurality of second laser beams (LB2) may have a higher intensity than each of the plurality of first laser beams (LB1). In one embodiment, the laser beam (LB) may include an excimer laser or a UV laser having a wavelength of 193 nm to 343 nm. Each of the plurality of first laser beams (LB1) may have an intensity of 40 mJ / cm² to 80 mJ / cm². Each of the plurality of second laser beams (LB2) may have an intensity of 90 mJ / cm² to 120 mJ / cm².

[0066] The plurality of first laser beams (LB1) may be aligned to be irradiated adjacent to the center of the first semiconductor chip (21) when viewed in a plan view. The plurality of second laser beams (LB2) may be aligned to be irradiated adjacent to the edge of the first semiconductor chip (21) when viewed in a plan view. The irradiation range of the plurality of second laser beams (LB2) may extend to the outside of the first semiconductor chip (21). In one embodiment, the plurality of first laser beams (LB1) and the plurality of second laser beams (LB2) may be irradiated simultaneously. In one embodiment, each of the plurality of first laser beams (LB1) and each of the plurality of second laser beams (LB2) may be irradiated sequentially with a time interval. The plurality of first laser beams (LB1) and the plurality of second laser beams (LB2) may be irradiated repeatedly multiple times.

[0067] The area of ​​the above-mentioned preliminary underfill (35PRE) irradiated by the plurality of first laser beams (LB1) becomes the first part (35C) of the above-mentioned preliminary underfill (35PRE), and the area of ​​the above-mentioned preliminary underfill (35PRE) irradiated by the plurality of second laser beams (LB2) becomes the second part (35F) of the above-mentioned preliminary underfill (35PRE). The second part (35F) may be in continuity with the outside of the first part (35C).

[0068] The second portion (35F) may have a relatively higher degree of curing than the first portion (35C). In one embodiment, the first portion (35C) of the first underfill (35) may have a degree of curing of 10% to 35%. The second portion (35F) of the first underfill (35) may have a degree of curing of 50% to 80%. The degree of curing of the first underfill (35) can be verified using a measuring device such as FT-IR (Fourier-Transform Infrared Spectroscopy). The second portion (35F) of the first underfill (35) may have a relatively lower flowability than the first portion (35C).

[0069] The first portion (35C) of the first underfill (35) may be limited between the first semiconductor chip (21) and the substructure (11). The first portion (35C) of the first underfill (35) may be aligned adjacent to the center of the first semiconductor chip (21). The second portion (35F) of the first underfill (35) may be aligned adjacent to the edge of the first semiconductor chip (21). The second portion (35F) of the first underfill (35) may extend between the first semiconductor chip (21) and the substructure (11). The second portion (35F) of the first underfill (35) may protrude to the outside of the first semiconductor chip (21). The second portion (35F) may serve to prevent excessive lateral expansion of the first underfill (35).

[0070] While forming the first underfill (35) using the laser bonding process, the plurality of internal connection terminals (42) may be reflowed by heating to a second temperature higher than the first temperature. The second temperature may be 200°C to 280°C. In one embodiment, heating the plurality of internal connection terminals (42) to the second temperature may be performed by the laser beam (LB).

[0071] In one embodiment, a combination of the laser beam (LB) and a contact heating device may be used to heat the plurality of internal connection terminals (42) to the second temperature. For example, the contact heating device may include a heater block. In one embodiment, a combination of the laser beam (LB) and a non-contact heating device may be used to heat the plurality of internal connection terminals (42) to the second temperature. For example, the non-contact heating device may include IR reflow or hot air reflow. In one embodiment, a combination of the laser beam (LB), a contact heating device, and a non-contact heating device may be used to heat the plurality of internal connection terminals (42) to the second temperature.

[0072] Referring to FIG. 23, a plurality of first laser beams (LB1) can be aligned to be irradiated adjacent to the center of the first semiconductor chip (21) when viewed in a plan view. A plurality of second laser beams (LB2) can be aligned to be irradiated adjacent to the edge of the first semiconductor chip (21) when viewed in a plan view. The irradiation range of the plurality of second laser beams (LB2) can be limited to the interior of the first semiconductor chip (21) when viewed in a plan view.

[0073] Referring to FIG. 24, each of the plurality of first laser beams (LB1) and each of the plurality of second laser beams (LB2) can be spaced apart from each other.

[0074] Referring to FIG. 25, a second semiconductor chip (22) may be attached to the first semiconductor chip (21). A second underfill (39) may be formed between the first semiconductor chip (21) and the second semiconductor chip (22). A plurality of internal connection terminals (42) connected to the first semiconductor chip (21) and the second semiconductor chip (22) may be formed by penetrating the second underfill (39).

[0075] In one embodiment, forming the second semiconductor chip (22), the plurality of internal connection terminals (42), and the second underfill (39) on the first semiconductor chip (21) may include a thermocompression bonding (TC Bonding) process. The thermocompression bonding (TC Bonding) process may include applying pressure to the second semiconductor chip (22) toward the first semiconductor chip (21) and heating the plurality of internal connection terminals (42) to the second temperature. The second underfill (39) may include a configuration similar to the pre-underfill (35PRE). In one embodiment, while the thermocompression bonding (TC Bonding) process is being performed, heating the plurality of internal connection terminals (42) to the second temperature may be performed using a contact heating device, a non-contact heating device, or a combination thereof.

[0076] In one embodiment, the second underfill (39) may comprise a non-conductive film (NCF) having a laser-sensitive additive or a non-conductive film (NCF) not having a laser-sensitive additive. In one embodiment, the second underfill (39) may comprise the filler, the first epoxy, the second epoxy, the first polymer, the second polymer, the flux, and the laser-sensitive additive. In one embodiment, the second underfill (39) may comprise the filler, the first epoxy, the second epoxy, the first polymer, the second polymer, and the flux.

[0077] During the above TC Bonding process, the second underfill (39) may be cured by the second temperature. The second underfill (39) may have a substantially uniform degree of curing. In the second underfill (39), the degree of curing of the portion adjacent to the center of the second semiconductor chip (22) and the degree of curing of the portion adjacent to the edge may be substantially the same.

[0078] Referring to FIG. 26, a third semiconductor chip (23) and an upper semiconductor chip (28) may be stacked sequentially on the second semiconductor chip (22). A plurality of second underfills (39) may be formed between the second semiconductor chip (22), the third semiconductor chip (23), and the upper semiconductor chip (28). A plurality of internal connection terminals (42) that penetrate the plurality of second underfills (39) may be formed. Forming the third semiconductor chip (23), the upper semiconductor chip (28), the plurality of second underfills (39), and the plurality of internal connection terminals (42) on the second semiconductor chip (22) may include a thermal compression bonding (TC Bonding) process similar to that described with reference to FIG. 25.

[0079] Referring to FIG. 27, a sealing material (47) covering the first semiconductor chip (21), the second semiconductor chip (22), the third semiconductor chip (23), the upper semiconductor chip (28), the first underfill (35), and the plurality of second underfills (39) may be formed on the lower structure (11). In one embodiment, an injection molding method may be used to form the sealing material (47). The sealing material (47) may include an epoxy molding compound (EMC).

[0080] Referring to FIG. 28, a semiconductor package can be separated using a cutting process.

[0081] Referring once again to FIG. 1, a plurality of external connection terminals (13) may be formed on the lower surface of the lower structure (11). In one embodiment, the plurality of external connection terminals (13) may be omitted.

[0082] Referring to FIG. 29, a first semiconductor chip (21), a second semiconductor chip (22), a third semiconductor chip (23), and an upper semiconductor chip (28) may be stacked sequentially on a lower structure (11). A plurality of first underfills (35) may be formed between the lower structure (11), the first semiconductor chip (21), the second semiconductor chip (22), the third semiconductor chip (23), and the upper semiconductor chip (28). A plurality of internal connection terminals (42) connected to the lower structure (11), the first semiconductor chip (21), the second semiconductor chip (22), the third semiconductor chip (23), and the upper semiconductor chip (28) may be formed by penetrating the plurality of first underfills (35).

[0083] Forming the first semiconductor chip (21), the second semiconductor chip (22), the third semiconductor chip (23), the upper semiconductor chip (28), the plurality of first underfills (35), and the plurality of internal connection terminals (42) on the lower structure (11) may include a laser bonding process similar to that described with reference to FIGS. 19 to 24. Each of the plurality of first underfills (35) may include a non-conductive film (NCF) having a laser-sensitive additive. Each of the plurality of first underfills (35) may include a first portion (35C) and a second portion (35F) in continuity with the outside of the first portion (35C). The second portion (35F) may have a relatively higher degree of curing than the first portion (35C).

[0084] Referring to FIG. 30, a sealing material (47) covering the first semiconductor chip (21), the second semiconductor chip (22), the third semiconductor chip (23), the upper semiconductor chip (28), and the plurality of first underfills (35) can be formed on the lower structure (11). The semiconductor package can be separated using a cutting process.

[0085] Although embodiments according to the technical concept of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. The embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0086] 11: Substructure 13: External connection terminal 21: 1st semiconductor chip 22: 2nd semiconductor chip 23: Third semiconductor chip 28: Upper semiconductor chip 35: 1st underfill 39: 2nd underfill 42: Internal connection terminal 47: Bag material 582: Handling device 584: Beam Splitter 586: Laser Generator LB: Laser Beam

Claims

Claim 1 A semiconductor package comprising: a substructure; a first semiconductor chip on the substructure; a first underfill between the first semiconductor chip and the substructure, wherein the first underfill has a first portion adjacent to the center of the first semiconductor chip and a second portion adjacent to the edge of the first semiconductor chip, the second portion having a higher degree of curing than the first portion; and a plurality of internal connection terminals disposed between the first semiconductor chip and the substructure and extending within the first underfill, wherein the first underfill comprises a non-conductive film (NCF) having laser-sensitive additives. Claim 2 In claim 1, the second portion extends between the first semiconductor chip and the substructure and protrudes to the outside of the first semiconductor chip and contacts the side of the first semiconductor chip. Claim 3 A semiconductor package according to claim 1, wherein the first portion has a degree of curing of 10% to 35% and the second portion has a degree of curing of 50% to 80%. Claim 4 delete Claim 5 A semiconductor package according to claim 1, wherein the laser-sensitive additive comprises polybenzoxazole (PBO), polyimide (PI) such as photosensitive polyimides (PSPI), benzocyclobutene (BCB), or a combination thereof. Claim 6 A semiconductor package according to claim 1, wherein the content of the laser-sensitive additive in the first underfill is 0.01 wt% to 10 wt%. Claim 7 A semiconductor package according to claim 1, wherein the first underfill comprises a filler, a first epoxy, a second epoxy, a first polymer, a second polymer, a flux, and a laser-sensitive additive, wherein the filler comprises SiO, TiO, AlO, SiC, BN, or a combination thereof, the first epoxy comprises a liquid type material for controlling adhesive properties, the second epoxy comprises a solid type material for controlling adhesive properties, the first polymer comprises a hardener, and the second polymer comprises a thermoplastic resin for film formation. Claim 8 A semiconductor package according to claim 1, further comprising: a second semiconductor chip on the first semiconductor chip; and a second underfill between the second semiconductor chip and the second semiconductor chip. Claim 9 A method for forming a semiconductor package comprising a substructure, a first semiconductor chip on the substructure, a first underfill between the first semiconductor chip and the substructure, wherein the first underfill has a first portion adjacent to the center of the first semiconductor chip and a second portion adjacent to the edge of the first semiconductor chip, wherein the second portion has a higher degree of curing than the first portion, and a plurality of internal connection terminals disposed between the first semiconductor chip and the substructure and extending within the first underfill, the method comprising forming the plurality of internal connection terminals and a preliminary underfill covering the plurality of internal connection terminals on the first semiconductor chip, stacking the first semiconductor chip on the substructure, wherein the preliminary underfill is bonded between the first semiconductor chip and the substructure, and forming the first underfill by curing the preliminary underfill using a laser bonding process, and reflowing the plurality of internal connection terminals while curing the preliminary underfill to form the first underfill, wherein the first A semiconductor package formation method comprising an underfill having a non-conductive film (NCF) having laser-sensitive additives. Claim 10 A semiconductor package comprising: a substructure; a plurality of semiconductor chips stacked sequentially on the substructure; a plurality of underfills disposed between the plurality of semiconductor chips and the substructure and between the plurality of semiconductor chips, wherein each of the plurality of underfills has a first portion adjacent to the center of one adjacent semiconductor chip and a second portion adjacent to the edge of one adjacent semiconductor chip, wherein the second portion has a higher degree of curing than the first portion; and a plurality of internal connection terminals disposed between the plurality of semiconductor chips and the substructure and between the plurality of semiconductor chips and extending within the plurality of underfills, wherein the plurality of underfills comprises a non-conductive film (NCF) having laser-sensitive additives.

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