Semiconductor device

Abstract

The present invention relates to a semiconductor device comprising an active pattern having sharp edges. The semiconductor device comprises a substrate having an active pattern, a cell region provided on the substrate and having a cell circuit, and a core region provided on the substrate and having a peripheral circuit. When viewed in a planar view, the active pattern on the core region comprises edges. Each of the edges has a rounding index of 15 nm or less, which is the distance between the edge tip when the edge is not rounded and the edge tip when the edge is rounded.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device comprising an active pattern having no or reduced corner rounding. Background Technology

[0002] During the substrate patterning process for forming an active pattern, it is common practice to round the corners of the active pattern. Corner rounding can cause contact between adjacent corners. Furthermore, corner rounding can increase the size of the active pattern. Consequently, there is a need for an improved substrate patterning method capable of eliminating or reducing such corner rounding. The problem to be solved

[0003] The object of the present invention is to provide a semiconductor device comprising an active pattern having no rounding or reduced edges.

[0004] Another objective of the present invention is to provide a semiconductor device including an active pattern with improved electrical characteristics.

[0005] Another objective of the present invention is to provide a semiconductor device comprising an active pattern with improved integration density. means of solving the problem

[0006] A semiconductor device according to the present invention for achieving the above objective is characterized by including an active pattern having angular corners implemented using a mask pattern formed by intersecting masks.

[0007] A semiconductor device according to an embodiment of the present invention capable of implementing the above features may include: a substrate having an active pattern; a cell region provided on the substrate and having a cell circuit; and a core region provided on the substrate and having a peripheral circuit. When viewed in a planar view, the active pattern on the core region may include edges. Each of the edges may have a rounding index of 15 nm or less, which is the distance between the edge tip when the edge is not rounded and the edge tip when the edge is rounded.

[0008] A semiconductor device according to an embodiment of the present invention capable of implementing the above features may include: a substrate comprising a cell region and a peripheral region; and an active pattern provided on each of the cell region and the peripheral region. The peripheral region may be divided into a plurality of regions, and when viewed planarly, the active pattern on each of the plurality of regions may include a plurality of angled corners. Each of the corners may have a rounding index of 15 nm or less, which is the distance between the corner tip when the corner is not rounded and the corner tip when the corner is rounded.

[0009] A semiconductor device according to an embodiment of the present invention capable of implementing the above features comprises: a semiconductor substrate including a cell region provided with a memory circuit and a peripheral region provided with a peripheral circuit; a plurality of cell active patterns provided on the cell region and having the same shape as each other, wherein the cell active patterns are regularly arranged; and a plurality of peripheral active patterns provided on the peripheral region, wherein, when viewed in a planar view, each of the peripheral active patterns may have angular corners. Each of the corners may have a rounding index of 15 nm or less, which is the distance between the corner tip when the corner is not rounded and the corner tip when the corner is rounded. Effects of the invention

[0010] According to the present invention, an active pattern having angled corners can be realized by forming the intersecting portions of the masks into a mask pattern. In this way, by preventing or reducing the corner rounding of the active pattern, an increase in the area of ​​the active pattern due to corner rounding and contact between adjacent corners can be prevented.

[0011] Accordingly, the size of the active patterns can be reduced, and electrical short circuits between the active patterns can be minimized. As a result, the integration density and electrical characteristics of the semiconductor device can be improved. Brief explanation of the drawing

[0012] FIGS. 1a to 1i are plan views illustrating a substrate patterning method according to embodiments of the present invention. Figure 1e is an enlarged view of the S1 region of Figure 1b. Figure 1f is an enlarged view of the S2 region of Figure 1d. Figure 1h is an enlarged view of the S3 region of Figure 1g. Figure 1i is an enlarged view of a part of Figure 1h. Figure 1j is an enlarged view of a part of Figure 1h. Figure 1k is a plan view illustrating an active pattern according to a comparative example. FIGS. 2a to 2c are plan views illustrating a substrate patterning method according to embodiments of the present invention. FIG. 2d is a block diagram illustrating a semiconductor device according to embodiments of the present invention. FIGS. 3a to 11a are plan views illustrating a substrate patterning method according to embodiments of the present invention. FIGS. 3b to 11b illustrate a substrate patterning method according to embodiments of the present invention, and are cross-sectional views taken by cutting along the lines A1-A2, B1-B2, and C1-C2 of FIGS. 3a to 11a, respectively. FIGS. 12a to 12d are cross-sectional views illustrating a substrate patterning method according to embodiments of the present invention. FIG. 12e is a plan view illustrating a substrate patterning method according to embodiments of the present invention. FIG. 13a is a plan view illustrating a semiconductor device including an active pattern of a substrate according to embodiments of the present invention. FIG. 13b illustrates a semiconductor device including an active pattern of a substrate according to embodiments of the present invention, and is a cross-sectional view taken by cutting along the lines I1-I2, I3-I4, and I5-I6 of FIG. 13a. Specific details for implementing the invention

[0013] Hereinafter, a substrate patterning method capable of implementing an active pattern with no or reduced corner rounding according to the present invention and a semiconductor device including said active pattern will be described in detail with reference to the attached drawings.

[0014] FIGS. 1a to 1i are plan views illustrating a substrate patterning method according to embodiments of the present invention. FIG. 1e is an enlarged view of region S1 of FIG. 1b. FIG. 1f is an enlarged view of region S2 of FIG. 1d. FIG. 1h is an enlarged view of region S3 of FIG. 1g. FIG. 1k is a plan view illustrating an active pattern according to a comparative example. FIG. 1f is an enlarged view of region S2 of FIG. 1d. FIG. 1h is an enlarged view of region S3 of FIG. 1g. FIG. 1i is an enlarged view of a part of FIG. 1h.

[0015] Referring to FIG. 1a, a first mask (12) can be formed on a substrate (10). The substrate (10) may be a semiconductor substrate containing a semiconductor material such as silicon. As another example, instead of the substrate (10), an etching target film such as a conductive film, an insulating film, or a combination thereof may be provided. The first mask (12) may have a plurality of rectangular shapes, and the first mask (12) may include a plurality of openings (12h). The shape of the first mask (12) may be a combination of a rectangle extending along a first direction (D1), a rectangle extending along a second direction (D2) that intersects (e.g., orthogonal) the first direction (D1), and a square or a similar shape. The openings (12h) may be arranged along the second direction (D2), and each of the openings (12h) may extend along the first direction (D1). The width of each opening (12h) may be equal or nearly constant along the first direction (D1). The openings (12h) may expose the substrate (10).

[0016] Referring to FIG. 1b, a second mask (16) can be formed on a substrate (10). The shape of the second mask (16) may be a combination of a rectangle extended along the second direction (D2), a ladder shape extended along the second direction (D2), and a rectangle extended along the first direction (D1). The second mask (16) may include a plurality of openings (16h). The openings (16h) may be arranged along the second direction (D2), and each of the openings (16h) may be extended along the first direction (D1). One or more of the openings (16h) may have a shape with both ends extended. For example, some of the openings (16h) may have a width that is equal or nearly constant along the first direction (D1). Some of the other openings (16h) have a width that is equal or nearly constant along the first direction (D1) and can be extended at both ends.

[0017] Referring to FIG. 1c, a second mask (16) may be formed on the first mask (12). The second mask (16) may have a shape that covers a portion of the first mask (12) and exposes another portion. In planar view, the openings (16h) of the second mask (16) may not overlap with the openings (12h) of the first mask (12). The openings (16h) may expose at least one of the substrate (10) and the first mask (12). The second mask (16) may include a material having an etching selectivity ratio with respect to the first mask (12). The first mask (12) may be patterned by an etching process using the second mask (16) as an etching mask. After patterning the first mask (12), the second mask (16) may be removed.

[0018] Referring to FIG. 1d, the above processes can finally form a mask pattern (12p) having various shapes. For example, the mask pattern (12p) may include at least one sub-pattern (12a) having a rectangular or similar shape, at least one sub-pattern (12b) having a dumbbell or similar shape, at least one sub-pattern (12c) having a comb or similar shape, and at least one sub-pattern (12d) having a square or similar shape.

[0019] According to the embodiments, the mask pattern (12p) may not include rounded corners. Referring to FIG. 1e as in FIG. 1c, the first mask (12) can be patterned by an etching process using a second mask (16). In this case, an overlapping portion (15) where the first and second masks (12, 16) overlap remains, which can form the mask pattern (12p) shown in FIG. 1d. In the overlapping portion (15), the first mask (12) and the second mask (16) may meet at an intersection angle (θ1), for example, 90 degrees, so as shown in FIG. 1f, there is no possibility of a round shape occurring in the mask pattern (12p) corresponding to the overlapping portion (15), or the possibility thereof may be significantly reduced. For example, the mask pattern (12p) may have a corner angle (θ2) of 90 degrees or a similar angle. In this way, the overlapping portion (15) formed by the first mask (12) and the second mask (16) can constitute the final mask pattern (12p). According to this principle, each of the sub-patterns (12a, 12b, 12c, 12d) of the mask pattern (12p) may include sharp corners.

[0020] Referring to FIG. 1g, the substrate (10) can be patterned by an etching process using the mask pattern (12p) of FIG. 1d as an etching mask. By the etching process, an active pattern (11) can be formed on the substrate (10). The active pattern (11) may have various shapes. For example, the active pattern (11) may include at least one active pattern (11a) having a rectangular or similar shape, at least one active pattern (11b) having a dumbbell or similar shape, at least one active pattern (11c) having a comb or similar shape, and at least one active pattern (11d) having a square or similar shape.

[0021] As previously mentioned with reference to FIG. 1f, since the mask pattern (12p) can have sharp corners, the active pattern (11) can also have sharp corners (E) as shown in FIG. 1h. As described above with reference to FIG. 1a through 1d, a mask pattern (12p) having sharp corners can be formed by forming a first mask (12) and patterning the first mask (12) using a second mask (16) that partially overlaps the first mask (12).

[0022] Referring to FIG. 1i, any corner (11e) of the active pattern (11) may have a corner angle (θ3) of 90 degrees or a similar angle. For example, the corner (11e) may have a sharp tip (110). The corner (11e) may have a rounding index of 0 or nearly 0, as described below with reference to FIG. 1j. This description may be applied similarly to other corners of the active pattern (11).

[0023] Referring to FIG. 1J, the corner (11e) of the active pattern (11) may be finely rounded. The degree of rounding of the corner (11e) can be represented by a rounding index (RI). The rounding index (RI) may represent the distance between the rounded tip (110r) and the virtual tip (110i), for example, the shortest distance. The location of the virtual tip (110i) may represent the point where the tip would exist if the corner (11e) were not rounded. For example, the virtual tip (110i) may correspond to the tip (110) of FIG. 1I. The rounding index (RI) may be about 15 nm or less. For example, the rounding index (RI) may be about 5 nm to 15 nm.

[0024] As such, according to embodiments of the present invention, the corner (11e) of the active pattern (11) may have a sharp tip (110) as can be seen in FIG. 1i, or a rounded tip (110r) as in FIG. 1j. Even if the corner (11e) has a rounded tip (110r), the rounding index (RI) is about 15 nm or less, that is, the degree of rounding is reduced, so the problems associated with corner rounding as described later with reference to FIG. 1k can be resolved.

[0025] Unlike the embodiment of the present invention, when a mask pattern similar to the mask pattern (12p) of FIG. 1d is formed in a single patterning process, the corners of the similar mask pattern may be rounded. The degree of rounding may be greater than the degree of rounding in FIG. 1j. When a substrate is etched with a mask pattern having rounded corners, an active pattern (11r) having rounded corner portions (Er) can be formed as shown in FIG. 1k.

[0026] In the active pattern (11r) of this comparative example, the corner portion (Er) may be expanded by the rounding of the corners, and the active pattern (11r) may have a relatively large length (L2) compared to the length (L1 in FIG. 1h) of the active pattern (11) of the present embodiment. An increase in the length of the active pattern (11r) may cause an increase in the area of ​​the active pattern (11r), which may act as a hindering factor in improving the integration density of the semiconductor device. Furthermore, due to the expansion of the corners of the active pattern (11r), adjacent corners of the active pattern (11r) or the corners of adjacent active patterns (11r) may come into direct contact, which may degrade the electrical characteristics of the semiconductor device.

[0027] In contrast, the present embodiment can prevent an increase in the length of the active pattern (11r) of the comparative example and / or contact between the corners. As a result, a semiconductor device including an active pattern (11) having sharp corners can achieve improved integration density and improved electrical characteristics.

[0028] FIGS. 2a to 2c are plan views illustrating a substrate patterning method according to embodiments of the present invention.

[0029] Referring to FIG. 2a, each of the openings (16h) of the second mask (16) may have the same or nearly constant width along the first direction (D1). The shape of the comb-shaped sub-pattern (12c) in the mask pattern (12p) of FIG. 2b formed using the second mask (16) may differ from the comb-shaped sub-pattern (12c) of FIG. 1d. Likewise, the shape of the comb-shaped active pattern (11c) in the active pattern (11) of FIG. 2c formed using the mask pattern (12p) of FIG. 2b may differ from the shape of the comb-shaped active pattern (11c) of FIG. 1g. Otherwise, the same or similar as described with reference to FIG. 1a through 1j may be applied to this embodiment.

[0030] FIG. 2d is a block diagram illustrating a semiconductor device according to embodiments of the present invention.

[0031] Referring to FIG. 2d, the semiconductor device may include one or more cell regions (1), core regions (2, 3, 4, 5), and peripheral regions (6). The semiconductor device may be, for example, a memory device. A cell circuit, such as a memory integrated circuit, may be placed in the cell region (1). The core regions (2, 3, 4, 5) and the peripheral region (6) may be electrically connected to the cell region (1) and may include various peripheral circuits necessary for the operation of the cell circuit placed in the cell region (1).

[0032] The core regions (2, 3, 4, 5) may include a first core region (2), a second core region (3), a third core region (4), and a fourth core region (5) surrounding the cell region (1). In the first to fourth core regions (2-5), sense amplifier (S / A) circuits, sub-wordline driver (SWD) circuits, and power supply and ground driver circuits for driving the sense amplifier may be disposed. For example, as merely an example and not at all intended to limit the invention, sense amplifier (S / A) circuits may be disposed in the first and third core regions (2, 4) facing each other, and sub-wordline driver (SWD) circuits may be disposed in the second and fourth core regions (3, 5) facing each other. Power supply and ground driver circuits for driving the sense amplifier may be disposed in the second and fourth core regions (3, 5) or in the surrounding region (6).

[0033] The mask pattern (12p) shown in FIG. 1d or FIG. 2b can be used to form an active pattern on the core regions (2, 3, 4, 5) and / or the peripheral region (6) of the semiconductor device shown in FIG. 2d. For example, an active pattern (11) identical or similar to that shown in FIG. 2c can be formed on each of the core regions (2, 3, 4, 5). Similarly, an active pattern (11) identical or similar to that shown in FIG. 2c can be formed on the peripheral region (6). The active pattern (11) on each of the core regions (2, 3, 4, 5) may be denser than the active pattern (11) on the peripheral region (6).

[0034] To form the mask pattern (12p), a patterning process for forming the first mask (12) and a patterning process for forming the second mask (16) may be required. These patterning processes can be performed together with the patterning process in the cell region (1). Therefore, there is no need to introduce a separate patterning process to form the mask pattern (12p). As a result, according to the present embodiments, the formation of the active pattern in the core regions (2, 3, 4, 5) and / or the peripheral region (6) can be applied in compatibility with the process of forming the active pattern in the cell region (1). This will be described below.

[0035] FIGS. 3a to 11a are plan views illustrating a substrate patterning method according to embodiments of the present invention. FIGS. 3b to 11b illustrate a substrate patterning method according to embodiments of the present invention and are cross-sectional views taken by cutting along the lines A1-A2, B1-B2, and C1-C2 of FIGS. 3a to 11a, respectively.

[0036] Referring to FIGS. 3a and 3b, a first mask (12) can be formed on a substrate (10). The substrate (10) may be a semiconductor substrate comprising a semiconductor material such as silicon, germanium, or silicon-germanium. Instead of the substrate (10), an etching target film such as a conductive film, an insulating film, or a combination thereof may be provided, or such an etching target film may be formed on the substrate (10).

[0037] The substrate (10) may be divided into a cell region (CELL) and a core region (CORE). For convenience, the core region (CORE) is divided into a first region (CORE1), a second region (CORE2), and a third region (CORE3). The first, second, and third regions (CORE1, CORE2, CORE3) may be placed on one side of the cell region (CELL) or on multiple sides of the cell region (CELL). For example, the cell region (CELL) may correspond to the cell region (1) of FIG. 2d, and the core region (CORE) may correspond to at least one of the core regions (2, 3, 4, 5) of FIG. 2d.

[0038] In this specification, for convenience of description and illustration, the first, second, and third regions (CORE1, CORE2, CORE3) are assumed to be arranged in a line along the first direction (D1), but the invention is not limited thereto. For instance, any one of the first to third regions (CORE1-CORE3) may correspond to the first core region (2) or the third core region (4) of FIG. 2d, and the other may correspond to the second core region (3) or the fourth core region (5).

[0039] As merely an example and not at all intended to limit the invention, a sense amplifier may be placed in any one of the first, second, and third regions (CORE1, CORE2, CORE3), a sub-wordline driver may be placed in any one of them, and a power driver and a ground driver for driving the sense amplifier may be placed in yet another.

[0040] The first mask (12) can be formed on the cell region (CELL) and the core region (CORE). For example, the first mask (12) may have a shape composed of multiple lines extending along a third direction (D3) on the cell region (CELL), and may have a plate shape covering the entire substrate (10) on the core region (CORE). The substrate (10) may be exposed between the lines composed of the first mask (12) on the cell region (CELL). The first mask (12) may be formed as an oxide film, a nitride film, an amorphous carbon layer, or a combination thereof by atomic layer deposition (ALD), chemical vapor deposition (CVD), spin coating, etc.

[0041] Referring to FIGS. 4a and 4b, a first photoresist pattern (14) can be formed on a substrate (10). The first photoresist pattern (14) can be formed on a cell region (CELL) and a core region (CORE). For example, the first photoresist pattern (14) may have an integrated shape that exposes parts of the first mask (12) on the cell region (CELL), and a separated shape that exposes parts of the first mask (12) on the core region (CORE).

[0042] The first photoresist pattern (14) on the cell area (CELL) may include a plurality of first openings (14h1). The first openings (14h1) may be spaced apart along a first direction (D1) or a second direction (D2). Each of the first openings (14h1) may have a square, circular, elliptical, polygonal, or various other shapes that expose a portion of the first mask (12).

[0043] A first photoresist pattern (14) on a core region (CORE) may include a plurality of second openings (14h2). The second openings (14h2) may be spaced apart along a second direction (D2), and each of the second openings (14h2) may extend along a first direction (D1) to expose a portion of the first mask (12). Each of the second openings (14h2) may have the same or nearly constant width along the first direction (D1).

[0044] Referring to FIGS. 5a and 5b, the first mask (12) can be patterned by an etching process using the first photoresist pattern (14) as an etching mask, and the first photoresist pattern (14) can then be removed. The etching process may include a dry etching process or a reactive ion etching process. The first photoresist pattern (14) can be removed from the substrate (10) using an ashing process or a stripping process.

[0045] The patterned first mask (12) may have a shape composed of multiple lines that are partially broken on the cell region (CELL). For example, any one patterned first mask (12) may have one or more first openings (12h1). The substrate (10) may be exposed through the first openings (12h1). The first openings (12h1) may be cutting regions that separate the patterned first mask (12) into multiple lines extending along the third direction (D3). Accordingly, the first mask (12) on the cell region (CELL) may have a discontinuous shape cut by the first openings (12h1).

[0046] The patterned first mask (12) may have a shape identical or similar to the first photoresist pattern (14) on the core region (CORE). For example, the patterned first mask (12) may have a separated shape that exposes parts of the substrate (10). The patterned first mask (12) may include a plurality of second openings (12h2). The second openings (12h2) may be spaced apart along the second direction (D2), and each of the second openings (12h2) may extend along the first direction (D1) to expose a part of the substrate (10). Each of the second openings (12h2) may have the same or nearly constant width along the first direction (D1). The description of the first mask (12) described above with reference to FIG. 1a may be applied identically or similarly to the patterned first mask (12).

[0047] Referring to FIGS. 6a and 6b, a second mask (16) can be formed on a substrate (10), and a second photoresist pattern (18) can be formed on the second mask (16). The second mask (16) may have a plate shape that completely covers the cell region (CELL) and the core region (CORE). The second mask (16) may be formed from an oxide film, a nitride film, an amorphous carbon layer, or a combination thereof by atomic layer deposition (ALD), chemical vapor deposition (CVD), spin coating, etc. The second mask (16) may have an etching selectivity ratio with respect to the patterned first mask (12).

[0048] The second photoresist pattern (18) may be formed on the cell region (CELL) and the core region (CORE). For example, the second photoresist pattern (18) may have an integrated shape that exposes parts of the second mask (16) on the cell region (CELL), and a separated shape that exposes parts of the second mask (16) on the core region (CORE).

[0049] The second photoresist pattern (18) on the cell area (CELL) may include a plurality of first openings (18h1). The first openings (18h1) may be spaced apart along a first direction (D1) or a second direction (D2). Each of the first openings (18h1) may have a square, circular, elliptical, polygonal, or various other shapes that expose a portion of the second mask (16). The first openings (18h1) of the second photoresist pattern (18) may be staggered along the first direction (D1) or the second direction (D2) with respect to the first openings (12h1) of the patterned first mask (12). For example, when viewed in a planar view, the first openings (18h1) of the photoresist pattern (18) may not overlap with the first openings (12h1) of the patterned first mask (12).

[0050] A second photoresist pattern (18) on a core region (CORE) may include a plurality of second openings (18h2). The second openings (18h2) may be spaced apart along a second direction (D2), and each of the second openings (18h2) may extend along a first direction (D1) to expose a portion of the second mask (16). Some of the second openings (18h2) may have a width that is equal or nearly constant along the first direction (D1). Other of the second openings (18h2) may have a width that is equal or nearly constant along the first direction (D1) and may extend at both ends.

[0051] Referring to FIGS. 7a and 7b, the second mask (16) can be patterned by an etching process using the second photoresist pattern (18) as an etching mask, and the second photoresist pattern (18) can then be removed. The etching process may include a dry etching process or a reactive ion etching process. The second photoresist pattern (18) can be removed from the substrate (10) by an ashing process or a stripping process.

[0052] The patterned second mask (16) may have a plate shape, for example, having a plurality of first openings (16h1) on the cell region (CELL). The patterned first mask (12) may be exposed through the first openings (16h1).

[0053] The first openings (16h1) may be spaced apart along the first direction (D1) or the second direction (D2). Each of the first openings (16h1) may have a square, circular, elliptical, polygonal, or various other shapes that expose a portion of the patterned first mask (12). The first openings (16h1) of the patterned second mask (16) may be staggered along the first direction (D1) or the second direction (D2) with respect to the first openings (12h1) of the patterned first mask (12). For example, when viewed in a planar view, the first openings (16h1) of the patterned second mask (16) may not overlap with the first openings (12h1 in FIG. 5a) of the patterned first mask (12).

[0054] The patterned second mask (16) may have a shape identical or similar to the second photoresist pattern (18) on the core region (CORE). For example, the patterned second mask (16) may have a separated shape that exposes parts of the patterned first mask (12). The patterned second mask (16) may include a plurality of second openings (16h2). The second openings (16h2) may be spaced apart along the second direction (D2), and each of the second openings (16h2) may extend along the first direction (D1) to expose parts of the patterned first mask (12). Some of the second openings (16h2) may have the same or nearly constant width along the first direction (D1). Some of the other second openings (16h2) have a width that is equal or nearly constant along the first direction (D1) and can be extended at both ends. The description of the second mask (16) given above with reference to FIG. 1b can be applied in the same or similar way to the patterned second mask (16).

[0055] In other embodiments, instead of forming a second mask (16) and a second photoresist pattern (18) on a substrate (10) on which a patterned first mask (12) is formed as described in FIGS. 6a and 6b, a second photoresist pattern (18) may be formed on a substrate (10) on which a patterned first mask (12) is formed as shown in FIGS. 8a and 8b. The second photoresist pattern (18) may have an integrated shape including a plurality of first openings (18h1) that expose portions of the patterned first mask (12) on a cell region (CELL). The photoresist pattern (18) may have a separated shape including a plurality of second openings (18h2) that expose portions of the first mask (12) on a core region (CORE). The description of the other second photoresist pattern (18) may be the same or similar as described in FIGS. 6a and 6b.

[0056] Referring to FIGS. 9a and 9b, the patterned first mask (12) can be patterned by an etching process using the patterned second mask (16) shown in FIGS. 7a and 7b as an etching mask, and the patterned second mask (16) can be removed. As another example, the patterned first mask (12) can be patterned by an etching process using the second photoresist pattern (18) shown in FIGS. 8a and 8b as an etching mask. In this way, a mask pattern (12p) can be formed on the substrate (10) by two patternings of the first mask (12).

[0057] The mask pattern (12p) on the cell region (CELL) may have an island shape. For example, the patterned first mask (12) exposed at the first opening (16h1) of the patterned second mask (16) described in FIGS. 7a and 7b may be removed. On the cell region (CELL), the first mask (12) may have a discontinuous shape as shown in FIGS. 5a and 5b by removing the portion exposed at the first opening (14h1) of the first photoresist pattern (14) described in FIGS. 4a and 4b. Furthermore, the patterned first mask (12) may have the portion exposed by the first opening (16h1) of the patterned second mask (16) described in FIGS. 7a and 7b removed. Accordingly, the first mask (12) on the cell region (CELL) may be changed to an island-shaped mask pattern (12p).

[0058] The mask pattern (12p) on the core region (CORE) may have various shapes. For example, as previously described with reference to FIG. 1d, the mask pattern (12p) may include at least one sub-pattern (12a) having a rectangular or similar shape, at least one sub-pattern (12b) having a dumbbell or similar shape, at least one sub-pattern (12c) having a comb or similar shape, and at least one sub-pattern (12d) having a square or similar shape.

[0059] The mask pattern (12p) on the core region (CORE) may not include rounded corners because it is composed of an overlapping portion (15) in which the first mask (12) and the second mask (16) are overlapped, as described above with reference to FIG. 1e. For example, each of the sub-patterns (12a-12d) of the mask pattern (12p) may include sharp corners.

[0060] Referring to FIGS. 10a and 10b, a substrate (10) can be patterned by an etching process using a mask pattern (12p) as an etching mask to form a trench (13) that defines active patterns (11). The active pattern (11) on the cell region (CELL) may have an island shape that is extended along a third direction (D3) and arranged regularly. As another example, the active pattern (11) on the cell region (CELL) may have a shape that is extended discontinuously or continuously along any one of the first, second, and third directions (D1, D2, D3).

[0061] The active pattern (11) on the core region (CORE) may include at least one active pattern (11a) having a rectangular or similar shape, at least one active pattern (11b) having a dumbbell or similar shape, at least one active pattern (11c) having a comb or similar shape, and at least one active pattern (11d) having a square or similar shape, as described above with reference to FIG. 1g. These active patterns (11a, 11b, 11c, 11d) may be spaced apart in a first direction (D1) and / or a second direction (D2).

[0062] Any one or more of the first, second, and third regions (CORE1, CORE2, CORE3) of the core region (CORE) may include any one or more of the active patterns (11a, 11b, 11c, 11d). Alternatively, any one or more of the first, second, and third regions (CORE1, CORE2, CORE3) of the core region (CORE) may include two or more of the active patterns (11a, 11b, 11c, 11d), and the two or more active patterns may have the same shape or different shapes.

[0063] For example, a rectangular active pattern (11a) and / or a square active pattern (11d) may be mainly formed in the first region (CORE1) of the core region (CORE). In the second region (CORE2) of the core region (CORE), a dumbbell-shaped active pattern (11b) may be mainly formed. In the third region (CORE3) of the core region (CORE), a comb-shaped active pattern (11c) and / or a square active pattern (11d) may be mainly formed. However, the present invention is not limited thereto.

[0064] Referring to FIGS. 11a and 11b, a trench (13) can be filled with an insulating material to form a device isolation film (17). By doing so, a semiconductor device can be implemented on a substrate (10) by forming word lines crossing active patterns (11), bit lines intersecting the word lines, various conductive patterns electrically connected to the word lines and bit lines, and various insulating films. The semiconductor device that can be implemented on the substrate (10) is not of any type. For example, the semiconductor device may include a memory device, a logic device, and a combination thereof. This will be described later with reference to FIGS. 13a and 13b.

[0065] As previously mentioned with reference to FIG. 1e, in addition to forming a mask pattern (12p) or active pattern (11) having sharp corners by utilizing the overlap portion (15) between the first mask (12) and the second mask (16), a mask pattern (12p) or active pattern (11) with a further reduced limit of critical dimension (CD) can be formed. This will be described later with reference to FIG. 12a to 12e.

[0066] FIGS. 12a to 12d are cross-sectional views illustrating a substrate patterning method according to embodiments of the present invention. FIG. 12e is a plan view illustrating a substrate patterning method according to embodiments of the present invention.

[0067] Referring to FIG. 12a, a first mask (12) can be formed on a substrate (10), and a first photoresist pattern (14) can be formed on the first mask (12). An etching target film may be provided instead of the substrate (10), or an etching target film may be formed on the substrate (10). The first mask (12) can be patterned by an etching process using the first photoresist pattern (14) as an etching mask.

[0068] Referring to FIG. 12b, a first mask (12) patterned on a substrate (10) can be formed by the etching process. The patterned first mask (12) may have a first width (W1). A second mask (16) covering the first mask (12) patterned on the substrate (10) may be formed, and a second photoresist pattern (18) may be formed on the second mask (16). The second photoresist (18) may have a shape that covers a portion of the patterned first mask (12).

[0069] Referring to FIG. 12c, the second mask (16) can be patterned by an etching process using the second photoresist pattern (18) as an etching mask. The patterned second mask (16) can cover a part of the patterned first mask (12) and expose another part. The patterned first mask (12) can be patterned by an etching process using the patterned second mask (16) as an etching mask.

[0070] Referring to FIG. 12d, a first mask (12) patterned twice, i.e., a mask pattern (12p), can be formed by the etching process. The mask pattern (12p) may have a second width (W2) that is smaller than the first width (W1) of the patterned first mask (12). For example, the mask pattern (12p) may have a second width (W2) that exceeds the limit of the minimum dimension.

[0071] For example, referring to FIG. 12e, even if the first width (W1) of the first mask (12) is the minimum dimension that can be implemented, the portion where the first mask (12) and the second mask (16) overlap can be formed as a mask pattern (12p). Accordingly, the mask pattern (12p) can have a second width (W2) that exceeds the minimum limit that can be implemented by patterning.

[0072] Referring again to FIG. 12d, the substrate (10) can be patterned by an etching process using a mask pattern (12p) as an etching mask. Through this patterning, an active pattern (11) having a second width (W2) can be formed on the substrate (10). The patterning method described with reference to FIG. 12a to 12e can be applied in the same or similar manner as described above to form not only the active pattern (11) but also all patterns.

[0073] FIG. 13a is a plan view illustrating a semiconductor device including an active pattern of a substrate according to embodiments of the present invention. FIG. 13b is a cross-sectional view illustrating a semiconductor device including an active pattern of a substrate according to embodiments of the present invention, taken by cutting along lines I1-I2, I3-I4, and I5-I6 of FIG. 13a.

[0074] Referring to FIGS. 13a and 13b, a semiconductor device (1000) may be provided. The semiconductor device (1000) may be a memory device such as a DRAM. Word lines (WL) may be provided on a cell region (CELL) of a substrate (10) having active patterns (11) defined by a device isolation film (17), and peripheral word lines (WLp) may be provided on a core region (CORE) of the substrate (10). The word lines (WL) may be spaced apart in a second direction (D2) and may extend along a first direction (D1). The word lines (WL) may have a form embedded within the substrate (10). Gate insulating films (307) may be provided below the word lines (WL).

[0075] A first doping region (312a) may be disposed within an active pattern (11) between a pair of word lines (WL), and a pair of second doping regions (312b) may be disposed within both edges of the active pattern (11). The first and second doping regions (312a, 312b) may be doped with, for example, N-type impurities. The first doping region (312a) may correspond to a common drain region, and the second doping regions (312b) may correspond to source regions. The word lines (WL) and the first and second doping regions (312a, 312b) adjacent thereto may form a transistor.

[0076] Wordline capping patterns (310) may be placed on corresponding wordlines (WL). The wordline capping pattern (310) may have a line shape that extends along the length direction of the wordline (WL). An interlayer insulating film (305) may be placed on the substrate (301). The interlayer insulating film (305) may be formed in the shape of islands spaced apart from each other in a planar manner.

[0077] Bitlines (BL) may be disposed on an interlayer insulating film (305). Bitlines (BL) may cross wordline capping patterns (310) and wordlines (WL). Bitlines (BL) may be spaced apart along a first direction (D1) and may extend along a second direction (D2). Bitlines (BL) may include a stacked bitline polysilicon pattern (330), a bitline ohmic pattern (331), and a bitline metal-containing pattern (332). Bitline capping patterns (337) may be disposed on each of the bitlines (BL). The bitline capping patterns (337) may be formed of an insulating material such as a silicon nitride film.

[0078] Bitline contacts (DC) partially embedded within the substrate (10) may be provided between adjacent wordlines (WL). The bitline contacts (DC) may electrically connect the first doping region (312a) and the bitline (BL). A lower embedded insulating film (341) may be placed on the side of the bitline contacts (DC).

[0079] Storage node contacts (BC) may be placed between adjacent pairs of bit lines (BL). The storage node contacts (BC) may be spaced apart from each other. The storage node contacts (BC) may comprise polysilicon that is doped with impurities or not doped. A bit line spacer (SP) may be interposed between the bit line (BL) and the storage node contact (BC). The bit line spacer (SP) may include a first sub-spacer (321) and a second sub-spacer (325) spaced apart from each other by an air gap (AG). The first sub-spacer (321) may cover the sidewall of the bit line (BL) and the sidewall of the bit line capping pattern (337). The second sub-spacer (325) may be adjacent to the storage node contact (BC). The first sub-spacer (321) and the second sub-spacer (325) may include the same material, such as a silicon nitride film.

[0080] A storage node ohmic layer (309) may be disposed on the storage node contact (BC). The storage node ohmic layer (309) may include a metal silicide. The storage node ohmic layer (309), the first and second sub-spacers (321, 325), and the bitline capping pattern (337) may be conformally covered by a diffusion prevention pattern (311a). The diffusion prevention pattern (311a) may include a metal nitride such as a titanium nitride film or a tantalum nitride film. A landing pad (LP) may be disposed on the diffusion prevention pattern (311a).

[0081] The landing pad (LP) may be formed of a metal-containing material such as tungsten. The upper portion of the landing pad (LP) may have a wider width than the storage node contact (BC). The center of the landing pad (LP) may be shifted from the center of the storage node contact (BC). A first capping pattern (358a) and a second capping pattern (360a) may be provided between adjacent landing pads (LP). The first and second capping patterns (358a, 360a) may each independently include a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a porous film. The porosity of the first capping pattern (358a) may be greater than the porosity of the second capping pattern (360a).

[0082] The air gap (AG) between the first and second sub-spacers (321, 325) may extend between the landing pads (LP). The first capping pattern (358a), the bitline capping pattern (337), and the landing pad (LP) may be partially exposed by the air gap (AG).

[0083] Lower electrodes (BE) may be disposed on each of the landing pads (LP). The lower electrode (BE) may include at least one of impurity-doped polysilicon, a metal nitride film such as titanium nitride, and a metal film such as tungsten, aluminum, and copper. The lower electrode (BE) may have a cylindrical shape, a hollow cylinder, or a cup shape. The upper sidewalls of adjacent lower electrodes (BE) may be connected by a support pattern (374a). The support pattern (374a) may include an insulating material such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film.

[0084] The first and second capping patterns (358a, 360a) between the lower electrodes (BE) may be covered with an etch stop layer (370). The etch stop layer (370) may include an insulating material such as, for example, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. The surface of the lower electrodes (BE) and the surface of the support pattern (374a) may be covered with a dielectric film (DL). The dielectric film (DL) may be covered with an upper electrode (TE). The upper electrode (TE) may include at least one of a metal nitride film such as an impurity-doped polysilicon film, an impurity-doped silicon germanium film, or a titanium nitride film, and a metal film such as tungsten, aluminum, and copper. The lower electrode (BE), the dielectric film (DL), and the upper electrode (TE) may form a capacitor (CAP).

[0085] On the core region (CORE) of the substrate (10), the surrounding word line (WLp) may include a gate insulating film (411), a first electrode (413), a second electrode (415), and a spacer (417) surrounding the first and second electrodes (413, 415). For example, the first electrode (413) may include polysilicon, and the second electrode (415) may include tungsten. An interlayer insulating film (421) may cover the substrate (10) of the core region (CORE). Contact plugs (431) electrically connected to the substrate (10) by penetrating the interlayer insulating film (421), and wiring (435) electrically connected to the contact plugs (431) and provided on the interlayer insulating film (421) may be provided.

[0086] An additional interlayer insulating film (441) may be further provided on the interlayer insulating film (421). Although not illustrated, additional contact plugs penetrating the additional interlayer insulating film (441) and additional wiring disposed on the additional interlayer insulating film (441) and electrically connected to the additional contact plugs may be further provided.

[0087] According to the embodiments, the active patterns (11) on the core region (CORE) may have sharp corners with no or reduced corner rounding. Therefore, an increase in the size of the active patterns (11) due to corner rounding and contact between adjacent corners can be prevented. As a result, the integration density of the active patterns (11) and the electrical characteristics of the semiconductor device (1000) can be improved.

[0088] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments and may be used in various other combinations, modifications, and environments without departing from the essence of the invention. The appended claims should be interpreted as including other embodiments.

Claims

Claim 1 A semiconductor device comprising: a substrate having an active pattern; a cell region provided on the substrate and having a cell circuit; and a core region provided on the substrate and having a peripheral circuit, wherein the core region includes a first core region, a second core region, and a third core region surrounding the cell region, and, when viewed in a planar view, the active pattern on the core region includes corners, and the active pattern on the core region includes: a first active pattern having a square shape disposed on the first core region; a second active pattern having a dumbbell shape disposed on the second core region; and a third active pattern having a comb shape disposed on the third core region, wherein each of the corners has a rounding index of 15 nm or less, which is the distance between the corner tip when the corner is not rounded and the corner tip when the corner is rounded, and, when viewed in a planar view, the active pattern on the cell region has an island shape that extends in a certain direction and is regularly arranged. Claim 2 A semiconductor device according to claim 1, wherein the rounding index of each of the corners is in the range of 5 nm to 15 nm. Claim 3 A semiconductor device according to claim 1, wherein the rounding index of each of the corners is 0. Claim 4 delete Claim 5 A semiconductor device according to claim 1, wherein either of the first and second core regions includes a sense amplifier circuit, and the other of the first and second core regions includes a sub-wordline driver circuit. Claim 6 A semiconductor device according to claim 1, wherein each of the corners has a corner angle of 90 degrees. Claim 7 A semiconductor device according to claim 1, further comprising a peripheral region provided on the substrate and having a peripheral circuit, wherein the active pattern on the core region is relatively denser than the active pattern on the peripheral region. Claim 8 A semiconductor device according to claim 1, wherein the core region comprises: first core regions having identical first peripheral circuits provided on mutually facing sides of the cell region; and second core regions having identical second peripheral circuits provided on mutually facing sides of the cell region. Claim 9 A semiconductor device according to claim 8, wherein the cell circuit includes a memory circuit, the first peripheral circuit includes a sense amplifier circuit, and the second peripheral circuit includes a sub-wordline driver circuit. Claim 10 A semiconductor device comprising a substrate including a cell region and a core region; and an active pattern provided on each of the cell region and the core region, wherein the core region is divided into a plurality of regions including a first core region, a second core region, and a third core region surrounding the cell region, and, when viewed in a planar view, the active pattern on each of the plurality of regions includes corners, and the active pattern of the core region includes: a first active pattern having a square shape disposed on the first core region; a second active pattern having a dumbbell shape disposed on the second core region; and a third active pattern having a comb shape disposed on the third core region, wherein each of the corners has a rounding index of 15 nm or less, which is the distance between the corner tip when the corner is not rounded and the corner tip when the corner is rounded, and, when viewed in a planar view, the active pattern on the cell region has an island shape that extends in a certain direction and is regularly arranged. Claim 11 delete Claim 12 In claim 10, a semiconductor device provided with one or more of the above-mentioned first to third active patterns. Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 A semiconductor substrate comprising a cell region provided with a memory circuit and a core region provided with a peripheral circuit; a plurality of cell active patterns provided on the cell region and having the same shape as each other, wherein the cell active patterns, when viewed planarly, have an island shape that extends in a certain direction and is regularly arranged; and a plurality of peripheral active patterns including corners provided on the core region, wherein the core region includes a first core region, a second core region, and a third core region surrounding the cell region, and the peripheral active patterns include: a first active pattern having a rectangular shape disposed on the first core region; a second active pattern having a dumbbell shape disposed on the second core region; A semiconductor device comprising a third active pattern having a comb shape disposed on the third core region, wherein each of the peripheral active patterns has angular corners when viewed in a planar view, and each of the corners has a rounding index of 15 nm or less, which is the distance between the corner tip when the corner is not rounded and the corner tip when the corner is rounded, and when viewed in a planar view, the cell active pattern on the cell region has an island shape that is extended in a certain direction and is regularly arranged. Claim 19 In paragraph 18, the above peripheral active patterns are semiconductor devices having shapes different from the island shape. Claim 20 delete

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