Display device and operating method of display device

Abstract

A display device comprises: a memory; a display panel comprising an under-display camera (UDC) region and a non-under-display camera (UDC) region including a plurality of sub-regions; and an image processor configured to receive image data, select at least one first filter corresponding to each of the plurality of sub-regions based on spatial coordinate values ​​for the received image data, and perform a first pixel rendering for the UDC region using the at least one first filter, wherein the at least one first filter may be generated based on a pixel placement pattern.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to a semiconductor device, and in particular to a display device for controlling pixel rendering of image data in a display device including a camera module, and a method of operating the display device. Background Technology

[0002] A display device includes a display panel that displays an image, a display driving circuit that drives the display panel, and a processor. The processor can transmit image data and control pixel rendering for the image data. Recently, as the demand for multimedia devices increases, the use of various display devices with built-in camera modules is increasing.

[0003] In the case of the UDC area within the display area, a camera module may be placed beneath the display panel. In this case, in order to enable the capture of a subject through a portion of the display activation area within the UDC area, the configuration or pixel placement structure of the pixels in the UDC area may differ from that of the non-UDC area. The problem to be solved

[0004] The problem that the technical concept of the present disclosure aims to solve is to provide a display device and a method of operating the display device to prevent image quality degradation in the UDC (Under display camera) area and to prevent the waste of hardware resources due to redundant pixel rendering. means of solving the problem

[0005] A display device according to an exemplary embodiment of the present disclosure for solving the above technical problem comprises: a memory; a display panel comprising an under-display camera (UDC) region and a non-under-display camera (UDC) region including a plurality of sub-regions; and an image processor configured to receive image data, select at least one first filter corresponding to each of the plurality of sub-regions based on spatial coordinate values ​​for the received image data, and perform a first pixel rendering for the UDC region using the at least one first filter, wherein the at least one first filter may be generated based on a pixel placement pattern.

[0006] A method of operation of a display device according to an exemplary embodiment of the present disclosure for solving the above technical problem comprises: the display device including a display panel composed of an under-display camera (UDC) area and a non-under-display camera (UDC) area including a plurality of sub-regions; receiving image data; selecting at least one first filter corresponding to each of the plurality of sub-regions based on spatial coordinate values ​​of the received image data; and performing a first pixel rendering for the UDC area using the at least one first filter, wherein the at least one first filter may be generated based on a pixel arrangement pattern.

[0007] A display device according to another exemplary embodiment of the present disclosure for solving the above technical problem may be configured to include: a display panel comprising an under-display camera (UDC) area and a non-under-display camera (UDC) area including a plurality of sub-areas; and an image processor configured to utilize a first rendering path for the UDC area and a second rendering path for the non-UDC area in parallel, and to perform dithering for the UDC area based on a pixel arrangement pattern of the UDC area. Effects of the invention

[0008] According to the display device, the display system including the same, and the method of operation of the display device according to exemplary embodiments of the present disclosure, pixel rendering is performed by sub-region based on the structural characteristics of the display panel, thereby improving the problem of image quality degradation in the UDC area. By performing pixel rendering specialized for the UDC area independently of the non-UDC area, the waste of hardware resources caused by redundant pixel rendering can be prevented.

[0009] In addition, the display device can reduce the screen door effect by reducing aliasing of the output image data through dithering on the image data for which pixel rendering has been performed. Brief explanation of the drawing

[0010] FIG. 1 is a block diagram showing a display system according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram showing a display driving circuit according to an exemplary embodiment of the present disclosure. FIG. 3 is a block diagram for explaining the display panel of FIG. 1 and the method of operation of the display panel. Figure 4 is a circuit diagram showing one implementation example of the pixel of Figure 3. FIG. 5 is a flowchart illustrating a method of operation of a display device according to an exemplary embodiment of the present disclosure. FIG. 6 is a flowchart illustrating the dithering operation of a display device according to an exemplary embodiment of the present disclosure. FIG. 7 is a flowchart illustrating a second pixel rendering operation of a display device according to an exemplary embodiment of the present disclosure. FIG. 8 is a flowchart illustrating a third pixel rendering operation of a display device according to an exemplary embodiment of the present disclosure. FIG. 9 is a block diagram showing rendering operations performed in parallel in a display device according to an exemplary embodiment of the present disclosure. FIG. 10 is a block diagram showing masking operations in a display device according to an exemplary embodiment of the present disclosure. FIG. 11 is a block diagram showing a display system and a brightness control method according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0011] Various embodiments of the present disclosure are described below in conjunction with the accompanying drawings. The terms used in the present disclosure are used merely to describe specific embodiments and are not intended to limit the scope of other embodiments. A singular expression may include a plural expression unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as generally understood by those skilled in the art as described in the present disclosure.

[0012] FIG. 1 is a block diagram showing a display system according to an exemplary embodiment of the present disclosure.

[0013] A display system (1000) according to an exemplary embodiment of the present disclosure may be mounted on an electronic device having an image display function. For example, the electronic device may include a smartphone, a tablet personal computer, a portable multimedia player (PMP), a camera, a wearable device, an internet of things device, a television, a digital video disk (DVD) player, a refrigerator, an air conditioner, an air purifier, a set-top box, a robot, a drone, various medical devices, a navigation device, a global positioning system receiver (GPS receiver), an Advanced Driver Assistance System (ADAS), a vehicle device, furniture, or various measuring instruments.

[0014] Referring to FIG. 1, a display system (1000) may include a processor (100), a display driving circuit (200) (or referred to as a display driving integrated circuit), and a display panel (300). In an embodiment, the display driving circuit (200) and the display panel (300) may be implemented as a single module, and the module may be referred to as a display device.

[0015] The processor (100) can control the display system (1000) overall. The processor (100) can generate image data (IDT) to be displayed on the display panel (300) and transmit the image data (IDT) and control commands (CMD) to the display driving circuit (200). The processor (100) may be a graphics processor. However, it is not limited thereto, and the processor (100) may be implemented as various types of processors such as a CPU (Central Processing Circuit), a microprocessor, a multimedia processor, an application processor, etc. In an embodiment, the processor (100) may be implemented as an integrated circuit (IC) and may be implemented as a mobile AP (Application Processor) or a SoC (system on chip).

[0016] Although not shown, the processor (100) may include a pixel rendering circuit and a dithering circuit.

[0017] Although not illustrated, a filter for pixel rendering or a mask for dithering may be generated in advance based on a pixel placement pattern for each of the multiple sub-regions of the Under Display Camera (UDC) area. An external device may generate a filter or mask for each sub-region in advance based on a pixel placement pattern for each of the multiple sub-regions of the display panel (300). For example, the pixel placement pattern may be determined based on the placement structure between emitting pixels and non-emitting pixels for each of the multiple sub-regions of the UDC area. For pixel rendering, the generated filter or mask may be stored in the memory of the display device along with corresponding spatial coordinate values. In this specification, a non-emitting pixel may correspond to a pixel that does not emit light because it is structurally and functionally constrained by a camera module in the UDC area. A non-emitting pixel may have a configuration that is lacking compared to an emitting pixel. In some embodiments, a non-emitting pixel may have the same configuration as an emitting pixel, but its light emission may be limited.

[0018] In an embodiment, the pixel rendering circuit may select a filter to be used for pixel rendering based on the spatial coordinate values ​​of the received image data. In this specification, selecting a filter may mean determining a filter index based on the spatial coordinate values ​​of the image data. The selected filter may refer to a filter corresponding to the spatial coordinate values ​​of the received image data among a plurality of pre-generated filters. The pixel rendering circuit may perform pixel rendering using the selected filter. For example, a first pixel rendering may be performed using a first filter selected for a plurality of sub-regions of the UDC region, and a second pixel rendering may be performed using a second filter selected for the non-UDC region.

[0019] In an embodiment, the pixel rendering circuit may be configured to perform a first pixel rendering and a second pixel rendering in parallel.

[0020] In an embodiment, the dithering circuit (60) may select a mask to perform dithering from among pre-generated masks based on the spatial coordinate values ​​of the received image data. The selected mask may refer to a mask corresponding to the spatial coordinate values ​​of the received image data among a plurality of pre-generated masks. The dithering circuit may perform dithering by setting a predetermined frequency offset for each of the plurality of sub-regions using the selected mask.

[0021] The display panel (300) is a display unit that displays an actual image and may be one of a display device that receives an electrically transmitted image signal and displays a two-dimensional image, such as a thin film transistor-liquid crystal display (TFT-LCD), an organic light emitting diode display (OLED), a field emission display, or a plasma display panel (PDP). In an embodiment, the display panel (300) may be an OLED display panel in which each pixel includes an organic light emitting diode (OLED). However, it is not limited thereto, and the display panel (300) may be implemented as a different type of flat panel display or flexible display panel.

[0022] The display driving circuit (200) converts image data (IDT) received from the processor (100) into video signals for driving the display panel (300), and supplies the converted video signals to the display panel (300), thereby enabling the display panel (300) to display an image.

[0023] Meanwhile, depending on the operation mode of the display driving circuit (200) (e.g., front camera operation mode), an image may be displayed in the Under Display Camera (UDC) area (310) of the display panel (300). The UDC area (310) may refer to an area where a camera module is placed below the display panel (300). For example, the UDC area (310) may refer to an area where the camera module is visually exposed through at least a portion of the display panel (300) in a display system (1000) that includes the camera module. As another example, the camera module may be configured such that at least a portion is placed below the display module (300) and that a subject can be captured through a portion of the active area of ​​the display module (300). As yet another example, the camera module may not be visually exposed on the area of ​​the display module (300). The non-UDC area (320) may refer to at least a portion of the remaining area of ​​the display panel (300) excluding the UDC area (310).

[0024] The UDC area (310) does not mean a fixed area on the display panel (300), and the position, size, number, etc. of the camera module on the display panel (300) may change over time or depending on operating conditions, etc.

[0025] In FIG. 1, the display panel (300) is shown as being composed of a UDC region and a non-UDC region, but the embodiments of the present disclosure are not limited thereto. In the embodiments, the display panel (300) may further include a boundary region between the UDC region and the non-UDC region.

[0026] FIG. 2 is a block diagram showing a display driving circuit according to an exemplary embodiment of the present disclosure.

[0027] Referring to FIG. 2, the display driving circuit (200) may include an interface circuit (210), control logic (220), memory (230), data driver (240), gamma voltage generator (250), scan driver (260), and light emission control driver (270). In an embodiment, the interface circuit (210), control logic (220), memory (230), data driver (240), gamma voltage generator (250), scan driver (260), and light emission control driver (270) may be integrated on a single semiconductor chip. Alternatively, the interface circuit (210), control logic (220), memory (230), data driver (240), and gamma voltage generator (250) may be formed on a single semiconductor chip, and the scan driver (260) and light emission control driver (270) may be formed on a display panel (300 in FIG. 1). For example, a display panel (300) can be produced by forming an amorphous silicon layer on a glass substrate and then undergoing a Low Temperature Poly Silicon (LTPS) process, and the thin-film transistors of such an LTPS display panel have fast response speed and uniformity. A plurality of transistors can be formed using the poly silicon formed by the LTPS process, and a scan driver (260) and a light-emitting control driver (270) can be formed on the display panel (300) using the plurality of transistors.

[0028] The processor (100) may include a pixel rendering circuit (40) and a dithering circuit (60). For example, a filter or mask for pixel rendering may be generated in advance based on a pixel placement pattern of the UDC area. The pre-generated filter for pixel rendering or mask for dithering may be stored in the memory of the display device along with corresponding spatial coordinate values.

[0029] The pixel placement pattern for each sub-region can be determined based on at least one of the placement structure between emitting pixels and non-emitting pixels in each sub-region, the amount of pixel loss in the UDC region compared to the non-UDC region, the amount of pixel size change, and the amount of pixel position change.

[0030] In an embodiment, the pixel rendering circuit may select a filter used for pixel rendering based on the spatial coordinate values ​​of the received image data. In this specification, selecting a filter may mean determining a filter index based on the spatial coordinate values ​​of the image data. The selected filter may mean a filter corresponding to the received spatial coordinate values ​​among a plurality of pre-generated filters.

[0031] The pixel rendering circuit can perform pixel rendering using a selected filter. For example, a first pixel rendering can be performed using a first filter selected for each of the multiple sub-regions of the UDC area, and a second pixel rendering can be performed using a second filter selected for the non-UDC area.

[0032] In an embodiment, the pixel rendering circuit may be configured to perform a first pixel rendering and a second pixel rendering in parallel.

[0033] In an embodiment, the dithering circuit may select a mask to perform dithering from among pre-generated masks based on the spatial coordinate values ​​of the received image data. The selected mask may refer to a mask among a plurality of pre-generated masks that corresponds to the spatial coordinate values ​​of the received image data.

[0034] In an embodiment, the dithering circuit can perform dithering by setting a predetermined frequency offset for each of a plurality of sub-regions using a selected mask.

[0035] In an exemplary embodiment, the pixel rendering circuit (40) and the dithering circuit (60) may be implemented as part of the processor (100). However, not limited thereto, the pixel rendering circuit (40) and the dithering circuit (60) may be implemented as logic circuits separate from the processor (100).

[0036] The interface circuit (210) can interface signals or data exchanged between the processor (100) and the display driving circuit (200). The interface circuit (210) can be implemented as one of a serial interface such as MIPI (Mobile Industry Processor Interface (MIPI®)), MDDI (Mobile Display Digital Interface), DisplayPort, or embedded DisplayPort (eDP).

[0037] The control logic (220) controls the overall operation of the display driving circuit (200) and can control the components of the display driving circuit (200), such as the interface circuit (210), memory (230), data driver (240), gamma voltage generator (250), scan driver (260), and light emission control driver (270), so that image data received from the processor (100) is displayed on the display panel (300). Additionally, the control logic (220) may perform image processing for the received image data, such as changing brightness, changing size, or changing format, or may generate new image data to be displayed on the display panel (300) based on the received image data.

[0038] The memory (230) can store image data received from the processor (100) in frames. The memory (230) may be referred to as a graphics RAM, a frame buffer, etc. The memory (230) may include volatile memory such as DRAM (dynamic random access memory) or SRAM (static random access memory), or non-volatile memory such as ROM, Flash memory, ReRAM (resistive random access memory), or MRAM (megnatic random access memory). The memory (230) can store filters used for pixel rendering for a UDC area that includes a plurality of sub-regions. For example, the memory may store at least one filter or mask that is used for pixel rendering for a UDC area and is generated in advance based on the pixel placement pattern of the UDC area.

[0039] In an embodiment, partial image frames including symbol image data (e.g., standardized numbers, letters, special characters, etc.) received from a processor (100) or standardized images such as a time screen or a date screen may be stored in the memory (230). However, it is not limited thereto, and the display driving circuit (200) may further include a separate memory physically separated from the memory (230), such as a symbol memory, and the symbol image data or partial image frames may be stored in the symbol memory.

[0040] The control logic (220) provides image data stored in memory (230) or image data received from the interface circuit (210) to the data driver (240) in line data units, that is, in pixel data units corresponding to one horizontal line of the display panel, and the data driver (240) includes a plurality of decoders that convert the received data into an image signal based on a plurality of gamma voltages (GVs) (or grayscale voltages) received from the gamma voltage generator (250), and a plurality of amplifiers each connected to the plurality of decoders, and can convert the line data into a plurality of image signals (D1~Dm) (m is an integer greater than or equal to 2) and output them to the display panel (300).

[0041] The gamma voltage generator (250) can generate a plurality of gamma voltages (GVs), for example, 256 gradations of gamma voltages (GVs), based on a set gamma curve, and provide the gamma voltages (GVs) to the data driver (240). The gamma voltage generator (250) can change the maximum gamma voltage and / or minimum gamma voltage and change the gamma curve under the control of the control logic (220), for example, according to the control register value.

[0042] The operation of the data driver (240), scan driver (260), and light emission control driver (270) will be explained with reference to FIG. 3.

[0043] FIG. 3 is a block diagram for explaining the display panel of FIG. 1 and the method of operation of the display panel. An OLED panel will be described as an example of a display panel (300).

[0044] Referring to FIG. 3, the display panel (300) may include a plurality of data lines (DL1~DLm), a plurality of scan lines (SL0~SLn), a plurality of light emission control lines (EL1~Eln), and a plurality of pixels (PX) disposed between the lines. Each of the plurality of pixels (PX) may be connected to a corresponding scan line (SL), data line (DL), and light emission control line (EL).

[0045] Each of the multiple pixels (PX) can output light of a preset color, and two or more pixels (PX) (e.g., red, blue, and green pixels) that are placed adjacent to each other on the same or adjacent lines and output light of different colors can constitute a single unit pixel. In this case, the two or more pixels (PX) constituting the unit pixel may be referred to as sub-pixels. The display panel (300) may have an RGB structure in which red, blue, and green pixels constitute a single unit pixel. However, it is not limited thereto, and the display panel (300) may have an RGBW structure in which the unit pixel further includes a white pixel for brightness enhancement. Alternatively, the unit pixel of the display panel (300) may be composed of a combination of pixels of colors other than red, green, and blue.

[0046] Meanwhile, in FIG. 3, for convenience of expression, a plurality of pixels (PX) are shown as being arranged in a certain pattern, but the pattern or configuration of the pixels in the UDC area may vary and may differ from the pattern or configuration of the pixels in the non-UDC area.

[0047] The scan driver (260) is connected to a plurality of scan lines (SL0~SL1) and sequentially applies a scan signal to the pixels (PX) line by line to sequentially select the pixels (PX).

[0048] The light emission control driver (270) is connected to a plurality of light emission control lines (EL1~ELn) and sequentially applies light emission control signals (E1~En) to pixels (PX) to control the light emission time of the pixels (PX).

[0049] As described with reference to FIG. 2, the scan driver (260) can generate a plurality of image signals (D1 to Dm in FIG. 2) and provide the plurality of image signals (D1 to Dm in FIG. 2) to pixels (PX) through each of the plurality of data lines (DL1 to DLm).

[0050] Figure 4 is a circuit diagram showing one implementation example of the pixel of Figure 3.

[0051] Referring to FIG. 4, the pixel (30) may include a pixel driver (31) and an OLED (32).

[0052] The pixel driver (31) can receive an image signal (Dm), a previous scan signal (Sn-1), a scan signal (Sn), and a light emission control signal (En) through a data line (DLm), a previous scan line (Sn-1), a scan line (Sn), and a light emission control line (ELn), and can receive a first power supply voltage (VDD) and a second power supply voltage (Vsus). A driving current corresponding to the image signal (Dm) can be supplied to the OLED (32) from the first power supply voltage (VDD).

[0053] The OLED (32) consists of an anode electrode, a cathode electrode, and an organic light-emitting layer. The anode electrode is connected to a pixel driver (31), and the cathode electrode is connected to a ground voltage (VSS). Accordingly, the OLED (32) can receive a driving current supplied from the pixel driver (31) and emit light with a luminous brightness corresponding to the amount of current.

[0054] As an example, as illustrated, the pixel driver (31) may be composed of first to fifth transistors (M1-M5) and two capacitors (Cst, Cvth). The first electrode of the first transistor (M1) is connected to the data line (DLm), and the gate terminal is connected to the scan line (SLn). Additionally, the first transistor (M1) is turned on in response to a scan signal (Sn) transmitted through the scan line (SLn) to transmit an image signal (Dm) received through the data line (DLm) to the two capacitors (Cst, Cvth).

[0055] A first power supply voltage (VDD) is applied to the first electrode of the second transistor (M2), and a driving current (I) corresponding to a voltage applied to the gate terminal, such as an image signal (Dm). OLED ) can be generated. The second transistor (M2) can be referred to as a driving transistor.

[0056] The third transistor (M3) is connected between the gate terminal of the second transistor (M2) and the second electrode, and is turned on by a scan signal (Sn-1) applied to the gate terminal connected to the previous scan line (SLn-1) to compensate for the gate turn voltage of the second transistor (M2), i.e., the driving transistor.

[0057] The first capacitor (Cvth) is connected between the second electrode of the first transistor (M1) and the gate terminal of the second transistor (M2) to store the threshold voltage (Vth) of the second transistor (M2).

[0058] The second capacitor (Cst) is connected between the first power supply voltage (VDD) and one end of the first capacitor and can store an image signal (Dm) transmitted through the data line (DLm).

[0059] The fourth transistor (M4) has its first electrode connected to the second power supply voltage (Vsus) and its second electrode connected in common to the first capacitor (Cvth) and the second capacitor (Cst). The second power supply voltage application transistor (M4) is turned on by a previous scan signal (Sn-1) applied to its gate terminal to apply the second power supply voltage (Vsus) to the first capacitor (Cvth) and the second capacitor (Cst).

[0060] The fifth transistor (M5) is connected between the second electrode of the second transistor (M2) and the anode electrode of the OLED (32), and performs an on / off operation according to the control of the light emission control signal (En) applied to the gate terminal, thereby supplying or blocking the driving current supplied from the second transistor (M2) to the OLED (32), so that the light emission time of the OLED (32) can be controlled.

[0061] Referring to FIG. 4, an embodiment of the pixel (30) has been described. However, this is merely one embodiment, and the structure of the pixel (30) can be varied.

[0062] FIG. 5 is a flowchart illustrating a method of operation of a display device according to an exemplary embodiment of the present disclosure.

[0063] Referring to FIG. 5, in step S11, the processor can receive image data. In an embodiment, the processor can receive image data including spatial coordinate values ​​for an area where an image is to be displayed on a display panel.

[0064] In step S13, the processor can identify whether the area to be displayed is included in the UDC area. In an embodiment, the processor can identify whether the area to be displayed is included in the UDC area of ​​the display panel by comparing the spatial coordinate values ​​of the previously stored display panel with the spatial coordinate values ​​of the received image data.

[0065] In step S15, if it is included in the UDC area, the processor can perform a first pixel rendering using a first filter selected based on the spatial coordinate values ​​of the image data.

[0066] Although not illustrated in FIG. 5, a filter for pixel rendering can be generated in advance based on a pixel placement pattern for each of the multiple sub-regions of the Under Display Camera (UDC) area. The first filter can correspond to each of the multiple sub-regions included in the UDC area.

[0067] The pixel placement pattern for each sub-region represents the structural characteristics of the display panel and can be determined based on at least one of the placement structure between emitting pixels and non-emitting pixels in each sub-region, the amount of pixel loss in the UDC region compared to the non-UDC region, the amount of change in pixel size, and the amount of change in pixel position. For pixel rendering, a pre-generated filter can be stored in the memory of the display device along with corresponding spatial coordinate values.

[0068] In an embodiment, the processor may select a filter having spatial coordinate values ​​that match the spatial coordinate values ​​of the received image data as a first filter. For example, the processor may select a first filter corresponding to the received image data from among a plurality of first filters that are pre-generated by searching for the spatial coordinate values ​​of the received image data in memory.

[0069] In an embodiment, the processor can perform a first pixel rendering by applying a selected first filter to image data in the UDC area.

[0070] In step S17, if it is included in a non-UDC region, the processor may perform a second pixel rendering of the image data using a second filter. In an embodiment, if it is identified as a non-UDC region, the processor may perform a second pixel rendering of the image data in the non-UDC region using a second filter corresponding to the spatial coordinate values ​​of the non-UDC region.

[0071] As an exemplary embodiment, a first pixel rendering for the UDC area and a second pixel rendering for the non-UDC area can be performed in parallel. By doing so, by performing a first pixel rendering specialized for the UDC area independently of the non-UDC area, unnecessary pixel rendering can be prevented, thereby preventing image quality degradation and waste of hardware resources.

[0072] Although not explicitly stated, selecting a filter in this specification may be interpreted as determining filter coefficients based on the spatial coordinate values ​​of the image data.

[0073] FIG. 6 is a flowchart illustrating the dithering operation of a display device according to an exemplary embodiment of the present disclosure.

[0074] Referring to Fig. 6, in step S31, the processor can select a mask based on the spatial coordinate values ​​of the image data.

[0075] Although not shown in FIG. 6, a mask for dithering can be generated in advance based on a pixel placement pattern for each of the multiple sub-regions of the UDC (Under display camera) area. The mask for each sub-region can correspond to each of the multiple sub-regions.

[0076] The pixel placement pattern for each sub-region represents the structural characteristics of the display panel and can be determined based on at least one of the placement structure between emitting pixels and non-emitting pixels in each sub-region, the amount of pixel loss in the UDC region compared to the non-UDC region, the amount of pixel size change, and the amount of pixel position change. A mask generated in advance for dithering can be stored in the memory of the display device along with the spatial coordinate values ​​of the corresponding sub-region.

[0077] In an embodiment, the processor may select a mask having spatial coordinate values ​​that match the spatial coordinate values ​​of the received image data. For example, the processor may select a mask corresponding to the received image data from among a plurality of pre-generated masks by searching for the spatial coordinate values ​​of the received image data in memory.

[0078] In step S33, the processor can perform dithering by applying a frequency offset set according to the selected mask to the image data.

[0079] In an embodiment, the processor can perform dithering by applying a frequency offset that changes according to a predetermined time series order to the image data for each of the plurality of sub-regions.

[0080] As described in Fig. 6, by performing dithering through a mask generated based on a pixel arrangement pattern, which is a structural characteristic of the display panel, the occurrence of the screen door effect in the output image data can be reduced.

[0081] FIG. 7 is a flowchart illustrating a second pixel rendering operation of a display device according to an exemplary embodiment of the present disclosure.

[0082] Referring to FIG. 7, in step S41, a non-UDC area can be identified. In an embodiment, the processor stores spatial coordinate values ​​on a display panel for a non-UDC area in advance, and by comparing the stored spatial coordinate values ​​of the non-UDC area with the spatial coordinate values ​​of the identified area, the identified area can be identified as a non-UDC area.

[0083] In step S43, a second filter corresponding to the spatial coordinate values ​​of the non-UDC region can be selected. For example, the second filter may refer to a filter for performing a second pixel rendering for the non-UDC region. The second filter may be matched to the spatial coordinate values ​​for the non-UDC region and stored in memory in advance.

[0084] In an embodiment, when the target sub-region corresponding to the spatial coordinate value of the image data is a non-UDC area, the processor can select a filter corresponding to the spatial coordinate value '(x,y,z)' from among a plurality of second filters stored in memory by searching for the spatial coordinate value '(x,y,z)' of the image data in memory. For example, the spatial coordinate value 'x' is intended to represent a relative position in the horizontal axis direction of the display panel, the spatial coordinate value 'y' is intended to represent a relative position in the vertical axis direction of the display panel, and the spatial coordinate value 'z' is intended to represent a relative channel on the display panel.

[0085] In step S45, a second pixel rendering can be performed using a second filter.

[0086] FIG. 8 is a flowchart illustrating a third pixel rendering operation of a display device according to an exemplary embodiment of the present disclosure.

[0087] Referring to FIG. 8, in step S51, a boundary region can be identified based on spatial coordinate values. For example, the processor can store spatial coordinate values ​​on a display panel for a UDC region and a non-UDC region in advance, and by comparing the stored spatial coordinate values ​​with the spatial coordinate values ​​of the region where image data will be displayed, the identified region can be identified as a boundary region between the UDC region and the non-UDC region.

[0088] In step S53, the processor can select at least one third filter based on the spatial coordinate values ​​of the image data.

[0089] Although not shown in FIG. 8, a third filter for pixel rendering can be generated in advance based on a pixel placement pattern for a boundary region between a UDC region and a non-UDC region. The third filter can correspond to each of a plurality of sub-boundary regions included in the boundary region.

[0090] The pixel placement pattern for each sub-boundary region represents the structural characteristics of the boundary region among the display panel and can be determined based on at least one of the placement structure between emitting pixels and non-emitting pixels in each sub-boundary region, the amount of pixel loss in the UDC region compared to the non-UDC region, the amount of change in pixel size, and the amount of change in pixel position. For pixel rendering, a pre-generated filter can be stored in the memory of the display device along with corresponding spatial coordinate values.

[0091] In an embodiment, the processor may select a filter having spatial coordinate values ​​that match the spatial coordinate values ​​of the received image data as a third filter. For example, the processor may select a third filter corresponding to the received image data from among a plurality of previously generated third filters by searching for the spatial coordinate values ​​of the received image data in memory.

[0092] In step S55, a third pixel rendering can be performed using the selected third filter.

[0093] As described in FIG. 8, by performing independent pixel rendering based on the pixel placement structure in the boundary area between the UDC area and the non-UDC area of ​​the display panel, redundant rendering for each area of ​​the display panel (e.g., UDC area, non-UDC area, boundary area between the UDC area and the non-UDC area) can be prevented, and pixel rendering can be performed while considering the structural characteristics of each area.

[0094] FIG. 9 is a block diagram (900) showing rendering operations performed in parallel in a display device according to an exemplary embodiment of the present disclosure.

[0095] More specifically, it is a block diagram illustrating an operation for performing parallel rendering and dithering masking on images of a UDC area and a non-UDC area using the pixel rendering circuit (40) and dithering circuit (60) of the processor (100) of FIG. 2.

[0096] Referring to FIG. 9, to perform parallel rendering and dithering masking on an image, the processor may include a UDC identification circuit (1001), a pre-gamma processing circuit (1002), a filter selection circuit (1005), a first pixel rendering circuit (1007), a dithering circuit (1009), a second pixel rendering circuit (1011), and a post-gamma processing circuit (1013).

[0097] The pre-gamma processing circuit (1002) can perform pre-gamma processing on the received image data (Input).

[0098] Afterwards, first and second pixel rendering operations can be performed in parallel on image data output from the pre-gamma processing circuit (1002).

[0099] The first pixel rendering operation is performed by the filter selection circuit (1005) and the first pixel rendering circuit (1007), and the second pixel rendering operation can be performed by the second pixel rendering circuit (1011).

[0100] In this specification, the path between the first pixel rendering circuit (1007) and the multiplexer may be referred to as the first pixel rendering path, and the path between the second pixel rendering circuit (1011) and the multiplexer may be referred to as the second pixel rendering path. In an exemplary embodiment, the display device may perform a rendering operation on image data (Input) by utilizing the first and second pixel rendering paths in parallel.

[0101] Image data output from the pre-gamma processing circuit (1002) can pass through the first and second pixel rendering paths in parallel.

[0102] First, the first pixel rendering circuit (1005) can perform first pixel rendering on image data (Input) using a first filter selected by the filter selection circuit (1005). The dithering circuit (1009) can mask the image data output from the first pixel rendering circuit (1007) according to the embodiments described in FIG. 1 and then output it to a multiplexer (MUX).

[0103] The second pixel rendering circuit (1011) can perform a second rendering operation on image data (Input) in parallel with the first pixel rendering circuit (1007).

[0104] The UDC identification circuit (1001) can identify whether the received image data is displayed in the UDC area based on the spatial coordinates (x, y, z) of the received image data. The UDC identification circuit (1001) can generate a control signal to control the multiplexer (MUX) based on the identification result. In response to the control signal received from the UDC identification circuit (1001), the multiplexer (MUX) can output either the image data that has passed through the first pixel rendering path or the image data that has passed through the second pixel rendering path to the post-gamma processing circuit (1013).

[0105] The post-gamma processing circuit (1013) can perform post-gamma processing operations on image data output from the multiplexer (MUX) to output final image data (Output).

[0106] Although not shown, a filter for pixel rendering or a mask for dithering can be generated in advance based on a pixel placement pattern for multiple sub-regions of the UDC (Under display camera) area.

[0107] The pixel placement pattern for each sub-region can be determined based on at least one of the placement structure between emitting pixels and non-emitting pixels in each sub-region, the amount of pixel loss in the UDC region compared to the non-UDC region, the amount of pixel size change, and the amount of pixel position change. For pixel rendering, a pre-generated filter or mask can be stored in the memory of the display device along with corresponding spatial coordinate values.

[0108] A UDC identifying circuit (1001) receives image data and can identify whether the target area where the image data is to be displayed is a UDC area based on the spatial coordinate values ​​of the image data. In an embodiment, the UDC identifying circuit (1001) can identify whether the target area is a UDC area by comparing the spatial coordinate values ​​of the UDC area stored in advance with the spatial coordinate values ​​of the target area (e.g., (x,y,z)). For example, the spatial coordinate value 'x' is intended to indicate the relative position of the target area in the horizontal axis direction of the display panel, the spatial coordinate value 'y' is intended to indicate the relative position of the target area in the vertical axis direction of the display panel, and the spatial coordinate value 'z' is intended to indicate the relative channel of the target area on the display panel.

[0109] A filter selection circuit (1005) can select at least one first filter based on the spatial coordinate values ​​of the received image data when the target area is identified as a UDC area. The selected filter may refer to a filter corresponding to the spatial coordinate values ​​of the image data among a plurality of pre-generated filters. In this specification, selecting a filter may be interpreted as determining a filter index based on the spatial coordinate values ​​of the image data.

[0110] In an embodiment, the filter selection circuit (1005) can select a first filter corresponding to the spatial coordinate value of the target area among a plurality of first filters stored in memory in advance by searching for the spatial coordinate value of the target area in memory.

[0111] The first pixel rendering circuit (1007) can perform first pixel rendering for a target area using a selected first filter when the target area is identified as a UDC area.

[0112] The dithering circuit (1009) can perform dithering based on the spatial coordinate values ​​of the target area when the target area is identified as a UDC area.

[0113] In an embodiment, the dithering circuit (1009) can select a mask corresponding to the spatial coordinate value of the target area from among a plurality of masks stored in memory in advance by searching for the spatial coordinate value of the target area in memory.

[0114] In an embodiment, the dithering circuit (1009) can perform dithering by setting a predetermined frequency offset for a target area using a selected mask.

[0115] The second pixel rendering circuit (1011) can perform second pixel rendering for a target area when the target area is identified as a non-UDC area.

[0116] In an embodiment, the second pixel rendering circuit (1011) can select a second filter corresponding to the spatial coordinate values ​​of the target area when the target area is identified as a non-UDC area, and perform a second pixel rendering for the target area using the selected second filter.

[0117] In an embodiment, the processor can perform a first pixel rendering and a second pixel rendering in parallel. For example, the processor can perform the first pixel rendering and the second pixel rendering in parallel by selectively outputting the first pixel rendered image data and the second pixel rendered image data through a multiplexer (MUX).

[0118] The processor may further include a pre-gamma processing circuit that performs luminance linearization before pixel rendering for image data (e.g., input data of Red (R), Green (G), and Blue (B)), and a post-gamma processing circuit that converts it into an output image data after pixel rendering.

[0119] Although not illustrated in FIG. 9, the processor may perform a third pixel rendering of the boundary region using a third filter selected based on the pixel placement pattern of the boundary region between the UDC region and the non-UDC region. The third pixel rendering may be performed in parallel with at least one of the first pixel rendering or the second pixel rendering.

[0120] In FIG. 9, dithering is shown to be performed by a dithering circuit (1009) after a rendering process by a first pixel rendering circuit (1007) for a UDC area, but embodiments according to the present disclosure are not limited thereto. In FIG. 10, described below, an operation to perform dithering based on a pixel arrangement pattern of a UDC area is explained in order to solve the screen door effect problem appearing in an image of a UDC area.

[0121] A display device according to an embodiment of the present disclosure can effectively improve the image data quality and prevent waste of hardware resources caused by redundant filtering by performing parallel pixel rendering in a UDC area and a non-UDC area based on a pixel arrangement pattern of a display panel.

[0122] FIG. 10 is a block diagram (1010) showing masking operations in a display device according to an exemplary embodiment of the present disclosure.

[0123] More specifically, this is a block diagram illustrating an operation to prevent image distortion (e.g., screen door effect) by performing dithering masking on an image of the UDC area using the dithering circuit (60) of the processor (100) of FIG. 2.

[0124] Referring to FIG. 10, to perform dithering masking on an image of a UDC area, the processor may include a UDC identification circuit (1101), a mask selection circuit (1105), a dithering control circuit (1107), and a dithering circuit (1109).

[0125] A UDC identifying circuit (1101) can identify whether the received image data is displayed in the UDC area based on the spatial coordinates (x, y, z) of the received image data. The UDC identifying circuit (1101) can transmit a signal containing the identification result to a dithering control circuit (1107).

[0126] For example, the UDC identification circuit (1101) can identify whether the target area where the image data is to be displayed is a UDC area based on the spatial coordinate values ​​of the image data. In an embodiment, the UDC identification circuit (1101) can identify whether the target area is a UDC area by comparing the spatial coordinate values ​​of the UDC area stored in advance with the spatial coordinate values ​​of the target area (e.g., (x,y,z)). For example, the spatial coordinate value 'x' is intended to indicate the relative position of the target area in the horizontal axis direction of the display panel, the spatial coordinate value 'y' is intended to indicate the relative position of the target area in the vertical axis direction of the display panel, and the spatial coordinate value 'z' is intended to indicate the relative channel of the target area on the display panel.

[0127] For example, if the spatial coordinate value of the image data belongs to the UDC area, the UDC identification circuit (1101) can transmit a signal containing the identification result to the dithering control circuit (1107).

[0128] If the spatial coordinate value of the image data belongs to the UDC area, the dithering control circuit (1107) can transmit a signal to the dithering circuit (1109) instructing it to perform dithering on the image data in the UDC area.

[0129] For example, if the spatial coordinate value of the image data belongs to the UDC area, the dithering control circuit (1107) controls the dithering circuit (1109) to perform dithering on the image data in the UDC area by configuring a switch so that the wire (1) and the wire (2) between the dithering control circuit (1107) and the dithering circuit (1109) are connected.

[0130] For example, if the spatial coordinate value of the image data belongs to a non-UDC region, the dithering control circuit (1107) controls the dithering of the image data in the non-UDC region to be skipped by configuring a switch so that the wire (1) and the wire (3) between the dithering control circuit (1107) and the dithering circuit (1109) are connected.

[0131] The mask selection circuit (1105) can select a mask based on the spatial coordinate values ​​of the received image data.

[0132] For example, the mask selection circuit (1105) can select a mask corresponding to the spatial coordinate values ​​(e.g., (x,y,z)) of the image data from among a plurality of pre-generated masks. In this specification, selecting a mask can be interpreted as determining a mask index based on the spatial coordinate values ​​of the image data.

[0133] A mask for dithering can be pre-generated based on pixel placement patterns for multiple sub-regions of the UDC area. Each pre-generated mask can be matched with each of the multiple sub-regions of the UDC area and stored in memory.

[0134] A pixel placement pattern for multiple sub-regions can be determined based on at least one of the placement structure between emitting pixels and non-emitting pixels in each sub-region, the amount of pixel loss in the UDC region compared to the non-UDC region, the amount of pixel size change, and the amount of pixel position change.

[0135] In an embodiment, the mask selection circuit (1105) can select a mask corresponding to the spatial coordinate value of the target area from among a plurality of masks stored in memory in advance by searching for the spatial coordinate value of the target area in memory.

[0136] In an embodiment, the mask selection circuit (1105) can transmit information about the selected mask to the dithering circuit (1109).

[0137] The dithering circuit (1109) can perform dithering masking based on the spatial coordinate values ​​of the target area when the target area is identified as a UDC area.

[0138] In an embodiment, the dithering circuit (1109) can perform dithering by setting a predetermined frequency offset for a target area using a mask selected by the mask selection circuit (1105). At this time, the frequency offset can be set to a randomly different value for each pixel location. Additionally, the frequency offset can be changed to a random value according to a predetermined period even at the same pixel location.

[0139] A display device according to an embodiment of the present disclosure can effectively improve the image quality in the UDC area of ​​the display device by preventing distortion (e.g., screen door effect) in output image data by performing dithering based on a pixel arrangement pattern for a plurality of sub-areas of the UDC area.

[0140] FIG. 11 is a block diagram showing a display system and a brightness control method according to an exemplary embodiment of the present disclosure.

[0141] Referring to FIG. 11, the display system (1000a) may include a processor (100), a display driving circuit (200), a display panel (300), a sensor controller (410), and a sensor module (420). In an embodiment, the sensor controller (410) and the processor (100) may be mounted on a main board, or the sensor controller (410) may be implemented as a part of the processor (100).

[0142] The sensor module (420) may include various sensors, such as a fingerprint sensor (411), a motion sensor (412), a proximity sensor (413), and an illuminance sensor (414). The sensors provided in the sensor module (420) can transmit sensing data to the sensor controller (410).

[0143] The sensor controller (410) can provide the received sensing data (SDT) to the display driving circuit (200) either through the processor (100) or directly. In an embodiment, when the processor (100) is operating in a low-power mode, such as a sleep mode, the sensor controller (410) can provide the sensing data (SDT) directly to the display driving circuit (200).

[0144] Although not explicitly stated, a filter for pixel rendering or a mask for dithering may be generated in advance based on a pixel placement pattern for each of the multiple sub-regions of the Under Display Camera (UDC) area. For pixel rendering and dithering, the generated filter or mask may be stored in the memory of the display device along with corresponding spatial coordinate values.

[0145] The pixel placement structure for each sub-region can be determined based on at least one of the placement structure between emitting pixels and non-emitting pixels for each of the plurality of sub-regions, the amount of pixel loss, the amount of pixel size change, and the amount of pixel position change in each of the plurality of sub-regions relative to the non-UDC area.

[0146] The pixel rendering circuit (40) can perform pixel rendering for a target area based on the spatial coordinate values ​​of the image data. For example, the target area may represent a UDC area or a non-UDC area.

[0147] In an embodiment, when the target area is a UDC area, the pixel rendering circuit (40) can perform a first pixel rendering for the UDC area by using at least one first filter selected based on the spatial coordinate values ​​of the image data.

[0148] In an embodiment, when the target area is a non-UDC area, the pixel rendering circuit (40) can perform a second pixel rendering for the non-UDC area by using a second filter which is a filter for the non-UDC area.

[0149] In an embodiment, when the target area is a boundary area between a UDC area and a non-UDC area, the pixel rendering circuit (40) can perform a third pixel rendering for the boundary area by using a third filter selected based on the spatial coordinate values ​​of the image data.

[0150] In an embodiment, the pixel rendering circuit (40) can perform at least two pixel renderings in parallel among the first pixel rendering, the second pixel rendering, or the third pixel rendering. In this specification, selecting a filter can be interpreted as determining a filter index based on the spatial coordinate values ​​of the image data.

[0151] The dithering circuit (60) can perform dithering on a target area using a mask selected based on the spatial coordinate values ​​of the image data. The selected mask may refer to a mask corresponding to the spatial coordinate values ​​of the target area among a plurality of pre-generated masks.

[0152] In an embodiment, the dithering circuit (60) can perform dithering by setting a predetermined frequency offset for a target area using a selected mask.

[0153] As illustrated in FIG. 11, pixel rendering is performed based on the structural characteristics of the display panel region, thereby adaptively improving the problem of image quality degradation in the UDC region and preventing the waste of hardware resources caused by redundant pixel rendering. In addition, by performing dithering that reflects the structural characteristics of the display panel, noise in the output image data can be reduced, thereby reducing the screen door effect.

[0154] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 A display device comprising: a memory; a display panel composed of an under-display camera (UDC) region and a non-under-display camera (NUDC) region including a plurality of sub-regions; and an image processor configured to receive image data, select at least one first filter corresponding to each of the plurality of sub-regions based on spatial coordinate values ​​for the received image data, and perform a first pixel rendering for the UDC region using the at least one first filter, wherein the at least one first filter is generated based on a pixel arrangement pattern of each of the plurality of sub-regions. Claim 2 A display device according to claim 1, wherein the image processor is configured to select a second filter corresponding to the spatial coordinate values ​​of the non-UDC region and to perform a second pixel rendering for the non-UDC region using the second filter. Claim 3 A display device according to claim 2, wherein the image processor is configured to perform the first pixel rendering for the UDC region and the second pixel rendering for the non-UDC region in parallel. Claim 4 A display device according to claim 1, wherein the pixel arrangement pattern is configured to be determined based on at least one of the arrangement structure between a emitting pixel and a non-emitting pixel for each of the plurality of sub-regions, a pixel loss amount, a pixel size change amount, and a pixel position change amount in each of the plurality of sub-regions relative to the non-UDC area. Claim 5 A display device according to claim 4, wherein the image processor is configured to select a mask based on a pixel arrangement pattern for each of the plurality of sub-regions for the image data on which the first pixel rendering is performed, and to perform dithering using the selected mask. Claim 6 A display device according to claim 5, wherein the image processor is configured to perform the dithering by applying a predetermined frequency offset to each of the plurality of sub-regions according to the selected mask. Claim 7 A display device according to claim 4, wherein the image processor is configured to select at least one third filter corresponding to a boundary region between the UDC region and the non-UDC region based on the spatial coordinate values ​​of the image data, and to perform a third pixel rendering for the boundary region using the at least one third filter, and wherein the at least one third filter is generated based on the pixel arrangement structure of the boundary region. Claim 8 A method of operating a display device, wherein the display device comprises a display panel composed of an under-display camera (UDC) area and a non-under-display camera (UDC) area including a plurality of sub-regions, and the method comprises receiving image data, selecting at least one first filter corresponding to each of the plurality of sub-regions based on spatial coordinate values ​​of the received image data, and performing a first pixel rendering for the UDC area using the at least one first filter, wherein the at least one first filter is generated based on a pixel arrangement pattern of each of the plurality of sub-regions. Claim 9 A display device comprising: a display panel comprising an under-display camera (UDC) area and a non-under-display camera (UDC) area including a plurality of sub-areas; and an image processor configured to utilize a first rendering path for the UDC area and a second rendering path for the non-UDC area in parallel, and to perform dithering for the UDC area based on a pixel arrangement pattern of the UDC area. Claim 10 A display device according to claim 9, wherein the pixel arrangement pattern is determined based on at least one of the arrangement structure between a light-emitting pixel and a non-light-emitting pixel, the amount of pixel loss in a target sub-region relative to the non-UDC region, the amount of pixel size change, and the amount of pixel position change.

Images