Memory controller and storage device using a fragmentation ratio, and operating method thereof

Abstract

A method of operation of a memory controller configured to control a memory device comprising at least one memory block comprising a plurality of pages according to an exemplary embodiment of the present disclosure may include: transmitting a program instruction to the memory device based on a write request from a host; updating a valid page bitmap indicating the validity of the plurality of pages based on valid page information received from the memory device; calculating a fragmentation rate indicating the degree of fragmentation of valid pages and invalid pages for the at least one memory block based on the valid page bitmap; determining source blocks among the at least one memory blocks in order of the lowest fragmentation rate; and performing garbage collection on the source blocks.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to a method of operation of a storage device, and more specifically, to a memory device utilizing a fragmentation rate, a storage device including a memory device, and a method of operation of a storage device utilizing a fragmentation rate. Background Technology

[0002] Storage devices such as SSD (Solid State Drive), NVMe (Non-Volatile Memory express), eMMC (embedded Multi-Media Card), and UFS (Universal Flash Storage) that utilize non-volatile memory devices are widely used.

[0003] As data is continuously written to the flash memory, valid data may be scattered throughout the entire flash memory. In order to secure free memory blocks, which are storage areas where data can be written, it is necessary to perform garbage collection by moving valid pages of at least one memory block to another memory block and performing an erase operation on said memory block.

[0004] The Valid Page Count is referenced for garbage collection, but a garbage collection method with higher data I / O efficiency is required for high-speed processing of data I / O. The problem to be solved

[0005] The technical concept of the present disclosure is to provide a method of operation for a memory controller that efficiently performs garbage collection by utilizing a fragmentation rate. Furthermore, the technical concept of the present disclosure is to provide a storage device that efficiently performs garbage collection based on a fragmentation rate and a method of operation thereof. means of solving the problem

[0006] To solve the above problems, a method of operation of a memory controller configured to control a memory device comprising at least one memory block comprising a plurality of pages according to an exemplary embodiment of the present disclosure may include: transmitting a program instruction to the memory device based on a write request from a host; updating a valid page bitmap indicating the validity of the plurality of pages based on valid page information received from the memory device; calculating a fragmentation rate indicating the degree of fragmentation between valid pages and invalid pages for the at least one memory block based on the valid page bitmap; determining source blocks among the at least one memory blocks in order of the lowest fragmentation rate; and performing garbage collection on the source blocks.

[0007] A method of operation of a storage device comprising a memory device including at least one memory block including a plurality of pages according to an exemplary embodiment of the present disclosure and a memory controller configured to control the memory device may include the steps of: the memory controller receiving a write request and data from a host; the memory controller transmitting a program command to the memory device; the memory device writing the data to a memory space and generating valid page information which is whether the page corresponding to the written memory space is valid; the memory controller updating a valid page bitmap indicating the validity of the plurality of pages based on the valid page information received from the memory device; the memory controller calculating a fragmentation rate indicating the degree of separation between valid pages and invalid pages based on the valid page bitmap; and the memory controller performing garbage collection based on the fragmentation rate.

[0008] A storage device according to an exemplary embodiment of the present disclosure may include a memory device configured to provide valid page information of the plurality of memory blocks, each comprising at least one page, and a memory controller configured to perform garbage collection by calculating a fragmentation rate, which represents the degree of fragmentation between valid pages and invalid pages based on the valid page information, and rearranging the plurality of memory blocks based on the fragmentation rate. Effects of the invention

[0009] A memory controller and a storage device according to the technical concept of the present disclosure can determine source blocks to be garbage collected based on the fragmentation rate. Accordingly, the storage device can maximize I / O efficiency by performing garbage collection on optimized source blocks. Furthermore, the storage device according to the technical concept of the present disclosure can reduce the number of garbage collection operations by selecting optimal source blocks, and as a result, reduce the Write Amplification Factor (WAF). Additionally, according to the technical concept of the present disclosure, improvements in write operation performance and an extension of the lifespan of the storage device can be expected. Brief explanation of the drawing

[0010] FIG. 1 is a block diagram illustrating a storage device according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram illustrating a memory controller according to an exemplary embodiment of the present disclosure. FIG. 3 is a block diagram illustrating a storage device according to an exemplary embodiment of the present disclosure. FIG. 4 is a block diagram illustrating a memory device according to an exemplary embodiment of the present disclosure. FIG. 5 is a block diagram illustrating a storage device according to an exemplary embodiment of the present disclosure. FIG. 6 is a flowchart illustrating a method of operation of a memory controller according to an exemplary embodiment of the present disclosure. FIG. 7 is a conceptual diagram illustrating the structure of data stored in a memory device according to an exemplary embodiment of the present disclosure. FIG. 8 is a conceptual diagram illustrating garbage collection performed in a memory device according to an exemplary embodiment of the present disclosure. FIG. 9 is a conceptual diagram illustrating the fragmentation rate calculated in a memory controller according to an exemplary embodiment of the present disclosure. FIG. 10 is a flowchart illustrating a method of operation of a memory controller according to an exemplary embodiment of the present disclosure. FIG. 11 is a conceptual diagram illustrating a valid page bitmap according to an exemplary embodiment of the present disclosure. FIG. 12 is a conceptual diagram illustrating the fragmentation rate calculated in a memory controller according to an exemplary embodiment of the present disclosure. FIG. 13 is a flowchart illustrating a method of operation of a memory controller according to an exemplary embodiment of the present disclosure. FIG. 14 is a conceptual diagram illustrating the fragmentation calculated in a memory controller according to an exemplary embodiment of the present disclosure. FIG. 15 is a conceptual diagram illustrating garbage collection performed using fragmentation rate and fragmentation degree according to an exemplary embodiment of the present disclosure. FIG. 16 is a flowchart illustrating a method of operation of a storage device according to an exemplary embodiment of the present disclosure. FIG. 17 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure. FIG. 18 is a block diagram illustrating an electronic system to which a storage device according to an exemplary embodiment of the present invention is applied. FIG. 19 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure. FIG. 20 is a block diagram illustrating a UFS system according to an exemplary embodiment of the present invention. FIG. 21 is a cross-sectional view of the structure of a memory device that can be applied to a storage device according to an exemplary embodiment of the present disclosure. FIG. 22 is a block diagram illustrating a data center to which a storage device according to an exemplary embodiment of the present disclosure is applied. Specific details for implementing the invention

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0012] FIG. 1 is a block diagram illustrating a storage device (10) according to an exemplary embodiment of the present disclosure.

[0013] Fig. 1 is referenced. A storage device (10) can store data in a storage area. The storage area may refer to a logical or physical storage area within the storage device (10), such as a sector, page, or block.

[0014] According to an exemplary embodiment of the present disclosure, a storage device (10) can calculate a fragmentation rate based on the validation of a page in which data is stored, and the storage device (10) can perform data rearrangement based on the fragmentation rate.

[0015] According to an exemplary embodiment, page validity may refer to whether data can be rewritten to the page. For example, data can be rewritten to a valid page, and data cannot be rewritten to an invalid page. Blocks containing a relatively large number of invalid pages need to be erased. The method of rearranging valid and invalid pages may be referred to as garbage collection.

[0016] In an exemplary embodiment, the storage device (10) may be an embedded memory embedded in a storage system or a memory system. In an exemplary embodiment, the storage device (10) may be an eMMC (embedded Multi-Media Card) or an embedded UFS (Universal Flash Storage) memory device. In an exemplary embodiment, the storage device (10) may be an external memory that is removable from the storage system. For example, the storage device (10) may be a UFS memory card, CF (Compact Flash), SD (Secure Digital), Micro-SD (Micro Secure Digital), Mini-SD (Mini Secure Digital), xD (Extreme Digital), or Memory Stick, but is not limited thereto.

[0017] The storage device (10) may include a memory controller (100) and a memory device (200). The memory controller (100) may include a fragmentation ratio (FR calculator; hereinafter abbreviated as FR) calculator (330), and the memory device (200) may include a plurality of memory blocks (BLK) (210).

[0018] The memory controller (100) can control the storage device (10) overall. The memory controller (100) can control the memory device (200) to read data stored in the memory device (200) or to program data in the memory device (200) in response to a read request or write request from a host. In an exemplary embodiment, the memory controller (100) can control program, read, and erase operations for the memory device (200) by providing an address, command, and control signal to the memory device (200). Additionally, data for programming data in the memory device (200) according to the host's request and data that has been read can be transmitted and received between the memory controller (100) and the memory device (200).

[0019] The fragmentation rate calculator (330) can calculate the fragmentation rate based on the validity of the pages where data is stored. According to an exemplary embodiment of the present disclosure, the fragmentation rate (FR) may represent the degree of fragmentation of data. More specifically, the fragmentation rate (FR) may represent the degree of fragmentation between valid pages and invalid pages. According to an exemplary embodiment, the fragmentation rate (FR) may correspond to the number of times Direct Memory Access (DMA) is performed during a series of processes in which data is transferred to a page buffer (not shown) of a memory device (200).

[0020] According to an exemplary embodiment of the present disclosure, the fragmentation rate (FR) can be calculated based on a valid page bitmap. In an exemplary embodiment, the valid page bitmap may represent the validity of each of a plurality of pages. According to an exemplary embodiment, validity may be represented as "0" or "1". For example, a valid page may be represented by bit "1" in the valid page bitmap, and an invalid page may be represented by bit "0" in the valid page bitmap. According to an exemplary embodiment, if the values ​​of the bitmap are different, it may be understood that the validity is different.

[0021] According to an exemplary embodiment of the present disclosure, the fragmentation rate (FR) may correspond to the number of valid page groups.

[0022] According to an exemplary embodiment of the present disclosure, the fragmentation rate calculator (330) can calculate the fragmentation degree. According to an exemplary embodiment, the fragmentation degree may correspond to the number of valid page groups and invalid page groups that are adjacent to each other and have the same validity. For example, the fragmentation rate calculator (330) can calculate the fragmentation degree by detecting consecutive bits for a single memory block in a valid page bitmap, grouping the consecutive bits, and counting the number of groups with the same validity.

[0023] The storage device (10) can perform data rearrangement based on the fragmentation rate. In an exemplary embodiment, the storage device (10) can perform data rearrangement based more on the degree of fragmentation when the fragmentation rates are the same.

[0024] The process by which the fragmentation rate calculator (330) calculates the fragmentation rate is described in detail in FIGS. 5 and FIGS. 9.

[0025] The memory device (200) may include a non-volatile memory device. In an exemplary embodiment, the memory device (200) may be a device to which various types of memory are applied, such as NAND-type Flash Memory, Magnetic RAM (MRAM), Spin-Transfer Torque MRAM, Conductive Bridging RAM (CBRAM), Ferroelectric RAM (FeRAM), Phase RAM (PRAM), Resistive RAM, Nanotube RAM, Polymer RAM (PoRAM), Nano Floating Gate Memory (NFGM), Holographic Memory, Molecular Electronics Memory, or Insulator Resistance Change Memory.

[0026] In an exemplary embodiment, the memory device (200) may include a flash memory, and the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. The 3D memory array may be formed monolithically at at least one physical level of a circuit formed on or within the substrate as an array of memory cells having an active region disposed on a silicon substrate, or as a circuit related to the operation of said memory cells. The term “monolithic” means that the layers of each level constituting the array are stacked directly on top of the layers of each lower level of the array. In one embodiment, the 3D memory array may include vertical NAND strings arranged vertically such that at least one memory cell is positioned above another memory cell. The at least one memory cell may include a charge trap layer. U.S. Patent Publication No. 7,679,133, No. 8,553,466, No. 8,654,587, No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 describe suitable configurations for a 3D memory array in which the 3D memory array is composed of multiple levels and word lines and / or bit lines are shared between the levels, and may be incorporated herein by reference.

[0027] A memory device (200) may include a plurality of memory blocks (BLK) (210). Each of the plurality of memory blocks may include at least one page, and each page may include a plurality of memory cells in which a plurality of wordlines are connected. In an exemplary embodiment, the memory device (200) may include a plurality of planes containing a plurality of memory blocks (BLK) (210), and in particular, may include a plurality of memory dies each containing a plurality of planes. According to an exemplary embodiment, the memory device (200) may perform write operations or read operations on a page-by-page basis, and erase operations may be performed on a block-by-block basis.

[0028] According to an exemplary embodiment of the present disclosure, a memory device (200) may store data upon a request from a memory controller (100) and provide valid page information to the memory controller (100) indicating the validity of the page in which the data is stored. According to an exemplary embodiment, validation may mean whether the data in the page can be rewritten. According to an exemplary embodiment, the memory device (200) may check the validity of the page in which the data is stored at each time data writing is completed, at a certain period, or upon a request from the memory controller (100), generate valid page information, and provide it to the memory controller (100).

[0029] The memory device (200) may include a single-level cell (SLC) that stores 1 bit of data or a multi-level cell (MLC) that stores multi-bit data (e.g., 2 bits or more bits). For example, the memory device (200) may include a triple-level cell (TLC) that can store 3 bits of data or a quadruple-level cell (QLC) that can store 4 bits of data, or a memory cell that can store 5 bits or more bits of data.

[0030] In an exemplary embodiment, the host can provide a command to the storage device (10) and transmit and receive data. In an exemplary embodiment, the host can provide a write command and write data to the storage device (10). In an exemplary embodiment, the host can transmit a read command to the storage device (10) and receive read data from the storage device (10). The data provided by the host may have various characteristics.

[0031] The host may include at least one processor core or be implemented as a System-On-a-Chip. For example, the host may include a general-purpose processor or a dedicated processor. The host may be the processor itself or may be an electronic device or system corresponding to the processor. In exemplary embodiments, the host may correspond to a Central Processing Unit (CPU), a processor, a microprocessor, or an Application Processor (AP), etc.

[0032] The host and the memory device (200) can transmit and receive data, i.e., interface according to a set standard. As an example of an interface for communication between the memory device (200) and the host, various interface methods such as ATA (advanced technology attachment), SATA (serial ATA), e-SATA (external SATA), SCSI (small computer small interface), SAS (serial attached SCSI), PATA (Parallel Advanced Technology Attachment), PCI (peripheral component interconnection), PCI-E (PCI-Express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (Multi Media Card), eMMC (embedded Multi Media Card), CF (Compact Flash) card interface, ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), MIPI (Mobile Industry Processor Interface) may be applied, but are not limited thereto.

[0033] The memory controller (100) and the memory device (200) can transmit and receive commands, addresses, and data through one or more channels. Whether a command transmitted from a host will be executed in which storage area of ​​the memory device through which channel can be determined by a logical address or logical block address (LBA) transmitted from the host.

[0034] FIG. 2 is a block diagram illustrating a memory controller (100) according to an exemplary embodiment of the present disclosure.

[0035] Fig. 2 and Fig. 1 are referenced together. A memory controller (100) can receive a request provided by a host and can access a memory device (Fig. 1, 200) in response to the request. More specifically, the memory controller (100) can control read, program, or erase operations of the memory device (200) in response to a request input from the host. The request may include a read request, a write request, an erase request, etc. Depending on the write request from the host, the memory controller (100) can control the memory device (200) to program data immediately, or it can control the memory device to program data after erasing data that has already been programmed.

[0036] The memory controller (100) may include a host interface (Host I / F) (110), a processor (120), RAM (Random Access Memory) (130), ROM (Read Only Memory) (140), a power management circuit (150), and a NAND interface (NAND I / F) (160). The host interface (110), processor (120), RAM (130), ROM (140), power management circuit (150), and NAND interface (160) may be electrically connected via a bus (170). The bus (170) may represent a transmission path for transmitting information between the configuration means of the memory controller (100). In addition to the listed configurations, the memory controller (100) may include other configurations for memory operation.

[0037] The host interface (110) may be equipped with a data exchange protocol between the host and the memory controller (100). Thus, various devices may be connected to the host interface (110) as hosts. In an exemplary embodiment, the host interface (110) may provide interfacing with the memory controller (100) in correspondence with the host's bus format. The host's bus format may include USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCI express, ATA, PATA (Parallel ATA), SATA (Serial ATA), SAS (Serial Attached SCSI), etc. In an exemplary embodiment, the host interface (110) may be equipped with a Non-volatile Memory Express (NVMe) protocol that is installed on a host device that exchanges data in a PCI express manner.

[0038] The processor (120) can control the overall operation of the storage device (Fig. 1, 10). Specifically, the processor (120) can control the storage device (10) to decode a request received from a host and perform an operation according to the decoded result.

[0039] The processor (120) can provide a Read command and an address to the memory device (Fig. 1, 200) during a Read operation in response to a Read request, and can provide a Write command, an address, and write data to the memory device (200) during a Write operation in response to a Write request.

[0040] The processor (120) can perform a process of converting a logical address received from a host into a physical page address using metadata stored in the memory controller (100). Here, metadata can be understood as management information generated in a storage device (Fig. 1, 10) to manage a memory device (Fig. 1, 200). The metadata may include mapping table information used to convert a logical address into a physical page address of a flash memory (310-330), and may also include information for managing the storage area of ​​the memory device (Fig. 1, 200).

[0041] More specifically, the processor (120) can perform a conversion of a logical address received from a host along with a read / write request into a physical address for a read / write operation in the memory device (200). The conversion of the logical address into a physical address can be performed in a Flash Translation Layer (FTL) (300). By executing firmware loaded in the ROM (140), the processor (120) can perform garbage collection, address mapping, wear leveling, etc., to manage the memory device (200) in the Flash Translation Layer (300).

[0042] Data transmitted from a host, data generated by a processor (120), and / or data read from a memory device (Fig. 1, 200) may be temporarily stored in the RAM (130). Software or firmware for the operation of a storage device may be loaded from the ROM (140) into the RAM (130). Additionally, metadata read from a memory device (Fig. 1, 200) may also be stored in the RAM (130). The RAM (130) may be implemented as a DRAM (Dynamic-RAM), SRAM (Static-RAM), etc.

[0043] The RAM (130) may include a flash conversion layer (300). The flash conversion layer (300) is a configuration capable of mapping addresses between a file system and a memory device. In an exemplary embodiment, the flash conversion layer (300) may convert a logical block address (LBA) of a host into a physical block address (PBA) of a memory device (200). The flash conversion layer (300) is described in detail in FIG. 5.

[0044] The ROM (140) may be a read-only memory that stores a program executed by the processor (120). The ROM (140) may store a program that implements the operation method of the memory controller (100) or firmware on which the program is written.

[0045] The power management circuit (150) can supply power or clock required for each component of the storage device (10). The NAND interface (160) can be configured to control signals driving the memory device (Fig. 1, 200) and to access the memory device (Fig. 1, 200) under control from the processor (120). The NAND interface (160) can be configured so that software and hardware interleaving operations are selectively performed through at least one channel.

[0046] Although not illustrated in the drawings, various additional configurations may be included for the efficient operation of the storage device (10). For example, the storage device may further include machine learning IP (Intellectual Property) (not illustrated). The machine learning IP may include one or more processors to accelerate operations performed by the neural network models and may further include separate memory to store programs corresponding to the neural network models. For example, the processor included in the machine learning IP may correspond to a Neural Network Processing Unit (NPU) and may include a Fixed Function Engine for executing convolution layers and a programmable layer for executing non-convolution layers. As another example, the processor included in the machine learning IP may be implemented as at least one of a Graphics Processing Unit (GPU) for high-speed parallel processing, or an Application Specific Integrated Circuit (ASIC)-based Tensor Processing Unit (TPU) for parallel processing of vector and matrix operations. According to various embodiments, machine learning IP may be referred to by various terms including neural network processing device, neural network integrated circuit, Neuromorphic Computing Unit, or Deep Learning Device.Machine learning includes CNN (Convolution Neural Network), R-CNN (Region with Convolution Neural Network), RPN (Region Proposal Network), RNN (Recurrent Neural Network), S-DNN (Stacking-based deep Neural Network), S-SDNN (State-Space Dynamic Neural Network), Deconvolution Network, DBN (Deep Belief Network), RBM (Restricted Network) such as GoogleNet, AlexNet, VGG Network, etc. Boltzman Machine), Fully Convolutional Network, LSTM (Long Short-Term Memory) Network, Classification Network, DQN (Deep Q-Network), Double DQN, Dueling DQN, Distribution Reinforcement Learning, Multi-Step Learning, PER (Prioritized Experience Replay), Noisy DQN, Categorical DQN, Rainbow DQN, DPN (Decentralized Policy Network), DDPN (Deep Decentralized Policy) Network), Model-based Learning, Monte Carlo, SARSA, Policy Search, Actor-Critic, A3C, etc. Various types of network models can be applied, but are not limited to them.

[0047] FIG. 3 is a block diagram illustrating a storage device (10) according to an exemplary embodiment of the present disclosure.

[0048] Referring to FIG. 3, the storage device (10) may include a memory controller (100) and a memory device (200). Since the memory controller (100) and memory device (200) of FIG. 3 can perform the same functions as the memory controller (100) and memory device (200) of FIG. 1 and FIG. 2, redundant descriptions are omitted within the scope of not being placed together. The storage device (10) may support a plurality of channels (CH1 to CHm), and the memory device (200) and the memory controller (100) may be connected through the plurality of channels (CH1 to CHm). For example, the storage device (10) may be implemented as a storage device such as an SSD (Solid State Drive).

[0049] The memory controller (100) can transmit and receive signals to and from the memory device (200) through multiple channels (CH1~CHm). For example, the memory controller (100) can transmit commands (CMDa~CMDm), addresses (ADDRa~ADDRm), and data (DATAa~DATAm) to the memory device (200) through the channels (CH1~CHm), or receive data (DATAa~DATAm) from the memory device (200).

[0050] The memory controller (100) can select one of the non-volatile memory devices connected to the corresponding channel through each channel and transmit and receive signals with the selected non-volatile memory device. For example, the memory controller (100) can select a non-volatile memory device (NVM11) among the non-volatile memory devices (NVM11 to NVM1n) connected to the first channel (CH1). The memory controller (100) can transmit a command (CMDa), an address (ADDRa), and data (DATAa) to the selected non-volatile memory device (NVM11) through the first channel (CH1), or receive data (DATAa) from the selected non-volatile memory device (NVM11).

[0051] The memory controller (100) can transmit and receive signals to and from the memory device (200) in parallel through different channels. For example, the memory controller (100) can transmit a command (CMDb) to the memory device (200) through a second channel (CH2) while transmitting a command (CMDa) to the memory device (200) through a first channel (CH1). For example, the memory controller (100) can receive data (DATAa) from the memory device (200) through a second channel (CH2) while receiving data (DATAb) from the memory device (200) through a first channel (CH1).

[0052] The memory controller (100) can control the overall operation of the memory device (200). The memory controller (100) can control each of the non-volatile memory devices (NVM11~NVMmn) connected to the channels (CH1~CHm) by transmitting signals to the channels (CH1~CHm). For example, the memory controller (100) can control one of the selected non-volatile memory devices (NVM11~NVM1n) by transmitting a command (CMDa) and an address (ADDRa) to the first channel (CH1).

[0053] The memory device (200) may include a plurality of non-volatile memory devices (NVM11 to NVMmn). Each of the non-volatile memory devices (NVM11 to NVMmn) may be connected to one of a plurality of channels (CH1 to CHm) through a corresponding way. For example, the non-volatile memory devices (NVM11 to NVM1n) may be connected to a first channel (CH1) through ways (W11 to W1n), and the non-volatile memory devices (NVM21 to NVM2n) may be connected to a second channel (CH2) through ways (W21 to W2n). In an exemplary embodiment, each of the non-volatile memory devices (NVM11 to NVMmn) may be implemented as any memory unit capable of operating according to individual commands from the memory controller (100). For example, each of the non-volatile memory devices (NVM11 to NVMmn) may be implemented as a chip or a die, but the present invention is not limited thereto.

[0054] Each of the non-volatile memory devices (NVM11 to NVMmn) can operate under the control of the memory controller (100). For example, the non-volatile memory device (NVM11) can program data (DATAa) according to a command (CMDa), an address (ADDRa), and data (DATAa) provided through the first channel (CH1). For example, the non-volatile memory device (NVM21) can read data (DATAb) according to a command (CMDb) and an address (ADDRb) provided through the second channel (CH2), and transmit the read data (DATAb) to the memory controller (100).

[0055] FIG. 3 illustrates a memory device (200) communicating with a memory controller (100) through m channels, and the memory device (200) including n non-volatile memory devices corresponding to each channel, but the number of channels and the number of non-volatile memory devices connected to one channel can be varied.

[0056] FIG. 4 is a block diagram illustrating a memory device (200) according to an exemplary embodiment of the present disclosure.

[0057] Referring to FIG. 4 together with FIG. 2, the memory device (200) may include control logic (230), a memory cell array (220), a page buffer (240), a voltage generator (250), and a row decoder (260). Although not shown in FIG. 4, the memory device (200) may further include a NAND interface (not shown) corresponding to the NAND interface (160) of the memory controller (Fig. 2, 100), and may also further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0058] The control logic (230) can control various operations within the memory device (200) overall. The control logic (230) can output various control signals in response to a command (CMD) and / or an address (ADDR) from the memory interface. For example, the control logic (230) can output a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR).

[0059] The memory cell array (220) may include a plurality of memory blocks (BLK1 to BLKz) (z is a positive integer), and each of the plurality of memory blocks (BLK1 to BLKz) may include a plurality of memory cells. The memory cell array (220) may be connected to a page buffer (240) via bit lines (BL) and may be connected to a row decoder (260) via word lines (WL), string select lines (SSL), and ground select lines (GSL).

[0060] In an exemplary embodiment, the memory cell array (220) may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines stacked vertically on a substrate. In an exemplary embodiment, the memory cell array (220) may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0061] The page buffer (240) may include a plurality of page buffers (PB1 to PBn) (where n is an integer greater than or equal to 3), and the plurality of page buffers (PB1 to PBn) may each be connected to memory cells through a plurality of bit lines (BL). The page buffer (240) may select at least one bit line among the bit lines (BL) in response to a column address (Y-ADDR). The page buffer (240) may operate as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, the page buffer (240) may apply a bit line voltage corresponding to the data to be programmed with the selected bit line. During a read operation, the page buffer (240) may detect the current or voltage of the selected bit line to detect the data stored in the memory cell.

[0062] The voltage generator (250) can generate various types of voltages to perform program, readout, and erase operations based on the voltage control signal (CTRL_vol). For example, the voltage generator (250) can generate a program voltage, a readout voltage, a program verification voltage, an erase voltage, etc. as a word line voltage (VWL).

[0063] The row decoder (260) can select one of a plurality of word lines (WL) and one of a plurality of string selection lines (SSL) in response to a row address (X-ADDR). For example, during a program operation, the row decoder (260) can apply a program voltage and a program verification voltage to the selected word line, and during a read operation, it can apply a read voltage to the selected word line.

[0064] FIG. 5 is a block diagram illustrating a storage device (10) according to an exemplary embodiment of the present disclosure. Since the storage device (10) of FIG. 5 can perform the same function as the storage device (10) of FIG. 1 and FIG. 2, redundant descriptions are omitted within the scope of not being placed. Hereinafter, the memory device (200) is described as a flash memory device (i.e., a non-volatile memory (NVM) device). As previously stated, the memory controller (100) may include a flash conversion layer (FTL) (300).

[0065] In an exemplary embodiment, the flash conversion layer (300) may provide an interface to conceal the erase operation of the memory device (200) between the file system of the host and the memory device (200). By the flash conversion layer (300), disadvantages of the memory device (200), such as erase-before-write and the mismatch between the erase unit and the write unit, and disadvantages such as the existence of a maximum number of erases of the flash memory, can be compensated for. By executing at least a portion of the flash conversion layer (300) by a processor (Fig. 2, 120), the following operations by the flash conversion layer (300) may be performed.

[0066] In the flash conversion layer (300), mapping can be performed to assign a logical address (LBA) generated by the file system to a physical address (PBA) of the memory device (200) during a write operation of the memory device (200). In the flash conversion layer (300), the number of writes per block of the memory device (200) can be counted, and wear leveling can be performed to distribute the degree of writes among multiple blocks evenly. In addition, in the flash conversion layer (300), garbage collection can be performed to rearrange data in order to resolve the increase in an invalid area (i.e., garbage) caused by repeated data writing / deletion in the storage area.

[0067] According to an exemplary embodiment of the present disclosure, a memory controller (100) can calculate a fragmentation rate based on page information corresponding to a storage area written to a memory device (200), and garbage collection can be performed on the memory device (200) based on the fragmentation rate, and thus an invalid (InValid) area of ​​the storage area can be converted into a valid (Valid) area.

[0068] The flash conversion layer (300) may include an input and output interface (I / OI / F) (310), a fragmentation rate calculator (FR calculator) (330), and a GC manager (350).

[0069] The input / output interface (310) can receive data (DATA) to be written to a storage area and a logical address (LBA) of the data (DATA) in response to a write request from a host, and can provide a physical address (PBA) for the logical address (LBA) to a memory device (200) based on a mapping table stored in RAM (130 in FIG. 2) or ROM (140 in FIG. 2). According to an exemplary embodiment, the input / output interface (310) can provide the physical address (PBA) to the control logic (230) and the data (DATA) to the page buffer (240), respectively.

[0070] The memory device (200) can perform a write operation to write data (DATA) to a storage area within the memory device (200) (e.g., a plurality of non-volatile memories (NVM 1 to NVM n) (n is a natural number greater than or equal to 2)) according to a physical address (PBA) received from the input / output interface (310).

[0071] According to an exemplary embodiment, the control logic (230) receives a physical address (PBA) and can output a row address (Fig. 4, X-ADDR) and a column address (Fig. 4, Y-ADDR) of a memory cell array (Fig. 4, 220) so that data (DATA) can be written to a storage area corresponding to the physical address (PBA).

[0072] According to an exemplary embodiment, data (DATA) can be written to a memory cell array (220). Since the bandwidth of data that can be transmitted at once is limited, the data (DATA) can be buffered in a page buffer (240) and then sequentially stored in a specific storage area (e.g., a page) among a plurality of blocks (210) in response to a signal of a column address (Y-ADDR) output from the control logic (230).

[0073] According to an exemplary embodiment of the present disclosure, as data (DATA) is written to a storage area, the validity of the pages contained in each of the plurality of blocks (210) of the memory device (200) may differ from before the data (DATA) is written. As data is repeatedly written to the pages and the blocks containing the pages are erased, some pages of the memory device (200) may be transformed into invalid pages that can no longer store data. According to an exemplary embodiment of the present disclosure, the control logic (230) may provide valid page information (VI), which is information regarding the validity of the pages contained in the plurality of memory blocks (210), to the flash conversion layer (300).

[0074] The fragmentation rate calculator (330) receives valid page information (VI) and can calculate the fragmentation rate (FR) based on the valid page information (VI). According to an exemplary embodiment of the present disclosure, the fragmentation rate (FR) may represent the degree of fragmentation between valid pages and invalid pages. According to an exemplary embodiment of the present disclosure, the fragmentation rate calculator (330) can classify (group) a plurality of pages constituting a single memory block based on validity and calculate the fragmentation rate (FR) corresponding to the number of valid page groups among the valid page groups and invalid page groups.

[0075] According to an exemplary embodiment of the present disclosure, the fragmentation rate calculator (330) can calculate the fragmentation rate (FR) based on a valid page bitmap. In an exemplary embodiment, the valid page bitmap is a bitmap representing the validation of each of a plurality of pages.

[0076] The valid page bitmap may have the number of memory blocks included in the memory device (200) as the column size and the number of pages included in one memory block (BLK) as the row size, respectively, but is not limited thereto.

[0077] In an exemplary embodiment, the validity of each of the plurality of pages contained in a single memory block may be represented by a bit "0" or a bit "1". For example, a valid page may be represented by a bit "1" in the valid page bitmap, and an invalid page may be represented by a bit "0" in the valid page bitmap. According to an exemplary embodiment, if the values ​​of the bitmap are different, it may be understood that the validity is different.

[0078] According to an exemplary embodiment of the present disclosure, the fragmentation rate calculator (330) can calculate the fragmentation degree. According to an exemplary embodiment, the fragmentation degree may correspond to the number of valid page groups and invalid page groups that are adjacent to each other and have the same validity. For example, the fragmentation rate calculator (330) can calculate the fragmentation degree by detecting consecutive bits for a single memory block in a valid page bitmap, grouping the consecutive bits, and counting the number of groups with the same validity. The fragmentation rate calculator (330) can provide the fragmentation rate (FR), or the fragmentation rate (FR) and the fragmentation degree (FD), to the GC manager (350).

[0079] The GC manager (350) can copy data stored in a valid page within a source block (BLK_S) (211) that is subject to garbage collection among a plurality of memory blocks (210) to a free page within a destination block (BLK_D) (213), and erase the source block (BLK_S).

[0080] As data is continuously written to and erased in the memory device (200), some areas of the storage region may be invalidated. In order to secure a free memory block, which is a valid area where data can be written, it is necessary to perform garbage collection (GC) by moving valid pages of at least one memory block to another memory block and performing an erase operation on the memory block. According to an exemplary embodiment of the present disclosure, the GC manager (350) can more efficiently select the source block (211) by performing garbage collection (GC) based on the fragmentation rate (FR).

[0081] Garbage collection (GC) based on the Valid Page Count (VPC) is used, but it cannot be considered the optimal method for selecting source blocks (BLK_S) (211). According to the technical concept of the present disclosure, a GC manager (350) receives a fragmentation rate (FR) based on page validity information (VI), which is page validity information corresponding to a storage area where data (DATA) is stored, selects the block with the lowest fragmentation rate (FR) as the source block (BLK_S) (211), and can perform garbage collection (GC) in order of lowest fragmentation rate (FR). Accordingly, a storage device (10) according to the technical concept of the present disclosure can maximize input / output efficiency by performing garbage collection (GC) on the optimized source blocks (BLK_S) (211). In addition, the storage device (10) according to the technical concept of the present disclosure can ensure sequential reads of the storage device (10) by performing garbage collection starting from memory blocks with a low fragmentation rate, and input / output efficiency can be improved according to sequential reads. Furthermore, the storage device (10) according to the technical concept of the present disclosure can reduce the number of times garbage collection is performed. According to an exemplary embodiment, the Write Amplification Factor (WAF) may be reduced as a result of increased garbage collection performance. Accordingly, the lifespan or performance of the storage device (10) including the memory device (200) may be improved. Furthermore, improvement in the write operation performance and extension of the lifespan of the storage device may be expected. In the present disclosure, WAF means that it is calculated based on the ratio of data requested by the host and the data actually written to the memory device.

[0082] In this disclosure, a method for improving the input / output efficiency of a storage device (10) by performing garbage collection based on the fragmentation rate (FR) is discussed, but the technical concept of this disclosure is not limited thereto. According to an exemplary embodiment, the dependency between a plurality of commands transmitted by a memory controller (100) to a memory device (200), the state of the host, the request history of the host, the command issuance history of the memory controller (100), etc., may be related to the input / output efficiency of the storage device (10). The storage device (10) may increase the input / output efficiency by performing garbage collection based on the dependency between a plurality of commands, the state of the host, the request history of the host, and the command issuance history of the memory controller (100).

[0083] FIG. 6 is a flowchart illustrating the operation method of a memory controller (100) according to an exemplary embodiment of the present disclosure. FIG. 6 is referenced together with FIG. 5.

[0084] In step S110, the memory controller (100) may receive a data write request from a host. The host may provide data (DATA) and a logical address (LBA) of the data (DATA) to the memory controller (100). According to an exemplary embodiment, the input / output interface (310 in FIG. 5) of the memory controller (100) may process an operation corresponding to the write request. For example, the input / output interface (310) may convert the logical address (LBA) into a physical address (PBA) and provide the physical address (PBA) to the memory device (200).

[0085] In step S120, the memory controller (100) may command the memory device (Fig. 5, 200) to program data (DATA). According to an exemplary embodiment, the memory controller (100) may issue a Write Command and provide it to the memory device (200) to instruct the memory device (200) to perform a write operation. The control logic (Fig. 5, 230) of the memory device (200) may receive a physical address (PBA), and the page buffer (Fig. 5, 250) may buffer the data (DATA). The buffered data may be written sequentially to an effective page among a plurality of memory blocks (Fig. 5, 210).

[0086] In step S130, the memory controller (100) can update the valid page bitmap. According to an exemplary embodiment, the control logic (230) can provide the memory controller (100) with page validity information (VI), which is information regarding the validity of the page in which data (DATA) is written, and the memory controller can update the valid page bitmap based on the page validity information (VI). The valid page bitmap is a bitmap representing the validity (validation) of each of a plurality of pages, and the validity may be represented by bits "0" or "1".

[0087] In step S140, the memory controller (100) can calculate the fragmentation rate (FR). According to an exemplary embodiment of the present disclosure, the fragmentation rate (FR) is a classification (grouping) of a plurality of pages constituting a single memory block based on validity, and may correspond to the number of valid page groups among valid page groups and invalid page groups. According to an exemplary embodiment of the present disclosure, the fragmentation rate (FR) may correspond to the number of times Direct Memory Access (DMA) is performed during a series of processes in which data is transferred to a page buffer (not shown) of a memory device (200).

[0088] In step S150, the memory controller (100) can perform garbage collection (GC) based on the fragmentation rate (FR). According to an exemplary embodiment of the present disclosure, the memory controller (100) can select a source block (BLK_S) starting from a memory block with a low fragmentation rate (FR), and as continuous reading is guaranteed, the input / output efficiency of the storage device (10) including the memory controller (100) can be improved.

[0089] FIG. 7 is a conceptual diagram illustrating the structure of data stored in a memory device according to an exemplary embodiment of the present disclosure. FIG. 7 is referenced together with FIG. 5.

[0090] A memory device (Fig. 5, 200) may include a plurality of memory blocks (BLK) (210). Each of the plurality of memory blocks may include at least one page, and each page may include a plurality of memory cells connected by a plurality of wordlines. The memory cells may include at least one transistor, and the transistor may store data by trapping electrons.

[0091] The memory device (200) may include at least one memory block (BLK). For example, the memory device (200) may include M memory blocks (first to Mth memory blocks (BLK 0 to BLK M-1, where M is a natural number)). In the storage device (Figs. 5, 10), read and write operations may be performed on a page (or sector) basis, and erase operations may be performed on a block basis.

[0092] One memory block (BLK) may include N pages, for example, the first to the Nth pages (Page 0 to Page N-1). Data (DATA) written to the storage device (Fig. 5, 10) may be stored in a valid or free page existing in at least one memory block (BLK) of the memory device (200).

[0093] A page may be divided into a data area where data is stored and an extra area where data is not stored. In an exemplary embodiment, 2 KB (kilo-byte) may be allocated to the data area and 64 B (byte) to the extra area, but is not limited thereto.

[0094] FIG. 8 is a conceptual diagram illustrating garbage collection performed in a memory device (200) according to an exemplary embodiment of the present disclosure.

[0095] For convenience of explanation, it is assumed that there are four pages (Page0 to Page3) for each of the first memory block (BLK1) to the third memory block (BLK3) of the storage area of ​​the memory device (Fig. 5, 200). The first to third memory blocks (BLK1 to BLK3) of Fig. 8 may be part of the first to M memory blocks (BLK0 to BLK(M-1)) of Fig. 7.

[0096] The first page (Page0) of the first memory block (BLK1) is a valid area where data can be validly written, the second page (Page1) is a free area, and the third page (Page2) and the fourth page (Page3) may be invalid areas due to repeated data writing / deletion.

[0097] Likewise, the first page (Page0) of the second memory block (BLK2) may be a valid area, the second page (Page1) and the fourth page (Page3) may be invalid areas, and the third page (Page2) may be a free area. The first page (Page0) and the second page (Page1) of the third memory block (BLK3) may be free areas, and the third page (Page2) and the fourth page (Page3) may be valid areas.

[0098] In response to a signal indicating garbage collection (GC), garbage collection may be performed in a memory device (Fig. 5, 200), and data stored in memory blocks (BLK) may be rearranged. According to an exemplary embodiment, a second memory block (BLK2) with many invalid areas may be determined as a source block (BLK_S), and a third memory block (BLK_3) with many free areas may be determined as a destination block (BLK_D).

[0099] According to an exemplary embodiment, data stored in the first page (Page0) of the second memory block (BLK2) can be copied to the second page (Page1) of the third memory block (BLK3), and as a result, the data stored in the second memory block (BLK2) is insignificant. Therefore, the storage device (Figs. 5, 10) can make the entire second memory block (BLK2) writable again by erasing the second memory block (BLK2). In other words, garbage collection can be performed.

[0100] FIG. 9 is a conceptual diagram illustrating a fragmentation rate (FR) calculated in a memory controller (100) according to an exemplary embodiment of the present disclosure. FIG. 9 is referenced together with FIG. 5.

[0101] FIG. 9 assumes that one memory block contains five pages (PAGE0 to PAGE4). However, the technical concept of the present disclosure is not limited to the number of disclosed pages.

[0102] As previously mentioned, the fragmentation rate (FR) is a classification (grouping) of multiple pages constituting a single memory block based on validity, and may correspond to the number of valid page groups among valid page groups and invalid page groups.

[0103] When five pages (PAGE0 to PAGE4) constituting a single memory block are all valid, the first to fifth pages (PAGE0 to PAGE4) that are adjacent to each other and have the same validity can be grouped into one valid page group. In this case, since the number of valid page groups is one, the fragmentation rate (FR) can be 1.

[0104] If at least one of the five pages (PAGE0 to PAGE4) constituting a single memory block is invalid, two or more valid page groups may occur. Since continuous reading must be guaranteed, the occurrence of invalid pages can cause an increase in the fragmentation rate (FR).

[0105] According to an exemplary embodiment, if the first page (PAGE0) and the third to fifth pages (PAGE2 to PAGE4) are valid but the second page (PAGE1) is invalid, there may be two valid page groups. That is, the fragmentation rate (FR) may be 2.

[0106] Similarly, if the first page (PAGE0) and the fourth to fifth pages (PAGE3~PAGE4) are valid but the second to third pages (PAGE1~PAGE2) are invalid, there may be two valid page groups and the fragmentation rate (FR) may be 2. Similarly, if the first page (PAGE0) and the fifth page (PAGE4) are valid but the second to fourth pages (PAGE1~PAGE3) are invalid, there may be two valid page groups and the fragmentation rate (FR) may be 2.

[0107] According to an exemplary embodiment, if the first page (PAGE0), the third page (PAGE2), and the fifth page (PAGE4) are valid, but the second page (PAGE1) and the fourth page (PAGE3) are invalid, there may be three valid page groups. That is, the fragmentation rate (FR) may be three.

[0108] According to an exemplary embodiment of the present disclosure, the fragmentation rate (FR) may correspond to the number of valid page groups.

[0109] FIG. 10 is a flowchart illustrating a method of operation of a memory controller (100) according to an exemplary embodiment of the present disclosure. FIG. 10 is a flowchart further elaborating on step S130 of FIG. 6. FIG. 5 is referenced together.

[0110] In step S131, after step S121 has been performed, the memory controller (100) may receive valid page information (VI) from the memory device (200). The valid page information (VI) may be information regarding the validity of pages contained in a plurality of memory blocks (210).

[0111] In step S132, the memory controller (100) may set a valid page to bit "1" and an invalid page, which is an invalid page, to bit "0" based on the valid page information (VI). According to an exemplary embodiment, the valid page information (VI) may indicate the validity of a page, and the memory controller (100) may use a bitmap to schematically represent the validity of the page.

[0112] In step S133, the memory controller (100) may update the valid page bitmap based on valid page information (VI). According to an exemplary embodiment, the memory controller (100) may write a bitmap corresponding to the valid page information (VI) to the valid page bitmap. According to an exemplary embodiment, a bit may be updated at a location in the bitmap corresponding to a storage area where data is written. For example, a bit indicating the validity of the page may be updated at a specific location in the bitmap corresponding to a memory block and page where data (DATA) is written.

[0113] After that, step S140 is performed.

[0114] FIG. 11 is a conceptual diagram illustrating a valid page bitmap according to an exemplary embodiment of the present disclosure. FIG. 10 is referenced together.

[0115] Referring to FIG. 11, the first to fourth memory blocks (BLK1 to BLK4) may each include four pages (PAGE0 to PAGE3).

[0116] According to an exemplary embodiment, the first page (PAGE0) and the third and fourth pages (PAGE2~PAGE3) of the first memory block (BLK1) are valid, but the second page (PAGE1) may be invalid. According to an exemplary embodiment, the first to fourth pages (PAGE3) of the second memory block (BLK2) may all be valid. According to an exemplary embodiment, the first page (PAGE0) and the fourth page (PAGE3) of the third memory block (BLK3) are valid, but the second and third pages (PAGE1~PAGE2) may be invalid. According to an exemplary embodiment, the first page (PAGE0) of the fourth memory block (BLK4) is valid, but the second to fourth pages (PAGE1~PAGE3) may be invalid.

[0117] According to an exemplary embodiment, one memory block may correspond to a column of the valid page bitmap. According to an exemplary embodiment, valid pages may be assigned bit "1" and invalid pages may be assigned bit "0".

[0118] According to an exemplary embodiment of the present disclosure, a first column of an effective page bitmap corresponding to a first memory block (BLK1) may each include bits 1, 0, 1, 1, and a second column of an effective page bitmap corresponding to a second memory block (BLK2) may each include bits 1, 1, 1, 1, and a third column of an effective page bitmap corresponding to a third memory block (BLK3) may each include bits 1, 0, 0, 1, and a fourth column of an effective page bitmap corresponding to a fourth memory block (BLK4) may each include bits 1, 0, 0, 1.

[0119] FIG. 12 is a conceptual diagram illustrating the fragmentation rate calculated in a memory controller (100) according to an exemplary embodiment of the present disclosure. FIG. 5 and FIG. 11 are referenced together.

[0120] According to an exemplary embodiment of the present disclosure, the fragmentation rate calculator (330) can detect consecutive bits for one memory block in an effective page bitmap and group the consecutive bits. The effective page bitmap determined or updated in FIG. 12 can be used by the fragmentation rate calculator (330) to calculate the fragmentation rate (FR).

[0121] When reading sequentially starting from the top row of the valid page bitmap, the first column of the valid page bitmap contains bits 1, 0, 1, and 1. At this time, there may be one consecutive bit for 1, one for 0, and two for 1 again. Among these, since the number of valid bitmap groups is 2, the fragmentation rate (FR) may be 2.

[0122] Similarly, the second column of the effective page bitmap contains bits 1, 1, 1, 1 respectively, with four consecutive bits for 1, so the number of effective bitmap groups is 1, and the fragmentation rate (FR) can be 1.

[0123] Similarly, the third column of the valid page bitmap contains bits 1, 0, 0, and 1, respectively, and the consecutive bits may be one for 1, two for 0, and one again for 1. Of these, since the number of valid bitmap groups is 2, the fragmentation rate (FR) may be 2.

[0124] Similarly, the fourth column of the valid page bitmap contains bits 1, 0, 0, and 0, respectively, with one consecutive bit for 1 and three for 0, and the number of valid bitmap groups is 1, but unlike the second column, not all have the same validity, so the fragmentation rate (FR) can be 2.

[0125] FIG. 13 is a flowchart illustrating a method of operation of a memory controller (100) according to an exemplary embodiment of the present disclosure. FIG. 13 is a flowchart further elaborating on step S140 of FIG. 6. FIG. 5 is referenced together.

[0126] In step S141, after step S130 is performed, the memory controller (100) can analyze the fragmentation rate (FR), which is the degree of fragmentation of the valid page bitmap.

[0127] In step S142, the memory controller (100) can identify a memory block having the minimum fragmentation rate among a plurality of memory blocks (Fig. 5, 210) included in the memory device (200), and can identify whether the memory block having the minimum fragmentation rate is unique.

[0128] In step S143, if the memory controller (100) is the only memory block with the minimum fragmentation rate, it can select the memory block with the minimum fragmentation rate as the source block (BLK_S) (211).

[0129] In step S144, if the memory controller (100) is not unique in having a minimum fragmentation rate, it may select a block with a small fragmentation degree as the source block (Fig. 5, 211). According to an exemplary embodiment of the present disclosure, the fragmentation degree may correspond to the number of valid page groups and invalid page groups that are adjacent to each other and have the same validity. For example, the fragmentation degree may be calculated from the number of groups with the same validity among consecutive bits for a single memory block in a valid page bitmap. The fragmentation degree will be described later with reference to Fig. 14.

[0130] After that, step S150 is performed.

[0131] FIG. 14 is a conceptual diagram illustrating the fragmentation calculated in a memory controller (100) according to an exemplary embodiment of the present disclosure.

[0132] According to an exemplary embodiment of the present disclosure, the fragmentation degree (FD) may correspond to the number of valid page groups and invalid page groups that are adjacent to each other and have the same validity. For example, the fragmentation degree (FD) may correspond to the number of valid groups among page groups in which consecutive bits for a single memory block are grouped in a valid page bitmap.

[0133] According to an exemplary embodiment, the first column and the third and fourth columns of the valid page bitmap may all have a fragmentation rate (FR) of 2. According to an exemplary embodiment of the present disclosure, the first column of the valid page bitmap may have a total of three page groups, with two valid page groups and one invalid page group, and thus the fragmentation degree (FD) may be 3. Similarly, the third column of the valid page bitmap may have a total of three page groups, with two valid page groups and one invalid page group, and thus the fragmentation degree (FD) may be 3. Similarly, the fourth column of the valid page bitmap may have a total of two page groups, with one valid page group and one invalid page group, and thus the fragmentation degree (FD) may be 2.

[0134] FIG. 15 is a conceptual diagram illustrating garbage collection performed using the fragmentation rate (FR) and fragmentation degree (FD) according to an exemplary embodiment of the present disclosure. FIG. 5 is referenced together.

[0135] According to an exemplary embodiment of the present disclosure, the GC manager (350) may select the second memory block (BLK2) with the lowest fragmentation rate (FR) as the source block (BLK_S) (Fig. 5, 211). As a result of performing a first garbage collection on the second memory block (BLK2) as the source block (BLK_S), the second memory block (BLK2) may be erased.

[0136] After that, a second garbage collection is required. The first memory block (BLK1), the third memory block (BLK3), and the fourth memory block (BLK) all have the same fragmentation rate (FR) (=2).

[0137] According to an exemplary embodiment of the present disclosure, the fourth memory block (BLK4) has a fragmentation degree (FD) of 2, so it may have a relatively lower fragmentation degree (FD) compared to the first memory block (BLK) or the third memory block (BLK3), and accordingly may be selected as a source block (BLK_S) for a second garbage collection.

[0138] FIG. 16 is a flowchart illustrating a method of operation of a storage device (10) according to an exemplary embodiment of the present disclosure. FIG. 5 is referenced together.

[0139] In step S210, the memory controller (100) can receive a write request and data (DATA) corresponding to the write request from the host.

[0140] In step S220, the memory controller (100) can issue a program command to the memory device (200) and transmit it.

[0141] In step S230, the memory device (200) may write data (DATA) to a free page among memory blocks in response to a program command. According to an exemplary embodiment, the data (DATA) may be provided after being buffered in a page buffer (Fig. 5, 250).

[0142] In step S240, the memory device (200) may provide the state of the memory block (S250). According to an exemplary embodiment, the state of the memory block may include valid page information (VI), which is the validity of the page that stores data (DATA).

[0143] In step S250, the memory controller (100) can update the valid page bitmap. According to an exemplary embodiment, the memory controller (100) receives the validity information of the page in which data has been written and can update the information of the changed page.

[0144] In step S260, the memory controller (100) can calculate the fragmentation rate (FR) based on the valid page information (VI). According to an exemplary embodiment, the fragmentation rate (FR) can be calculated based on the bit continuity of the valid page bitmap and may correspond to a valid page group among groups of bits that are adjacent to each other and have the same validity.

[0145] In step S270, the memory controller (100) may determine a memory block with a low fragmentation rate (FR) as the source block (Fig. 1, 211). According to an exemplary embodiment, the memory controller (100) may sort the fragmentation rates (FR) in order of size and select the memory blocks with the lowest fragmentation rate (FR) as the source blocks (211).

[0146] In step S280, the memory controller (100) may command the memory device (200) to perform garbage collection. According to an exemplary embodiment of the present disclosure, the memory controller (100) may increase input / output efficiency by selecting a memory block with a low fragmentation rate (FR) as a source block (BLK_S) and performing garbage collection on the source block (BLK_S).

[0147] In step S290, the memory device (200) can perform garbage collection by copying the source block (BLK_S) to the destination block (BLK_D). According to an exemplary embodiment, the memory device (200) can copy the valid pages of the source block (BLK_S) (211) to the free pages of the destination block (BLK_V) (Fig. 5, 213).

[0148] FIG. 17 is a block diagram illustrating a memory system (1) according to an exemplary embodiment of the present disclosure. Since the storage system (500) illustrated in FIG. 17 is functionally similar to the storage device (10) of FIG. 5, redundant descriptions are omitted.

[0149] The host system (400) and the storage system (500) can configure the memory system (1). As an exemplary embodiment, the memory system (1) is capable of transmitting and receiving information in a wireless environment, comprising a computer, UMPC (Ultra Mobile PC), workstation, netbook, PDA (Personal Digital Assistants), portable computer, web tablet, tablet computer, wireless phone, mobile phone, smartphone, e-book, PMP (portable multimedia player), portable game console, navigation device, black box, digital camera, DMB (Digital Multimedia Broadcasting) player, 3-dimensional television, smart television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, storage constituting a data center, and storage constituting a data center. It can be configured as a device, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID (radio frequency identification) device, or one of various components constituting a computing system.

[0150] The host system (400) includes at least one operating system (410), and the operating system (410) manages and controls the functions and operations of the host overall and can provide interaction between the host and a user using the memory system (1).

[0151] The operating system (410) supports functions and operations corresponding to the user's purpose and use, and, for example, can be classified into a general operating system and a mobile operating system according to the mobility of the host. In addition, the general operating system in the operating system (410) can be classified into a personal operating system and an enterprise operating system according to the user's usage environment. For example, the personal operating system is a system specialized to support service provision functions for general users and includes Windows and Chrome, etc., and the enterprise operating system is a system specialized to secure and support high performance and may include Windows Server, Linux and Unix, etc.

[0152] A mobile operating system in an operating system (410) is a system specialized to support mobility service provision functions and system power saving functions for users, and may include Android, iOS, Windows Mobile, etc. In an exemplary embodiment, the host may include a plurality of operating systems and also executes an operating system to perform operations with a memory system (1) corresponding to a user request. Here, the host transmits a plurality of commands corresponding to the user request to the memory system (1), and accordingly, the memory system (1) can perform operations corresponding to the commands, i.e., operations corresponding to the user request.

[0153] Read and write requests of the host system (400) can be performed on a file basis. That is, through file read (READ_F) and file write (WRITE_F) requests, data can be stored in the storage system (500) from the host system (400), or data stored in the storage system (500) can be read out to the host system (400).

[0154] The storage system (500) may be implemented as, for example, a PC (personal computer), a data server, a network-attached storage (NAS), an IoT (Internet of Things) device, or a portable electronic device. The portable electronic device may be a laptop computer, a mobile phone, a smartphone, a tablet PC, a PDA (personal digital assistant), an EDA (enterprise digital assistant), a digital still camera, a digital video camera, an audio device, a PMP (portable multimedia player), a PND (personal navigation device), an MP3 player, a handheld game console, an e-book, a wearable device, etc.

[0155] The storage system (500) may include a host interface layer (510), a flash conversion layer (520), a flash interface layer (530), and a non-volatile memory (540).

[0156] The host interface layer (510) may be a logical area where interfacing between the host system (400) and the storage system (500) takes place.

[0157] The flash conversion layer (520) can be understood as another form of the flash conversion layer (300) of FIG. 5, and the input / output interface (521) can provide the same function as the input / output interface (310) of FIG. 5, the fragmentation rate calculator (522) can provide the same function as the fragmentation rate calculator (330) of FIG. 5, and the GC manager (523) can provide the same function as the GC manager (350) of FIG. 5, so redundant descriptions are omitted.

[0158] The host interface layer (510) and the flash conversion layer (520) can write or read data on a sector basis. That is, depending on the read / write request of the host system, the host interface layer (510) can request read / write requests (READ_S, WRITE_S) on a sector basis to the flash conversion layer (520).

[0159] The flash interface layer (530) can provide interfacing between the flash conversion layer (520) and the non-volatile memory (540). According to an exemplary embodiment, reading data (READ_P) and writing data (WRITE_P) may be performed on a page basis, but erasing data (ERASE_B) may be performed on a block basis.

[0160] The non-volatile memory (540) can be understood as the memory device (200) of FIG. 5, so a redundant description is omitted.

[0161] The memory system (1) according to the present invention can be mounted using various types of packages. For example, the memory system (1) according to the present invention can be mounted in the form of a PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip on Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package, etc.

[0162] FIG. 18 is a block diagram illustrating a storage system (1000) according to an exemplary embodiment of the present disclosure.

[0163] FIG. 18 is a diagram illustrating a storage system (1000) to which a storage device (e.g., 10 of FIG. 5) according to an embodiment of the present invention is applied. The system (1000) of FIG. 18 may basically be a mobile system such as a mobile phone, smartphone, tablet PC, wearable device, healthcare device, or IoT (Internet of Things) device as a portable communication terminal. However, the system (1000) of FIG. 18 is not necessarily limited to a mobile system and may be a personal computer (PC), laptop computer, server, media player, or automotive device such as navigation.

[0164] Referring to FIG. 18, the system (1000) may include a main processor (1100), memory (1200a, 1200b) and storage devices (1300a, 1300b), and additionally may include one or more of an image capturing device (1410), a user input device (1420), a sensor (1430), a communication device (1440), a display (1450), a speaker (1460), a power supplying device (1470), and a connecting interface (1480).

[0165] The main processor (1100) can control the overall operation of the system (1000), more specifically, the operation of other components that make up the system (1000). Such a main processor (1100) can be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0166] The main processor (1100) may include one or more CPU cores (1110) and may further include a controller (1120) for controlling memory (1200a, 1200b) and / or storage devices (1300a, 1300b). According to an embodiment, the main processor (1100) may further include an accelerator (1130), which is a dedicated circuit for high-speed data computation, such as artificial intelligence (AI) data computation. Such an accelerator (1130) may include a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), and / or a Data Processing Unit (DPU), and may be implemented as a separate chip physically independent from other components of the main processor (1100).

[0167] The memory (1200a, 1200b) can be used as the main memory of the system (1000) and may include volatile memory such as SRAM and / or DRAM, but may also include non-volatile memory such as flash memory, PRAM and / or RRAM. The memory (1200a, 1200b) may also be implemented within the same package as the main processor (1100).

[0168] The storage device (1300a, 1300b) can function as a non-volatile storage device that stores data regardless of whether power is supplied, and can have a relatively large storage capacity compared to the memory (1200a, 1200b). The storage device (1300a, 1300b) may include a storage controller (1310a, 1310b) and a non-volatile memory (NVM) (1320a, 1320b) that stores data under the control of the storage controller (1310a, 1310b). The non-volatile memory (1320a, 1320b) may include V-NAND flash memory with a 2D (2-dimensional) or 3D (3-dimensional) structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM.

[0169] The storage device (1300a, 1300b) may be included in the system (1000) in a state physically separated from the main processor (1100), or it may be implemented within the same package as the main processor (1100). Additionally, the storage device (1300a, 1300b) may have a form such as a solid state device (SSD) or a memory card, and may be detachably coupled to other components of the system (1000) through an interface such as the connection interface (1480) described later. Such storage device (1300a, 1300b) may be a device to which standard protocols such as universal flash storage (UFS), embedded multi-media card (eMMC), or non-volatile memory express (NVMe) are applied, but is not necessarily limited thereto.

[0170] The shooting device (1410) can take still images or video and may be a camera, camcorder and / or webcam, etc.

[0171] The user input device (1420) can receive various types of data input from a user of the system (1000) and may be a touch pad, keypad, keyboard, mouse and / or microphone, etc.

[0172] The sensor (1430) can detect various types of physical quantities that may be obtained from outside the system (1000) and convert the detected physical quantities into electrical signals. Such a sensor (1430) may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor and / or a gyroscope sensor, etc.

[0173] The communication device (1440) can transmit and receive signals between other devices outside the system (1000) according to various communication protocols. Such a communication device (1440) may be implemented including an antenna, a transceiver and / or a modem.

[0174] The display (1450) and speaker (1460) can function as output devices that output visual information and auditory information, respectively, to the user of the system (1000).

[0175] The power supply unit (1470) can appropriately convert power supplied from a battery (not shown) and / or an external power source built into the system (1000) and supply it to each component of the system (1000).

[0176] The connection interface (1480) can provide a connection between the system (1000) and an external device connected to the system (1000) that can exchange data with the system (1000). The connection interface (1480) can be implemented in various interface methods such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage), CF (compact flash) card interface, etc.

[0177] FIG. 19 is a block diagram showing a memory system (20) according to an exemplary embodiment of the present disclosure.

[0178] Referring to FIG. 19, the memory system (20) may include a memory controller (100) and a memory device (200). The memory controller (100) may correspond to the memory controller (100) of FIG. 5, and the memory device (200) may correspond to one of the non-volatile memory devices (NVM11~NVMmn) that communicate with the memory controller (100) based on one of the plurality of channels (CH1~CHm) of FIG. 3, so redundant descriptions are omitted.

[0179] The memory device (200) may include first to eighth pins (P11 to P18), a memory interface (270), control logic (230), and a memory cell array (220).

[0180] The memory interface (270) can receive a chip enable signal (nCE) from the memory controller (100) through the first pin (P11). The memory interface (270) can transmit and receive signals with the memory controller (100) through the second to eighth pins (P12 to P18) according to the chip enable signal (nCE). For example, when the chip enable signal (nCE) is in an enable state (e.g., low level), the memory interface (270) can transmit and receive signals with the memory controller (100) through the second to eighth pins (P12 to P18).

[0181] The memory interface (270) can receive a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) from the memory controller (100) through the second to fourth pins (P12 to P14). The memory interface (270) can receive a data signal (DQ) from the memory controller (100) or transmit a data signal (DQ) to the memory controller (100) through the seventh pin (P17). A command (CMD), an address (ADDR), and data (DATA) can be transmitted through the data signal (DQ). For example, the data signal (DQ) can be transmitted through a plurality of data signal lines. In this case, the seventh pin (P17) may include a plurality of pins corresponding to the plurality of data signals.

[0182] The memory interface (270) can obtain a command (CMD) from a data signal (DQ) received during the enable period (e.g., high level state) of a command latch enable signal (CLE) based on the toggle timings of a write enable signal (nWE). The memory interface (270) can obtain an address (ADDR) from a data signal (DQ) received during the enable period (e.g., high level state) of an address latch enable signal (ALE) based on the toggle timings of a write enable signal (nWE).

[0183] In an exemplary embodiment, the write enable signal (nWE) may maintain a static state (e.g., high level or low level) and then toggle between the high level and the low level. For example, the write enable signal (nWE) may toggle during the interval in which a command (CMD) or an address (ADDR) is transmitted. Accordingly, the memory interface (270) may obtain a command (CMD) or an address (ADDR) based on the toggle timings of the write enable signal (nWE).

[0184] The memory interface (270) can receive a read enable signal (nRE) from the memory controller (100) through the fifth pin (P15). The memory interface (270) can receive a data strobe signal (DQS) from the memory controller (100) through the sixth pin (P16) or transmit a data strobe signal (DQS) to the memory controller (100).

[0185] In the data (DATA) output operation of the memory device (200), the memory interface (270) may receive a read-enable signal (nRE) that toggles through the fifth pin (P15) before outputting the data (DATA). The memory interface (270) may generate a data strobe signal (DQS) that toggles based on the toggling of the read-enable signal (nRE). For example, the memory interface (270) may generate a data strobe signal (DQS) that begins to toggle after a predetermined delay (e.g., tDQSRE) based on the toggling start time of the read-enable signal (nRE). The memory interface (270) may transmit a data signal (DQ) containing data (DATA) based on the toggling timing of the data strobe signal (DQS). Accordingly, data (DATA) can be aligned with the toggle timing of the data strobe signal (DQS) and transmitted to the memory controller (100).

[0186] In the data (DATA) input operation of the memory device (200), when a data signal (DQ) containing data (DATA) is received from the memory controller (100), the memory interface (270) may receive a data strobe signal (DQS) that toggles along with the data (DATA) from the memory controller (100). The memory interface (270) may acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS). For example, the memory interface (270) may acquire data (DATA) by sampling the data signal (DQ) at the rising edge and falling edge of the data strobe signal (DQS).

[0187] The memory interface (270) can transmit a ready / busy output signal (nR / B) to the memory controller (100) via the eighth pin (P18). The memory interface (270) can transmit status information of the memory device (200) to the memory controller (100) via the ready / busy output signal (nR / B). When the memory device (200) is in a busy state (i.e., when internal operations of the memory device (200) are being performed), the memory interface (270) can transmit a ready / busy output signal (nR / B) indicating the busy state to the memory controller (100). When the memory device (200) is in a ready state (i.e., when internal operations of the memory device (200) are not being performed or have been completed), the memory interface (270) can transmit a ready / busy output signal (nR / B) indicating the ready state to the memory controller (100). For example, while the memory device (200) reads data (DATA) from the memory cell array (220) in response to a page read command, the memory interface (270) can transmit a ready / busy output signal (nR / B) indicating a busy state (e.g., low level) to the memory controller (100). For example, while the memory device (200) programs data (DATA) into the memory cell array (220) in response to a program command, the memory interface (270) can transmit a ready / busy output signal (nR / B) indicating a busy state to the memory controller (100).

[0188] The control logic (230) can control various operations of the memory device (200) overall. The control logic (230) can receive a command / address (CMD / ADDR) obtained from the memory interface (270). The control logic (230) can generate control signals to control other components of the memory device (200) according to the received command / address (CMD / ADDR). For example, the control logic (230) can generate various control signals to program data (DATA) into the memory cell array (220) or to read data (DATA) from the memory cell array (220).

[0189] The memory cell array (220) can store data (DATA) obtained from the memory interface (270) under the control of the control logic (230). The memory cell array (220) can output the stored data (DATA) to the memory interface (270) under the control of the control logic (230).

[0190] The memory cell array (220) may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells may be RRAM (Resistive Random Access Memory) cells, FRAM (Ferroelectric Random Access Memory) cells, PRAM (Phase Change Random Access Memory) cells, TRAM (Thyristor Random Access Memory) cells, or MRAM (Magnetic Random Access Memory) cells. Hereinafter, embodiments of the present invention will be described with a focus on embodiments in which the memory cells are NAND flash memory cells.

[0191] The memory controller (100) may include first to eighth pins (P21 to P28) and a NAND interface (160). The first to eighth pins (P21 to P28) may correspond to the first to eighth pins (P11 to P18) of the memory device (200).

[0192] The NAND interface (160) can transmit a chip enable signal (nCE) to a memory device (200) through the first pin (P21). The NAND interface (160) can transmit and receive signals to and from the selected memory device (200) through the second to eighth pins (P22~P28) via the chip enable signal (nCE).

[0193] The NAND interface (160) can transmit a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) to the memory device (200) through the second to fourth pins (P22 to P24). The NAND interface (160) can transmit a data signal (DQ) to the memory device (200) or receive a data signal (DQ) from the memory device (200) through the seventh pin (P27).

[0194] The NAND interface (160) can transmit a data signal (DQ) containing a command (CMD) or an address (ADDR) to the memory device (200) along with a toggling write enable signal (nWE). The NAND interface (160) can transmit a data signal (DQ) containing a command (CMD) to the memory device (200) by transmitting a command latch enable signal (CLE) having an enable state, and can transmit a data signal (DQ) containing an address (ADDR) to the memory device (200) by transmitting an address latch enable signal (ALE) having an enable state.

[0195] The NAND interface (160) can transmit a read-enable signal (nRE) to the memory device (200) through the fifth pin (P25). The NAND interface (160) can receive a data strobe signal (DQS) from the memory device (200) or transmit a data strobe signal (DQS) to the memory device (200) through the sixth pin (P26).

[0196] In the data (DATA) output operation of the memory device (200), the NAND interface (160) can generate a toggle read-enable signal (nRE) and transmit the read-enable signal (nRE) to the memory device (200). For example, the NAND interface (160) can generate a read-enable signal (nRE) that changes from a fixed state (e.g., high level or low level) to a toggle state before the data (DATA) is output. Accordingly, a toggle data strobe signal (DQS) can be generated in the memory device (200) based on the read-enable signal (nRE). The NAND interface (160) can receive a data signal (DQ) containing data (DATA) along with the toggle data strobe signal (DQS) from the memory device (200). The NAND interface (160) can acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS).

[0197] In the data (DATA) input operation of the memory device (200), the NAND interface (160) can generate a toggling data strobe signal (DQS). For example, the NAND interface (160) can generate a data strobe signal (DQS) that changes from a fixed state (e.g., high level or low level) to a toggling state before transmitting the data (DATA). Based on the toggling timings of the data strobe signal (DQS), the NAND interface (160) can transmit a data signal (DQ) containing the data (DATA) to the memory device (200).

[0198] The NAND interface (160) can receive a ready / busy output signal (nR / B) from the memory device (200) through the eighth pin (P28). The NAND interface (160) can determine the status information of the memory device (200) based on the ready / busy output signal (nR / B).

[0199] FIG. 20 is a block diagram illustrating a UFS system (2000) according to an exemplary embodiment of the present invention.

[0200] The UFS system (2000) is a system that follows the UFS standard published by JEDEC (Joint Electron Device Engineering Council) and may include a UFS host (2100), a UFS device (2200), and a UFS interface (2300). The description of the storage device (10) of FIG. 5 described above may also be applied to the UFS system (2000) of FIG. 20 to the extent that it does not conflict with the description below.

[0201] Referring to FIG. 20, a UFS host (2100) and a UFS device (2200) can be interconnected via a UFS interface (2300). The UFS device (2200) may correspond to the storage device (10) of FIG. 5, and the UFS device controller (2210) and non-volatile memory (2220) may correspond to the memory controller (100) and memory device (200) of FIG. 5, respectively.

[0202] A UFS host (2100) may include a UFS host controller (2110), an application (2120), a UFS driver (2130), a host memory (2140), and a UIC (UFS interconnect) layer (2150). A UFS device (2200) may include a UFS device controller (2210), non-volatile memory (2220), a storage interface (2230), device memory (2240), a UIC layer (2250), and a regulator (2260). The non-volatile memory (2220) may be composed of a plurality of memory units (2221), and such memory units (2221) may include V-NAND flash memory of a 2D or 3D structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM. The UFS device controller (2210) and the non-volatile memory (2220) can be connected to each other through a storage interface (2230). The storage interface (2230) can be implemented to comply with standard protocols such as Toggle or ONFI.

[0203] The application (2120) may refer to a program that wishes to communicate with the UFS device (2200) in order to use the functions of the UFS device (2200). The application (2120) may send an input-output request (IOR) to the UFS driver (2130) for input / output to the UFS device (2200). The input-output request (IOR) may refer to a data read request, a write request, and / or a discard request, but is not necessarily limited thereto.

[0204] The UFS driver (2130) can manage the UFS host controller (2110) through the UFS-HCI (host controller interface). The UFS driver (2130) can convert an I / O request generated by an application (2120) into a UFS command defined by the UFS standard and transmit the converted UFS command to the UFS host controller (2110). A single I / O request can be converted into multiple UFS commands. The UFS commands may be commands defined by the SCSI standard by default, but they may also be commands specific to the UFS standard.

[0205] The UFS host controller (2110) can transmit UFS commands converted by the UFS driver (2130) to the UIC layer (2250) of the UFS device (2200) through the UIC layer (2150) and the UFS interface (2300). In this process, the UFS host register (2111) of the UFS host controller (2110) can serve as a command queue (CQ).

[0206] The UIC layer (2150) on the UFS host (2100) side may include MIPI M-PHY (2151) and MIPI UniPro (2152), and the UIC layer (2250) on the UFS device (2200) side may also include MIPI M-PHY (2251) and MIPI UniPro (2252).

[0207] The UFS interface (2300) may include a line transmitting a reference clock (REF_CLK), a line transmitting a hardware reset signal (RESET_n) for the UFS device (2200), a pair of lines transmitting a differential input signal pair (DIN_t and DIN_c), and a pair of lines transmitting a differential output signal pair (DOUT_t and DOUT_c).

[0208] The frequency value of the reference clock provided from the UFS host (2100) to the UFS device (2200) may be one of four values: 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not necessarily limited thereto. The UFS host (2100) may change the frequency value of the reference clock even while in operation, that is, while data transmission and reception is being performed between the UFS host (2100) and the UFS device (2200). The UFS device (2200) may generate clocks of various frequencies from the reference clock provided by the UFS host (2100) using a phase-locked loop (PLL), etc. Additionally, the UFS host (2100) may set the value of the data rate between the UFS host (2100) and the UFS device (2200) through the frequency value of the reference clock. That is, the value of the data rate may be determined depending on the frequency value of the reference clock.

[0209] The UFS interface (2300) may support multiple lanes, and each lane may be implemented as a differential pair. For example, the UFS interface (2300) may include one or more receive lanes and one or more transmit lanes. In FIG. 5, a pair of lines transmitting a differential input signal pair (DIN_T and DIN_C) may each constitute a receive lane, and a pair of lines transmitting a differential output signal pair (DOUT_T and DOUT_C) may each constitute a transmit lane. Although FIG. 5 shows one transmit lane and one receive lane, the number of transmit lanes and receive lanes may be changed.

[0210] The receiving lane and the transmitting lane can transmit data in a serial communication manner, and full-duplex communication between the UFS host (2100) and the UFS device (2200) is possible due to the structure in which the receiving lane and the transmitting lane are separated. That is, the UFS device (2200) can transmit data to the UFS host (2100) through the transmitting lane even while receiving data from the UFS host (2100) through the receiving lane. In addition, control data such as commands from the UFS host (2100) to the UFS device (2200), and user data that the UFS host (2100) intends to store in the non-volatile memory (2220) of the UFS device (2200) or read from the non-volatile memory (2220) can be transmitted through the same lane. Accordingly, there is no need to provide additional lanes for data transmission between the UFS host (2100) and the UFS device (2200) in addition to a pair of receiving lanes and a pair of transmitting lanes.

[0211] The UFS device controller (2210) of the UFS device (2200) can control the overall operation of the UFS device (2200). The UFS device controller (2210) can manage non-volatile memory (2220) through a logical unit (LU) (2211), which is a logical data storage unit. The number of LUs (2211) may be eight, but is not limited thereto. The UFS device controller (2210) may include a flash translation layer (FTL) and can convert a logical data address, such as a logical block address (LBA), transmitted from the UFS host (2100) into a physical data address, such as a physical block address (PBA), using the address mapping information of the FTL. A logical block for storing user data in the UFS system (2000) may have a size within a predetermined range. For example, the minimum size of a logical block can be set to 4Kbyte.

[0212] When a command from the UFS host (2100) is input to the UFS device (2200) through the UIC layer (2250), the UFS device controller (2210) performs an operation according to the input command, and when the operation is completed, it can send a completion response to the UFS host (2100).

[0213] For example, if a UFS host (2100) intends to store user data in a UFS device (2200), the UFS host (2100) may send a data storage command to the UFS device (2200). When the UFS host (2100) receives a response from the UFS device (2200) that the user data is ready to be transferred, the UFS host (2100) may transfer the user data to the UFS device (2200). The UFS device controller (2210) may temporarily store the transferred user data in the device memory (2240) and, based on the address mapping information of the FTL, store the user data temporarily stored in the device memory (2240) in a selected location in the non-volatile memory (2220).

[0214] As another example, when a UFS host (2100) intends to read user data stored in a UFS device (2200), the UFS host (2100) may transmit a data read command to the UFS device (2200). Upon receiving the command, the UFS device controller (2210) may read user data from the non-volatile memory (2220) based on the data read command and temporarily store the read user data in the device memory (2240). During this read process, the UFS device controller (2210) may detect and correct errors in the read user data using an embedded ECC (error correction code) engine (not shown). More specifically, the ECC engine may generate parity bits for the data to be written to the non-volatile memory (2220), and the generated parity bits may be stored in the non-volatile memory (2220) together with the data to be written. When reading data from non-volatile memory (2220), the ECC engine can correct errors in the read data using parity bits read from non-volatile memory (2220) along with the read data, and output the read data with the errors corrected.

[0215] Additionally, the UFS device controller (2210) can transmit user data temporarily stored in the device memory (2240) to the UFS host (2100). Furthermore, the UFS device controller (2210) may further include an AES (advanced encryption standard) engine (not shown). The AES engine can perform at least one of encryption and decryption operations on data input to the UFS device controller (2210) using a symmetric-key algorithm.

[0216] The UFS host (2100) can store commands to be transmitted to the UFS device (2200) in order in a UFS host register (2111) that can function as a command queue, and can transmit commands to the UFS device (2200) in the said order. At this time, the UFS host (2100) can transmit the next command waiting in the command queue to the UFS device (2200) even if the previously transmitted command is still being processed by the UFS device (2200), that is, before receiving notification that the previously transmitted command has been completed by the UFS device (2200), and accordingly, the UFS device (2200) can also receive the next command from the UFS host (2100) even while processing the previously transmitted command. The maximum number of commands that can be stored in such a command queue (queue depth) may be, for example, 32. Additionally, the command queue can be implemented as a circular queue type, which indicates the start and end of the column of commands stored in the queue through a head pointer and a tail pointer, respectively.

[0217] Each of the plurality of memory units (2221) may include a memory cell array (not shown) and a control circuit (not shown) that controls the operation of the memory cell array. The memory cell array may include a two-dimensional memory cell array or a three-dimensional memory cell array. The memory cell array includes a plurality of memory cells, and each memory cell may be a single-level cell (SLC) that stores 1 bit of information, but may also be a cell that stores 2 bits or more of information, such as an MLC (multi-level cell), TLC (triple-level cell), or QLC (quadruple-level cell). The three-dimensional memory cell array may include a vertically oriented NAND string such that at least one memory cell is positioned above another memory cell.

[0218] VCC, VCCQ, VCCQ2, etc., may be input as power voltages to the UFS device (2200). VCC is the main power voltage for the UFS device (2200) and may have a value of 2.4 to 3.6 V. VCCQ is a power voltage for supplying a low range of voltage, mainly for the UFS device controller (2210), and may have a value of 1.14 to 1.26 V. VCCQ2 is a power voltage for supplying a range of voltage lower than VCC but higher than VCCQ, mainly for an input / output interface such as MIPI M-PHY (2251), and may have a value of 1.7 to 1.95 V. The above power voltages may be supplied to each component of the UFS device (2200) through a regulator (2260). The regulator (2260) may be implemented as a set of unit regulators each connected to different of the aforementioned power voltages.

[0219] FIG. 21 is a cross-sectional view of the structure of a memory device that can be applied to a storage device (10) according to an exemplary embodiment of the present disclosure.

[0220] Referring to FIG. 21, the memory device (600) may have a C2C (chip-to-chip) structure. A C2C structure may mean fabricating an upper chip containing a cell region (CELL) on a first wafer, fabricating a lower chip containing a peripheral circuit region (PERI) on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other by a bonding method. For example, the bonding method may mean electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For instance, if the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten.

[0221] Each of the peripheral circuit region (PERI) and cell region (CELL) of the memory device (600) may include an external pad bonding region (PA), a wordline bonding region (WLBA), and a bitline bonding region (BLBA). The peripheral circuit region (PERI) may include a first substrate (710), an interlayer insulating layer (715), a plurality of circuit elements (720a, 720b, 720c) formed on the first substrate (710), a first metal layer (730a, 730b, 730c) connected to each of the plurality of circuit elements (720a, 720b, 720c), and a second metal layer (740a, 740b, 740c) formed on the first metal layer (730a, 730b, 730c). In one embodiment, the first metal layer (730a, 730b, 730c) may be formed of tungsten, which has relatively high resistance, and the second metal layer (740a, 740b, 740c) may be formed of copper, which has relatively low resistance.

[0222] In this specification, only the first metal layer (730a, 730b, 730c) and the second metal layer (740a, 740b, 740c) are illustrated and described, but are not limited thereto, and at least one additional metal layer may be formed on the second metal layer (740a, 740b, 740c). At least some of the one or more metal layers formed on the upper part of the second metal layer (740a, 740b, 740c) may be formed of aluminum or the like, having a lower resistance than the copper forming the second metal layer (740a, 740b, 740c).

[0223] The interlayer insulating layer (715) is disposed on a first substrate (710) to cover a plurality of circuit elements (720a, 720b, 720c), a first metal layer (730a, 730b, 730c), and a second metal layer (740a, 740b, 740c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0224] A lower bonding metal (771b, 772b) may be formed on the second metal layer (740b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (771b, 772b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (871b, 872b) of the cell region (CELL) by a bonding method, and the lower bonding metal (771b, 772b) and the upper bonding metal (871b, 872b) may be formed of aluminum, copper, or tungsten, etc. The upper bonding metal (871b, 872b) of the cell region (CELL) may be referred to as the first metal pads, and the lower bonding metal (771b, 772b) of the peripheral circuit region (PERI) may be referred to as the second metal pads.

[0225] A cell region (CELL) may provide at least one memory block. The cell region (CELL) may include a second substrate (810) and a common source line (820). On the second substrate (810), a plurality of word lines (831-838; 830) may be stacked along a direction perpendicular to the upper surface of the second substrate (810) (Z-axis direction). String selection lines and ground selection lines may be disposed on the upper and lower portions of the word lines (830), respectively, and a plurality of word lines (830) may be disposed between the string selection lines and the ground selection lines.

[0226] In the bitline bonding region (BLBA), the channel structure (CH) may extend in a direction perpendicular to the upper surface of the second substrate (810) and penetrate word lines (830), string select lines, and ground select lines. The channel structure (CH) may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to a first metal layer (850c) and a second metal layer (860c). For example, the first metal layer (850c) may be a bitline contact, and the second metal layer (860c) may be a bitline. In one embodiment, the bitline may extend along a first direction (Y-axis direction) parallel to the upper surface of the second substrate (810).

[0227] In one embodiment illustrated in FIG. 21, the area where the channel structure (CH) and bitlines are placed may be defined as a bitline bonding area (BLBA). The bitlines may be electrically connected to circuit elements (720c) that provide a page buffer (893) in the peripheral circuit area (PERI) in the bitline bonding area (BLBA). As an example, the bitlines may be connected to upper bonding metals (871c, 872c) in the peripheral circuit area (PERI), and the upper bonding metals (871c, 872c) may be connected to lower bonding metals (771c, 772c) that are connected to circuit elements (720c) of the page buffer (893).

[0228] In the wordline bonding area (WLBA), wordlines (830) may extend along a second direction (X-axis direction) parallel to the upper surface of the second substrate (810) and may be connected to a plurality of cell contact plugs (841-847; 840). The wordlines (830) and the cell contact plugs (840) may be connected to each other at pads provided by extending at least some of the wordlines (830) at different lengths along the second direction (X-axis direction). A first metal layer (850b) and a second metal layer (860b) may be connected in sequence to the upper portion of the cell contact plugs (840) connected to the wordlines (830). The cell contact plugs (840) can be connected to the peripheral circuit area (PERI) through the upper bonding metal (871b, 872b) of the cell area (CELL) and the lower bonding metal (771b, 772b) of the peripheral circuit area (PERI) in the wordline bonding area (WLBA).

[0229] Cell contact plugs (840) may be electrically connected to circuit elements (720b) ​​that provide a row decoder (894) in the peripheral circuit region (PERI). In one embodiment, the operating voltage of the circuit elements (720b) ​​that provide the row decoder (894) may be different from the operating voltage of the circuit elements (720c) that provide the page buffer (893). For example, the operating voltage of the circuit elements (720c) that provide the page buffer (893) may be greater than the operating voltage of the circuit elements (720b) ​​that provide the row decoder (894).

[0230] A common source line contact plug (880) may be disposed in the external pad bonding area (PA). The common source line contact plug (880) is formed of a conductive material such as a metal, a metal compound, or polysilicon and may be electrically connected to the common source line (820). A first metal layer (850a) and a second metal layer (860a) may be sequentially laminated on top of the common source line contact plug (880). For example, the area where the common source line contact plug (880), the first metal layer (850a), and the second metal layer (860a) are disposed may be defined as the external pad bonding area (PA).

[0231] Meanwhile, input / output pads (705, 805) may be disposed in the external pad bonding area (PA). Referring to FIG. 21, a lower insulating film (701) covering the lower surface of the first substrate (710) may be formed on the lower surface of the first substrate (710), and a first input / output pad (705) may be formed on the lower insulating film (701). The first input / output pad (705) is connected to at least one of a plurality of circuit elements (720a, 720b, 720c) disposed in the peripheral circuit area (PERI) through the first input / output contact plug (703), and may be separated from the first substrate (710) by the lower insulating film (701). Additionally, a side insulating film is disposed between the first input / output contact plug (703) and the first substrate (710) to electrically separate the first input / output contact plug (703) and the first substrate (710).

[0232] Referring to FIG. 21, an upper insulating film (801) covering the upper surface of the second substrate (810) may be formed on the upper surface of the second substrate (810), and a second input / output pad (805) may be disposed on the upper insulating film (801). The second input / output pad (805) may be connected to at least one of a plurality of circuit elements (720a, 720b, 720c) disposed in the peripheral circuit region (PERI) through a second input / output contact plug (803).

[0233] According to the embodiments, the second substrate (810) and common source line (820), etc., may not be placed in the area where the second input / output contact plug (803) is placed. Additionally, the second input / output pad (805) may not overlap with the word lines (830) in the third direction (Z-axis direction). Referring to FIG. 21, the second input / output contact plug (803) is separated from the second substrate (810) in a direction parallel to the upper surface of the second substrate (810) and may be connected to the second input / output pad (805) by penetrating the interlayer insulating layer (815) of the cell area (CELL).

[0234] According to embodiments, the first input / output pad (705) and the second input / output pad (805) may be formed optionally. For example, the memory device (600) may include only the first input / output pad (705) disposed on the upper part of the first substrate (710), or only the second input / output pad (805) disposed on the upper part of the second substrate (810). Alternatively, the memory device (600) may include both the first input / output pad (705) and the second input / output pad (805).

[0235] In each of the external pad bonding region (PA) and bitline bonding region (BLBA) included in the cell region (CELL) and peripheral circuit region (PERI), the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0236] The memory device (600) may form a lower metal pattern (773a) of the same shape as the upper metal pattern (872a) of the cell region (CELL) on the upper metal layer of the peripheral circuit region (PERI) in the external pad bonding region (PA), corresponding to the upper metal pattern (872a) formed on the upper metal layer of the cell region (CELL). The lower metal pattern (773a) formed on the upper metal layer of the peripheral circuit region (PERI) may not be connected to a separate contact in the peripheral circuit region (PERI). Similarly, the memory device may form an upper metal pattern of the same shape as the lower metal pattern of the peripheral circuit region (PERI) on the upper metal layer of the cell region (CELL) in the external pad bonding region (PA), corresponding to the lower metal pattern formed on the upper metal layer of the peripheral circuit region (PERI).

[0237] A lower bonding metal (771b, 772b) may be formed on the second metal layer (740b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (771b, 772b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (871b, 872b) of the cell region (CELL) by a bonding method.

[0238] Additionally, in the bitline bonding area (BLBA), an upper metal pattern (892) of the same shape as the lower metal pattern (752) of the peripheral circuit area (PERI) can be formed on the upper metal layer of the cell area (CELL) in correspondence with the lower metal pattern (752) formed on the upper metal layer of the peripheral circuit area (PERI). In an exemplary embodiment, a contact may not be formed on the upper metal pattern (892) formed on the upper metal layer of the cell area (CELL).

[0239] In an exemplary embodiment, corresponding to a metal pattern formed on the uppermost metal layer of one of the cell region (CELL) and peripheral circuit region (PERI), a reinforced metal pattern having the same cross-sectional shape as the formed metal pattern may be formed on the uppermost metal layer of the other of the cell region (CELL) and peripheral circuit region (PERI). Contacts may not be formed in the reinforced metal pattern.

[0240] FIG. 22 is a block diagram illustrating a data center (3000) to which a storage device (10) according to an exemplary embodiment of the present disclosure is applied.

[0241] Referring to FIG. 22, the data center (3000) is a facility that collects various data and provides services, and may be referred to as a data storage center. The data center (3000) may be a system for operating search engines and databases, and may be a computing system used by companies such as banks or government agencies. The data center (3000) may include application servers (3100 to 3100n) and storage servers (3200 to 3200m). The number of application servers (3100 to 3100n) and the number of storage servers (3200 to 3200m) may be selected in various ways according to the embodiment, and the number of application servers (3100 to 3100n) and the number of storage servers (3200 to 3200m) may differ from each other.

[0242] The application server (3100) or storage server (3200) may include at least one of a processor (3110, 3210) and memory (3120, 3220). To describe the storage server (3200) as an example, the processor (3210) can control the overall operation of the storage server (3200) and can access the memory (3220) to execute instructions and / or data loaded into the memory (3220). The memory (3220) may be DDR SDRAM (Double Data Rate Synchronous DRAM), HBM (High Bandwidth Memory), HMC (Hybrid Memory Cube), DIMM (Dual In-line Memory Module), Optane DIMM, or NVMDIMM (Non-Volatile DIMM). Depending on the embodiment, the number of processors (3210) and the number of memory (3220) included in the storage server (3200) may be selected in various ways. In one embodiment, the processor (3210) and memory (3220) may provide a processor-memory pair. In one embodiment, the number of processors (3210) and memory (3220) may differ. The processor (3210) may include a single-core processor or a multi-core processor. The above description of the storage server (3200) may similarly apply to the application server (3100). Depending on the embodiment, the application server (3100) may not include a storage device (3150). The storage server (3200) may include at least one storage device (3250). The number of storage devices (3250) included in the storage server (3200) may be selected differently depending on the embodiment.

[0243] Application servers (3100 to 3100n) and storage servers (3200 to 3200m) can communicate with each other through a network (3300). The network (3300) can be implemented using Fibre Channel (FC) or Ethernet, etc. In this case, FC is a medium used for relatively high-speed data transmission, and an optical switch providing high performance / high availability can be used. Depending on the access method of the network (3300), the storage servers (3200 to 3200m) can be provided as file storage, block storage, or object storage.

[0244] In one embodiment, the network (1300) may be a storage-dedicated network such as a Storage Area Network (SAN). For example, the SAN may be an FC-SAN that utilizes an FC network and is implemented according to the FC Protocol (FCP). As another example, the SAN may be an IP-SAN that utilizes a TCP / IP network and is implemented according to the iSCSI (SCSI over TCP / IP or Internet SCSI) protocol. In another embodiment, the network (1300) may be a general network such as a TCP / IP network. For example, the network (1300) may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

[0245] Hereinafter, the description will focus on the application server (3100) and the storage server (3200). The description of the application server (3100) may also apply to other application servers (3100n), and the description of the storage server (3200) may also apply to other storage servers (3200m).

[0246] The application server (3100) can store data requested for storage by a user or client in one of the storage servers (3200 to 3200m) via the network (3300). Additionally, the application server (3100) can obtain data requested for reading by a user or client from one of the storage servers (3200 to 3200m) via the network (3300). For example, the application server (3100) can be implemented as a web server or a DBMS (Database Management System), etc.

[0247] The application server (3100) can access memory (3120n) or storage device (3150n) contained in another application server (3100n) via the network (3300), or can access memory (3220-3220m) or storage device (3250-3250m) contained in storage servers (3200-3200m) via the network (3300). Thus, the application server (3100) can perform various operations on data stored in the application servers (3100-3100n) and / or storage servers (3200-3200m). For example, the application server (3100) can execute commands to move or copy data between the application servers (3100-3100n) and / or storage servers (3200-3200m). At this time, data may be moved from the storage devices (3250-3250m) of the storage servers (3200-3200m) through the memories (3220-3220m) of the storage servers (3200-3200m), or directly to the memories (3120-3120n) of the application servers (3100-3100n). Data moving through the network (3300) may be encrypted data for security or privacy.

[0248] To illustrate with an example of a storage server (3200), the interface (3254) can provide a physical connection between the processor (3210) and the controller (3251) and a physical connection between the NIC (3240) and the controller (3251). For example, the interface (3254) can be implemented in a Direct Attached Storage (DAS) manner, which directly connects the storage device (3250) with a dedicated cable. In addition, for example, the interface (1254) can be implemented in various interface methods such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage), CF (compact flash) card interface, etc.

[0249] The storage server (3200) may further include a switch (3230) and a NIC (3240). The switch (3230) may selectively connect the processor (3210) and the storage device (3250) or selectively connect the NIC (3240) and the storage device (3250) under the control of the processor (3210).

[0250] In one embodiment, the NIC (3240) may include a network interface card, a network adapter, etc. The NIC (3240) may be connected to a network (3300) by a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC (3240) may include internal memory, a DSP, a host bus interface, etc. and may be connected to a processor (3210) and / or a switch (3230), etc., through the host bus interface. The host bus interface may be implemented as one of the examples of the interface (3254) described above. In one embodiment, the NIC (3240) may be integrated with at least one of a processor (3210), a switch (3230), and a storage device (3250).

[0251] In storage servers (3200-3200m) or application servers (3100-3100n), a processor may program or read data by sending a command to a storage device (3130-3130n, 3250-3250m) or memory (3120-3120n, 3220-3220m). The data may be data that has been error-corrected through an Error Correction Code (ECC) engine. The data may be data that has undergone Data Bus Inversion (DBI) or Data Masking (DM) processing and may include Cyclic Redundancy Code (CRC) information. The data may be data that has been encrypted for security or privacy.

[0252] The storage device (3150-3150m, 3250-3250m) can transmit a control signal and a command / address signal to the NAND flash memory device (3252-3252m) in response to a read command received from the processor. Accordingly, when reading data from the NAND flash memory device (3252-3252m), the RE (Read Enable) signal is input as a data output control signal and can serve to output data to the DQ bus. A DQS (Data Strobe) can be generated using the RE signal. The command and address signals can be latched in the page buffer according to the rising edge or falling edge of the WE (Write Enable) signal.

[0253] The controller (3251) can control the overall operation of the storage device (3250). In one embodiment, the controller (3251) may include a Static Random Access Memory (SRAM). The controller (3251) can write data to the NAND flash (3252) in response to a write command, or read data from the NAND flash (3252) in response to a read command. For example, the write command and / or read command may be provided by a processor (3210) in the storage server (3200), a processor (3210m) in another storage server (3200m), or a processor (3110, 3110n) in the application server (3100, 3100n). The DRAM (3253) may temporarily store (buffer) data to be written to the NAND flash (3252) or data read from the NAND flash (3252). Additionally, the DRAM (3253) can store metadata. Here, the metadata is data generated by the controller (3251) to manage user data or NAND flash (3252). The storage device (3250) may include a Secure Element (SE) for security or privacy.

[0254] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 A method of operation of a memory controller configured to control a memory device comprising memory blocks each storing a plurality of pages, comprising: transmitting a program instruction to the memory device based on a write request from a host; updating a valid page bitmap indicating the validity of the plurality of pages of the memory blocks based on valid page information received from the memory device; calculating a fragmentation rate indicating the degree of fragmentation between at least one valid page and at least one invalid page of the memory blocks based on the valid page bitmap; determining source blocks among the memory blocks in order of the lowest fragmentation rate; and performing garbage collection on the source blocks. Claim 2 A method of operation of a memory controller according to claim 1, wherein the step of calculating the fragmentation rate includes the step of grouping pages that are adjacent to each other and have the same validity state. Claim 3 A method of operation of a memory controller according to paragraph 2, wherein the fragmentation rate is calculated based on the number of valid page groups among the grouped pages of the valid page bitmap. Claim 4 A method of operation of a memory controller according to claim 1, wherein the valid page bitmap is characterized in that among the plurality of pages, the valid page is represented as bit 1 and the invalid page is represented as bit 0, or vice versa. Claim 5 A method of operation of a memory controller according to claim 1, wherein the step of determining the source blocks includes the step of selecting the specific memory block as the first source block of the source blocks when the specific memory block among the set of memory blocks is the only memory block having a minimum fragmentation rate. Claim 6 A method of operation of a memory controller according to claim 1, wherein the step of determining the source blocks comprises: a step of checking whether a memory block having a minimum fragmentation rate is unique among the set of memory blocks; and, if the memory block having the minimum fragmentation rate is not unique, a step of selecting a memory block with a small fragmentation degree calculated based on the bit continuity of one memory block of the effective page bitmap as the first source block of the source blocks. Claim 7 A method of operation of a memory controller according to claim 6, wherein the fragmentation diagram corresponds to the number of valid page groups and invalid page groups that are adjacent to each other and have the same validity state. Claim 8 A method of operation of a memory controller according to claim 1, wherein the step of updating the valid page bitmap comprises: receiving valid page information, which is whether a page corresponding to a memory space in which data is written is valid; and updating the valid page information in the valid page bitmap. Claim 9 A method of operation of a storage device comprising a memory device including memory blocks storing multiple pages and a memory controller configured to control the memory device, wherein the operations performed by the memory controller include: receiving a write request and data from a host; transmitting a program command to the memory device; and writing the data to a memory space through the use of the memory device and generating valid page information which is the validity of a page corresponding to the written memory space, and the operations additionally performed by the memory controller include: updating a valid page bitmap indicating the validity of the multiple pages based on the valid page information received from the memory device; calculating a fragmentation rate indicating the degree of fragmentation between at least one valid page and at least one invalid page of a memory block among the memory blocks based on the valid page bitmap; and performing garbage collection based on the fragmentation rate. Claim 10 A method of operation of a storage device according to claim 9, wherein the step of calculating the fragmentation rate includes the step of grouping pages that are adjacent to each other and have the same validity state. Claim 11 A method of operation of a storage device according to claim 10, wherein the fragmentation rate is calculated based on the number of valid page groups among the grouped pages of the valid page bitmap. Claim 12 A method of operation of a storage device according to claim 9, wherein the step of performing garbage collection comprises: a step of sorting the fragmentation rate in order of size; and a step of determining source blocks in order of lowest fragmentation rate. Claim 13 A method of operation of a storage device according to claim 9, wherein the step of performing garbage collection comprises: setting the memory block with the lowest fragmentation rate as the source block; replicating data stored in the source block to a destination block; and erasing the source block. Claim 14 A method of operation of a storage device according to claim 9, wherein the step of performing garbage collection comprises: a step of searching for a specific memory block having the minimum fragmentation rate; and a step of determining whether the specific memory block having the minimum fragmentation rate is the only memory block having the minimum fragmentation rate among the set of memory blocks. Claim 15 A method of operation of a storage device according to claim 14, further comprising the step of selecting the specific memory block having the minimum fragmentation rate as a source block when the specific memory block is the only memory block having the minimum fragmentation rate among the set of memory blocks. Claim 16 A method of operation of a storage device according to claim 14, further comprising the step of selecting a memory block with a small fragmentation calculated based on bit continuity for one memory block of the effective page bitmap as a source block when the memory block with the minimum fragmentation rate is not unique. Claim 17 A method of operation of a storage device according to claim 16, wherein the above fragmentation diagram corresponds to the number of valid page groups and invalid page groups that are adjacent to each other and have the same validity status. Claim 18 A method of operation of a storage device according to claim 17, characterized in that the valid page group is a set of adjacent pages in which the validity of the pages is represented by bit 1, and the invalid page group is a set of adjacent pages in which the validity of the pages is represented by bit 0. Claim 19 A storage device comprising: a memory device configured to include a plurality of memory blocks, each containing a plurality of pages, and to provide valid page information of the plurality of memory blocks; and a memory controller configured to calculate a fragmentation rate, which represents the degree of fragmentation between at least one valid page and at least one invalid page among the memory blocks of the plurality of memory blocks based on the valid page information, and to rearrange and erase data within the plurality of memory blocks based on the fragmentation rate within a garbage collection procedure. Claim 20 A storage device according to claim 19, wherein the memory controller performs garbage collection based on the number of valid page groups and invalid page groups among adjacent pages with the same validity state when the fragmentation rate among the set of the plurality of memories is the same.

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