Display device

Abstract

A display device is provided. The display device comprises a plurality of subpixels including a first electrode and a second electrode spaced apart from each other, and light-emitting elements disposed on the first electrode and the second electrode and electrically connected to the first electrode and the second electrode, a bank layer surrounding an area where the light-emitting elements of the subpixels are disposed, a thermal control layer disposed to cover the light-emitting elements and disposed in an area surrounded by the bank layer, an upper bank layer disposed on the bank layer, and a color control layer disposed on the thermal control layer and disposed in an area surrounded by the upper bank layer, wherein the thermal control layer comprises a resin layer, a core portion including a phase transition material, and a first shell surrounding the core portion, and includes phase transition particles dispersed in the resin layer.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] The importance of display devices is increasing along with the development of multimedia. In response to this, various types of display devices, such as Organic Light Emitting Displays (OLEDs) and Liquid Crystal Displays (LCDs), are being used.

[0003] There are self-luminous display devices that include a light-emitting element as a device for displaying images. Self-luminous display devices include organic light-emitting display devices that use organic materials as light-emitting materials as light-emitting elements, or inorganic light-emitting display devices that use inorganic materials as light-emitting materials. Prior art literature

[65535] Korean Patent Publication No. 10-2260453 The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device capable of effectively controlling heat generated from a light-emitting element.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem comprises a plurality of subpixels including a first electrode and a second electrode spaced apart from each other, and light-emitting elements disposed on the first electrode and the second electrode and electrically connected to the first electrode and the second electrode, a bank layer surrounding an area where the light-emitting elements of the subpixels are disposed, a thermal control layer disposed to cover the light-emitting elements and disposed in an area surrounded by the bank layer, an upper bank layer disposed on the bank layer, and a color control layer disposed on the thermal control layer and disposed in an area surrounded by the upper bank layer, wherein the thermal control layer comprises a core portion including a resin layer and a phase transition material and a first shell surrounding the core portion, and includes phase transition particles dispersed in the resin layer.

[0007] The core portion comprises at least one of dodecane, docosane, and aluminum-silicon alloy, and the first shell may comprise at least one of polystyrene, polymethyl methacrylate, aluminum oxide, and polymethyl methacrylate-silica.

[0008] The above-mentioned phase transition particle further comprises a second shell containing a thermally conductive material surrounding the core portion, and the first shell may surround the second shell.

[0009] The second shell may include at least one of graphite, carbon black, and a conductive polymer.

[0010] The diameter of the above phase transition particles may be 1 μm or less.

[0011] The resin layer of the heat control layer may include any one of an epoxy resin, an acrylic resin, a cardo resin, and an imide resin.

[0012] The above heat control layer may further include a scatterer.

[0013] The thickness of the color control layer may be greater than the thickness of the heat control layer.

[0014] The thickness of the color control layer may range from 8㎛ to 10㎛, and the thickness of the heat control layer may have a value of approximately 2㎛.

[0015] The apparatus includes a first insulating layer disposed on the first electrode and the second electrode, a second insulating layer disposed on the light-emitting elements and the bank layer, and a third insulating layer disposed on the second insulating layer and the bank layer, wherein the bank layer may be disposed on the first insulating layer.

[0016] The height of the upper surface of the heat control layer may be the same as or lower than the height of the upper surface of the third insulating layer disposed on the bank layer.

[0017] The height of the upper surface of the heat control layer may be higher than the height of the upper surface of the third insulating layer disposed on the bank layer.

[0018] A portion of the side of the above heat control layer may come into contact with the upper bank layer.

[0019] A portion of the heat control layer is disposed on the bank layer, and the color control layer and the upper bank layer may be disposed on the heat control layer.

[0020] The color control layer comprises a first wavelength conversion layer disposed in a first subpixel and including a first wavelength conversion particle, a second wavelength conversion layer disposed in a second subpixel and including a second wavelength conversion particle, and a light-transmitting layer disposed in a third subpixel and including a scatterer, and the heat control layer may be disposed between the first wavelength conversion layer, the second wavelength conversion layer, the light-transmitting layer, and the light-emitting element.

[0021] It may include a first connecting electrode disposed on the first electrode and in contact with the light-emitting element, and a second connecting electrode disposed on the second electrode and in contact with the light-emitting element.

[0022] A display device according to one embodiment for solving the above problem comprises a plurality of subpixels including a first electrode and a second electrode spaced apart from each other, and light-emitting elements disposed on the first electrode and the second electrode and electrically connected to the first electrode and the second electrode, a bank layer surrounding an area where the light-emitting elements of the subpixels are disposed, an upper bank layer disposed on the bank layer, and a color control layer disposed on the light-emitting element and disposed in an area surrounded by the upper bank layer, wherein the color control layer comprises a first wavelength conversion layer disposed on the first subpixel and comprising a first wavelength conversion particle, a second wavelength conversion layer disposed on the second subpixel and comprising a second wavelength conversion particle, and a light-transmitting layer disposed on the third subpixel and comprising a scatterer, wherein the first wavelength conversion layer, the second wavelength conversion layer, and the light-transmitting layer comprise a phase transition particle comprising a core portion comprising a phase transition material and a first shell surrounding the core portion.

[0023] The core portion comprises at least one of dodecane, docosane, and aluminum-silicon alloy, and the first shell may comprise at least one of polystyrene, polymethyl methacrylate, aluminum oxide, and polymethyl methacrylate-silica.

[0024] The above-mentioned phase transition particle further comprises a second shell containing a thermally conductive material surrounding the core portion, and the first shell may surround the second shell.

[0025] The diameter of the above phase transition particles may be 1 μm or less.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0027] A display device according to one embodiment may include a thermal control layer disposed between light-emitting elements and a color control layer. The thermal control layer may include a phase transition material to effectively control heat generated from the light-emitting elements.

[0028] Accordingly, the display device can reduce thermal deformation of the color control layer caused by heat generated from the light-emitting element, and the product quality and lifespan of the display device can be improved.

[0029] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0030] FIG. 1 is a schematic plan view of a display device according to one embodiment. FIG. 2 is a plan view showing the arrangement of a plurality of wires included in a display device according to one embodiment. FIGS. 3 and FIGS. 4 are equivalent circuit diagrams of one subpixel of a display device according to one embodiment. FIG. 5 is a plan view of one pixel of a display device according to one embodiment. Figure 6 is a cross-sectional view taken along the N1-N1' line of Figure 5. Figure 7 is a cross-sectional view taken along the line N2-N2' of Figure 5. Figure 8 is a cross-sectional view taken along the line N3-N3' of Figure 5. FIG. 9 is a cross-sectional view showing color control layers and heat control layers disposed in a pixel of a display device according to one embodiment. FIG. 10 is a cross-sectional view showing the first wavelength conversion layer and the thermal control layer of the first subpixel of FIG. 9. FIG. 11 is a schematic diagram showing phase transition particles included in the thermal control layer of a display device according to one embodiment. FIG. 12 is a schematic diagram showing phase transition particles included in the thermal control layer of a display device according to another embodiment. FIG. 13 is a schematic diagram of a light-emitting element according to one embodiment. FIG. 14 is a cross-sectional view showing a wavelength conversion layer and a thermal control layer of a subpixel of a display device according to another embodiment. FIG. 15 is a cross-sectional view showing color control layers and heat control layers placed in one pixel according to another embodiment. FIG. 16 is a cross-sectional view showing color control layers and heat control layers placed in one pixel according to another embodiment. FIG. 17 is a cross-sectional view showing a wavelength conversion layer and a thermal control layer of a subpixel of a display device according to another embodiment. Specific details for implementing the invention

[0031] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0032] Elements or layers referred to as "on" another element or layer include cases where another layer or element is interposed directly above or in the middle of another element. Likewise, "below," "left," and "right" refer to cases where they are interposed immediately adjacent to another element or where another layer or material is interposed in the middle. Throughout the specification, the same reference numerals refer to the same components.

[0033] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0034] Hereinafter, embodiments will be described with reference to the attached drawings.

[0035] FIG. 1 is a schematic plan view of a display device according to one embodiment.

[0036] Referring to FIG. 1, the display device (10) displays a video or a still image. The display device (10) may refer to any electronic device that provides a display screen. For example, a television, laptop, monitor, billboard, Internet of Things, mobile phone, smartphone, tablet PC (Personal Computer), electronic watch, smart watch, watch phone, head-mounted display, mobile communication terminal, electronic notebook, electronic book, PMP (Portable Multimedia Player), navigation, game console, digital camera, camcorder, etc. that provide a display screen may be included in the display device (10).

[0037] The display device (10) includes a display panel that provides a display screen. Examples of display panels include an inorganic light-emitting diode display panel, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a plasma display panel, a field emission display panel, etc. In the following examples, an inorganic light-emitting diode display panel is used as an example of a display panel, but it is not limited thereto, and if the same technical concept is applicable, it can be applied to other display panels.

[0038] The shape of the display device (10) can be varied in many ways. For example, the display device (10) may have a shape such as a horizontally elongated rectangle, a vertically elongated rectangle, a square, a rectangle with rounded corners (vertices), other polygons, or a circle. The shape of the display area (DPA) of the display device (10) may also be similar to the overall shape of the display device (10). In FIG. 1, a display device (10) in the shape of a rectangle with a long length in the second direction (DR2) is illustrated.

[0039] The display device (10) may include a display area (DPA) and a non-display area (NDA). The display area (DPA) is an area where the screen can be displayed, and the non-display area (NDA) is an area where the screen is not displayed. The display area (DPA) may also be referred to as an active area, and the non-display area (NDA) as an inactive area. The display area (DPA) may generally occupy the center of the display device (10).

[0040] The display area (DPA) may include a plurality of pixels (PX). The plurality of pixels (PX) may be arranged in a matrix direction. The shape of each pixel (PX) may be a planar rectangle or a square, but is not limited thereto, and may be a rhombus shape with each side tilted toward one direction. Each pixel (PX) may be arranged in a stripe type or an island type. Additionally, each of the pixels (PX) may include one or more light-emitting elements that emit light of a specific wavelength range to display a specific color.

[0041] A non-display area (NDA) may be placed around a display area (DPA). The non-display area (NDA) may surround the display area (DPA) in whole or in part. The display area (DPA) is rectangular in shape, and the non-display area (NDA) may be placed adjacent to the four sides of the display area (DPA). The non-display area (NDA) may form the bezel of the display device (10). In each non-display area (NDA), wiring or circuit drivers included in the display device (10) may be placed, or external devices may be mounted.

[0042] FIG. 2 is a plan view showing the arrangement of a plurality of wires included in a display device according to one embodiment.

[0043] Referring to FIG. 2, the display device (10) may include a plurality of wires. The display device (10) may include a plurality of scan lines (SL; SL1, SL2, SL3), a plurality of data lines (DTL; DTL1, DTL2, DTL3), an initial voltage wire (VIL), and a plurality of voltage wires (VL; VL1, VL2, VL3, VL4). Additionally, although not shown in the drawing, the display device (10) may have additional wires arranged therein. The plurality of wires may include wires formed of a first conductive layer and extended in a first direction (DR1), and wires formed of a third conductive layer and extended in a second direction (DR2). However, the extension direction of each wire is not limited thereto.

[0044] The first scan line (SL1) and the second scan line (SL2) may be arranged to extend in a first direction (DR1). The first scan line (SL1) and the second scan line (SL2) may be arranged adjacent to each other and spaced apart from other first scan lines (SL1) and second scan lines (SL2) in a second direction (DR2). The first scan line (SL1) and the second scan line (SL2) may be connected to a scan wiring pad (WPD_SC) connected to a scan drive unit (not shown). The first scan line (SL1) and the second scan line (SL2) may be arranged to extend from a pad area (PDA) located in a non-display area (NDA) to a display area (DPA).

[0045] A third scan line (SL3) may be extended and arranged in a second direction (DR2) and spaced apart from another third scan line (SL3) in a first direction (DR1). A single third scan line (SL3) may be connected to one or more first scan lines (SL1) or one or more second scan lines (SL2). Multiple scan lines (SL) may have a mesh structure across the entire front of the display area (DPA), but are not limited thereto.

[0046] Data lines (DTL) may be arranged to extend in a first direction (DR1). The data lines (DTL) include a first data line (DTL1), a second data line (DTL2), and a third data line (DTL3), and the first to third data lines (DTL1, DTL2, DTL3) form a pair and are arranged adjacent to each other. Each data line (DTL1, DTL2, DTL3) may be arranged to extend from a pad area (PDA) located in a non-display area (NDA) to a display area (DPA). However, this is not limited thereto, and multiple data lines (DTL) may be arranged spaced apart at equal intervals between the first voltage line (VL1) and the second voltage line (VL2) described later.

[0047] The initial voltage wiring (VIL) may be extended and arranged in a first direction (DR1). The initial voltage wiring (VIL) may be arranged between the data lines (DTL) and the first voltage wiring (VL1). The initial voltage wiring (VIL) may be extended and arranged from the pad area (PDA) located in the non-display area (NDA) to the display area (DPA).

[0048] The first voltage wiring (VL1) and the second voltage wiring (VL2) are arranged to extend in the first direction (DR1), and the third voltage wiring (VL3) and the fourth voltage wiring (VL4) are arranged to extend in the second direction (DR2). The first voltage wiring (VL1) and the second voltage wiring (VL2) may be arranged alternately in the second direction (DR2), and the third voltage wiring (VL3) and the fourth voltage wiring (VL4) may be arranged alternately in the first direction (DR1). The first voltage line (VL1) and the second voltage line (VL2) are arranged to extend in the first direction (DR1) and cross the display area (DPA), and the third voltage line (VL3) and the fourth voltage line (VL4) may each have parts of their lines placed in the display area (DPA) and other parts placed in the non-display area (NDA) located on both sides of the first direction (DR1) of the display area (DPA). Multiple voltage lines (VL) may have a mesh structure across the entire front of the display area (DPA). However, they are not limited thereto.

[0049] The first scan line (SL1), the second scan line (SL2), the data line (DTL), the initial voltage line (VIL), the first voltage line (VL1), and the second voltage line (VL2) may be electrically connected to at least one wiring pad (WPD). Each wiring pad (WPD) may be placed in a non-display area (NDA). In one embodiment, each wiring pad (WPD) may be placed in a pad area (PDA) located on the lower side, which is the other side of the first direction (DR1) of the display area (DPA). The first scan line (SL1) and the second scan line (SL2) are connected to a scan wiring pad (WPD_SC) placed in the pad area (PDA), and a plurality of data lines (DTL) are each connected to a different data wiring pad (WPD_DT). The initial voltage wiring (VIL) is connected to the initial wiring pad (WPD_Vint), and the first voltage wiring (VL1) is connected to the first voltage wiring pad (WPD_VL1), and the second voltage wiring (VL2) is connected to the second voltage wiring pad (WPD_VL2). An external device may be mounted on the wiring pad (WPD). The external device may be mounted on the wiring pad (WPD) through an anisotropic conductive film, ultrasonic bonding, etc. In the drawing, each wiring pad (WPD) is exemplified as being placed in a pad area (PDA) located below the display area (DPA), but is not limited thereto. Some of the plurality of wiring pads (WPD) may be placed above the display area (DPA) or in either the left or right side area.

[0050] Each pixel (PX) or subpixel (SPXn, where n is an integer from 1 to 3) of the display device (10) includes a pixel driving circuit. The wiring described above may pass through each pixel (PX) or around it and apply a driving signal to each pixel driving circuit. The pixel driving circuit may include transistors and capacitors. The number of transistors and capacitors in each pixel driving circuit may vary. According to one embodiment, each subpixel (SPXn) of the display device (10) may have a pixel driving circuit with a 3T1C structure that includes three transistors and one capacitor. Hereinafter, the pixel driving circuit is described using a 3T1C structure as an example, but is not limited thereto, and various other modified structures such as a 2T1C structure, a 7T1C structure, and a 6T1C structure may be applied.

[0051] FIGS. 3 and FIGS. 4 are equivalent circuit diagrams of one subpixel of a display device according to one embodiment.

[0052] Referring to FIG. 3, each subpixel (SPXn) of a display device (10) according to one embodiment includes, in addition to a light-emitting diode (EL), three transistors (T1, T2, T3) and one storage capacitor (Cst).

[0053] A light-emitting diode (EL) emits light according to the current supplied through a first transistor (T1). The light-emitting diode (EL) includes a first electrode, a second electrode, and at least one light-emitting element disposed between them. The light-emitting element can emit light of a specific wavelength range by means of an electrical signal transmitted from the first electrode and the second electrode.

[0054] One end of the light-emitting diode (EL) is connected to the source electrode of the first transistor (T1), and the other end can be connected to a second voltage wiring (VL2) to which a low potential voltage (hereinafter referred to as the second power supply voltage) lower than the high potential voltage (hereinafter referred to as the first power supply voltage) of the first voltage wiring (VL1) is supplied.

[0055] The first transistor (T1) adjusts the current flowing from the first voltage wiring (VL1), to which the first power supply voltage is supplied, to the light-emitting diode (EL) according to the voltage difference between the gate electrode and the source electrode. For example, the first transistor (T1) may be a driving transistor for driving the light-emitting diode (EL). The gate electrode of the first transistor (T1) may be connected to the source electrode of the second transistor (T2), the source electrode may be connected to the first electrode of the light-emitting diode (EL), and the drain electrode may be connected to the first voltage wiring (VL1), to which the first power supply voltage is applied.

[0056] The second transistor (T2) is turned on by a scan signal of the scan line (SL) to connect the data line (DTL) to the gate electrode of the first transistor (T1). The gate electrode of the second transistor (T2) is connected to the scan line (SL), the source electrode is connected to the gate electrode of the first transistor (T1), and the drain electrode can be connected to the data line (DTL).

[0057] The third transistor (T3) is turned on by a scan signal of the scan line (SL) to connect the initial voltage wire (VIL) to one end of the light-emitting diode (EL). The gate electrode of the third transistor (T3) is connected to the scan line (SL), the drain electrode is connected to the initial voltage wire (VIL), and the source electrode can be connected to one end of the light-emitting diode (EL) or the source electrode of the first transistor (T1).

[0058] In one embodiment, the source electrode and drain electrode of each transistor (T1, T2, T3) are not limited to those described above, and may be the opposite. Each of the transistors (T1, T2, T3) may be formed as a thin film transistor. Although FIG. 3 describes each transistor (T1, T2, T3) as being formed as an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), it is not limited thereto. That is, each transistor (T1, T2, T3) may be formed as a P-type MOSFET, or some may be formed as an N-type MOSFET and others as a P-type MOSFET.

[0059] A storage capacitor (Cst) is formed between the gate electrode and the source electrode of the first transistor (T1). The storage capacitor (Cst) stores the difference voltage between the gate voltage and the source voltage of the first transistor (T1).

[0060] In the embodiment of FIG. 3, the gate electrode of the second transistor (T2) and the gate electrode of the third transistor (T3) may be connected to the same scan line (SL3). The second transistor (T2) and the third transistor (T3) may be turned on by a scan signal applied on the same scan line. However, they are not limited thereto.

[0061] Referring to FIG. 4, the gate electrodes of the second transistor (T2) and the third transistor (T3) may be connected to different scan lines (SL1, SL2). For example, the gate electrode of the second transistor (T2) may be electrically connected to the first scan line (SL1), and the gate electrode of the third transistor (T3) may be electrically connected to the second scan line (SL2). The second transistor (T2) and the third transistor (T3) may be turned on simultaneously by a scan signal applied from different scan lines.

[0062] Hereinafter, the structure of a pixel (PX) of a display device (10) according to one embodiment will be described in detail with further reference to other drawings.

[0063] FIG. 5 is a plan view of one pixel of a display device according to one embodiment.

[0064] FIG. 5 illustrates the planar arrangement of electrodes (RME: RME1, RME2), partitions (BP1, BP2), a bank layer (BNL), a plurality of light-emitting elements (ED: ED1, ED2) and connecting electrodes (CNE: CNE1, CNE2, CNE3) placed in one pixel (PX) of a display device (10).

[0065] Referring to FIG. 5, each of the pixels (PX) of the display device (10) may include a plurality of subpixels (SPXn). For example, one pixel (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). The first subpixel (SPX1) may emit light of a first color, the second subpixel (SPX2) may emit light of a second color, and the third subpixel (SPX3) may emit light of a third color. As an example, the first color may be blue, the second color may be green, and the third color may be red. However, not limited thereto, each subpixel (SPXn) may emit light of the same color. In one embodiment, each subpixel (SPXn) may emit blue light. In the drawing, one pixel (PX) is illustrated as containing three subpixels (SPXn), but is not limited thereto, and the pixel (PX) may contain a larger number of subpixels (SPXn).

[0066] Each subpixel (SPXn) of the display device (10) may include a light-emitting region (EMA) and a non-light-emitting region. The light-emitting region (EMA) may be an area where a light-emitting element (ED) is placed and light of a specific wavelength range is emitted. The non-light-emitting region may be an area where a light-emitting element (ED) is not placed and light emitted from the light-emitting element (ED) does not reach and is not emitted.

[0067] The light-emitting region (EMA) may include an area where a light-emitting element (ED) is placed and an area adjacent to the light-emitting element (ED) through which light emitted from the light-emitting element (ED) is emitted. For example, the light-emitting region (EMA) may also include an area where light emitted from the light-emitting element (ED) is reflected or refracted by another component and emitted. A plurality of light-emitting elements (ED) are placed in each subpixel (SPXn), and a light-emitting region may be formed by including the area where they are placed and an area adjacent thereto.

[0068] In the drawings, the light-emitting regions (EMAs) of each subpixel (SPXn) are illustrated as having uniform areas, but are not limited thereto. In some embodiments, each light-emitting region (EMA) of each subpixel (SPXn) may have different areas depending on the color or wavelength of light emitted from the light-emitting element (ED) placed in the corresponding subpixel.

[0069] Each sub-pixel (SPXn) may further include sub-regions (SA1, SA2) disposed in a non-emissive region. The sub-regions (SA1, SA2) may include a first sub-region (SA1) disposed on the upper side, which is one side of the first direction (DR1) of the emitting region (EMA), and a second sub-region (SA2) disposed on the lower side, which is the other side of the first direction (DR1) of the emitting region (EMA). The emitting region (EMA) and the sub-regions (SA1, SA2) are alternately arranged in the first direction (DR1) according to the arrangement of pixels (PX) and sub-pixels (SPXn), and the first sub-region (SA1) or the second sub-region (SA2) may be disposed between different emitting regions (EMA) spaced apart in the first direction (DR1). For example, a plurality of emitting regions (EMA) may be repeatedly arranged in the first direction (DR1) with the first sub-region (SA1) or the second sub-region (SA2) in between. Each of the plurality of light-emitting regions (EMA), first sub-regions (SA1), and second sub-regions (SA2) may be arranged repeatedly in the second direction (DR2). The first sub-region (SA1) and the second sub-region (SA2) may be regions distinguished according to the arrangement of the wiring connection electrode (EP) and electrode (RME) described later. However, not limited thereto, the light-emitting regions (EMA) and sub-regions (SA1, SA2) in the plurality of pixels (PX) may have an arrangement different from that of FIG. 5.

[0070] The first sub-region (SA1) and the second sub-region (SA2) may be areas shared by sub-pixels (SPXn) adjacent in the first direction (DR1). For example, the second sub-region (SA2) illustrated in FIG. 5 may be shared by a sub-pixel (SPXn) illustrated in the drawing and a sub-pixel (SPXn) adjacent in the first direction (DR1) that is not illustrated in the drawing. The sub-pixels (SPXn) illustrated in the drawing are sub-pixels located above the light-emitting region (EMA) of the first sub-region (SA1), and the sub-pixels (SPXn) adjacent to them in the first direction (DR1) may be sub-pixels located above the light-emitting region (EMA) of the second sub-region (SA2).

[0071] In the sub-regions (SA1, SA2), light-emitting elements (ED) are not placed so that light is not emitted, but some of the electrodes (RME) placed in each sub-pixel (SPXn) may be placed therein. The electrodes (RME) placed in different sub-pixels (SPXn) may be separated from each other in the separation sections (ROP1, ROP2) of the sub-regions (SA1, SA2).

[0072] The display device (10) may include a plurality of electrodes (RME1, RME2), partitions (BP1, BP2), a bank layer (BNL), light-emitting elements (ED), and connecting electrodes (CNE1, CNE2, CNE3).

[0073] Multiple partitions (BP1, BP2) may be placed in the light-emitting region (EMA) of each subpixel (SPXn). The partitions (BP1, BP2) may generally extend in a first direction (DR1) and be spaced apart from each other in a second direction (DR2).

[0074] For example, the partitions (BP1, BP2) may include a first partition (BP1) and a second partition (BP2) spaced apart from each other in a second direction (DR2) within the light-emitting region (EMA) of each subpixel (SPXn). The first partition (BP1) may be positioned in the center of the light-emitting region (EMA), and the second partitions (BP2) may be positioned spaced apart from the first partition (BP1). The first partition (BP1) and the second partition (BP2) may be positioned alternately along the second direction (DR2) and may be arranged in an island pattern in the display region (DPA). A plurality of light-emitting elements (ED) may be positioned between the first partition (BP1) and the second partition (BP2).

[0075] The second barrier (BP2) may have a wider width in the second direction (DR2) than the first barrier (BP1). While the first barrier (BP1) is placed in the light-emitting region (EMA) of each subpixel (SPXn), the second barrier (BP2) may be placed across the light-emitting region (EMA) of two subpixels (SPXn) adjacent to each other in the second direction (DR2). The second barrier (BP2) is placed across the boundary of subpixels (SPXn) adjacent to each other in the second direction (DR2) and may overlap with the bank layer (BNL) described later. However, it is not limited thereto, and the first barrier (BP1) and the second barrier (BP2) may have the same width.

[0076] The partitions (BP1, BP2) have the same length in the first direction (DR1) and may be larger than the length in the first direction (DR1) of the light-emitting region (EMA) surrounded by the bank layer (BNL). The partitions (BP1, BP2) may overlap with the portion of the bank layer (BNL) that extends in the second direction (DR2). However, they are not limited thereto, and the partitions (BP1, BP2) may be integrated with the bank layer (BNL) or separated from the portion of the bank layer (BNL) that extends in the second direction (DR2). In this case, the length in the first direction (DR1) of the partitions (BP1, BP2) may be the same as or smaller than the length in the first direction (DR1) of the light-emitting region (EMA) surrounded by the bank layer (BNL).

[0077] In the drawing, one first partition (BP1) and two second partitions (BP2) are partially arranged for each subpixel (SPXn), but are not limited thereto. The number and shape of the partitions (BP1, BP2) may vary depending on the number or arrangement structure of the electrodes (RME).

[0078] Electrodes (RME1, RME2) are arranged in a shape extending in one direction for each subpixel (SPXn). Each of the electrodes (RME1, RME2) may extend in a first direction (DR1) and be placed in the light-emitting region (EMA) and sub-region (SA1, SA2) of the subpixel (SPXn), and may be spaced apart from each other in a second direction (DR2). The electrodes (RME1, RME2) may be electrically connected to the light-emitting element (ED) described below. However, they are not limited thereto, and the electrodes (RME) may not be electrically connected to the light-emitting element (ED).

[0079] The display device (10) may include a first electrode (RME1) positioned at the center of each subpixel (SPXn) and a second electrode (RME2) positioned across different subpixels (SPXn). The first electrode (RME1) and the second electrode (RME2) generally have a shape extending in a first direction (DR1), but the shape of the portion positioned in the light-emitting region (EMA) may differ from each other. The first electrode (RME1) may be positioned adjacent to the center of the subpixel (SPXn) and may be positioned across the light-emitting region (EMA) and sub-regions (SA1, SA2). The second electrode (RME2) may be spaced apart from the first electrode (RME1) in the light-emitting region (EMA) in a second direction (DR2) and may be positioned across a plurality of subpixels (SPXn). The first electrode (RME1) and the second electrode (RME2) generally have a shape that extends in the first direction (DR1), but the length extended in the first direction (DR1) and the shape of the portion placed in the light-emitting region (EMA) may be different from each other.

[0080] The first electrode (RME1) is positioned at the center of the subpixel (SPXn), and the portion positioned in the light-emitting region (EMA) may be positioned on the first partition (BP1). The first electrode (RME1) may extend from the first sub-region (SA1) in the first direction (DR1) and extend to the second sub-region (SA2). The first electrode (RME1) may have a shape in which the width measured in the second direction (DR2) varies depending on the position, and at least the portion overlapping with the first partition (BP1) in the light-emitting region (EMA) may have a width greater than that of the first partition (BP1).

[0081] The second electrode (RME2) may include a portion extending in the first direction (DR1) and portions branched from the light-emitting region (EMA). In one embodiment, the second electrode (RME2) may include an electrode stem portion (RM_S) extending in the first direction (DR1) and electrode branch portions (RM_B1, RM_B2) branched from the electrode stem portion (RM_S), bent into the second direction (DR2), and then extended again in the first direction (DR1). The electrode stem portion (RM_S) may be positioned to overlap with the portion extending in the first direction (DR1) of the bank layer (BNL) and may be positioned on one side of the second direction (DR2) of the sub-region (SA). The electrode branch portions (RM_B1, RM_B2) branch off from the electrode stem portion (RM_S) located in the part extending in the first direction (DR1) of the bank layer (BNL) and can be bent toward both sides in the second direction (DR2). The electrode branch portions (RM_B1, RM_B2) are arranged across the light-emitting region (EMA) in the first direction (DR1) and can be bent again to be connected to the electrode stem portion (RM_S). For example, the electrode branch portions (RM_B1, RM_B2) of the second electrode (RME2) can be branched from the upper side and then connected to each other again from the lower side, based on the light-emitting region (EMA) of a certain subpixel (SPXn).

[0082] The second electrode (RME2) may include a first electrode branch (RM_B1) positioned to the left of the first electrode (RME1) and a second electrode branch (RM_B2) positioned to the right of the first electrode (RME1). The electrode branch (RM_B1, RM_B2) included in one second electrode (RME2) are each positioned in the light-emitting region (EMA) of subpixels (SPXn) adjacent to the second direction (DR2), and the electrode branch (RM_B1, RM_B2) of different second electrodes (RME2) may be positioned in one subpixel (SPXn). The first electrode branch (RM_B1) of the second electrode (RME2) may be positioned to the left of the first electrode (RME1), and the second electrode branch (RM_B2) of another second electrode (RME2) may be positioned to the right of the first electrode (RME1).

[0083] Each electrode branch (RM_B1, RM_B2) of the second electrode (RME2) may overlap with one side of the second partition (BP2). The first electrode branch (RM_B1) may partially overlap with the second partition (BP2) positioned to the left of the first partition (BP1), and the second electrode branch (RM_B2) may partially overlap with the second partition (BP2) positioned to the right of the first partition (BP1). The first electrode (RME1) may be spaced apart from the different electrode branches (RM_B1, RM_B2) of the second electrode (RME2) on both sides, and the gap between the first electrode (RME1) and each electrode branch (RM_B1, RM_B2) may be smaller than the gap between the different partitions (BP1, BP2).

[0084] The width measured in the second direction (DR2) of the first electrode (RME1) may be larger than the width of the electrode stem portion (RM_S) and the electrode branch portions (RM_B1, RM_B2) of the second electrode (RME2). The first electrode (RME1) has a width greater than that of the first partition (BP1) and overlaps with both sides, whereas the second electrode (RME2) is formed with a relatively smaller width so that the electrode branch portions (RM_B1, RM_B2) overlap with only one side of the second partition (BP2).

[0085] Among the first electrode (RME1) and the second electrode (RME2), the first electrode (RME1) is arranged to extend to the first separation portion (ROP1) of the first sub-region (SA1) and the second separation portion (ROP2) of the second sub-region (SA2), whereas the second electrode (RME2) may not be separated from the sub-regions (SA1, SA2). A single second electrode (RME2) may have a shape that extends in a first direction (DR1) including a plurality of electrode stem portions (RM_S) and electrode branch portions (RM_B1, RM_B2) and branches near the light-emitting region (EMA) of each sub-pixel (SPXn). The first electrode (RME1) may be arranged between the separation portions (ROP1, ROP2) placed in different sub-regions (SA1, SA2) of each sub-pixel (SPXn) and may be arranged across the light-emitting region (EMA).

[0086] The display device (10) may include a wiring connection electrode (EP) disposed in the first sub-region (SA1) among the plurality of sub-regions (SA1, SA2) of each sub-pixel (SPXn) and disposed between the first electrodes (RME1) of different sub-pixels (SPXn). The wiring connection electrode (EP) may not be disposed in the second sub-region (SA) of the sub-pixel (SPXn), and the first electrodes (RME1) of other sub-pixels (SPXn) adjacent in the first direction (DR1) may be spaced apart from each other. Among the plurality of sub-pixels (SPXn), the pixel (PX) shown in FIG. 5 may have the first sub-region (SA1) where the wiring connection electrode (EP) is disposed placed above the light-emitting region (EMA) and the second sub-region (SA2) placed below the light-emitting region (EMA). On the other hand, for a pixel (PX) in FIG. 5 and a pixel (PX) adjacent to the first direction (DR1), a first sub-region (SA1) in which a wiring connection electrode (EP) is placed may be positioned below the light-emitting region (EMA), and a second sub-region (SA2) may be positioned above the light-emitting region (EMA).

[0087] The first electrode (RME1) may be spaced apart from the wiring connection electrode (EP) in the first sub-region (SA1) with the first separation part (ROP1) in between. Two first separation parts (ROP1) may be arranged in the first sub-region (SA1), and the wiring connection electrode (EP) may be spaced apart from the first electrode (RME1) placed in the corresponding sub-pixel (SPXn) with the lower first separation part (ROP1) in between, and spaced apart from the first electrode (RME1) placed in another sub-pixel (SPXn) with the upper first separation part (ROP1) in between. One second separation part (ROP2) may be arranged in the second sub-region (SA2), and different first electrodes (RME1) may be spaced apart in the first direction (DR1).

[0088] In the drawing, it is illustrated that one first electrode (RME1) is disposed for each subpixel (SPXn) and different second electrodes (RME2) are disposed, but is not limited thereto. For example, the display device (10) may have a larger number of electrodes (RME) disposed in one subpixel (SPXn), or the arrangement and shape of the electrodes (RME) may vary.

[0089] A bank layer (BNL) may be arranged to surround a plurality of subpixels (SPXn), a light-emitting region (EMA), and sub-regions (SA1, SA2). The bank layer (BNL) may be arranged between subpixels (SPXn) adjacent in a first direction (DR1) and a second direction (DR2), and may also be arranged between a light-emitting region (EMA) and sub-regions (SA1, SA2). The subpixels (SPXn), light-emitting region (EMA), and sub-regions (SA1, SA2) of the display device (10) may be regions separated by the arrangement of the bank layer (BNL). The spacing between the plurality of subpixels (SPXn), light-emitting regions (EMA), and sub-regions (SA1, SA2) may vary depending on the width of the bank layer (BNL).

[0090] Light-emitting elements (EDs) may be placed in a light-emitting region (EMA). Light-emitting elements (EDs) may be placed between partitions (BP1, BP2) and may be spaced apart from each other in a first direction (DR1) or a second direction (DR2). In one embodiment, a plurality of light-emitting elements (EDs) may have a shape that extends in one direction, and both ends may be placed on different electrodes (RMEs). The length of a light-emitting element (ED) may be longer than the spacing between electrodes (RMEs) spaced apart in the second direction (DR2). Generally, the light-emitting elements (EDs) may be arranged such that their extended direction is perpendicular to the first direction (DR1) in which the electrodes (RMEs) extend. However, they are not limited thereto, and the extended direction of the light-emitting element (ED) may be arranged to face the second direction (DR2) or a direction inclined obliquely thereto.

[0091] A light-emitting element (ED) may include a first light-emitting element (ED1) with both ends disposed on either a first electrode (RME1) or a second electrode (RME2), and a second light-emitting element (ED2) with both ends disposed on the first electrode (RME1) and the other second electrode (RME2). With respect to a first subpixel (SPX1), the first light-emitting element (ED1) may be disposed on the second electrode branch (RM_B2) of the first electrode (RME1) and the second electrode (RME2), and the second light-emitting element (ED2) may be disposed on the first electrode branch (RM_B1) of the first electrode (RME1) and the other second electrode (RME2). The first light-emitting elements (ED1) may be disposed to the right of the first electrode (RME1), and the second light-emitting elements (ED2) may be disposed to the left of the first electrode (RME1). The first light-emitting elements (ED1) and the second light-emitting elements (ED) are each placed on the first electrode (RME1) and the second electrode (RME2), respectively, and the second electrode (RME2) on which they are placed may be different from each other.

[0092] Connecting electrodes (CNE; CNE1, CNE2, CNE3) can be placed on electrodes (RME) and partitions (BP1, BP2). Each connecting electrode (CNE) has a shape that extends in one direction and can be spaced apart from each other. Each connecting electrode (CNE) can be in contact with a light-emitting element (ED) and electrically connected to an underlying conductive layer.

[0093] The connection electrodes (CNE) may include a first connection electrode (CNE1), a second connection electrode (CNE2), and a third connection electrode (CNE3) disposed in each subpixel (SPXn).

[0094] The first connecting electrode (CNE1) may be disposed on the first electrode (RME1) having a shape that extends in the first direction (DR1). The first connecting electrode (CNE1) is disposed to overlap the first partition (BP1) and the first electrode (RME1), and may be disposed to extend from the light-emitting region (EMA) in the first direction (DR1) to the first sub-region (SA1) located above the light-emitting region (EMA). The first connecting electrode (CNE1) may contact the first electrode (RME1) through a first contact hole (CT1) formed on the first electrode (RME1) in the first sub-region (SA1).

[0095] The second connecting electrode (CNE2) may be spaced apart from the first connecting electrode (CNE1) in the second direction (DR2) and may be disposed on the second electrode (RME2) having a shape that extends in the first direction (DR1). The second connecting electrode (CNE2) may be disposed on the second electrode branch (RM_B2) of the second electrode (RME2) which is disposed to the left of the first electrode (RME1). The second connecting electrode (CNE2) may be disposed to overlap the second partition (BP2) and the second electrode branch (RM_B2) of the second electrode (RME2), and may be disposed to extend from the light-emitting region (EMA) in the second direction (DR2) to the first sub-region (SA1) located above the light-emitting region (EMA). The second connecting electrode (CNE2) can contact the second electrode (RME2) through a second contact hole (CT2) formed on the second electrode (RME2) in the first sub-region (SA1).

[0096] The third connecting electrode (CNE3) may include extension portions (CN_E1, CN_E2) extending in a first direction (DR1), and a first connecting portion (CN_B1) connecting the extension portions (CN_E1, CN_E2). The first extension portion (CN_E1) ​​may be positioned on the second electrode (RME2) facing the first connecting electrode (CNE1) within the light-emitting region (EMA). With respect to the first subpixel (SPX1), the first extension portion (CN_E1) ​​may be positioned on the second electrode branch portion (RM_B2) of the second electrode (RME2). The second extension portion (CN_E2) may be positioned on the first electrode (RME1) facing the second connecting electrode (CNE2) within the light-emitting region (EMA). The first connection portion (CN_B1) can be extended in a second direction (DR2) on a bank layer (BNL) located below the light-emitting region (EMA) to connect the first extension portion (CN_E1) ​​and the second extension portion (CN_E2). The third connection electrode (CNE3) is located on the light-emitting region (EMA) and the bank layer (BNL) and may not be directly connected to the electrode (RME). The second electrode (RME2) located below the first extension portion (CN_E1) ​​is electrically connected to the second voltage wiring (VL2), but the second power supply voltage applied to the second electrode (RME2) may not be transmitted to the third connection electrode (CNE3).

[0097] As described below, the light-emitting elements (ED) can have their two ends in an extended direction separated from each other and can be connected in series through connecting electrodes (CNE) that contact the two ends. The display device (10) can include a larger number of light-emitting elements (ED) for each subpixel (SPXn) and can configure their series connection so that the amount of light emitted per unit area can be increased.

[0098] The display device (10) may further include insulating layers (PAS1, PAS2, PAS3) disposed between electrodes (RME1, RME2), light-emitting elements (ED), and connecting electrodes (CNE1, CNE2, CNE3). The electrodes (RME1, RME2), light-emitting elements (ED), and connecting electrodes (CNE1, CNE2, CNE3) are arranged to overlap each other, but only a portion of them may come into contact with each other by means of insulating layers (PAS1, PAS2, PAS3) disposed between them.

[0099] FIG. 6 is a cross-sectional view taken along the line N1-N1' of FIG. 5. FIG. 7 is a cross-sectional view taken along the line N2-N2' of FIG. 5. FIG. 8 is a cross-sectional view taken along the line N3-N3' of FIG. 5.

[0100] FIG. 6 illustrates a cross-section across both ends of light-emitting elements (ED; ED1, ED2) placed on different electrodes (RME: RME1, RME2). FIG. 7 and FIG. 8 illustrate cross-sections across electrode contact holes (CTD, CTS, CTA) and contact holes (CT1, CT2).

[0101] Referring to FIGS. 5 to 8, the display device (10) may include a first substrate (SUB), a semiconductor layer disposed thereon, a plurality of conductive layers, and a plurality of insulating layers. Additionally, the display device (10) may include a plurality of electrodes (RME), a light-emitting element (ED), and a connecting electrode (CNE).

[0102] The first substrate (SUB) may be an insulating substrate. The first substrate (SUB) may be made of an insulating material such as glass, quartz, or a polymer resin. Additionally, the first substrate (SUB) may be a rigid substrate, but may also be a flexible substrate capable of bending, folding, rolling, etc. The first substrate (SUB) includes a display area (DPA) and a non-display area (NDA) surrounding it, and the display area (DPA) may include a light-emitting area (EMA) and sub-areas (SA1, SA2) that are part of the non-light-emitting area.

[0103] The first conductive layer may include a lower metal layer (BML), a first voltage line (VL1), and a second voltage line (VL2). The lower metal layer (BML) is positioned to overlap with the active layer (ACT1) of the first transistor (T1). The lower metal layer (BML) may perform the function of preventing light from being incident on the first active layer (ACT1) of the first transistor, or electrically connecting to the first active layer (ACT1) to stabilize the electrical characteristics of the first transistor (T1). However, the lower metal layer (BML) may be omitted.

[0104] A high potential voltage (or a first power supply voltage) delivered to the first electrode (RME1) may be applied to the first voltage wiring (VL1), and a low potential voltage (or a second power supply voltage) delivered to the second electrode (RME2) may be applied to the second voltage wiring (VL2). The first voltage wiring (VL1) may be electrically connected to the first transistor (T1) through a conductive pattern of the second conductive layer (e.g., a third conductive pattern (CDP3)). The second voltage wiring (VL2) may be electrically connected to the second electrode (RME2) through a conductive pattern of the third conductive layer (e.g., a second conductive pattern (CDP2)).

[0105] In the drawings, the first voltage line (VL1) and the second voltage line (VL2) are illustrated as being disposed in the first conductive layer, but are not limited thereto. In some embodiments, the first voltage line (VL1) and the second voltage line (VL2) may be disposed in the third conductive layer and directly electrically connected to the first transistor (T1) and the second electrode (RME2), respectively.

[0106] A buffer layer (BL) may be disposed on a first conductive layer and a first substrate (SUB). The buffer layer (BL) is formed on the first substrate (SUB) to protect the transistors of the pixel (PX) from moisture penetrating through the first substrate (SUB), which is susceptible to moisture permeability, and can perform a surface planarization function.

[0107] The semiconductor layer is disposed on the buffer layer (BL). The semiconductor layer may include a first active layer (ACT1) of the first transistor (T1) and a second active layer (ACT2) of the second transistor (T2). The first active layer (ACT1) and the second active layer (ACT2) may be disposed to partially overlap with the first gate electrode (G1) and the second gate electrode (G2) of the second conductive layer, respectively, which will be described later.

[0108] The semiconductor layer may include polycrystalline silicon, single-crystal silicon, oxide semiconductors, etc. In an exemplary embodiment, the semiconductor layer may include polycrystalline silicon or an oxide semiconductor. The oxide semiconductor may include indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0109] In the drawing, one first transistor (T1) and one second transistor (T2) are shown arranged in a subpixel (SPXn) of the display device (10), but the display device (10) is not limited thereto and may include a larger number of transistors.

[0110] A first gate insulating layer (GI) is disposed on a semiconductor layer. The first gate insulating layer (GI) can serve as a gate insulating film for each transistor (T1, T2). In the drawings, the first gate insulating layer (GI) is illustrated as being patterned together with the gate electrodes (G1, G2) of the second conductive layer and partially disposed between the second conductive layer and the active layer (ACT1, ACT2) of the semiconductor layer, but is not limited thereto. In some embodiments, the first gate insulating layer (GI) may be disposed entirely on the buffer layer (BL) covering the semiconductor layer.

[0111] The second conductive layer is disposed on the first gate insulating layer (GI). The second conductive layer may include a first gate electrode (G1) of the first transistor (T1) and a second gate electrode (G2) of the second transistor (T2). The first gate electrode (G1) may be disposed to overlap the channel region of the first active layer (ACT1) in the third direction (DR3), which is the thickness direction, and the second gate electrode (G2) may be disposed to overlap the channel region of the second active layer (ACT2) in the third direction (DR3), which is the thickness direction. Although not shown in the drawing, the second conductive layer may further include one electrode of the storage capacitor.

[0112] The first interlayer insulating layer (IL1) is disposed on the second conductive layer. The first interlayer insulating layer (IL1) functions as an insulating film between the second conductive layer and other layers disposed thereon, and can protect the second conductive layer.

[0113] The third conductive layer is disposed on the first interlayer insulating layer (IL1). The third conductive layer may include a plurality of conductive patterns (CDP1, CDP2, CDP3) and source electrodes (S1, S2) and drain electrodes (D1, D2) of each transistor (T1, T2). Some of the conductive patterns (CDP1, CDP2, CDP3) electrically connect the conductive layers or semiconductor layers of different layers to each other and may serve as source / drain electrodes of transistors (T1, T2).

[0114] The first conductive pattern (CDP1) can contact the first active layer (ACT1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (IL1). The first conductive pattern (CDP1) can contact the lower metal layer (BML) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). The first conductive pattern (CDP1) can serve as the first source electrode (S1) of the first transistor (T1). The first conductive pattern (CDP1) can be electrically connected to the first electrode (RME1) or the first connection electrode (CNE1). The first transistor (T1) can transmit the first power supply voltage applied from the first voltage wiring (VL1) to the first electrode (RME1) or the first connection electrode (CNE1).

[0115] The second conductive pattern (CDP2) can contact the second voltage wiring (VL2) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). The second voltage wiring (VL2) can transmit the second power supply voltage to the second connecting electrode (CNE2) through the second conductive pattern (CDP2).

[0116] The third conductive pattern (CDP3) can contact the first voltage wiring (VL1) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). Additionally, the second conductive pattern (CDP2) can contact the first active layer (ACT1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (IL1). The second conductive pattern (CDP2) electrically connects the first voltage wiring (VL1) to the first transistor (T1) and can serve as the first drain electrode (D1) of the first transistor (T1).

[0117] The second source electrode (S2) and the second drain electrode (D2) can each contact the second active layer (ACT2) of the second transistor (T2) through a contact hole penetrating the first interlayer insulating layer (IL1).

[0118] The first protective layer (PV1) is disposed on the third conductive layer. The first protective layer (PV1) functions as an insulating film between the third conductive layer and other layers and can protect the third conductive layer.

[0119] The above-described buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be composed of a plurality of inorganic layers stacked alternately. For example, the buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be silicon oxide (SiO₂). x ), Silicon Nitride (SiN x ), Silicon Oxynitride (SiO₂ x N y It may be formed into a double layer in which an inorganic layer comprising at least one of ) is stacked, or a multilayer in which the same is stacked alternately. However, it is not limited thereto, and the buffer layer (BL), the first gate insulating layer (GI), the first interlayer insulating layer (IL1), and the first protective layer (PV1) may be formed into a single inorganic layer including the insulating material described above. In addition, in some embodiments, the first interlayer insulating layer (IL1) may be made of an organic insulating material such as polyimide (PI).

[0120] A via layer (VIA) is disposed on a third conductive layer in a display area (DPA). The via layer (VIA) may comprise an organic insulating material, such as polyimide (PI), to compensate for the step difference caused by the underlying conductive layers and to form a flat upper surface. However, in some embodiments, the via layer (VIA) may be omitted.

[0121] The display device (10) may include a display element layer disposed on a via layer (VIA), partitions (BP1, BP2), electrodes (RME1, RME2), a bank layer (BNL), light-emitting elements (ED1, ED2), and connecting electrodes (CNE1, CNE2, CNE3). Additionally, the display device (10) may include insulating layers (PAS1, PAS2, PAS3).

[0122] The partitions (BP1, BP2) can be disposed on the via layer (VIA). For example, the partitions (BP1, BP2) can be disposed directly on the via layer (VIA) and may have a structure in which at least a portion protrudes with respect to the upper surface of the via layer (VIA). As described above, the first partition (BP1) and the second partition (BP2) are disposed spaced apart from each other, and the first partition (BP1) may be disposed between a plurality of second partitions (BP2). The partitions (BP1, BP2) may have inclined or curved sides with a certain curvature, and light emitted from the light-emitting elements (ED1, ED2) may be reflected from the electrodes (RME1, RME2) disposed on the partitions (BP1, BP2) and emitted in the upper direction of the via layer (VIA). Unlike as illustrated in the drawing, the partitions (BP1, BP2) may have a shape in which the outer surface of the cross-sectional view is bent with a certain curvature, such as a semicircle or a semi-ellipse. The partitions (BP1, BP2) may include an organic insulating material such as polyimide (PI), but are not limited thereto.

[0123] Electrodes (RME1, RME2) may be placed on partitions (BP1, BP2) and via layers (VIA). For example, a portion of each electrode (RME1, RME2) may be placed on at least the inclined side of the partition (BP1, BP2). The first electrode (RME1) may be placed to cover the first partition (BP1), and the second electrode (RME2) may be placed such that electrode branches (RM_B1, RM_B2) cover the side of the second partition (BP2). The width of the first electrode (RME1) may be greater than that of the first partition (BP1), and the width of the electrode branches (RM_B1, RM_B2) of the second electrode (RME2) may be smaller than that of the second partition (BP2). The spacing between the electrodes (RME) spaced apart in the second direction (DR2) may be narrower than the spacing between the partitions (BP1, BP2). Each of the electrodes (RME) has at least a portion of its area directly placed on the via layer (VIA) so that they can be placed on the same plane.

[0124] A light-emitting element (ED) placed between partitions (BP1, BP2) emits light in both end directions, and the emitted light can be directed toward an electrode (RME) placed on the partitions (BP1, BP2). Each electrode (RME) may have a structure in which the portion placed on the partitions (BP1, BP2) can reflect the light emitted from the light-emitting element (ED). The electrodes (RME) are arranged to cover at least one side of the partitions (BP1, BP2) so as to reflect the light emitted from the light-emitting element (ED).

[0125] The first electrode (RME1) and the second electrode (RME2) can directly contact the third conductive layer through electrode contact holes (CTD, CTS) placed in the portion overlapping with the bank layer (BNL). For example, the first electrode contact hole (CTD) may be formed in the portion overlapping with the first electrode (RME1) and the bank layer (BNL), and the second electrode contact hole (CTS) may be formed in the portion overlapping with the second electrode (RME2) and the bank layer (BNL). The first electrode (RME1) can contact the first conductive pattern (CDP1) through the first electrode contact hole (CTD) penetrating the via layer (VIA) and the first protective layer (PV1), and can be electrically connected to the first transistor (T1). The second electrode (RME2) can contact the second conductive pattern (CDP2) through a second electrode contact hole (CTS) that penetrates the via layer (VIA) and the first protective layer (PV1), and can be electrically connected to the second voltage wiring (VL2).

[0126] A wiring connection electrode (EP) is positioned in a first sub-region (SA1) and can directly contact a third conductive layer through a third electrode contact hole (CTA). For example, the wiring connection electrode (EP) can contact a third conductive pattern (CDP3) through a third electrode contact hole (CTA) that penetrates a via layer (VIA) and a first protective layer (PV1). The wiring connection electrode (EP) can be electrically connected to a first voltage wiring (VL1) through the third conductive pattern (CDP3).

[0127] In the manufacturing process of the display device (10), the first electrode (RME1) is formed in a state connected to the wiring connection electrode (EP), and an electrical signal applied to place light-emitting elements (ED) can be applied from the first voltage wiring (VL1) to the first electrode (RME1) through the wiring connection electrode (EP). In the process of placing the light-emitting elements (ED), a signal is applied to the first voltage wiring (VL1) and the second voltage wiring (VL2), and these can be transmitted to the first electrode (RME1) and the second electrode (RME2), respectively.

[0128] In one embodiment, the first electrode contact hole (CTD) and the second electrode contact hole (CTS) may have different relative arrangements to the third electrode contact hole (CTA). The first electrode contact hole (CTD) may be placed in the first sub-region (SA1) and the second sub-region (SA2), respectively, and the second electrode contact hole (CTS) may be formed to overlap with the bank layer (BNL) located on one side of the second direction (DR2) of each sub-region (SA1, SA2). On the other hand, the third electrode contact hole (CTA) may be placed only in the first sub-region (SA1). This may be because the second electrode contact hole (CTS) and the third electrode contact hole (CTA) each expose the upper surface of different voltage wirings (VL1, VL2), and the position of each electrode contact hole may be determined accordingly. Even in the case of a separation section (ROP1, ROP2) where the electrodes (RME) are separated, the first separation section (ROP1) may be positioned in the first sub-region (SA1) and formed on the upper and lower sides of the wiring connection electrode (EP), respectively. On the other hand, the second separation section (ROP2) may be positioned in the second sub-region (SA2) and positioned between the first electrodes (RME1). Two first separation sections (ROP1) may be formed in the first sub-region (SA1), and one second separation section (ROP2) may be formed in the second sub-region (SA2).

[0129] The electrodes (RME) may include a highly reflective conductive material. For example, the electrodes (RME) may include a metal such as silver (Ag), copper (Cu), aluminum (Al), an alloy such as aluminum (Al), nickel (Ni), lanthanum (La), or a structure in which a metal layer such as titanium (Ti), molybdenum (Mo), and niobium (Nb) is stacked with said alloy. In some embodiments, the electrodes (RME) may be composed of a double layer or a multilayer structure in which an alloy containing aluminum (Al) and at least one metal layer consisting of titanium (Ti), molybdenum (Mo), and niobium (Nb) are stacked.

[0130] Each electrode (RME) may further include a transparent conductive material, without being limited thereto. For example, each electrode (RME) may include a material such as ITO, IZO, ITZO, etc. In some embodiments, each electrode (RME) may have a structure in which a transparent conductive material and a highly reflective metal layer are each stacked one or more times, or may be formed as a single layer including these. For example, each electrode (RME) may have a stacked structure such as ITO / Ag / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO. The electrodes (RME) are electrically connected to a light-emitting element (ED) and may reflect some of the light emitted from the light-emitting element (ED) toward the upper direction of the first substrate (SUB).

[0131] The first insulating layer (PAS1) is placed on the front surface of the display area (DPA) and can be placed on via layers (VIA) and electrodes (RME). The first insulating layer (PAS1) can protect the electrodes (RME) and simultaneously insulate different electrodes (RME) from each other. Since the first insulating layer (PAS1) is placed to cover the electrodes (RME) before the bank layer (BNL) is formed, it can prevent the electrodes (RME) from being damaged during the process of forming the bank layer (BNL). Additionally, the first insulating layer (PAS1) can prevent the light-emitting element (ED) placed thereon from being damaged by direct contact with other components.

[0132] In an exemplary embodiment, the first insulating layer (PAS1) may have a step formed such that a portion of its upper surface is recessed between electrodes (RME) spaced apart in the second direction (DR2). A light-emitting element (ED) is disposed on the upper surface of the first insulating layer (PAS1) where the step is formed, and a space may be formed between the light-emitting element (ED) and the first insulating layer (PAS1).

[0133] According to one embodiment, the first insulating layer (PAS1) may include separation openings and contact holes (CT1, CT2) formed corresponding to separation portions (ROP1, ROP2). The first insulating layer (PAS1) is disposed entirely on the via layer (VIA), but may partially expose the lower layers in the portions where the plurality of separation openings and contact holes (CT1, CT2) are formed.

[0134] Separation openings formed in the first insulating layer (PAS1), corresponding to separation portions (ROP1, ROP2) of sub-regions (SA1, SA2), can expose a via layer (VIA) disposed below. In the separation openings of the first insulating layer (PAS1), a process of separating first electrodes (RME1) that were connected to each other can be performed. A first electrode (RME1) extending in the first direction (DR1) is formed in a state connected to the first electrode (RME1) or wiring connection electrode (EP) of other sub-pixels (SPXn) adjacent in the first direction (DR1), and then the portion exposed by the separation openings of the first insulating layer (PAS1) can be etched to separate them from each other. The separation openings of the first insulating layer (PAS1) may be positioned to correspond to the separation portions (ROP1, ROP2) located between the first electrodes (RME1) or between the first electrode (RME1) and the wiring connection electrode (EP).

[0135] The contact holes (CT1, CT2) of the first insulating layer (PAS1) may be arranged to overlap with different electrodes (RME) in sub-regions (SA1, SA2), respectively. For example, the contact holes (CT1, CT2) may include first contact holes (CT1) arranged to overlap with the first electrode (RME1), and second contact holes (CT2) arranged to overlap with the second electrode (RME2). The first contact holes (CT1) and the second contact holes (CT2) may be arranged in sub-regions (SA1, SA2), respectively. The first contact hole (CT1) arranged in the first sub-region (SA1) may be placed on the first electrode (RME1) spaced apart from the first separation part (ROP1) arranged below the wiring connection electrode (EP). The first contact hole (CT1) disposed in the second sub-region (SA2) may be disposed on the first electrode (RME1) of another sub-pixel (SPXn), spaced apart from the second separation part (ROP2). The second contact hole (CT2) may be disposed on the portion of the electrode stem part (RM_S) of the second electrode (RME2) that protrudes into the sub-regions (SA1, SA2).

[0136] The first contact holes (CT1) and the second contact holes (CT2) can penetrate the first insulating layer (PAS1) to expose a portion of the upper surface of the first electrode (RME1) or the second electrode (RME2) below it. The first contact holes (CT1) and the second contact holes (CT2) can each further penetrate a portion of other insulating layers disposed on the first insulating layer (PAS1). The electrode (RME) exposed by each contact hole (CT1, CT2) can come into contact with the connecting electrode (CNE).

[0137] A bank layer (BNL) may be disposed on a first insulating layer (PAS1). The bank layer (BNL) includes a portion extending in a first direction (DR1) and a second direction (DR2) and may surround each subpixel (SPXn). The bank layer (BNL) may surround and distinguish the light-emitting region (EMA) and sub-regions (SA1, SA2) of each subpixel (SPXn), and may surround the outermost edge of a display region (DPA) and distinguish the display region (DPA) from the non-display region (NDA). The portion of the bank layer (BNL) extended in the first direction (DR1) may distinguish the light-emitting region (EMA) and the sub-regions (SA1, SA2), and the portion extended in the second direction (DR2) may distinguish adjacent subpixels (SPXn). The portion of the bank layer (BNL) extended in the second direction (DR2) may be disposed on a second partition (BP2).

[0138] The bank layer (BNL) may have a certain height similar to the partitions (BP1, BP2). In some embodiments, the height of the upper surface of the bank layer (BNL) may be higher than that of the partitions (BP1, BP2), and its thickness may be equal to or greater than that of the partitions (BP1, BP2). The bank layer (BNL) can prevent ink from overflowing into adjacent subpixels (SPXn) during the inkjet printing process in the manufacturing process of the display device (10). The bank layer (BNL) may include an organic insulating material such as polyimide, similar to the partitions (BP1, BP2). However, it is not limited thereto, and the bank layer (BNL) may include a different material than that of the partitions (BP1, BP2).

[0139] Light-emitting elements (EDs) may be placed in a light-emitting region (EMA). Light-emitting elements (EDs) may be placed on a first insulating layer (PAS1) between partitions (BP1, BP2). A light-emitting element (ED) may be placed such that one extended direction is parallel to the upper surface of a first substrate (SUB). As described below, the light-emitting element (ED) may include a plurality of semiconductor layers arranged along the one extended direction, and the plurality of semiconductor layers may be arranged sequentially along a direction parallel to the upper surface of the first substrate (SUB). However, not limited thereto, if the light-emitting element (ED) has a different structure, the plurality of semiconductor layers may be arranged in a direction perpendicular to the first substrate (SUB).

[0140] The light-emitting elements (EDs) placed in each subpixel (SPXn) can emit light of different wavelengths depending on the material of the semiconductor layer. However, not limited thereto, the light-emitting elements (EDs) placed in each subpixel (SPXn) may include a semiconductor layer of the same material and emit light of the same color.

[0141] Light-emitting elements (ED) can be placed on different electrodes (RME) between different partitions (BP1, BP2). A first light-emitting element (ED1) can be placed between the first partition (BP1) and the second partition (BP2), with both ends placed on the second electrode branch (RM_B2) of the first electrode (RME1) and the second electrode (RME2). A second light-emitting element (ED2) can be placed between the second partition (BP2) and the first partition (BP1), with both ends placed on the first electrode branch (RM_B1) of the first electrode (RME1) and the second electrode (RME2). The first light-emitting element (ED1) can be placed to the right of the first partition (BP1) in the light-emitting region (EMA), and the second light-emitting element (ED2) can be placed to the left of the first partition (BP1).

[0142] The light-emitting elements (EDs) can be electrically connected to the conductive layers under the electrode (RME) and via layer (VIA) by contacting the connecting electrodes (CNE), and can emit light of a specific wavelength range when an electrical signal is applied.

[0143] A second insulating layer (PAS2) may be disposed on a plurality of light-emitting elements (ED), a first insulating layer (PAS1), and a bank layer (BNL). The second insulating layer (PAS2) includes a pattern portion that extends in a first direction (DR1) between partitions (BP1, BP2) and is disposed on a plurality of light-emitting elements (ED). The pattern portion is disposed to partially cover the outer surface of the light-emitting element (ED), and may not cover both sides or both ends of the light-emitting element (ED). The pattern portion may form a linear or island pattern within each subpixel (SPXn) in a planar view. The pattern portion of the second insulating layer (PAS2) can protect the light-emitting element (ED) and, at the same time, fix the light-emitting elements (ED) during the manufacturing process of the display device (10). Additionally, the second insulating layer (PAS2) may be disposed to fill the space between the light-emitting element (ED) and the second insulating layer (PAS2) below it. A portion of the second insulating layer (PAS2) may be placed on the upper part of the bank layer (BNL) and in the sub-regions (SA).

[0144] According to one embodiment, the second insulating layer (PAS2) may include separation openings and contact holes (CT1, CT2) formed corresponding to the separation portions (ROP1, ROP2). The second insulating layer (PAS2) is disposed entirely on the first insulating layer (PAS1), but may partially expose the underlying layers in the portions where the separation openings and contact holes (CT1, CT2) are formed. The description of the separation openings and contact holes (CT1, CT2) is the same as described above in relation to the first insulating layer (PAS1).

[0145] Connecting electrodes (CNE) can be placed on electrodes (RME) and partitions (BP1, BP2). Connecting electrodes (CNE) can be divided into connecting electrodes of a first connecting electrode layer placed between a second insulating layer (PAS2) and a third insulating layer (PAS3), and connecting electrodes of a second connecting electrode layer placed on the third insulating layer (PAS3). The third connecting electrode (CNE3) is a connecting electrode of the first connecting electrode layer, and the first connecting electrode (CNE1) and the second connecting electrode (CNE2) may be connecting electrodes of the second connecting electrode layer.

[0146] The first connecting electrode (CNE1) may be placed on the first electrode (RME1) and the first partition (BP1). The second connecting electrode (CNE2) may be placed on the second electrode (RME2) and the second partition (BP2). The third connecting electrode (CNE3) may be placed across the first electrode (RME1), the second electrode (RME2), the second partition (BP2), and the first partition (BP1). The description of the planar arrangement of each connecting electrode (CNE) is the same as described above with reference to FIG. 5.

[0147] The first connecting electrode (CNE1), the second connecting electrode (CNE2), and the third connecting electrode (CNE3) are each disposed on the second insulating layer (PAS2) and can come into contact with light-emitting elements (ED). The first connecting electrode (CNE1) can come into contact with the first end of the first light-emitting elements (ED1). The second connecting electrode (CNE2) can come into contact with the second end of the second light-emitting elements (ED2). The third connecting electrode (CNE3) can have a first extension (CN_E1) ​​come into contact with the second end of the first light-emitting elements (ED1) and a second extension (CN_E2) come into contact with the first end of the second light-emitting elements (ED2).

[0148] The first connecting electrode (CNE1) and the second connecting electrode (CNE2) are positioned across the light-emitting region (EMA) and sub-regions (SA1, SA2), and can directly contact the electrodes (RME1, RME2) through contact holes (CT1, CT2) formed in the respective sub-regions (SA1, SA2). The first connecting electrode (CNE1) can contact the first electrode (RME1) through a first contact hole (CT1) that penetrates the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) in the sub-regions (SA1, SA2). The second connecting electrode (CNE2) can contact the second electrode (RME2) through a second contact hole (CT2) that penetrates the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) in the sub-regions (SA1, SA2). On the other hand, the third connecting electrode (CNE3) may not come into contact with the electrode (RME).

[0149] The first connecting electrode (CNE1) is electrically connected to the first transistor (T1) through the first electrode (RME1) so that the first power supply voltage is transmitted, and the second connecting electrode (CNE2) is electrically connected to the second voltage wiring (VL2) through the second electrode (RME2) so that the second power supply voltage can be applied. The light-emitting elements (ED) can emit light by the power supply voltage transmitted through the first connecting electrode (CNE1) and the second connecting electrode (CNE2).

[0150] The first connecting electrode (CNE1) and the second connecting electrode (CNE2) are each first-type connecting electrodes connected to electrodes (RME1, RME2) directly connected to the third conductive layer, and the third connecting electrode (CNE3) may be a second-type connecting electrode not connected to the electrode (RME). The third connecting electrode (CNE3) is not connected to the electrode (RME) but contacts the light-emitting elements (ED) and can form an electrical connection circuit of the light-emitting elements (ED) together with other connecting electrodes (CNE).

[0151] However, it is not limited thereto. In some embodiments, some of the connecting electrodes (CNE) of the display device (10) may be directly connected to the third conductive layer. For example, the first connecting electrode (CNE1) and the second connecting electrode (CNE2), which are first type connecting electrodes, may each be directly connected to the third conductive layer and may not be electrically connected to the electrode (RME). The second type connecting electrode may also not be electrically connected to the electrode (RME) and may be connected only to the light-emitting elements (ED).

[0152] Connecting electrodes (CNEs) may include a conductive material. For example, they may include ITO, IZO, ITZO, aluminum (Al), etc. As an example, the connecting electrode (CNE) may include a transparent conductive material, and light emitted from the light-emitting element (ED) may pass through the connecting electrode (CNE) and be emitted.

[0153] A third insulating layer (PAS3) is disposed on the connecting electrodes of the second connecting electrode layer and on the second insulating layer (PAS2). The third insulating layer (PAS3) is disposed entirely on the second insulating layer (PAS2) to cover the third connecting electrode (CNE3), and the first connecting electrode (CNE1) and the second connecting electrode (CNE2) may be disposed on the third insulating layer (PAS3). The third insulating layer (PAS3) may be disposed entirely on the via layer (VIA), except for the area where the third connecting electrode (CNE3) is disposed. The third insulating layer (PAS3) may insulate the connecting electrodes of the first connecting electrode layer and the connecting electrodes of the second connecting electrode layer from each other so that they do not come into direct contact.

[0154] According to one embodiment, the third insulating layer (PAS3) may include a plurality of contact holes (CT1, CT2). The third insulating layer (PAS3) is disposed entirely on the second insulating layer (PAS2), but may partially expose the lower layers in the portion where the plurality of contact holes (CT1, CT2) are formed. The first contact hole (CT1) and the second contact hole (CT2) may penetrate the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3). Each of the contact holes (CT1, CT2) may expose a portion of the upper surface of the electrode (RME) below it.

[0155] The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) described above may each comprise an inorganic insulating material or an organic insulating material. For example, the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may each comprise an inorganic insulating material, or the first insulating layer (PAS1) and the third insulating layer (PAS3) may comprise an inorganic insulating material, while the second insulating layer (PAS2) may comprise an organic insulating material. The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may each, or at least one of them, be formed in a structure in which a plurality of insulating layers are stacked alternately or repeatedly. In an exemplary embodiment, the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may each be silicon oxide (SiO₂). x ), silicon nitride (SiN x ), and silicon oxynitride (SiO₂ x N y It may be any one of the following. The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may be made of the same material, some of which may be made of the same material and some of which may be made of different material, or each of which may be made of different material.

[0156] According to one embodiment, the display device (10) may further include a heat control layer ('HCL' in FIG. 9), a color control layer ('TPL', 'WCL1', 'WCL2' in FIG. 9), and a color filter layer ('CFL1', 'CFL2', 'CFL3' in FIG. 9) disposed on light-emitting elements (ED). Light emitted from the light-emitting elements (ED) may be emitted through the color control layer (TPL, WCL1, WCL2) and the color filter layer (CFL1, CFL2, CFL3), and even if the same type of light-emitting elements (ED) are disposed for each subpixel (SPXn), the color of the emitted light may differ for each subpixel (SPXn). Additionally, heat generated when the light-emitting elements (ED) emit light may be absorbed by the heat control layer (HCL), and the heat control layer (HCL) may prevent said heat from being transferred to the color control layer (TPL, WCL1, WCL2).

[0157] FIG. 9 is a cross-sectional view showing color control layers and a thermal control layer disposed in a pixel of a display device according to one embodiment. FIG. 10 is a cross-sectional view showing a first wavelength conversion layer and a thermal control layer of a first subpixel of FIG. 9.

[0158] FIGS. 9 and 10 are cross-sectional views showing the arrangement of color control layers (TPL, WCL1, WCL2), color filter layers (CFL1, CFL2, CFL3), and thermal control layer (HCL) placed in one pixel (PX) of a display device (10). A detailed arrangement and description of the partitions (BP1, BP2), electrodes (RME1, RME2), bank layer (BNL), light-emitting elements (ED), and connecting electrodes (CNE1, CNE2) placed in each subpixel (SPXn) in FIGS. 9 and 10 can be understood by referring to FIGS. 5 through 8.

[0159] Referring to FIGS. 9 and 10, the display device (10) may include light-emitting elements (ED) disposed on a first substrate (SUB), a thermal control layer (HCL), a color control layer (TPL, WCL1, WCL2), and a color filter layer (CFL1, CFL2, CFL3) disposed thereon. The display device (10) may further include a plurality of layers disposed between the color control layers (TPL, WCL1, WCL2) and the color filter layers (CFL1, CFL2, CFL3) and on them.

[0160] On the third insulating layer (PAS3), an upper bank layer (UBM), a thermal control layer (HCL), a color control layer (TPL, WCL1, WCL2), a color pattern (CP1, CP2, CP3), and a color filter layer (CFL1, CFL2, CFL3) may be disposed. Between the color control layer (TPL, WCL1, WCL2) and the color filter layer (CFL1, CFL2, CFL3), capping layers (CPL1, CPL2), a low refractive index layer (LRL), and a planarization layer (PNL) may be disposed, and an overcoat layer (OC) may be disposed on the color filter layer (CFL1, CFL2, CFL3).

[0161] Each subpixel (SPXn) of the display device (10) may include a plurality of light-emitting regions (TA: TA1, TA2, TA3) through which light is emitted and where color filter layers (CFL1, CFL2, CFL3) are arranged, and a light-blocking region (BA) between the light-emitting regions (TA) from which light is not emitted. The light-emitting regions (TA) may be arranged to correspond to a part of the light-emitting region (EMA) of each subpixel (SPXn), and the light-blocking region (BA) may be an area other than the light-emitting region (TA). For example, the light-blocking region (BA) may surround each of the light-emitting regions (TA).

[0162] The upper bank layer (UBM) may be arranged to overlap with the bank layer (BNL) on the third insulating layer (PAS3). The upper bank layer (UBM) may be arranged in a grid pattern including portions extending in the first direction (DR1) and the second direction (DR2). The upper bank layer (UBM) may surround portions where light-emitting regions (EMA) or light-emitting elements (ED) are arranged. The upper bank layer (UBM) may form a region where color control layers (TPL, WCL1, WCL2) are arranged.

[0163] A thermal control layer (HCL) may be disposed on the third insulating layer (PAS3) and the second connecting electrode layer, which is the first connecting electrode (CNE1) and the second connecting electrode (CNE2). The thermal control layer (HCL) is disposed on the third insulating layer (PAS3) and may be disposed corresponding to the area partitioned by the bank layer (BNL) of each subpixel (SPXn). For example, the thermal control layer (HCL) may be disposed in the light-emitting region (EMA) surrounded by the bank layer (BNL), and may also be disposed in sub-regions (SA1, SA2) which are not shown in the drawings. Thermal control layers (HCL) disposed on different subpixels (SPXn) may be separated from each other by the bank layer (BNL). However, this is not limited thereto, and the thermal control layer (HCL) may be disposed as a single layer across multiple subpixels (SPXn) or the entire front of the display area (DPA) without being separated from each other. A detailed explanation thereof will be provided later.

[0164] According to one embodiment, the heat control layer (HCL) may include a resin layer (PRS) and phase transition particles (PCM) dispersed in the resin layer (PRS). The phase transition particles (PCM) may include a material that changes phase by absorbing or releasing heat, and the heat control layer (HCL) may absorb heat generated from the surroundings. The display device (10) may be configured such that the heat control layer (HCL) is placed on a third insulating layer (PAS3) to cover light-emitting elements (EDs) and can absorb heat generated from the light-emitting elements (EDs). The heat control layer (HCL) may reduce the transfer of heat generated from the light-emitting elements (EDs) to the color control layers (TPL, WCL1, WCL2) described later.

[0165] FIG. 11 is a schematic diagram showing phase transition particles included in the thermal control layer of a display device according to one embodiment.

[0166] Referring to FIG. 11, the phase transition particle (PCM) of the heat control layer (HCL) may have a core-shell structure. The phase transition particle (PCM) may include a core portion (C) containing a phase transition material and a first shell (S1) surrounding it. The core portion (C) may include a material with a large latent heat content that can change phases depending on the absorption and release of heat. For example, the core portion (C) may include materials such as alkanes with 10 or more carbon atoms, polyethylene glycol (PEG), polyethylene glycol derivatives, aluminum-silicon alloys (Al-Si alloys), or inorganic hydrates. In one embodiment, the core portion (C) of the phase transition particle (PCM) is a dodecane (C12), which is an alkane with 12 carbon atoms. 12 H 26 ), docosane (C2), an alkane with 22 carbon atoms 22 H 46 It may include ) or an aluminum-silicon alloy (Al-Si alloy).

[0167] Dodecane (C12 H 26 ) and docosane(C 22 H 46 ) have latent heat values ​​of approximately 210 kJ / kg and approximately 230 kJ / kg, respectively, and docosane (C 22 H 46 In the case of ), a phase change is possible at a temperature of approximately 44°C. Aluminum-silicon alloy (Al-Si alloy) has a latent heat of 180 kJ / kg and a phase change is possible at a temperature of approximately 577°C. Dodecane and docosane were exemplified as the core part (C) being an alkane with 10 or more carbon atoms, but is not limited thereto. The core part (C) may include alkanes other than dodecane and docosane as long as it is a material capable of a phase change with a latent heat similar to that of dodecane and docosane.

[0168] The core portion (C) of the phase transition particle (PCM) containing such material can change phase due to heat generated in the operating environment of the display device (10). The heat generated along with the light emitting element (ED) emitting light can be absorbed by the phase transition particle (PCM) of the heat control layer (HCL) and can prevent said heat from spreading to the surroundings.

[0169] The first shell (S1) of the phase transition particle (PCM) may include a relatively hard material to accommodate volume changes resulting from the phase change of the core part (C). For example, the first shell (S1) may include materials such as polystyrene (PS), polymethylmethacrylate (PMMA), aluminum oxide (Al2O3), and polymethylmethacrylate-silica (PMMA-silica). The first shell (S1) includes a material capable of maintaining the shape of the phase transition particle (PCM) even if the volume changes when the core part (C) absorbs or releases heat and undergoes a phase change, and can prevent volatilization and leakage of the core part (C) material.

[0170] FIG. 12 is a schematic diagram showing phase transition particles included in the thermal control layer of a display device according to another embodiment.

[0171] Referring to FIG. 12, the phase transition particle (PCM) may further include a second shell (S2) disposed between the first shell (S1) and the core portion (C). The second shell (S2) may be disposed to surround the core portion (C), and the first shell (S1) may be disposed to surround the second shell (S2). The second shell (S2) may include a thermally conductive material so that the core portion (C) can more easily absorb and release heat. For example, the second shell (S2) may include a material such as graphite, carbon black, or a conductive polymer such as PEDOT-PSS. As the phase transition particle (PCM) further includes the second shell (S2), the heat control layer (HCL) can more easily control the heat generated in the light-emitting element (ED).

[0172] Heat generated during the operation of the light-emitting element (ED) can cause a decrease in brightness of the display device (10). If heat generated from the light-emitting element (ED) is transferred to surrounding light-emitting elements (ED) or to the color control layers (TPL, WCL1, WCL2) described later, the brightness may decrease due to the degradation of the light-emitting element (ED) and the color control layers (TPL, WCL1, WCL2). This may lead to a decrease in the lifespan of the display device (10). To prevent this, the display device (10) may include a heat control layer (HCL) that covers the light-emitting elements (ED) and is disposed between the light-emitting elements (ED) and the color control layers (TPL, WCL1, WCL2). The heat control layer (HCL) can absorb heat generated from the light-emitting elements (ED) to minimize the transfer of heat to other surrounding components. As most of the heat generated during the operation of the display device (10) is absorbed by the heat control layer (HCL), the degradation of the light-emitting element (ED) and the color control layer (TPL, WCL1, WCL2) can be prevented, and the lifespan of the display device (10) can be increased.

[0173] According to one embodiment, the heat control layer (HCL) can be formed through an inkjet printing process, and the phase transition particles (PCM) of the heat control layer (HCL) can have a small size and be dispersed in the resin layer (PRS). Considering the nozzle diameter of the inkjet printing device, the phase transition particles (PCM) can have a sufficiently small diameter. According to one embodiment, the phase transition particles (PCM) can have a diameter of 1 μm or less, or 0.5 μm or less, or 0.2 μm or less.

[0174] The resin layer (PRS) of the heat control layer (HCL) may include an organic material having a viscosity sufficient to disperse phase transition particles (PCM) and allow them to be extruded through an inkjet printing device. Additionally, the resin layer (PRS) may include a transparent material so that light emitted from a light-emitting element (ED) can be transmitted. In one embodiment, the resin layer (PRS) may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin, etc.

[0175] The color control layers (TPL, WCL1, WCL2) may be placed directly on the thermal control layer (HCL) and within the area surrounded by the upper bank layer (UBM). The color control layers (TPL, WCL1, WCL2) may be placed in direct contact with the inner side of the upper bank layer (UBM). The color control layers (TPL, WCL1, WCL2) may be placed in the light-transmitting area (TA) surrounded by the upper bank layer (UBM) to form an island-shaped pattern in the display area (DPA). In FIG. 9, the color control layers (TPL, WCL1, WCL2) are exemplified as being placed to fill the area surrounded by the bank layer (BNL) and the upper bank layer (UBM), but are not limited thereto. The color control layers (TPL, WCL1, WCL2) may each extend in one direction and be placed across a plurality of subpixels (SPXn) to form a linear pattern.

[0176] In an embodiment where the light-emitting element (ED) of each subpixel (SPXn) emits a third color of blue light, the color control layer (TPL, WCL1, WCL2) may include wavelength conversion layers (WCL: WCL1, WCL2) and a light-transmitting layer (TPL). The wavelength conversion layers (WCL1, WCL2) may include a first wavelength conversion layer (WCL1) disposed in the first subpixel (SPX1) and a second wavelength conversion layer (WCL2) disposed in the second subpixel (SPX2). The light-transmitting layer (TPL) may be disposed in the third subpixel (SPX3). The first wavelength conversion layer (WCL1) may be disposed in the first light-transmitting region (TA1), and the second wavelength conversion layer (WCL2) may be disposed in the second light-transmitting region (TA2). The light-transmitting layer (TPL) may be disposed in the third light-transmitting region (TA3) of the third subpixel (SPX3).

[0177] The first wavelength conversion layer (WCL1) may include a first base resin (BRS1) and a first wavelength conversion material (WCP1) disposed within the first base resin (BRS1). The second wavelength conversion layer (WCL2) may include a second base resin (BRS2) and a second wavelength conversion material (WCP2) disposed within the second base resin (BRS2). The wavelength conversion layers (WCL1, WCL2) can convert and transmit the wavelength of a third color blue light incident from a light-emitting element (ED). The wavelength conversion layers (WCL1, WCL2) further include a scatterer (SCP) contained in each base resin, and the scatterer (SCP) can increase the wavelength conversion efficiency.

[0178] The light-transmitting layer (TPL) may include a third base resin (BRS3) and a scatterer (SCP) disposed within the third base resin (BSR3). The light-transmitting layer (TPL) can transmit the third color blue light incident from the light-emitting element (ED) while maintaining its wavelength. The scatterer (SCP) of the light-transmitting layer (TPL) may serve to regulate the emission path of light emitted through the light-transmitting layer (TPL). The light-transmitting layer (TPL) may not contain a wavelength conversion material.

[0179] The scattering body (SCP) may be a metal oxide particle or an organic particle. Examples of the metal oxide may include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), barium sulfate (BaSO4), zinc oxide (ZnO), or tin oxide (SnO2), and examples of the organic particle material may include acrylic resin or urethane resin.

[0180] The first to third base resins (BRS1, BRS2, ​​BRS3) may include a transparent organic material. For example, the first to third base resins (BRS1, BRS2, ​​BRS3) may be composed of an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first to third base resins (BRS1, BRS2, ​​BRS3) may all be composed of the same material, but are not limited thereto.

[0181] The first wavelength conversion material (WCP1) may be a material that converts third-color blue light into first-color red light, and the second wavelength conversion material (WCP2) may be a material that converts third-color blue light into second-color green light. The first wavelength conversion material (WCP1) and the second wavelength conversion material (WCP2) may be quantum dots, quantum rods, phosphors, etc. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or a combination thereof.

[0182] In some embodiments, the color control layers (TPL, WCL1, WCL2) may be formed through an inkjet printing process or a photoresist process. The color control layers (TPL, WCL1, WCL2) may be formed by spraying or applying the material constituting them within an area surrounded by an upper bank layer (UBM), followed by drying or exposure and development processes. For example, in an embodiment where the color control layers (TPL, WCL1, WCL2) are formed by an inkjet printing process, the upper surface of each layer of the color control layers (TPL, WCL1, WCL2) may be formed curved in the drawings so that the edge portion adjacent to the upper bank layer (UBM) is higher than the center. However, this is not limited thereto. In an embodiment where the color control layer (TPL, WCL1, WCL2) is formed by a photoresist process, the upper surface of each layer of the color control layer (TPL, WCL1, WCL2) may be formed flat so that the edge portion adjacent to the upper bank layer (UBM) is parallel to the upper surface of the upper bank layer (UBM), or, unlike the drawing, the center of the color control layer (TPL, WCL1, WCL2) may be formed higher.

[0183] A first wavelength conversion layer (WCL1) may be placed on a first subpixel (SPX1). The first wavelength conversion layer (WCL1) is placed on the light-emitting region (EMA) of the first subpixel (SPX1) and may be placed within the region surrounding the first subpixel (SPX1) where the bank layer (BNL) and the upper bank layer (UBM) are located. A second wavelength conversion layer (WCL2) may be placed on a second subpixel (SPX2). The second wavelength conversion layer (WCL2) is placed on the light-emitting region (EMA) of the second subpixel (SPX2) and may be placed within the region surrounding the second subpixel (SPX2) where the bank layer (BNL) and the upper bank layer (UBM) are located.

[0184] A light-transmitting layer (TPL) may be placed in the third subpixel (SPX3). The light-transmitting layer (TPL) is placed in the light-emitting region (EMA) of the third subpixel (SPX3), and the bank layer (BNL) and the upper bank layer (UBM) may be placed within the region surrounding the third subpixel (SPX3).

[0185] The light-emitting elements (EDs) placed in each subpixel (SPXn) are arranged to overlap with the color control layers (TPL, WCL1, WCL2) above them, and light emitted from the light-emitting elements (EDs) can be incident on the color control layers (TPL, WCL1, WCL2).

[0186] For example, the light-emitting element (ED) of each subpixel (SPXn) can emit the same third color of blue light, and the light emitted from each subpixel (SPXn) can be of different colors. Light emitted from the light-emitting element (ED) placed in the first subpixel (SPX1) is incident on the first wavelength conversion layer (WCL1), light emitted from the light-emitting element (ED) placed in the second subpixel (SPX2) is incident on the second wavelength conversion layer (WCL2), and light emitted from the light-emitting element (ED) placed in the third subpixel (SPX3) can be incident on the light-transmitting layer (TPL). Light incident on the first wavelength conversion layer (WCL1) is converted into red light, light incident on the second wavelength conversion layer (WCL2) is converted into green light, and light incident on the light-transmitting layer (TPL) can be transmitted as the same blue light without wavelength conversion. Even if the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) each include light-emitting elements (ED) that emit light of the same color, they can emit light of different colors depending on the arrangement of the color control layers (TPL, WCL1, WCL2) placed on top thereof.

[0187] The thermal control layer (HCL) and the color control layer (TPL, WCL1, WCL2) may each include a resin layer (PRS) or a base resin (BRS1, BRS2, ​​BRS3) and particles dispersed therein, such as phase transition particles (PCM), wavelength conversion materials (WCP1, WCP2), and scatterers (SCP). The thermal control layer (HCL) and the color control layer (TPL, WCL1, WCL2) may be similar in that they are disposed on a light-emitting element (ED) and include a resin layer (PRS) or a base resin (BRS1, BRS2, ​​BRS3) made of a transparent material. However, the thermal control layer (HCL) is a layer that controls heat generated from the light-emitting element (ED), and the color control layer (TPL, WCL1, WCL2) is a layer that controls the color of light emitted from the light-emitting element (ED), so their functions may differ.

[0188] If the heat control layer (HCL) covers the light-emitting element (ED) and contains phase transition particles (PCM) sufficient to control the heat generated by the light-emitting element (ED), its thickness and arrangement can be varied. For example, FIGS. 9 and 10 illustrate that the heat control layer (HCL) is positioned within the area surrounded by the bank layer (BNL), so that the height of the upper surface is equal to the height of the bank layer (BNL) and the uppermost layer of the second insulating layer (PAS2) and the third insulating layer (PAS3). However, this is not limited thereto, and the heat control layer (HCL) may have a thicker thickness, and its upper surface may be located above the bank layer (BNL), the second insulating layer (PAS2), and the third insulating layer (PAS3). Alternatively, the height of the upper surface of the heat control layer (HCL) may be lower than the height of the bank layer (BNL), the uppermost layer of the second insulating layer (PAS2), and the third insulating layer (PAS3).

[0189] On the other hand, the color control layer (TPL, WCL1, WCL2) may change the color coordinates or luminance of the light emitted from the light-emitting element (ED) and converted or transmitted through the color control layer (TPL, WCL1, WCL2) depending on its thickness. The color control layer (TPL, WCL1, WCL2) of the display device (10) may have a minimum thickness to have sufficient conversion efficiency of the light emitted from the light-emitting element (ED) depending on the materials of the wavelength conversion material (WCP1, WCP2) and the scatterer (SCP). According to one embodiment, the thickness of the color control layer (TPL, WCL1, WCL2) of the display device (10) may be thicker than the thickness of the thermal control layer (HCL). The upper bank layer (UBM) may be placed on the bank layer (BNL) and may have a thicker thickness. As the color control layer (TPL, WCL1, WCL2) is positioned within the area surrounded by the upper bank layer (UBM), it may have a thicker thickness than the thermal control layer (HCL) positioned within the area surrounded by the bank layer (BNL). In one embodiment, the thermal control layer (HCL) may have a thickness in the range of approximately 2 μm, and the color control layer (TPL, WCL1, WCL2) may have a thickness in the range of 8 μm to 10 μm. Even if the thermal control layer (HCL) has a thicker thickness, it may have a thickness that is at least smaller than that of the color control layer (TPL, WCL1, WCL2). The display device (10) can effectively control the heat generated in the light-emitting element (ED) and improve the conversion efficiency of the light emitted from the light-emitting element (ED) by adjusting the thickness of the thermal control layer (HCL) and the thickness of the color control layer (TPL, WCL1, WCL2).

[0190] As the functions of the heat control layer (HCL) and the color control layer (TPL, WCL1, WCL2) differ from one another, the functions of the resin layer (PRS) and the base resin (BRS1, BRS2, ​​BRS3) may also differ from one another. Various materials can be selected for the resin layer (PRS) within a range of transparency, provided that it has a viscosity sufficient to allow the phase transition particles (PCM) to be dispersed and the heat control layer (HCL) to be formed through an inkjet printing process. On the other hand, the base resin (BRS1, BRS2, ​​BRS3) can be selected for a viscosity sufficient to allow the wavelength conversion material (WCP1, WCP2) to be dispersed and the material to be discharged through a nozzle, in addition to considering the conversion efficiency of the light emitted from the light-emitting device (ED). The resin layer (PRS) and base resins (BRS1, BRS2, ​​BRS3) may each include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin, and these materials may be the same or different. They may be determined by the material of the phase transition particles (PCM) of the heat control layer (HCL), the performance of the inkjet printing device, and the color coordinates of the light emitted from the light-emitting element (ED).

[0191] The first capping layer (CPL1) may be disposed on a plurality of color control layers (TPL, WCL1, WCL2) and an upper bank layer (UBM). The first capping layer (CPL1) can prevent impurities, such as moisture or air, from penetrating from the outside and damaging or contaminating the color control layers (TPL, WCL1, WCL2). The first capping layer (CPL1) may include an inorganic insulating material.

[0192] The first capping layer (CPL1) is positioned to cover the color control layers (TPL, WCL1, WCL2) and may be positioned along the step formed by them. The color control layers (TPL, WCL1, WCL2) may be positioned to fill the area surrounded by the upper bank layer (UBM), and the first capping layer (CPL1) may be positioned to extend from the upper surface of the color control layers (TPL, WCL1, WCL2) to the upper surface of the upper bank layer (UBM).

[0193] A low refractive index layer (LRL) can be placed on the first capping layer (CPL1). The low refractive index layer (LRL) is an optical layer that recycles light passing through the color control layer (TPL, WCL1, WCL2) and can improve the light emission efficiency and color purity of the display device (10). The low refractive index layer (LRL) can be made of an organic material having a low refractive index and can compensate for the step difference formed by the color control layer (TPL, WCL1, WCL2) and the upper bank layer (UBM).

[0194] The second capping layer (CPL2) is placed on the low-refractive index layer (LRL) and can prevent impurities, such as moisture or air, from penetrating from the outside and damaging or contaminating the low-refractive index layer (LRL). The second capping layer (CPL2) may include an inorganic insulating material similar to the first capping layer (CPL1).

[0195] The planarization layer (PNL) can be disposed across the entire front of the display area (DPA) and non-display area (NDA) on the second capping layer (CPL2). The planarization layer (PNL) can overlap with the color control layers (TPL, WCL1, WCL2) in the display area (DPA). In addition to the capping layers (CPL1, CPL2) and the low-refractive index layer (LRL), the planarization layer (PNL) protects the members disposed on the first substrate (SUB) and can partially compensate for the step difference caused by them. In particular, the planarization layer (PNL) compensates for the step difference formed by the lower color control layers (TPL, WCL1, WCL2) and the upper bank layer (UBM) and bank layer (BNL) in the display area (DPA), so that the color filter layers (CFL1, CFL2, CFL3) disposed thereon can be formed on a flat surface.

[0196] Color filter layers (CLF1, CLF2, CFL3) may be placed on a planarization layer (PNL). Each of the color filter layers (CFL1, CFL2, CFL3) may be placed in the light-emitting region (TA) at the subpixel (SPXn), and a portion of it may extend to the light-blocking region (BA). The color filter layers (CFL1, CFL2, CFL3) may overlap with other color filter layers (CFL1, CFL2, CFL3) or color patterns (CP1, CP2, CP3) in the light-blocking region (BA). The part where the color filter layers (CFL1, CFL2, CFL3) do not overlap with other color filter layers (CFL1, CFL2, CFL3) is a light-transmitting area (TA) where light is emitted, and the part where different color filter layers (CFL1, CFL2, CFL3) overlap or where color patterns (CP1, CP2, CP3) are arranged may be a light-blocking area (BA) where light emission is blocked.

[0197] The color filter layers (CFL1, CFL2, CFL3) may include a first color filter layer (CFL1) disposed in a first subpixel (SPX1), a second color filter layer (CFL2) disposed in a second subpixel (SPX2), and a third color filter layer (CFL3) disposed in a third subpixel (SPX3). The color filter layers (CFL1, CFL2, CFL3) may be arranged in an island-shaped pattern corresponding to a light-transmitting region (TA) or a light-emitting region (EMA). However, they are not limited thereto. The color filter layers (CFL1, CFL2, CFL3) may be arranged across a plurality of light-transmitting regions (TA) or light-emitting regions (EMA) to form a linear pattern.

[0198] The color filter layers (CFL1, CFL2, CFL3) may include a colorant, such as a dye or pigment, that absorbs light of a wavelength other than that of a specific wavelength. The color filter layers (CFL1, CFL2, CFL3) may transmit only a portion of the light incident from the subpixel (SPXn) to the color filter layers (CFL1, CFL2, CFL3). In each subpixel (SPXn) of the display device (10), only the light transmitted by the color filter layers (CFL1, CFL2, CFL3) may be selectively displayed. In an exemplary embodiment, the first color filter layer (CFL1) may be a red color filter layer, the second color filter layer (CFL2) may be a green color filter layer, and the third color filter layer (CFL3) may be a blue color filter layer. Lights emitted from the light-emitting element (ED) can pass through the color control layer (TPL, WCL1, WCL2) and be emitted through the color filter layer (CFL1, CFL2, CFL3).

[0199] Color patterns (CP1, CP2, CP3) may be placed on a flattening layer (PNL) or a color filter layer (CFL1, CFL2, CFL3). Color patterns (CP1, CP2, CP3) may be placed in a light-blocking area (BA) containing the same material as the color filter layer (CFL1, CFL2, CFL3). In the light-blocking area (BA), color patterns (CP1, CP2, CP3) and different color filter layers (CFL1, CFL2, CFL3) are stacked and disposed, and the transmission of light can be blocked in the area where they are stacked.

[0200] The first color pattern (CP1) may be placed in a light-blocking area (BA) containing the same material as the first color filter layer (CFL1). The first color pattern (CP1) may be placed directly on the flattening layer (PNL) in the light-blocking area (BA) and may not be placed in the light-blocking area (BA) adjacent to the first light-emitting area (TA1) of the first subpixel (SPX1). The first color pattern (CP1) may be placed in the area between the second subpixel (SPX2) and the third subpixel (SPX3), or between the second light-emitting area (TA2) and the third light-emitting area (TA3). The first color filter layer (CFL1) may be extended and placed in the light-blocking area (BA) around the first subpixel (SPX1).

[0201] The second color pattern (CP2) may be placed in a light-blocking area (BA) containing the same material as the second color filter layer (CFL2). The second color pattern (CP2) may be placed directly on the first color pattern (CP1) or the first color filter layer (CFL1) on the flattening layer (PNL) of the light-blocking area (BA), and may not be placed in the light-blocking area (BA) adjacent to the second light-emitting area (TA2) of the second subpixel (SPX2). The second color pattern (CP2) may be placed in the area between the third subpixel (SPX3) and the first subpixel (SPX1), or between the third light-emitting area (TA3) and the first light-emitting area (TA1). The second color filter layer (CFL2) may be extended and placed in the light-blocking area (BA) around the second subpixel (SPX2).

[0202] Similarly, the third color pattern (CP3) may be placed in the light-blocking area (BA) and may contain the same material as the third color filter layer (CFL3). The third color pattern (CP3) may be placed directly on the second color pattern (CP2) or the second color filter layer (CFL2) on the flattening layer (PNL) of the light-blocking area (BA), and may not be placed in the light-blocking area (BA) adjacent to the third light-emitting area (TA3) of the third subpixel (SPX3). The third color pattern (CP3) may be placed in the area between the first subpixel (SPX1) and the second subpixel (SPX2), or between the first light-emitting area (TA1) and the second light-emitting area (TA2). The third color filter layer (CFL3) may be extended and placed in the light-blocking area (BA) around the third subpixel (SPX3).

[0203] The display device (10) has a region overlapping with the bank layer (BNL) and the upper bank layer (UBM) that becomes a light-blocking region (BA), and in the light-blocking region (BA), the first color pattern (CP1), the second color pattern (CP2), and the third color pattern (CP3) can each be arranged to overlap with at least one of the color filter layers (CFL1, CFL2, CFL3) that include different color materials. For example, in the region between different subpixels (SPXn), the first color pattern (CP1) can be arranged to overlap with the second color filter layer (CFL2) and the third color filter layer (CFL3), the second color pattern (CP2) can be arranged to overlap with the first color filter layer (CFL1) and the third color filter layer (CFL3), and the third color pattern (CP3) can be arranged to overlap with the first color filter layer (CFL1) and the second color filter layer (CFL2). The light-blocking region (BA) can block the transmission of light by overlapping color patterns (CP1, CP2, CP3) containing different color materials and color filter layers (CFL1, CFL2, CFL3) with each other.

[0204] Multiple color patterns (CP1, CP2, CP3) have a stacked structure with color filter layers (CFL1, CFL2, CFL3), and can prevent color mixing between adjacent regions by using materials containing different colors. Since the color patterns (CP1, CP2, CP3) contain the same material as the color filter layers (CFL1, CFL2, CFL3), external light or reflected light transmitted through the light-blocking region (BA) may have a specific color wavelength band. The eye color sensitivity perceived by the user's eyes varies depending on the color of the light, and in particular, light in the blue wavelength band may be perceived by the user less sensitively than light in the green wavelength band and light in the red wavelength band. The display device (10) has color patterns (CP1, CP2, CP3) placed in a light-blocking area (BA) so that the transmission of light is blocked, and at the same time, the user can perceive reflected light relatively less sensitively, and can reduce reflected light caused by external light by absorbing some of the light entering from outside the display device (10).

[0205] An overcoat layer (OC) may be placed on color filter layers (CFL1, CFL2, CFL3) and color patterns (CP1, CP2, CP3). The overcoat layer (OC) is placed across the entire front surface of the display area (DPA), and a portion may also be placed in the non-display area (NDA). The overcoat layer (OC) may include an organic insulating material to protect the components placed in the display area (DPA) from the outside.

[0206] A display device (10) according to one embodiment includes a color control layer (TPL, WCL1, WCL2) and a color filter layer (CFL1, CFL2, CFL3) disposed above light-emitting elements (ED), so that even if light-emitting elements (ED) of the same type are disposed for each subpixel (SPXn), different colors of light can be displayed.

[0207] For example, a light-emitting element (ED) placed in a first subpixel (SPX1) emits blue light of a third color, and said light can pass through a thermal control layer (HCL) and be incident on a first wavelength conversion layer (WCL1). The resin layer (PRS) of the thermal control layer (HCL) and the first base resin (BRS1) of the first wavelength conversion layer (WCL1) are made of a transparent material, and some of said light can pass through the resin layer (PRS) and the first base resin (BRS1) and be incident on a first capping layer (CPL1) placed above them. However, at least some of said light is incident on a scatterer (SCP) and a first wavelength conversion material (WCP1) placed within the first base resin (BRS1), and said light can be scattered and its wavelength converted to red light and be incident on the first capping layer (CPL1). Lights incident on the first capping layer (CPL1) pass through the low-refractive index layer (LRL), the second capping layer (CPL2), and the flattening layer (PNL) and are incident on the first color filter layer (CFL1), and the first color filter layer (CFL1) can block the transmission of other lights except red light. Accordingly, red light can be emitted from the first subpixel (SPX1).

[0208] Similarly, light emitted from a light-emitting element (ED) placed in a second subpixel (SPX2) can pass through a thermal control layer (HCL), a second wavelength conversion layer (WCL2), a first capping layer (CPL1), a low-refractive index layer (LRL), a second capping layer (CPL2), a flattening layer (PNL), and a second color filter layer (CFL2) and be emitted as green light.

[0209] The light-emitting element (ED) placed in the third subpixel (SPX3) emits third-color blue light and can pass through the thermal control layer (HCL) and be incident on the light-transmitting layer (TPL). The third base resin (BRS3) of the light-transmitting layer (TPL) is made of a transparent material, and some of the light can pass through the resin layer (PRS) and the third base resin (BRS3) and be incident on the first capping layer (CPL1) placed above them. The light incident on the first capping layer (CPL1) passes through the low-refractive index layer (LRL), the second capping layer (CPL2), and the flattening layer (PNL) and is incident on the third color filter layer (CFL3), and the third color filter layer (CFL3) can block the transmission of light other than blue light. Accordingly, blue light can be emitted from the third subpixel (SPX3).

[0210] A display device (10) according to one embodiment includes a heat control layer (HCL) disposed on a light-emitting element (ED), so as to be able to effectively control heat emitted from the light-emitting element (ED). The display device (10) can minimize degradation caused by heat emitted from the light-emitting element (ED) and has the effect of improving lifespan.

[0211] FIG. 13 is a schematic diagram of a light-emitting element according to one embodiment.

[0212] Referring to FIG. 13, the light-emitting element (ED) may be a light-emitting diode, and specifically, the light-emitting element (ED) may be an inorganic light-emitting diode made of inorganic material having a size in the nanometer to micrometer range. The light-emitting element (ED) may be aligned between two electrodes that form polarity when an electric field is formed in a specific direction between the two electrodes facing each other.

[0213] A light-emitting element (ED) according to one embodiment may have a shape that extends in one direction. The light-emitting element (ED) may have a shape such as a cylinder, a rod, a wire, or a tube. However, the shape of the light-emitting element (ED) is not limited thereto, and the light-emitting element (ED) may have various shapes, such as a polygonal prism shape like a cube, a rectangular prism, or a hexagonal prism, or a shape that extends in one direction but has a partially inclined outer surface.

[0214] The light-emitting element (ED) may include a semiconductor layer doped with any conductivity type (e.g., p-type or n-type) dopant. The semiconductor layer may emit light of a specific wavelength range when an electrical signal applied from an external power source is transmitted. The light-emitting element (ED) may include a first semiconductor layer (31), a second semiconductor layer (32), a light-emitting layer (36), an electrode layer (37), and an insulating film (38).

[0215] The first semiconductor layer (31) may be an n-type semiconductor. The first semiconductor layer (31) is Al x Ga y In 1-x-y It may include a semiconductor material having the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer (31) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant doped in the first semiconductor layer (31) may be Si, Ge, Sn, Se, etc.

[0216] The second semiconductor layer (32) is disposed on the first semiconductor layer (31) with the light-emitting layer (36) in between. The second semiconductor layer (32) may be a p-type semiconductor, and the second semiconductor layer (32) is Al x Ga y In 1-x-yIt may include a semiconductor material having the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer (32) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant doped in the second semiconductor layer (32) may be Mg, Zn, Ca, Ba, etc.

[0217] Meanwhile, the drawing shows the first semiconductor layer (31) and the second semiconductor layer (32) as being composed of a single layer, but is not limited thereto. Depending on the material of the light-emitting layer (36), the first semiconductor layer (31) and the second semiconductor layer (32) may further include a greater number of layers, such as a clad layer or a TSBR (Tensile strain barrier reducing) layer. For example, the light-emitting device (ED) may further include other semiconductor layers disposed between the first semiconductor layer (31) and the light-emitting layer (36), or between the second semiconductor layer (32) and the light-emitting layer (36). The semiconductor layer disposed between the first semiconductor layer (31) and the light-emitting layer (36) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, InN and SLs doped with an n-type dopant, and the semiconductor layer disposed between the second semiconductor layer (32) and the light-emitting layer (36) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN and InN doped with a p-type dopant.

[0218] The light-emitting layer (36) is disposed between the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include a material having a single or multiple quantum well structure. If the light-emitting layer (36) includes a material having a multiple quantum well structure, it may have a structure in which a quantum layer and a well layer are alternately stacked in multiple layers. The light-emitting layer (36) can emit light by the coupling of electron-hole pairs according to an electric signal applied through the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include materials such as AlGaN, AlGaInN, InGaN, etc. In particular, if the light-emitting layer (36) has a structure in which quantum layers and well layers are alternately stacked in a multiple quantum well structure, the quantum layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN or AlInN.

[0219] The light-emitting layer (36) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, and may include different group 3 to group 5 semiconductor materials depending on the wavelength range of the light emitted. The light emitted by the light-emitting layer (36) is not limited to light in the blue wavelength range, and may emit light in the red or green wavelength range depending on the case.

[0220] The electrode layer (37) may be an ohmic connection electrode. However, it is not limited thereto and may be a Schottky connection electrode. The light-emitting element (ED) may include at least one electrode layer (37). The light-emitting element (ED) may include one or more electrode layers (37), but is not limited thereto and the electrode layer (37) may be omitted.

[0221] The electrode layer (37) can reduce the resistance between the light-emitting element (ED) and the electrode or connecting electrode when the light-emitting element (ED) in the display device (10) is electrically connected to the electrode or connecting electrode. The electrode layer (37) may include a conductive metal. For example, the electrode layer (37) may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

[0222] The insulating film (38) is arranged to surround the outer surface of the plurality of semiconductor layers and electrode layers described above. For example, the insulating film (38) may be arranged to surround the outer surface of at least the light-emitting layer (36), but may be formed so that both ends in the longitudinal direction of the light-emitting element (ED) are exposed. Additionally, the insulating film (38) may be formed with a rounded upper surface in cross-section in an area adjacent to at least one end of the light-emitting element (ED).

[0223] The insulating film (38) is made of materials having insulating properties, for example, silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO₂ x It may include at least one of ). In the drawings, the insulating film (38) is illustrated as being formed as a single layer, but is not limited thereto, and in some embodiments, the insulating film (38) may be formed as a multilayer structure in which a plurality of layers are stacked.

[0224] The insulating film (38) can perform the function of protecting the semiconductor layers and electrode layers of the light-emitting element (ED). The insulating film (38) can prevent an electrical short circuit that may occur in the light-emitting layer (36) when in direct contact with the electrode through which an electrical signal is transmitted to the light-emitting element (ED). In addition, the insulating film (38) can prevent a decrease in the light-emitting efficiency of the light-emitting element (ED).

[0225] Additionally, the outer surface of the insulating film (38) may be surface-treated. The light-emitting element (ED) may be sprayed onto the electrode and aligned in a dispersed state within a predetermined ink. Here, in order for the light-emitting element (ED) to remain dispersed without aggregating with other adjacent light-emitting elements (ED) within the ink, the surface of the insulating film (38) may be treated to be hydrophobic or hydrophilic.

[0226] Hereinafter, other embodiments of the display device (10) will be described with reference to other drawings.

[0227] FIG. 14 is a cross-sectional view showing a wavelength conversion layer and a thermal control layer of a subpixel of a display device according to another embodiment.

[0228] Referring to FIG. 14, a display device (10_1) according to one embodiment may further include a scatterer (SCP) in the thermal control layer (HCL_1). Even if the thermal control layer (HCL_1) is placed between the light-emitting element (ED) and the color control layer (TPL, WCL1, WCL2), the thermal control layer (HCL_1) may include a scatterer (SCP) to minimize light emission loss from the light-emitting element (ED).

[0229] As described above, the thermal control layer (HCL_1) is structurally similar to the color control layer (TPL, WCL1, WCL2) by including a resin layer (PRS) and phase transition particles (PCM) dispersed therein. Considering this, the thermal control layer (HCL_1) may further include a scatterer (SCP) that scatters light emitted from the light-emitting element (ED). The thermal control layer (HCL_1) containing the scatterer (SCP) can disperse light emitted from the light-emitting element (ED) and incident on the color control layer (TPL, WCL1, WCL2), and can provide the light emitted from the light-emitting element (ED) to the color control layer (TPL, WCL1, WCL2) with uniform brightness.

[0230] FIG. 15 is a cross-sectional view showing color control layers and heat control layers placed in one pixel according to another embodiment.

[0231] Referring to FIG. 15, in a display device (10_2) according to one embodiment, the thickness of the thermal control layer (HCL_2) may be increased. The upper surface of the thermal control layer (HCL_2) may be positioned higher than the upper surface of the bank layer (BNL), the second insulating layer (PAS2), and the third insulating layer (PAS3). A portion of the thermal control layer (HCL_2) may be placed in an area surrounded by the upper bank layer (UBM), and a portion of its sides may be in contact with the upper bank layer (UBM). The upper surface of the thermal control layer (HCL_2) may rise up to the upper bank layer (UBM).

[0232] In the manufacturing process of the display device (10_2), the thermal control layer (HCL_2) can be formed by an inkjet printing process. As in the embodiments described above, if the thermal control layer (HCL) is printed before the upper bank layer (UBM) is formed, the upper surface of the thermal control layer (HCL) may have the same height as the upper surface of the bank layer (BNL) and the second insulating layer (PAS2) and the third insulating layer (PAS3). On the other hand, as in the present embodiment, if the thermal control layer (HCL_2) is printed after the upper bank layer (UBM) is formed, the upper surface of the thermal control layer (HCL_2) may be located higher than the upper surface of the bank layer (BNL) and the second insulating layer (PAS2) and the third insulating layer (PAS3). The color control layer (TPL, WCL1, WCL2) can be placed directly on the heat control layer (HCL_2) within the area surrounded by the upper bank layer (UBM). However, as described above, the thickness of the heat control layer (HCL_2) may be smaller than the thickness of the color control layer (TPL, WCL1, WCL2).

[0233] FIG. 16 is a cross-sectional view showing color control layers and heat control layers placed in one pixel according to another embodiment.

[0234] Referring to FIG. 16, a display device (10_3) according to one embodiment may have a thermal control layer (HCL_3) disposed across a plurality of subpixels (SPXn). The thermal control layer (HCL_3) may be disposed across a plurality of subpixels (SPXn) beyond the bank layer (BNL) in addition to the area surrounded by the bank layer (BNL). A portion of the thermal control layer (HCL_3) may be disposed on the bank layer (BNL), and an upper bank layer (UBM) and color control layers (TPL, WCL1, WCL2) may each be disposed on the thermal control layer (HCL_3).

[0235] Unlike the embodiment of FIG. 15, if the thermal control layer (HCL_3) is printed and its thickness increases before the formation of the upper bank layer (UBM), the thermal control layer (HCL_3) may be formed to cover the bank layers (BNL). The thermal control layer (HCL_3) may include a resin layer (PRS) to compensate for the lower step, and the upper bank layer (UBM) and the color control layer (TPL, WCL1, WCL2) may each be placed directly on the thermal control layer (HCL_3). Unlike the above-described embodiment, the upper bank layer (UBM) may overlap with the bank layer (BNL) but its lower surface may be in contact with the thermal control layer (HCL_3).

[0236] FIG. 17 is a cross-sectional view showing a wavelength conversion layer and a thermal control layer of a subpixel of a display device according to another embodiment.

[0237] Referring to FIG. 17, in a display device (10_4) according to one embodiment, the heat control layer (HCL) is omitted and the color control layer (TPL, WCL1, WCL2) may include phase transition particles (PCM_4). The color control layer (TPL, WCL1, WCL2) may include phase transition particles (PCM_4) in addition to wavelength conversion materials (WCP1, WCP2) or scatterers (SCP) dispersed in base resins (BRS1, BRS2, ​​BRS3). The color control layer (TPL, WCL1, WCL2) may further include phase transition particles (PCM_4) to control heat generated from the light-emitting element (ED) while converting light emitted from the light-emitting element (ED).

[0238] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0239] 10: Display device SUB: Substrate RME: Electrode VIA: Via layer PAS1, PAS2, PAS3: First to third insulating layers BP1, BP2: Bulkhead BNL: Bank Floor ED: Light-emitting element CNE: Connecting electrode HCL: Thermal control layer PCM: Phase transition particles

Claims

Claim 1 A display device comprising: a plurality of subpixels including a first electrode and a second electrode spaced apart from each other, and light-emitting elements disposed on the first electrode and the second electrode and electrically connected to the first electrode and the second electrode; a bank layer surrounding an area where the light-emitting elements of the subpixels are disposed; a thermal control layer disposed to cover the light-emitting elements and disposed in an area surrounded by the bank layer; an upper bank layer disposed on the bank layer; and a color control layer disposed on the thermal control layer and disposed in an area surrounded by the upper bank layer, wherein the thermal control layer comprises a core portion including a resin layer and a phase transition material and a first shell surrounding the core portion and phase transition particles dispersed in the resin layer, wherein the core portion comprises at least one of dodecane, docosane, and an aluminum-silicon alloy, and the first shell comprises at least one of polystyrene, polymethyl methacrylate, aluminum oxide, and polymethyl methacrylate-silica. Claim 2 delete Claim 3 In claim 1, the phase transition particle further comprises a second shell containing a thermally conductive material surrounding the core portion, and the first shell is a display device surrounding the second shell. Claim 4 In claim 3, the second shell comprises at least one of graphite, carbon black, and a conductive polymer. Claim 5 A display device according to claim 1, wherein the diameter of the phase transition particles is 1 μm or less. Claim 6 A display device according to claim 1, wherein the resin layer of the heat control layer comprises any one of an epoxy resin, an acrylic resin, a cardo resin, and an imide resin. Claim 7 In claim 1, the heat control layer further comprises a scatterer. Claim 8 A display device according to claim 1, wherein the thickness of the color control layer is greater than the thickness of the heat control layer. Claim 9 A display device according to claim 8, wherein the thickness of the color control layer has a range of 8㎛ to 10㎛ and the thickness of the heat control layer has a value of approximately 2㎛. Claim 10 A display device according to claim 1, comprising a first insulating layer disposed on the first electrode and the second electrode, a second insulating layer disposed on the light-emitting elements and the bank layer, and a third insulating layer disposed on the second insulating layer and the bank layer, wherein the bank layer is disposed on the first insulating layer. Claim 11 In claim 10, a display device in which the height of the upper surface of the heat control layer is equal to or lower than the height of the upper surface of the third insulating layer disposed on the bank layer. Claim 12 A display device according to claim 10, wherein the height of the upper surface of the heat control layer is higher than the height of the upper surface of the third insulating layer disposed on the bank layer. Claim 13 In claim 12, the heat control layer is a display device in which a portion of the side is in contact with the upper bank layer. Claim 14 A display device according to claim 1, wherein a portion of the heat control layer is disposed on the bank layer, and the color control layer and the upper bank layer are disposed on the heat control layer. Claim 15 In claim 1, the color control layer comprises a first wavelength conversion layer disposed in a first subpixel and including a first wavelength conversion particle, a second wavelength conversion layer disposed in a second subpixel and including a second wavelength conversion particle, and a light-transmitting layer disposed in a third subpixel and including a scatterer, and the heat control layer comprises a display device disposed between the first wavelength conversion layer, the second wavelength conversion layer, and the light-transmitting layer and the light-emitting element. Claim 16 A display device according to claim 1, comprising a first connecting electrode disposed on the first electrode and in contact with the light-emitting element, and a second connecting electrode disposed on the second electrode and in contact with the light-emitting element. Claim 17 A display device comprising: a plurality of subpixels including a first electrode and a second electrode spaced apart from each other, and light-emitting elements disposed on the first electrode and the second electrode and electrically connected to the first electrode and the second electrode; a bank layer surrounding an area where the light-emitting elements of the subpixels are disposed; an upper bank layer disposed on the bank layer; and a color control layer disposed on the light-emitting element and disposed in an area surrounded by the upper bank layer, wherein the color control layer comprises a first wavelength conversion layer disposed on the first subpixel and comprising a first wavelength conversion particle, a second wavelength conversion layer disposed on the second subpixel and comprising a second wavelength conversion particle, and a light-transmitting layer disposed on the third subpixel and comprising a scatterer, wherein the first wavelength conversion layer, the second wavelength conversion layer, and the light-transmitting layer comprise a phase transition particle comprising a core portion comprising a phase transition material and a first shell surrounding the core portion. Claim 18 A display device according to claim 17, wherein the core portion comprises at least one of dodecane, docosane, and aluminum-silicon alloy, and the first shell comprises at least one of polystyrene, polymethyl methacrylate, aluminum oxide, and polymethyl methacrylate-silica. Claim 19 In claim 18, the phase transition particle further comprises a second shell containing a thermally conductive material surrounding the core portion, and the first shell is a display device surrounding the second shell. Claim 20 A display device according to claim 17, wherein the diameter of the phase transition particles is 1 μm or less.

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