Multiplexer and serializer including the same

Abstract

A multiplexer and a serializer including the same are disclosed. A multiplexer that selects any one of first to fourth data signals in response to first to fourth pulses that correspond to each of the first to fourth data signals and are toggled sequentially comprises: a NAND gate that receives the first data signal, a fourth complementary data signal which is a complementary signal of the fourth data signal, and the first pulse, and outputs a first gate signal; and a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse which is complementary to the first pulse, and outputs a second gate signal, wherein the first data corresponds to the rising edge of the first pulse and the fourth complementary data corresponds to the rising edge of the fourth pulse.

Description

Technology Field

[0001] The present disclosure relates to a multiplexer included in a high-speed serial communication system and a serializer including the same. Background Technology

[0002] In high-speed serial link systems, bits of data can be transmitted serially through a channel. When signals are transmitted through channels such as coaxial cables or PCB traces, the channel bandwidth may be limited due to channel load, skin effects, and dielectric losses, and high-frequency components of the signal at the receiver may be attenuated. In particular, the reliability of the high-speed serial link system can be degraded due to intersymbol interference (ISI), where one symbol interferes with subsequent symbols.

[0003] For example, ISI can increase at the rising or falling edge, which is one of the high-frequency components and where the voltage level of the signal changes rapidly. Consequently, the signal output from the transmitter may be distorted, or the time it takes for the signal to be transmitted to the receiver may vary depending on the frequency. The problem to be solved

[0004] The purpose of the present disclosure is to provide a multiplexer and a serializer comprising the same. means of solving the problem

[0005] A multiplexer that selects any one of first to fourth data signals according to some embodiments of the present disclosure in response to first to fourth pulses that correspond to each of the first to fourth data signals and are sequentially toggled comprises: a NAND gate that receives the first data signal, a fourth complementary data signal which is a complementary signal of the fourth data signal, and the first pulse, and outputs a first gate signal; a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse which is complementary to the first pulse, and outputs a second gate signal; and a first transistor comprising a first terminal to which a first power supply voltage is applied, a gate that receives the first gate signal, and a second terminal connected to the output terminal of the multiplexer. and includes a first terminal connected to the output terminal of the multiplexer, a gate receiving the second gate signal, and a second transistor to which a ground voltage is applied, wherein the first data corresponds to the rising edge of the first pulse, and the fourth complementary data corresponds to the rising edge of the fourth pulse.

[0006] A serializer according to some embodiments of the present disclosure comprises: a clock multiplexer that generates first to fourth pulses that are sequentially toggled based on first to fourth clocks, each having a first phase difference; and a multiplexer that outputs an output signal based on first to fourth data signals corresponding to each of the first to fourth pulses in response to the first to fourth pulses and first to fourth complementary pulses that are complementary to each of the first to fourth pulses, wherein the multiplexer comprises: the first data signal, the fourth complementary data signal that is complementary to the fourth data signal, and the first pulse, and a NAND gate that receives the first pulse and outputs a first gate signal; and includes a NOR gate that receives the first data signal, the fourth complementary data signal, and the first complementary pulse that is complementary to the first pulse, and outputs a second gate signal, and the level of the output signal may be based on the first gate signal and the second gate signal.

[0007] A serializer according to some embodiments of the present disclosure comprises: a clock multiplexer that generates first to fourth pulses that are sequentially toggled based on first to fourth clocks, each having a first phase difference; and a multiplexer that outputs an output signal based on first to fourth data signals corresponding to each of the first to fourth pulses in response to the first to fourth pulses and first to fourth complementary pulses that are complementary to each of the first to fourth pulses, wherein the multiplexer comprises: a NAND gate that receives the first data signal, a fourth complementary data signal which is a complementary signal of the fourth data signal, and the first pulse, and outputs a first gate signal; and a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse, and outputs a second gate signal. A first transistor comprising a first terminal to which a first power supply voltage is applied, a gate receiving the first gate signal, and a second terminal connected to the output terminal of the multiplexer; and a second transistor comprising a first terminal connected to the output terminal of the multiplexer, a gate receiving the second gate signal, and a ground voltage to which a ground voltage is applied, wherein the first data signal corresponds to the rising edge of the first pulse, and the fourth complementary data signal may correspond to the rising edge of the fourth pulse. Effects of the invention

[0008] A multiplexer according to some embodiments of the present disclosure can pre-adjust the voltage level of a node electrically connected to the output terminal of the multiplexer based not only on first data corresponding to a first pulse but also on second data corresponding to a pulse prior to the first pulse. Accordingly, the transition speed of the output signal can be improved and interference between signals can be reduced. Brief explanation of the drawing

[0009] FIG. 1 illustrates a block diagram of a communication system according to some embodiments of the present disclosure. FIG. 2 illustrates a block diagram of a serializer according to some embodiments of the present disclosure. FIG. 3 illustrates a block diagram of a serializer in more detail according to some embodiments of the present disclosure. FIG. 4 illustrates a timing diagram of clocks and pulses used in a serializer according to some embodiments of the present disclosure. FIG. 5 illustrates a circuit diagram of a NAND gate of a multiplexer according to some embodiments of the present disclosure. FIGS. 6a and 6b illustrate the operation of a NAND gate of a multiplexer according to some embodiments of the present disclosure. FIG. 7 illustrates a circuit diagram of a NOR gate of a multiplexer according to some embodiments of the present disclosure. FIGS. 8a and 8b illustrate the operation of a NOR gate of a multiplexer according to some embodiments of the present disclosure. FIG. 9 illustrates a block diagram of a serializer according to some embodiments of the present disclosure. FIG. 10 illustrates a block diagram of a system according to some embodiments of the present disclosure. FIG. 11 illustrates a block diagram of a memory according to some embodiments of the present disclosure. Specific details for implementing the invention

[0010] In the following, embodiments of the present disclosure will be described clearly and in detail so that a person skilled in the art can easily practice the present disclosure.

[0011] Hereinafter, some embodiments of the present disclosure will be described in more detail with reference to the attached drawings. In order to facilitate an overall understanding of the present disclosure, similar reference numerals are used for similar components in the drawings, and redundant descriptions of similar components are omitted.

[0012] FIG. 1 illustrates a block diagram of a communication system (10) according to some embodiments of the present disclosure. The communication system (10) may include a transmitter (11) and a receiver (12) that communicate with each other through a channel (13). In some embodiments, the communication system (10) may be referred to as a transceiver, a data transmission and reception circuit, or a high-speed data transmission system, etc.

[0013] The transmitter (11) can transmit a data-based transmission signal to the receiver (12) through the channel (13). The channel (13), the pins of the integrated circuit in which the transmitter (11) is implemented, the pins of the integrated circuit in which the receiver (12) is implemented, etc., can increase the cost required to implement the communication system (10). To reduce the cost of implementing the aforementioned elements, the transmitter (11) can transmit a signal containing serialized bits of data. The transmitter (11) may include a serializer (100) for serializing data.

[0014] A channel (13) may be a path that physically or electrically connects a transmitter (11) and a receiver (12). For example, a channel (13) may be implemented using a trace on a printed circuit board (PCB) or a coaxial cable. A channel (13) may degrade high-frequency components of data transmitted through the channel (13) due to the skin effect, dielectric loss, etc. When a signal is transmitted through the channel (13), channel loss may occur at the receiver (12). Impedance discontinuities (mismatches) may occur in the channel (13) due to connectors and other physical interfaces between boards and cables. Impedance discontinuities in the channel (13) may appear as notches in the frequency response of the channel (13) and may cause reflection noise at the receiver (12). Each bit of data passing through the channel (13) may interfere with the next bit(s) due to channel loss or bandwidth limitation, and the bit error rate (BER) may increase as neighboring symbols overlap, i.e., intersymbol interference (ISI).

[0015] A receiver (12) can receive a signal transmitted from a transmitter (11) through a channel (13). The receiver (12) may include a deserializer (14) for parallelizing the transmitted signal. The receiver (12) can parallelize the transmitted signal using the deserializer (14).

[0016] FIG. 2 illustrates a block diagram of a serializer (100) according to some embodiments of the present disclosure. Referring to FIG. 1 and FIG. 2, the serializer (100) may include a multiplexer (110) and a clock multiplexer (120). The multiplexer (110) may receive data (D0–D3), pulses (PL0–PL3), and complementary pulses (PL0B–PL3B). The multiplexer (110) may output a data signal (DQ) based on the pulses (PL0–PL3), complementary pulses (PL0B–PL3B), and data (D0–D3). For example, the data signal (DQ) output from the multiplexer (110) may correspond to a signal obtained by sequentially serializing the data (D0–D3).

[0017] The clock multiplexer (120) can receive clocks (WCK0, WCK90, WCK180, WCK270). The clocks (WCK0, WCK90, WCK180, WCK270) can be generated by a processor (not shown) or a signal generator of the transmitter (11) for use within the clock multiplexer (120). The clock multiplexer (120) can generate pulses (PL0–PL3) and complementary pulses (PL0B–PL3B) based on the clocks (WCK0, WCK90, WCK180, WCK270). Each of the pulses (PL0–PL3) and complementary pulses (PL0B–PL3B) can be complementary to one another.

[0018] FIG. 3 illustrates a block diagram of a serializer (100) in more detail according to some embodiments of the present disclosure. Referring to FIG. 2 and FIG. 3, the serializer (100) may include a multiplexer (110) and a clock multiplexer (120), and the multiplexer (110) may include blocks (111 to 114) corresponding to data (D0 to D3), respectively. For example, block (111) may correspond to data (D0). Blocks (111 to 114) may receive pulses (PL0 to PL3), complementary pulses (PL0B to PL3B), data (D0 to D3; or data signals), and complementary data (for example, complementary data (D3B) in block (111)), respectively, and may output a data signal (DQ). Blocks (111~114) can each sample data (D0~D3) in response to pulses (PL0~PL3) and complementary pulses (PL0B~PL3B), respectively.

[0019] Each of the blocks (111–114) can receive data that is complementary to the data sampled from the previous pulse of the corresponding pulse (or data that is the subject of sampling in response to the previous pulse). For example, block (111) can receive complementary data (D3B) that is complementary to the data (D3) sampled from the previous pulse (PL3) of the corresponding pulse (PL0) (or data that is the subject of sampling in response to the pulse (PL3)) in the order of pulse numbers. Each of the blocks (111–113) can equalize the edges of the data signal (DQ) output from the multiplexer (110) based on the received complementary data. For example, each of the blocks (111–113) can improve the transition speed of the data signal (DQ) by pre-pull-down or pull-up the gating signals (SG1, SG2) based on the received complementary data.

[0020] A clock multiplexer (120) receives clocks (WCK0, WCK90, WCK270, WCK180) and can generate pulses (PL0–PL3) and complementary pulses (PL0B–PL3B) based on the clocks (WCK0, WCK90, WCK270, WCK180). The clock multiplexer (120) can generate pulses (PL0) and complementary pulses (PL0B) using a clock (WCK0) as a reference clock. For example, the clock multiplexer (120) may include NAND gates (121, 124) and inverters (122, 123, 124) for generating pulses (PL0) and complementary pulses (PL0B).

[0021] The NAND gate (121) may include input terminals that receive clocks (WCK0, WCK270) and an output terminal connected to the input terminal of the inverter (122). The inverter (122) may include an input terminal connected to the output terminal of the NAND gate (121) and an output terminal that outputs a pulse (PL0).

[0022] The inverter (123) may include an input terminal that receives a clock (WCK90) and an output terminal connected to a NAND gate (125). The inverter (124) may include an input terminal that receives a clock (WCK180) and an output terminal connected to a NAND gate (125). The NAND gate (125) may include input terminals connected to the output terminals of the inverters (123, 124), respectively, and an output terminal that outputs a complementary pulse (PL0B).

[0023] In the embodiment illustrated in FIG. 3, the clock multiplexer (120) includes components for generating a pulse (PL0) and a complementary pulse (PL0B), but the components of the clock multiplexer (120) are not limited thereto. For example, the clock multiplexer (120) may further include components for generating pulses (PL1 to PL3) and complementary pulses (PL1B to PL3B). The components for generating pulses (PL1 to PL3) may each generate pulses (PL1, PL2, PL3) and complementary pulses (PL1B, PL2B, PL3B) using clocks (WCK90, WCK180, WCK270) as reference clocks.

[0024] For example, the clock multiplexer (120) may include a NAND gate and an inverter for generating a pulse (PL1). The NAND gate for generating the pulse (PL1) may be implemented similarly to the NAND gate (121), receiving clocks (WCK90, WCK0) instead of clocks (WCK0, WCK270). The inverter for generating the pulse (PL1) may be implemented similarly to the inverter (122), including an input terminal connected to the NAND gate for generating the pulse (PL1). The clock multiplexer (120) may include a first inverter, a second inverter, and a NAND gate for generating a complementary pulse (PL1B). The first inverter for generating the complementary pulse (PL1B) may be implemented similarly to the inverter (123), receiving a clock (WCK180) instead of a clock (WCK90). A second inverter for generating a complementary pulse (PL1B) can be implemented similarly to an inverter (124) while receiving a clock (WCK270) instead of a clock (WCK180). A NAND gate for generating a complementary pulse (PL1B) can be implemented similarly to a NAND gate (125) while including an input terminal connected to a first inverter and a second inverter for generating a complementary pulse (PL1B).

[0025] In a similar manner, the clock multiplexer (120) may include a NAND gate and an inverter for generating a pulse (PL2). For example, the NAND gate for generating the pulse (PL2) may be implemented similarly to the NAND gate (121), receiving clocks (WCK180, WCK90) instead of clocks (WCK0, WCK270). The inverter for generating the pulse (PL2) may be implemented similarly to the inverter (122), including an input terminal connected to the NAND gate for generating the pulse (PL2). The clock multiplexer (120) may include a first inverter, a second inverter, and a NAND gate for generating a complementary pulse (PL2B). The first inverter for generating the complementary pulse (PL2B) may be implemented similarly to the inverter (123), receiving a clock (WCK270) instead of a clock (WCK90). A second inverter for generating a complementary pulse (PL2B) can be implemented similarly to an inverter (124) while receiving a clock (WCK0) instead of a clock (WCK180). A NAND gate for generating a complementary pulse (PL2B) can be implemented similarly to a NAND gate (125) while including an input terminal connected to a first inverter and a second inverter for generating a complementary pulse (PL2B).

[0026] In a similar manner, the clock multiplexer (120) may include a NAND gate and an inverter for generating a pulse (PL3). For example, the NAND gate for generating the pulse (PL3) may be implemented similarly to the NAND gate (121), receiving clocks (WCK270, WCK180) instead of clocks (WCK0, WCK270). The inverter for generating the pulse (PL3) may be implemented similarly to the inverter (122), including an input terminal connected to the NAND gate for generating the pulse (PL3). The clock multiplexer (120) may include a first inverter, a second inverter, and a NAND gate for generating a complementary pulse (PL3B). The first inverter for generating the complementary pulse (PL3B) may be implemented similarly to the inverter (123), receiving a clock (WCK0) instead of a clock (WCK90). A second inverter for generating a complementary pulse (PL3B) can be implemented similarly to an inverter (124) while receiving a clock (WCK90) instead of a clock (WCK180). A NAND gate for generating a complementary pulse (PL3B) can be implemented similarly to a NAND gate (125) while including an input terminal connected to a first inverter and a second inverter for generating a complementary pulse (PL3B).

[0027] Block (111) may include a NAND gate (210), a NOR gate (220), and transistors (M1, M2). The NAND gate (210) may include input terminals that receive data (D0) and a pulse (PL0), respectively, and an output terminal connected to the gate of transistor (M1). The NAND gate (210) may further receive complementary data (D3B). The complementary data (D3B) may be complementary to the data (D3B) sampled (or sampled) in response to a previous pulse (PL3) that toggles immediately before the pulse (PL0). The NAND gate (210) may output a gate signal (SG1) to transistor (M1) based on the data (D0), pulse (PL0), and complementary data (D3B).

[0028] The NOR gate (220) may include input terminals that receive data (D0) and a complementary pulse (PL0B), respectively, and an output terminal connected to the gate of the transistor (M2). The NOR gate (220) may further receive complementary data (D3B). Based on the data (D0), the complementary pulse (PL0B), and the complementary data (D3B), the NOR gate (220) may output a gate signal (SG2) to the transistor (M2).

[0029] The transistor (M1) may include a first terminal to which a voltage (VDD) is applied, a gate connected to the output terminal of a NAND gate (210), and a second terminal connected to the first terminal of the transistor (M2). The transistor (M1) may be turned on or turned off in response to a gate signal (SG1). The transistor (M2) may include a second terminal connected to the second terminal of the transistor (M1), a gate connected to the output terminal of a NOR gate (220), and a second terminal to which a ground voltage is applied. The transistor (M2) may be turned on or turned off in response to a gate signal (SG2). The second terminal of the transistor (M1) and the first terminal of the transistor (M2) may be connected to the output terminal of a multiplexer (110) to which a data signal (DQ) is output.

[0030] Blocks (112, 113, 114) can be implemented similarly to block (111) and can operate similarly. Blocks (112, 113, 114) can each be implemented corresponding to the corresponding data. For example, a block (112) corresponding to data (D1) may include a NAND gate that receives data (D1), pulse (PL1), and complementary data (D0B) instead of data (D0), pulse (PL0), and complementary data (D3B) and is implemented similarly to a NAND gate (210), and a NOR gate that receives data (D1), complementary pulse (PL1B), and complementary data (D0B) instead of data (D0), complementary pulse (PL0), and complementary data (D3B) and is implemented similarly to a NOR gate (220). In a similar manner, block (113) can be implemented to correspond to data (D2), pulse (PL2), and complementary data (D1B), and block (114) can be implemented to correspond to data (D3), pulse (PL3), and complementary data (D2B).

[0031] FIG. 4 illustrates a timing diagram of clocks (WCK0, WCK90, WCK180, WCK270) and pulses (PL0, PL1, PL2, PL3) used within a serializer (100) according to some embodiments of the present disclosure. Referring to FIGS. 2 through 4, the clocks (WCK0, WCK90, WCK180, WCK270) input to the clock multiplexer (120) may be signals whose phases differ from each other by multiples of 90 degrees. For example, the difference between the phase of clock (WCK0) and the phase of clock (WCK90) may be 90 degrees. The difference between the phase of clock (WCK0) and the phase of clock (WCK180) may be 180 degrees. The difference between the phase of clock (WCK0) and the phase of clock (WCK270) may be 270 degrees.

[0032] Data (D0, D1, D2, D3) can be input to the multiplexer (110) synchronized with the clocks (WCK0, WCK90, WCK180, WCK270), respectively. For example, data (D0) can be input to the multiplexer (110) synchronized with the rising edge of the clock (WCK0) (e.g., time points (tc1, tc5, tc9)). Data (D1) can be input to the multiplexer (110) synchronized with the rising edge of the clock (WCK90) (e.g., time points (tc2, tc6)). Data (D2) can be input to the multiplexer (110) synchronized with the rising edge of the clock (WCK180) (e.g., time points (tc3, tc7)). Data (D3) can be input to the multiplexer (110) synchronized with the rising edge of the clock (WCK270) (e.g., timestc4, tc8).

[0033] Each of the pulses (PL0, PL1, PL2, PL3) can be toggled in response to the rising edges of the clocks (WCK0, WCK90, WCK180, WCK270). For example, pulse (PL0) can be toggled in response to the rising edge of the clock (WCK0) (e.g., timestc1, tc5, tc9). Pulse (PL1) can be toggled in response to the rising edge of the clock (WCK90) (e.g., timestc2, tc6)). Pulse (PL2) can be toggled in response to the rising edge of the clock (WCK180) (e.g., timestc3, tc7)). Pulse (PL3) can be toggled in response to the rising edge of the clock (WCK270) (e.g., timestc4, tc8)). The clock multiplexer (120) can provide pulses (PL0, PL1, PL2, PL3) to the multiplexer (110), and the multiplexer (110) on the rising edges of the pulses (PL0, PL1, PL2, PL3). In response, data (D0, D1, D2, D3) can be sampled respectively.

[0034] In the present disclosure, a prior pulse of any pulse may refer to a pulse that is toggled immediately before that pulse in the sequence of pulse numbers. For example, a prior pulse of pulse (PL0) may be pulse (PL3), a prior pulse of pulse (PL1) may be pulse (PL0), a prior pulse of pulse (PL2) may be pulse (PL1), and a prior pulse of pulse (PL3) may be pulse (PL2).

[0035] In the present disclosure, data input prior to a certain data may refer to data input immediately before that data in the order of pulse numbers, or data input prior to a certain data may refer to data input corresponding to the previous pulse of the pulse corresponding to that data. For example, data input to the multiplexer (110) prior to data (D1) input at time point (tc2) may be data (D0) input at time point (tc1). Data input to the multiplexer (110) prior to data (D2) input at time point (tc3) may be data (D1) input at time point (tc2). Data input to the multiplexer (110) prior to data (D3) input at time point (tc4) may be data (D2) input at time point (tc3). Data input to the multiplexer (110) prior to data (D0) input at time point (tc5) may be data (D3) input at time point (tc4).

[0036] FIG. 5 illustrates a circuit diagram of a NAND gate (210) of a multiplexer (110) according to some embodiments of the present disclosure. Referring to FIGS. 2 through 5, the NAND gate (210) included in block (111) may include transistors (MND1, MND2, MND3, MND4) and a circuit (211). The transistors (MND1, MND2) may be implemented as PMOS, and the transistors (MND3, MND4) may be implemented as NMOS.

[0037] A transistor (MND1) may include a first terminal to which a voltage (VDD1) is applied, a gate to which a pulse (PL0) is applied, and a second terminal connected to the gate of a transistor (M1). A transistor (MND2) may include a first terminal to which a voltage (VDD2) is applied, a gate to which data (D0) is applied, and a second terminal connected to the gate of a transistor (M1). A transistor (MND3) may include a first terminal connected to the gate of a transistor (M1), a gate to which a pulse (PL0) is applied, and a second terminal connected to a node (ND1). A transistor (MND4) may include a first terminal connected to a node (ND1), a gate to which data (D0) is applied, and a second terminal to which a ground voltage is applied.

[0038] The circuit (211) may include transistors (MND5, MND6). Transistor (MND5) may include a first terminal to which a voltage (VDD3) is applied, a gate to which data (D0) is applied, and a second terminal connected to a node (ND1). Transistor (MND6) may include a first terminal connected to a node (ND1), a gate to which data (D3B) is applied, and a second terminal to which a ground voltage is applied. Transistor (MND5) may be implemented as a PMOS, and transistor (MND6) may be implemented as an NMOS. When data (D3) is sampled in block (114) in response to a rising edge pulse (PL3) (or when data (D3) is input into block (114), complementary data (D3B) may be input into block (111).

[0039] The circuit (211) can pull down the voltage level of the node (ND1) by a certain level (e.g., ground voltage or a voltage close to it) before the rising edge of the pulse (PL0) by using data (D3) (or data (D3B) which is its complementary data) corresponding to the pulse (PL3) which is the previous pulse of the pulse (PL0). Accordingly, the time required for the level of the gate signal (SG1) to drop below the threshold voltage of the transistor (M1) in response to the subsequently applied rising edge pulse (PL0) and the corresponding data (D0) can be reduced, and thus, the transition speed of the data signal (DQ) can be accelerated. As a result, intersymbol interference (ISI) due to the rising edge of the data input from the serializer (100) can be reduced.

[0040] FIGS. 6a and 6b illustrate the operation of a NAND gate (210) of a multiplexer (110) according to some embodiments of the present disclosure. Referring to FIGS. 2 through 5, FIGS. 6a, and FIGS. 6b, the NAND gate (210) can output a gate signal (SG1) corresponding to a pulse (PL0) and a signal (D0) based on complementary data (i.e., data (D3B)) of data (D3) corresponding to a previous pulse (PL3) of a pulse (PL0).

[0041] In the embodiment illustrated in FIG. 6a, a transition of data input to the serializer (100) may occur at the rising edge of the pulse (PL0). For example, when the data (D3) input corresponding to the rising edge of the previous pulse (PL3) corresponds to logic low, the data (D0) input corresponding to the rising edge of the pulse (PL0) may correspond to logic high.

[0042] In response to the previous pulse (PL3) of pulse (PL0), data (D3B) corresponding to a logic high can be pre-applied ('1') to the gate of transistor (MND6). In response to the data (D3B) corresponding to a logic high, transistor (MND6) can be turned on. In response to transistor (MND6) being turned on, the voltage of node (ND1) can be pulled down. In other words, it can be understood that the NAND gate (210) is partially turned on (or activated) in advance by the previous data (D3).

[0043] Subsequently, a pulse (PL0) corresponding to a logic high (or rising edge) can be applied to transistors (MND1, MND3), and data (D0) corresponding to a logic high can be applied to the gates of transistors (MND2, MND4, MND5) ('1'). Accordingly, transistors (MND1, MND2, MND5) can be turned off, and transistors (MND3, MND4) can be turned on. As a result, the level of the gate signal (SG1) applied to the gate of transistor (M1) can fall faster (e.g., faster than when the NAND gate (210) is not activated) due to the voltage of the node (ND1) that has been pulled down beforehand.

[0044] Due to the data (D3B) applied to the transistor (MND6), the level of the gate signal (SG1) applied to the gate of the transistor (M1) can fall more quickly, and accordingly, the time required for the transistor (M1) to turn on in response to the data (D0) can be reduced. As a result, the transition speed of the data signal (DQ) output from the serializer (100) can be improved. In other words, due to the circuit (211), the transition speed of the signal output from the serializer (100) in response to the transition of the data input to the serializer (100) can be improved. Accordingly, signal interference caused by the rising edge of the input data can be improved.

[0045] In the embodiment illustrated in FIG. 6b, a transition of data input to the serializer (100) may not occur at the rising edge of the pulse (PL0). For example, when the data (D3) input in response to the previous pulse (PL3) corresponds to a logic low, the data (D0) input in response to the pulse (PL0) may correspond to a logic low.

[0046] In response to the previous pulse (PL3) of pulse (PL0), data (D3B) corresponding to a logic high can be pre-applied ('1') to the gate of transistor (MND6). In response to the data (D3B) corresponding to a logic high, transistor (MND6) can be turned on.

[0047] Subsequently, a pulse (PL0) corresponding to a logic high (or a rising edge) can be applied to the transistors (MND1, MND3), and data (D0) corresponding to a logic low can be applied to the gates of the transistors (MND2, MND4, MND5) ('0'). Accordingly, the transistor (MND1) can be turned off, and the transistors (MND2, MND3, MND4, MND5) can be turned on. Due to the turned-on transistor (MND5), the voltage of the node (ND1) can rise to a certain level. As the voltage of the node (ND1) rises, the transistor (MND3) can be turned off, or the level of the current flowing through the transistor (MND3) to the node (ND1) can be lowered, and consequently, the level of the gate signal (SG1) output from the NAND gate (210) can be prevented from falling below the threshold voltage of the transistor (M1). In other words, the malfunction of the NAND gate (210) caused by the complementary data (D3B) is prevented by the transistor (MND5), so that the occurrence of a glitch can be prevented.

[0048] FIG. 7 illustrates a circuit diagram of a NOR gate (220) of a multiplexer (110) according to some embodiments of the present disclosure. Referring to FIGS. 2 through 4 and FIG. 7, the NOR gate (220) included in block (111) may include transistors (MNR1, MNR2, MNR3, MNR4) and a circuit (221). The transistors (MNR1, MNR2) may be implemented as PMOS, and the transistors (MNR3, MNR4) may be implemented as NMOS.

[0049] A transistor (MNR1) may include a first terminal to which a voltage (VDD4) is applied, a gate to which data (D0) is applied, and a second terminal connected to a node (ND2). A transistor (MNR2) may include a first terminal connected to a node (ND2), a gate to which a complementary pulse (PL0B) is applied, and a second terminal connected to the gate of a transistor (M2). A transistor (MNR3) may include a first terminal connected to the gate of a transistor (M2), a gate to which a complementary pulse (PL0B) is applied, and a second terminal to which a ground voltage is applied. A transistor (MNR4) may include a first terminal connected to the gate of a transistor (M2), a gate to which data (D0) is applied, and a second terminal to which a ground voltage is applied.

[0050] The circuit (221) may include transistors (MNR5, MNR6). Transistor (MNR5) may include a first terminal connected to a node (ND2), a gate to which data (D0) is applied, and a second terminal to which a ground voltage is applied. Transistor (MNR6) may include a first terminal to which a voltage (VDD5) is applied, a gate to which complementary data (D3B) is applied, and a second terminal connected to a node (ND2). Transistor (MNR5) may be implemented as an NMOS, and transistor (MNR6) may be implemented as a PMOS. When data (D3) is sampled in block (114) in response to a rising edge pulse (PL3) (or when data (D3) is input into block (114), complementary data (D3B) may be input into block (111).

[0051] The circuit (221) can pull up the voltage level of the node (ND2) to a certain level (e.g., voltage (VDD5) or a voltage approximated thereto) before the falling edge of the pulse (PLB0) (or before the rising edge of the pulse (PL0)) by using data (D3) (or data (D3B) which is the data corresponding to the data preceding the pulse (PL0). Accordingly, the time required for the level of the gate signal (SG2) to rise above the threshold voltage of the transistor (M2) in response to the falling edge of the pulse (PLB0) and the corresponding data (D0) can be reduced, and thus, the transition speed of the data signal (DQ) can be increased. As a result, signal-to-signal interference (ISI) due to the falling edge of the data input from the serializer (100) can be reduced.

[0052] FIGS. 8a and 8b illustrate the operation of a NOR gate (220) of a multiplexer (110) according to some embodiments of the present disclosure. Referring to FIGS. 2 through 4, FIGS. 8, FIGS. 8a, and FIGS. 8b, the NOR gate (220) can output a gate signal (SG2) corresponding to a complementary pulse (PL0B) and a signal (D0) based on complementary data (i.e., data (D3B)) of data (D3) corresponding to a previous pulse (PL3) of pulse (PL0).

[0053] In the embodiment illustrated in FIG. 8a, a transition of data input to the serializer (100) may occur at the falling edge of the complementary pulse (PL0B). For example, when the data (D3) input corresponding to the rising edge of the previous pulse (PL3) corresponds to logic high, the data (D0) input corresponding to the falling edge of the complementary pulse (PL0B) may correspond to logic low.

[0054] In response to the previous complementary pulse (PL3B) of the complementary pulse (PL0B), data (D3B) corresponding to a logic low can be pre-applied ('0') to the gate of the transistor (MNR6). In response to the data (D3B) corresponding to a logic low, the transistor (MNR6) can be turned on. In response to the transistor (MNR6) being turned on, the voltage of the node (ND2) can be pulled up. In other words, the NOR gate (220) can be understood as being partially turned on (or activated) in advance by the previous data (D3).

[0055] Subsequently, a complementary pulse (PL0B) corresponding to a logic low (or falling edge) can be applied to transistors (MNR2, MNR3), and data (D0) corresponding to a logic low can be applied to the gates of transistors (MNR1, MNR4, MNR5) ('0'). Accordingly, transistors (MNR1, MNR2) can be turned off, and transistors (MNR3, MNR4, MNR5) can be turned on. As a result, the level of the gate signal (SG2) applied to the gate of transistor (M2) can rise faster (e.g., faster than when the NOR gate (220) is not activated) due to the voltage of the pre-pull-up node (ND2).

[0056] Due to the data (D3B) applied to the transistor (MNR6), the level of the gate signal (SG2) applied to the gate of the transistor (M2) can fall more quickly, and accordingly, the time required for the transistor (M2) to turn on in response to the data (D0) can be reduced. As a result, the transition speed of the data signal (DQ) output from the serializer (100) can be improved. In other words, due to the circuit (211), the transition speed of the signal output from the serializer (100) in response to the transition of the data input to the serializer (100) can be improved. Accordingly, signal interference caused by the falling edge of the input data can be improved.

[0057] In the embodiment illustrated in FIG. 8b, a transition of data input to the serializer (100) may not occur at the falling edge of the complementary pulse (PL0B). For example, when the data (D3) input corresponding to the rising edge of the previous pulse (PL3) corresponds to a logic high, the data (D0) input corresponding to the falling edge of the complementary pulse (PL0B) may correspond to a logic high.

[0058] In response to the previous complementary pulse (PL3B) of the complementary pulse (PL0B), data (D3B) corresponding to a logic low can be pre-applied ('0') to the gate of the transistor (MNR6). In response to the data (D3B) corresponding to a logic low, the transistor (MNR6) can be turned on.

[0059] Subsequently, a complementary pulse (PL0B) corresponding to a logic low (or falling edge) can be applied to transistors (MNR2, MNR3), and data (D0) corresponding to a logic high can be applied to the gates of transistors (MNR1, MNR4, MNR5) ('1'). Accordingly, transistors (MNR1, MNR3) can be turned off, and transistors (MNR2, MNR4, MNR5) can be turned on. Due to the turned-on transistor (MNR5), the voltage of node (ND2) can be lowered to a certain level. As the voltage of the node (ND2) decreases, the transistor (MNR1) may turn on or the level of current flowing to the node (ND2) through the transistor (MNR1) may rise, and consequently, the level of the gate signal (SG2) output from the NOR gate (220) may be prevented from rising above the threshold voltage of the transistor (M2). In other words, the transistor (MNR5) prevents the NOR gate (220) from malfunctioning due to the complementary data (D3B), thereby preventing the occurrence of a glitch.

[0060] FIG. 9 illustrates a block diagram of a serializer (100a) according to some embodiments of the present disclosure. Referring to FIG. 1, FIG. 2, and FIG. 9, the serializer (100a) may further include pre-drivers (112A, 113A), a main driver (112B), a de-emphasis driver (113B), and a delay circuit (113C), in addition to the multiplexer (110) and clock multiplexer (120) of FIG. 2.

[0061] The pre-driver (112A) can be connected to the output terminal of the multiplexer (110). The pre-driver (112A) can pre-process the signal output from the multiplexer (110) and then transmit the pre-processed signal to the main driver (112B). The main driver (112B) can transmit the signal to the output terminal of the serializer (100) based on the signal transmitted from the multiplexer (110) through the pre-driver (112A).

[0062] The delay circuit (113C) can be connected to the output terminal of the multiplexer (110). The delay circuit (113C) can delay the signal output from the multiplexer (110) by a unit of time. For example, the delay circuit (113C) can delay the signal output from the multiplexer (110) by the time during which the rising edge of the pulse (PL0) is maintained (or the duty of the pulse (PL0)). The pre-driver (113A) can pre-process the signal output from the delay circuit (113C) and then transmit the pre-processed signal to the de-emphasis driver (113B). The pre-driver (113A) can be implemented similarly to the pre-driver (112A) and can operate similarly to the pre-driver (112A). The de-emphasis driver (113B) can attenuate the magnitude of the signal output from the pre-driver (113A). For example, the de-emphasis driver (113B) can reduce the magnitude of the signal output from the pre-driver (113A) by a certain ratio. Accordingly, the swing of the voltage output from the pre-driver (113A) can be reduced. The de-emphasis driver (113B) can transmit the attenuated (or amplified) signal to the output terminal of the serializer (100).

[0063] The data signal (DQ) output from the output terminal of the serializer (100) may correspond to the sum of the signal output from the main driver (112B) and the signal output from the de-emphasis driver (113B). Due to the signal output from the de-emphasis driver (113B), the magnitude of the edge of the data signal (DQ) corresponding to the edge of the input data of the serializer (100) may increase, and interference between signals caused by the edge may be prevented. At the same time, due to the attenuation operation of the de-emphasis driver (113B), the Power Supply Noise Induced Jitter (PSIJ) flowing into the data signal (DQ) may increase. Additionally, because the signal output from the multiplexer (110) passes further through the delay circuit (113C), the pre-driver (113A), and the de-emphasis circuit (113B), the operating speed of the serializer (100) may be slowed down. And, as the de-emphasis circuit (113B) operates in synchronization with the clocks (WCK0~WCK270), the de-emphasis circuit (113B) can be affected by the frequency of the clocks (WCK0~WCK270) and can increase the loading of the clocks (WCK0~WCK270).

[0064] In some embodiments, as the serializer (100a) includes the multiplexer (110) described above with reference to FIGS. 3 through 7b, signal interference is prevented, so the operation of the de-emphasis driver (113B) may be unnecessary. Accordingly, unlike the serializer (100a) of FIG. 10, the serializer (100) of FIG. 2 may not include a delay circuit (113C), a pre-driver (113A), and a de-emphasis driver (113B). As a result, the serializer (100) of FIG. 2 may have lower jitter than the serializer (100a) of FIG. 10 and may operate faster at the same time. Also, since the multiplexer (110) does not operate in synchronization with the clocks (WCK0 to WCK270), the influence of the clocks (WCK0 to WCK270) on the output signal of the multiplexer (110) may be reduced.

[0065] FIG. 10 illustrates a block diagram of a system (1000) according to some embodiments of the present disclosure. The system (1000) of FIG. 10 may basically be a mobile system such as a portable communication terminal (mobile phone), a smartphone, a tablet PC (tablet personal computer), a wearable device, a healthcare device, or an IoT (Internet of Things) device. However, the system (1000) of FIG. 1 is not necessarily limited to a mobile system and may be an automotive device such as a personal computer, a laptop computer, a server, a media player, or a navigation system.

[0066] Referring to FIG. 10, the system (1000) may include a main processor (1100), memory (1200a, 1200b) and storage devices (1300a, 1300b), and additionally may include one or more of an image capturing device (1410), a user input device (1420), a sensor (1430), a communication device (1440), a display (1450), a speaker (1460), a power supplying device (1470), and a connecting interface (1480).

[0067] In some embodiments, at least one of the components of the system (1000) may include a transmitter (11) of FIG. 1 to communicate with another component of the system (1000). For example, at least one of the components of the system (1000) (e.g., main processor (1100), memory (1200a, 1200b), storage device (1300a, 1300b), communication device (1440), or connection interface (1480)) may include a transmitter (11) including a serializer (100) of FIG. 2 for serializing a signal generated by the component.

[0068] The main processor (1100) can control the overall operation of the system (1000), more specifically, the operation of other components that make up the system (1000). Such a main processor (1100) can be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0069] The main processor (1100) may include one or more CPU cores (1110) and may further include a controller (1120) for controlling memory (1200a, 1200b) and / or storage devices (1300a, 1300b). According to an embodiment, the main processor (1100) may further include an accelerator (1130), which is a dedicated circuit for high-speed data computation, such as artificial intelligence (AI) data computation. Such an accelerator (1130) may include a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), and / or a Data Processing Unit (DPU), and may be implemented as a separate chip physically independent from other components of the main processor (1100).

[0070] The memory (1200a, 1200b) can be used as the main memory of the system (1000) and may include volatile memory such as SRAM and / or DRAM, but may also include non-volatile memory such as flash memory, PRAM and / or RRAM. The memory (1200a, 1200b) may also be implemented within the same package as the main processor (1100).

[0071] The storage device (1300a, 1300b) can function as a non-volatile storage device that stores data regardless of whether power is supplied, and can have a relatively large storage capacity compared to the memory (1200a, 1200b). The storage device (1300a, 1300b) may include a storage controller (1310a, 1310b) and a non-volatile memory (NVM) (1320a, 1320b) that stores data under the control of the storage controller (1310a, 1310b). The non-volatile memory (1320a, 1320b) may include a flash memory with a 2D (2-dimensional) structure or a 3D (3-dimensional) V-NAND (Vertical NAND) structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM.

[0072] The storage device (1300a, 1300b) may be included in the system (1000) in a state physically separated from the main processor (1100), or it may be implemented within the same package as the main processor (1100). Additionally, the storage device (1300a, 1300b) may have a form such as a solid state device (SSD) or a memory card, and may be detachably coupled to other components of the system (1000) through an interface such as the connection interface (1480) described later. Such storage device (1300a, 1300b) may be a device to which standard protocols such as Universal Flash Storage (UFS), embedded multi-media card (eMMC), or non-volatile memory express (NVMe) are applied, but is not necessarily limited thereto.

[0073] The shooting device (1410) can take still images or video and may be a camera, camcorder and / or webcam, etc.

[0074] The user input device (1420) can receive various types of data input from a user of the system (1000) and may be a touch pad, a keypad, a keyboard, a mouse and / or a microphone.

[0075] The sensor (1430) can detect various types of physical quantities that may be obtained from outside the system (1000) and convert the detected physical quantities into electrical signals. Such a sensor (1430) may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor and / or a gyroscope sensor, etc.

[0076] The communication device (1440) can transmit and receive signals between other devices outside the system (1000) according to various communication protocols. Such a communication device (1440) may be implemented including an antenna, a transceiver and / or a modem.

[0077] In some embodiments, the communication device (1440) may include the transmitter (11) of FIG. 1. For example, the communication device (1440) may include the transmitter (11) which includes the serializer (100) of FIG. 2 for serializing a signal generated from within the system (1000).

[0078] The display (1450) and speaker (1460) can function as output devices that output visual information and auditory information, respectively, to the user of the system (1000).

[0079] The power supply unit (1470) can appropriately convert power supplied from a battery (not shown) and / or an external power source built into the system (1000) and supply it to each component of the system (1000).

[0080] The connection interface (1480) can provide a connection between the system (1000) and an external device connected to the system (1000) that can exchange data with the system (1000). The connection interface (1480) can be implemented in various interface methods such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe, IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC, UFS, eUFS (embedded Universal Flash Storage), CF (compact flash) card interface, etc.

[0081] FIG. 11 illustrates a block diagram of a memory (1200a) according to some embodiments of the present disclosure. Referring to FIG. 1, FIG. 2, FIG. 10, and FIG. 11, a transmitter (11) including the serializer (100) of FIG. 2 may be included in a semiconductor memory device such as a memory (1200a).

[0082] The memory (1200a) may include a memory controller (1210) and n (n is a natural number) Dynamic Random Access Memory (DRAM) devices (DRAM1 to DRAMn). The DRAM devices (DRAM1 to DRAMn) may communicate with the memory controller (1210) through a channel (e.g., 1221). The memory controller (1210) and the DRAM devices (DRAM1 to DRAMn) may include a transmitter (11) comprising the serializer (100) of FIG. 2. Accordingly, the quality of serial communication between the DRAM devices (DRAM1 to DRAMn) within the memory (1200a) may be improved. For example, interference between data signals output from each of the DRAM devices (DRAM1 to DRAMn) may be prevented.

[0083] The above descriptions are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the embodiments described above, but also embodiments that are simply modified or can be easily modified. Furthermore, the present disclosure will include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present disclosure should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of the present invention. Explanation of the symbols

[0084] 100: Serializer 110: Multiplexer

Claims

Claim 1 A multiplexer for selecting any one of first to fourth data signals in response to first to fourth pulses that correspond to each of the first to fourth data signals and are sequentially toggled, comprising: a NAND gate that receives the first data signal, a fourth complementary data signal which is a complementary signal of the fourth data signal, and the first pulse, and outputs a first gate signal; a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse which is complementary to the first pulse, and outputs a second gate signal; and a first transistor comprising a first terminal to which a first power supply voltage is applied, a gate that receives the first gate signal, and a second terminal connected to an output terminal of the multiplexer. A multiplexer comprising a first terminal connected to the output terminal of the multiplexer, a gate receiving the second gate signal, and a second transistor to which a ground voltage is applied, wherein the first data signal corresponds to the rising edge of the first pulse and the fourth complementary data signal corresponds to the rising edge of the fourth pulse. Claim 2 In claim 1, the NAND gate comprises: a third transistor including a first terminal to which a second power supply voltage is applied, a gate to which a first pulse is applied, and a second terminal connected to the gate of the first transistor; a fourth transistor including a first terminal to which a third power supply voltage is applied, a gate to which a first data signal is applied, and a second terminal connected to the gate of the first transistor; a fifth transistor including a first terminal connected to the gate of the first transistor, a gate to which a first pulse is applied, and a second terminal connected to a first node; a sixth transistor including a first terminal connected to the first node, a gate to which a first data signal is applied, and a second terminal to which a ground voltage is applied; and a seventh transistor including a first terminal connected to the first node, a gate to which a fourth complementary data signal is applied, and a second terminal to which a ground voltage is applied. Claim 3 In claim 2, the NAND gate further comprises an eighth transistor including: a first terminal to which a fourth power supply voltage is applied, a gate to which a first data signal is applied, and a second terminal connected to the first node. Claim 4 In claim 1, the NOR gate comprises: a third transistor connected to a first terminal to which a second power supply voltage is applied, a gate to which a first data signal is applied, and a first node; a fourth transistor including a first terminal connected to the first node, a gate to which a first complementary pulse is applied, and a second terminal connected to the gate of the second transistor; a fifth transistor including a first terminal connected to the gate of the second transistor, a gate to which a first complementary pulse is applied, and a ground voltage is applied; a sixth transistor including a first terminal connected to the gate of the second transistor, a gate to which a first data signal is applied, and a ground voltage is applied; and a seventh transistor including a first terminal to which a third power supply voltage is applied, a gate to which a fourth complementary data signal is applied, and a second terminal connected to the first node. Claim 5 In claim 4, the NOR gate further comprises: a first terminal connected to the first node, a gate to which the first data signal is applied, and an eighth transistor to which the ground voltage is applied. Claim 6 A clock multiplexer that generates first to fourth pulses that are sequentially toggled based on first to fourth clocks, each having a first phase difference; and a multiplexer that outputs an output signal based on first to fourth data signals corresponding to each of the first to fourth pulses in response to the first to fourth pulses and first to fourth complementary pulses that are complementary to each of the first to fourth pulses, wherein the multiplexer comprises: a NAND gate that receives the first data signal, a fourth complementary data signal that is complementary to the fourth data signal, and the first pulse, and outputs a first gate signal; and a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse, and outputs a second gate signal, and the level of the output signal is based on the first gate signal and the second gate signal. Claim 7 In claim 6, the NAND gate comprises a first transistor including a first terminal to which the first gate signal is applied, a gate to which the first pulse is applied, and a second terminal connected to a first node, wherein in response to the fourth complementary data signal having a first logic value at the first rising edge of the fourth pulse, the level of the voltage of the first node is lowered, and in response to the first data signal having a second logic value at the second rising edge of the first pulse following the first rising edge of the fourth pulse, the voltage of the first node is transferred to the first terminal of the first transistor to which the first gate signal is applied, wherein the first logic value and the second logic value are different from each other. Claim 8 In claim 6, the NOR gate comprises a first transistor including a first terminal connected to a first node, a gate to which the first complementary pulse is applied, and a second terminal to which the second gate signal is applied, wherein in response to the fourth complementary data signal having a first logic value at the first rising edge of the fourth pulse, the level of the voltage of the first node is lowered, and in response to the first data signal having a second logic value at the second rising edge of the first pulse following the first rising edge of the fourth pulse, the voltage of the first node is transferred to the first terminal of the first transistor to which the second gate signal is applied, wherein the first logic value and the second logic value are different from each other. Claim 9 A clock multiplexer that generates first to fourth pulses that are sequentially toggled based on first to fourth clocks, each having a first phase difference; and a multiplexer that outputs an output signal based on first to fourth data signals corresponding to each of the first to fourth pulses in response to the first to fourth pulses and first to fourth complementary pulses that are complementary to each of the first to fourth pulses, wherein the multiplexer comprises: the first data signal, the fourth complementary data signal which is a complementary signal of the fourth data signal, and the first pulse, and a NAND gate that receives the first pulse and outputs a first gate signal; A serializer comprising: a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse complementary to the first pulse, and outputs a second gate signal; a first transistor including a first terminal to which a first power supply voltage is applied, a gate that receives the first gate signal, and a second terminal connected to the output terminal of the multiplexer; and a second transistor including a first terminal connected to the output terminal of the multiplexer, a gate that receives the second gate signal, and a second transistor to which a ground voltage is applied, wherein the first data signal corresponds to the rising edge of the first pulse, and the fourth complementary data signal corresponds to the rising edge of the fourth pulse. Claim 10 In claim 9, the NAND gate comprises a third transistor including a first terminal to which the first gate signal is applied, a gate to which the first pulse is applied, and a second terminal connected to a first node, and the NOR gate comprises a fourth transistor including a first terminal connected to a first node, a gate to which the first complementary pulse is applied, and a second terminal to which the second gate signal is applied, wherein the level of the voltage of the first node of the third transistor decreases in response to the fourth complementary data signal having a first logic value at the first rising edge of the fourth pulse.

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