Forksheet transistor architectures

Abstract

The embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device includes first transistor layers. The first transistor layers include a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further includes second transistor layers above the first transistor layers. The second transistor layers include a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to semiconductor devices, and more specifically, to forksheet transistors having various architectures and interconnects. Background Technology

[0002] Over the past few decades, the scaling of features in integrated circuits has been the driving force behind the sustained growth of the semiconductor industry. Scaling toward increasingly smaller features enables functional units with increased densities on the limited physical area of ​​semiconductor chips. For example, the reduction in transistor size allows for the integration of a larger number of memory or logic devices on a chip, leading to the manufacture of products with increased capacity. However, the relentless pursuit of greater capacity is not without its challenges. The need to optimize the performance of each individual device is becoming increasingly critical.

[0003] In the manufacturing of integrated circuit devices, as device dimensions continue to be scaled down, multi-gate transistors, such as tri-gate transistors, have become more common. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable less complex tri-gate fabrication processes. In other aspects, as microelectronic device dimensions scale down below the 10-nanometer (nm) node, maintaining improved mobility and single-channel control presents challenges in device manufacturing. The nanowires used to fabricate these devices provide improved single-channel control.

[0004] However, scaling up multi-gate and nanowire transistors came at a cost. As the dimensions of these basic building blocks of microelectronic circuits decreased, and as the number of basic building blocks fabricated within a given area increased, the constraints on the lithography processes used to pattern these blocks became overwhelming. In particular, there can be a trade-off between the smallest dimension (critical dimension) of patterned features in semiconductor stacks and the spacing between such features.

[0005] To address the requirements regarding spacing between features, a fork-sheet transistor architecture has been proposed. In the fork-sheet architecture, an insulating backbone is placed between the first and second transistors. The semiconductor channels (e.g., ribbons, wires, etc.) of the first and second transistors come into contact with the opposing sidewalls of the backbone. As a result, the spacing between the first and second transistors is reduced to the width of the backbone. Since one surface of the semiconductor channels comes into contact with the backbone, such architectures do not allow gate-all-around (GAA) control of the semiconductor channels. Additionally, dense interconnection architectures between the first and second transistors have not yet been proposed. Brief explanation of the drawing

[0006] FIG. 1a is an example of a perspective view of fork sheet transistors. Figure 1b is an example of a cross-section of fork sheet transistors across semiconductor channels. FIGS. 2a to 2c are cross-sectional examples of stacked fork sheet transistors according to various embodiments. FIGS. 3a to 3d are cross-sectional examples illustrating a process for manufacturing self-aligned stacked fork sheet transistors according to an embodiment. FIGS. 4a and 4b are cross-sectional examples of stacked fork sheet transistors having interconnections between the gate electrodes of a pair of fork sheet transistors according to various embodiments. FIGS. 5a to 5e are cross-sectional examples of stacked fork sheet transistors having interconnections between source / drain regions of a pair of fork sheet transistors according to various embodiments. FIG. 6 is a cross-sectional example of stacked fork sheet transistors having interconnections from the lowest contact portion to the source / drain region according to an embodiment. FIG. 7 is a cross-sectional example of stacked fork sheet transistors having an interconnection from the lowest contact portion to the gate electrode according to an embodiment. FIG. 8a is an example of a perspective view of fork sheet transistors having backbones including a liner according to an embodiment. FIGS. 8b to 8d are cross-sectional examples of fork sheet transistors of FIG. 8a along different planes according to embodiments. FIGS. 9a and 9b are cross-sectional examples of the fork sheet transistors of FIG. 8a according to additional embodiments. FIGS. 10a to 10l are cross-sectional examples illustrating a process for manufacturing fork sheet transistors using liners along backbones according to an embodiment. FIG. 11a is a cross-sectional example of fork sheet transistors using a catalytic oxidizing agent material on a liner on backbones according to an embodiment. FIGS. 11b and FIGS. 11c are zoomed-in examples illustrating the topography of a liner close to a semiconductor channel according to various embodiments. FIGS. 12a to 12d are cross-sectional examples illustrating a process for manufacturing fork sheet transistors using a liner containing a catalytic oxidizing agent material according to an embodiment. FIGS. 13a to 13c are cross-sectional examples illustrating a process for manufacturing fork sheet transistors having gate electrodes electrically coupled across a backbone using a time-set etching process according to an embodiment. FIG. 13d is a plan view example of the fork sheet transistors of FIG. 13c according to an embodiment. FIGS. 14a to 14c are cross-sectional examples illustrating a process for manufacturing fork sheet transistors having gate electrodes electrically coupled across a backbone using an etch stop layer in the backbone according to an embodiment. FIGS. 15a to 15d are cross-sectional examples of fork sheet transistors utilizing etch stop layers at various locations within the backbone according to various embodiments. FIGS. 16a to 16d are cross-sectional examples of a backbone having embedded etching stop layers according to various embodiments. FIG. 17a is a cross-sectional example of stacked fork sheet transistors having interconnections between source / drain regions across the backbone according to an embodiment. FIG. 17b is a plan view example of the fork sheet transistors of FIG. 17a according to an embodiment. FIG. 18 is a plan view example of fork sheet transistors configured as an inverter by interconnects across the backbone according to an embodiment. FIGS. 19a to 19c are cross-sectional examples of fork sheet transistors according to various embodiments, comprising an etchable selective layer between source / drain regions and a bottom contact region. FIGS. 20a and FIGS. 20b are cross-sectional examples of fork sheet transistors including different etchable selective layers between source / drain regions and bottom contacts according to various embodiments. FIG. 21 illustrates a computing device according to one implementation of an embodiment of the present disclosure. FIG. 22 is an interposer implementing one or more embodiments of the present disclosure. Specific details for implementing the invention

[0007] Forksheet transistors having various architectures and interconnection methods according to various embodiments are described herein. In the following description, various aspects of exemplary embodiments will be described using terms commonly used by those skilled in the art to convey the essence of their work to other those skilled in the art. However, it will be apparent to those skilled in the art that the invention may be practiced with only some of the described aspects. For the purposes of explanation, specific numbers, materials, and configurations are described to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that the invention may be practiced without specific details. In other examples, well-known features are omitted or simplified so as not to obscure the exemplary embodiments.

[0008] Various operations will be described in sequence as a number of distinct operations in a manner most helpful to understanding the invention, but the order of description should not be interpreted as implying that these operations are necessarily sequence-dependent. In particular, these operations do not need to be performed in the order presented.

[0009] As mentioned above, fork sheet transistors allow for increased density non-planar transistor devices. Fork sheet transistors (120 A and 120 B An example of a semiconductor device (100) having ) is shown in FIG. 1a. The fork sheet transistor includes a backbone (110) extending upward from a substrate (101), and transistors (120) are adjacent to both sidewalls of the backbone (110). Thus, the transistors (120 A and 120B The spacing between them is equal to the width of the backbone (110). Therefore, the density of such forksheet transistors (120) can be increased compared to other non-planar transistor architectures (e.g., fin-FETs, nanowire transistors, etc.).

[0010] Sheets (105) of the semiconductor material extend away (laterally) from the backbone (110). In the example of FIG. 1a, the sheets (105 A and 105 B ) is shown on both sides of the backbone (110). Sheets (105 A ) is the first transistor (120 A It is about ), and the sheets (105 B ) is the second transistor (120 B It is about ). Sheets (105 A and 105 B ) passes through the gate structure (112). Sheets (105) within the gate structure (112) A and 105 B Parts of ) are considered as channels, and sheets (105) on opposite sides of the gate structure (112) A and 105 B Parts of ) are considered source / drain regions. In some implementations, the source / drain regions include an epitaxially grown semiconductor body, and the sheets (105) may exist only within the gate structure (112). That is, stacked sheets (105 A and 105 B ) is replaced by a block of semiconductor material.

[0011] Now, referring to FIG. 1b, an example of a cross-section of a semiconductor device (100) through a gate structure (112) is illustrated. As illustrated, semiconductor channels (106 A and 106 B Vertical stacks of ) are provided through the gate structure (112). Semiconductor channels (106 A and 106 B) is connected to the source / drain regions outside the plane of Fig. 1b. Semiconductor channels (106 A and 106 B ) has three sides surrounded by a gate dielectric (108). Semiconductor channels (106 A and 106 B The surfaces (107) of the backbone (110) are in direct contact with the backbone. A work function metal (109) can surround the gate dielectric (108), and the gate filling metal (113 A and 113 B ) can surround the work function metal (109). In the example, semiconductor channels (106 A and 106 B ) is illustrated as having different shades. However, in some implementations, semiconductor channels (106 A and 106 B ) can be the same material. The insulating layer (103) is the gate filling metals (113 A and 113 B It can be placed on top of ).

[0012] Such fork sheet transistors (120 A and 120 B While it offers many advantages, there are still many areas for improvement to provide higher densities, improved interconnect architectures, and improved performance. For example, the embodiments disclosed herein provide additional density improvements by stacking multiple transistor layers on top of each other. The semiconductor device (100) of FIGS. 1a and 1b comprises single layers (i.e., a pair of adjacent fork sheet transistors (120 A and 120 BWhile )) exemplified, the embodiments disclosed herein include first layers and second layers within the same footprint as exemplified in FIG. 1a and 1b (e.g., to provide four fork sheet transistors). Additionally, the embodiments disclosed herein provide interconnect architectures that allow electrical coupling between the first layers and the second layers to effectively utilize multiple layers. Additionally, the embodiments disclosed herein include interconnect architectures that allow bottom-side connections to the buried layers.

[0013] The embodiments disclosed herein also include fork sheet transistors having architectures that allow gate-all-around (GAA) control of semiconductor channels. While conventional fork sheet transistors include surfaces of semiconductor channels in direct contact with the backbone, the embodiments disclosed herein include various liner architectures for the backbone that allow the semiconductor channels to be spaced apart from the backbone. In some embodiments, the liner is completely removed from the gate region. In other embodiments, the liner comprises a catalytic oxidizing agent, which allows for the selective removal of portions of the liner adjacent to the semiconductor channels or the removal of portions of the semiconductor immediately adjacent to the catalytic oxidizing agent material.

[0014] The embodiments disclosed herein also include interconnect architectures that allow interconnections between fork sheet transistors within the same layer. For example, the embodiments include interconnects that run through the backbone to connect the source / drain regions and / or gate electrodes of adjacent fork sheet transistors. In some embodiments, the interconnects are formed by a timed etching process. In other embodiments, the interconnects are formed using an etch stop layer embedded in the backbone.

[0015] The embodiments disclosed herein also include architectures for providing optional interconnects to contacts (i.e., bottom-side contacts) located beneath fork sheet transistors. The formation of optional bottom-side contacts is implemented using an etch-selective layer located beneath the fork sheet transistors. In some embodiments, the etch-selective layer may be aligned with the semiconductor channels located above it. In some architectures disclosed herein, etch-selective layers comprising the same material are located beneath both adjacent fork sheet transistors. In other embodiments, a first etch-selective layer is located beneath the first fork sheet transistor, and a second etch-selective layer (having an etch selectivity different from that of the first etch-selective layer) is located beneath the adjacent second fork sheet transistor.

[0016] Now, referring to FIG. 2a, a cross-sectional example of a semiconductor device (200) according to an embodiment is shown. The cross-sectional example of FIG. 2a is through the gate region and perpendicular to the semiconductor channels (206). The semiconductor device (200) comprises fork sheet transistors (220) of the first layer A and 220 B ) and fork sheet transistors (220) of the second layers above the first layers C and 220 D Includes ). In an embodiment, the insulating layer (214) may separate the first layers from the second layers. The insulating layer (214) may be part of the insulating layer (203) surrounding both layers. In other embodiments, the insulating layer (214) may be a separate layer from the insulating layer (203).

[0017] In an embodiment, the first layers and the second layers may be placed on a substrate (201). In an embodiment, the substrate (201) is an insulating layer. In some embodiments, the substrate (201) may be placed on a semiconductor substrate. In an embodiment, the semiconductor substrate placed underneath represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often comprises a wafer or other piece of silicon or other semiconductor material. Suitable semiconductor substrates include, but are not limited to, single-crystal silicon, polycrystalline silicon, and insulator-phase silicon (SOI), as well as similar substrates formed from other semiconductor materials, such as substrates comprising germanium, carbon, or Group III-V materials.

[0018] In the illustrated embodiment, the first layers are fork sheet transistors (220) having a first conductivity type A and 220 B ) including, and the second layers are fork sheet transistors (220) having a second conductivity type C and 220 D ...includes ). For example, the first layers may include P-type transistors (220), and the second layers may include N-type transistors (220). However, in other embodiments, one or both of the first layers and the second layers may include transistors (220) having both conductivity types. For example, the first transistor (220 A ) can be P-type, and the second transistor (220 B ) may be N-type. In the illustrated embodiment, each of the transistors (220) is shown to have three semiconductor channels (206). However, it will be recognized that any number of semiconductor channels (206) may be used in various transistors (220).

[0019] In the embodiment, the first layers are the first backbone (210 AIt may include ). The semiconductor channels (206) are the first backbone (210 A It may extend outward (laterally) from ). In an embodiment, the semiconductor channels (206) may comprise materials such as, but are not limited to, silicon, germanium, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the surface of the semiconductor channels (206) is a first backbone (210 A It can come into direct contact with the edge of ). In other embodiments, (as will be described in more detail below) the semiconductor channels (206) are the first backbone (210 A It can be spaced apart from ). In the illustrated embodiment, the semiconductor channels (206) are shown to have a substantially rectangular cross-section. However, it will be recognized that the cross-section of the semiconductor channels (206) may have any suitable shape. In some examples, the semiconductor channels (206) may be referred to as nanoribbons or nanowires.

[0020] In an embodiment, the perimeter of the semiconductor channels (206) may be surrounded (at least partially) by a gate dielectric (208). The gate dielectric (208) may be, for example, any suitable oxide, such as silicon dioxide or high-k gate dielectric materials. Examples of high-k gate dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric (208) layer to improve its quality.

[0021] In an example, the work function metal (209) may surround the gate dielectric (208). When the work function metal (209) acts as an N-type work function metal, the work function metal (209) preferably has a work function of about 3.9 eV to about 4.2 eV. N-type materials that can be used to form the work function metal (209) include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and metal carbides containing these elements, namely titanium carbide, zirconium carbide, tantalum carbide, hafnium carbide, and aluminum carbide. When the work function metal (209) acts as a P-type work function metal, the work function metal preferably has a work function of about 4.9 eV to about 5.2 eV. P-type materials that can be used to form the work function metal (209) include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide.

[0022] In an embodiment, the gate charge metal (213) may surround the work function metal (209). The gate charge metal (213) may comprise, for example, polysilicon, silicon nitride, silicon carbide, or a wide range of suitable metals or metal alloys, such as aluminum, tungsten, titanium, tantalum, copper, titanium nitride, or tantalum nitride. The combination of the gate charge metal (213) and the work function metal (209) may sometimes be referred to herein as the gate electrode for simplification.

[0023] In the embodiment, the second layers are the second backbone (210 B It may include ). A third transistor (220 C ) and the fourth transistor (220 D ) is the second backbone (210 B It can be located on the opposing edges of ). The third transistor (220 C ) and the fourth transistor (220 DThe structures and materials for ) are the first transistor (220 A ) and the second transistor (220 B It may be substantially similar to the things described above in relation to ).

[0024] In the embodiment, the first layers and the second layers may be manufactured using different processing flows. That is, the first layers may be manufactured using a first lithography process, and the second layers may be manufactured using a second lithography process. As a result, a slight registration error may exist between the first layers and the second layers due to the overlay limitations of existing lithography tools. For example, a registration error (M) is illustrated in FIG. 2a. That is, the first backbone (210 A The edge of ) is the second backbone (210 B It can be misaligned with respect to the edges of ).

[0025] To eliminate registration error (M), some embodiments disclosed herein utilize a self-alignment process to form stacked layers of fork sheet transistors. An example of such an embodiment is shown in FIG. 2b.

[0026] As illustrated in FIG. 2b, the semiconductor device (200) comprises first layers (i.e., first transistors (220) A ) and the second transistor (220 B )) and second layers (i.e., third transistor (220 C ) and the fourth transistor (220 DIncludes )). The semiconductor device (200) of FIG. 2b is substantially similar to the semiconductor device (200) of FIG. 2a, except that a single backbone (210) is provided and there is no registration error between the two layers. In an embodiment, the first and second layers of transistors (220) may both be adjacent to the backbone (210). The elimination of registration error between the layers is made possible by using a self-aligned manufacturing process. For example, a single lithography operation is used to pattern the backbone (210) (used by both layers), and a single lithography operation is used to pattern the semiconductor channels (206) of both layers. A more detailed description of such a self-aligned process flow is provided in connection with FIGS. 3a through 3d below.

[0027] Now, referring to FIG. 2c, a cross-sectional example of a semiconductor device (200) according to an additional embodiment is shown. The semiconductor device (200) of FIG. 2c has third layers (i.e., a fifth transistor (220) E ) and the 6th transistor (220 F The semiconductor device (200) of FIG. 2b is substantially similar to the semiconductor device (200) except that it is positioned above the second layers. As illustrated, the third layers are also self-aligned with the layers placed below and share a single backbone (210). Although examples of two layers and three layers are illustrated herein, it will be recognized that the semiconductor device (200) can be implemented with any number of stacked layers. Multiple stacked layers can be implemented by a self-alignment process (e.g., similar to FIG. 2b and FIG. 2c) or by separate processing (e.g., similar to FIG. 2a).

[0028] Now, referring to FIGS. 3a through 3d, a series of examples illustrating a process for manufacturing self-aligned stacked fork sheet transistors according to an embodiment are shown.

[0029] Now, referring to FIG. 3a, an example perspective view of a semiconductor device (300) according to an embodiment is shown. In the embodiment, the semiconductor device (300) comprises a substrate (301) and a plurality of epitaxially grown layers (393, 394) on the substrate (301). The layers (393, 394) may be arranged as first layers (391) and second layers (392) on the first layers (391). The layers (393) may be a semiconductor material to be used in the channels of the transistor devices. For example, the layers (393) may comprise silicon. The layers (394) may be sacrificial layers that are etch-optional with respect to the layers (393). For example, when the layer (393) is silicon, the layer (394) may comprise silicon germanium. In an embodiment, the layers (393 and 394) may be patterned into pins. In another embodiment, the layers (393) may be composed of semiconductor layers, and the layers (394) may be composed of dielectric layers, such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0030] Referring now to FIG. 3b, there is an example of a perspective view of a semiconductor device (300) after a backbone trench (395) has been formed through the first layers (391) and the second layers (392). A single lithography operation provides self-alignment between the portion of the backbone between the first layers (391) and the portion of the backbone between the second layers (392). In an embodiment, the backbone trench (395) may be formed by one or more etching processes. The backbone trench (395) defines a plurality of transistor devices (320) in the semiconductor device (300). The first transistor (320 A ) and the second transistor (320 B ) is in the first layers (391), and the third transistor (320 C ) and the fourth transistor (320 D ) is in the second layer (392).

[0031] Now, referring to FIG. 3c, there is an example of a perspective view of a semiconductor device (300) after the backbone (310) has been placed in the backbone trench (395). The backbone (310) is an insulating material. The backbone (310) can be deposited by any suitable deposition process. In some embodiments, portions of the backbone (310) outside the backbone trench (395) can be removed by an etching process.

[0032] Now, referring to FIG. 3d, an example perspective view of a semiconductor device (300) after the formation of source / drain regions (305) and a gate electrode (313) according to an embodiment is shown. The formation of the source / drain regions (305) can be implemented using standard processes. In the embodiment, a portion (314) of the insulating layer (303) is the first transistor (320 A The source / drain regions (305) in the third transistor (320) C It can be separated from the source / drain regions (305) in ), and the portion (314) is the second transistor (320 B The source / drain regions (305) in the fourth transistor (320 D It can be separated from the source / drain regions (305) in ). Some details of the semiconductor device (300) (e.g., spacers) are omitted in FIG. 3d for simplification.

[0033] Now, referring to FIG. 4a, a cross-sectional example of a semiconductor device (400) having stacked fork sheet transistors according to an embodiment is shown. The semiconductor device (400) may include a backbone (410) disposed on a substrate (401). A first transistor (420 A ) and the second transistor (420 B The first layers including ) are the third transistor (420 C ) and the fourth transistor (420 DIt may be located below second layers including ). Each transistor (420) may include semiconductor channels (406). An insulating layer (403) may surround the first and second layers.

[0034] In an embodiment, the semiconductor device (400) is a second transistor (420 B The gate electrode (413) of the fourth transistor (420) D The semiconductor device (200) of FIG. 2b may be substantially similar to the one in FIG. 2b, except that an interconnection portion (415) is disposed between the first and second layers through an insulating layer (414) to connect the gate electrodes (413). In an embodiment, the interconnection portion (415) may be the same material as the gate electrodes (413). However, in other embodiments, such as the embodiment illustrated in FIG. 4b, the interconnection portion (415) may be a different material from the material of the gate electrodes (413).

[0035] In the embodiment, the first transistor (420 A The gate electrode (413) of the third transistor (420) is supported by an insulating layer (414). C It can be electrically isolated from the gate electrode (413) of the ). Additionally, when looking globally at various locations on the semiconductor die, some fork sheet transistor stacks may include interconnects (415) for connecting the stacked gate electrodes (413), while other fork sheet transistor stacks may not include any interconnects (415) between the stacked gate electrodes (413). In another embodiment, the first interconnect (415) is the first transistor (420 A The gate electrode (413) of the ) and the third transistor (420 C It may be included between the gate electrodes (413) of the second interconnect (415), and the second transistor (420) B The gate electrode (413) of the ) and the fourth transistor (420 DIt may be included between the gate electrodes (413) of the ). In the illustrated embodiment, a self-aligned architecture between the first and second layers is shown. However, it will be recognized that substantially similar interconnects (415) between the gate electrodes (413) can be implemented using an architecture similar to that of FIG. 2a.

[0036] Now, referring to FIG. 5a, a cross-sectional example of a semiconductor device (500) according to an embodiment is shown. The illustrated plane is perpendicular to the channel and through the source / drain regions (505). That is, transistors (520) on both sides of the backbone (510) A-D A source / drain area (505) for each is illustrated. An insulating layer (503) around the substrate (501) and transistors (520) is also illustrated.

[0037] In an embodiment, the source / drain regions (505) are optionally shaped. This is due to the source / drain regions (505) being epitaxially grown from semiconductor channels (not shown). In some embodiments, the source / drain regions (505) may be in contact with the backbone (510). In other embodiments, the source / drain regions (505) are spaced apart from the backbone (510), as shown in FIG. 5a. The source / drain regions (505) may be formed by conventional processes. For example, depressions adjacent to the gate stack are formed by an etching process. The depressions may expose the ends of the semiconductor channels within the gate stack. These depressions may then be filled with semiconductor using an optional epitaxial deposition process grown from the ends of the semiconductor channels. In some embodiments, the epitaxial semiconductor may be doped in-situ. For example, the epitaxial semiconductor may comprise in-situ doped silicon germanium, in-situ doped silicon carbide, or in-situ doped silicon. In alternative embodiments, other silicon alloys may be used. For example, alternative silicon alloy materials that may be used include, but are not limited to, nickel silicide, titanium silicide, and cobalt silicide, and may possibly be doped with one or more of boron and / or aluminum.

[0038] In an embodiment, an interconnection portion (516) for electrically coupling source / drain regions (505) of different layers of a semiconductor device (500) may be provided. For example, the interconnection portion (516) is a fourth transistor (520 D ) and the second transistor (520 BIt provides an electrical connection between the source / drain regions (505) of the interconnect (516). The interconnect (516) may pass through the insulating layer (514) between the layers. In an embodiment, the interconnect (516) may be formed by any suitable process. For example, a trench may be etched into the source / drain regions (505) and filled with a conductive material. In an illustrated embodiment, the interconnect (516) is formed by the fourth transistor (520 D The second transistor (520) completely passes through the source / drain region (505) of the ) B It passes into (but does not pass through) the source / drain area (505) of ).

[0039] In the embodiment, the first transistor (520 A The source / drain region (505) of the third transistor (520) is formed by an insulating layer (514). C It can be electrically isolated from the source / drain region (505) of the ). Additionally, when looking globally at various locations on the semiconductor die, some fork sheet transistor stacks may include interconnects (516) for connecting the stacked source / drain regions (505), while other fork sheet transistor stacks may not include any interconnects (516) between the stacked source / drain regions (505). In another embodiment, the first interconnect (516) is the first transistor (520 A The source / drain region (505) of ) and the third transistor (520 C It may be included between the source / drain regions (505) of the second interconnect (516), and the second transistor (520) B The source / drain region (505) of ) and the fourth transistor (520 DIt may be included between the source / drain zones (505). In the illustrated embodiment, a self-aligned architecture between the first and second layers is shown. However, it will be recognized that substantially similar interconnects between the source / drain zones (505) can be implemented using an architecture similar to that of FIG. 2a.

[0040] Now, referring to FIG. 5b, a cross-sectional example of the semiconductor device (500) of FIG. 5a along the line (B-B') according to an embodiment is shown. The plane of FIG. 5b is parallel to the semiconductor channels (506). As shown, a pair of source / drain regions (505) are located on opposite ends of the semiconductor channels (506) of each transistor (520). In an embodiment, spacers (511) may define the channel regions. The channel regions may include a gate dielectric (508) surrounding the semiconductor channels (506) and a gate electrode (513) surrounding the gate dielectric (508). The work function metal between the gate electrode (513) and the gate dielectric (508) is omitted for simplification.

[0041] As described, the interconnection portion (516) is the fourth transistor (520 D Through the source / drain region (505) of the second transistor (520 B It extends into the source / drain zone (505). The interconnect (516) may be aligned with the edge of the source / drain zones (505). In other embodiments, the interconnect (516) may be entirely within the width of the source / drain zones (505).

[0042] Now, referring to FIG. 5c, a cross-sectional example of a semiconductor device (500) according to an additional embodiment is shown. The semiconductor device (500) of FIG. 5c has an interconnection portion (516) that is a second transistor (520 BIt is substantially similar to the semiconductor device (500) of FIG. 5b, except that it does not pass into the source / drain region (505) of the ). Instead, the interconnect portion (516) is the second transistor (520 B It is placed on the uppermost surface of the source / drain zone (505) of the ).

[0043] Now, referring to FIG. 5d, a cross-sectional example of a semiconductor device (500) according to another embodiment is shown. The semiconductor device (500) of FIG. 5d has an interconnection portion (516) that is a second transistor (520 B It is substantially similar to the semiconductor device (500) of FIG. 5b, except that it completely passes through the source / drain region (505) of ).

[0044] Now, referring to FIG. 5e, a cross-sectional example of a semiconductor device (500) according to another embodiment is shown. The semiconductor device (500) of FIG. 5e is substantially similar to the semiconductor device (500) of FIG. 5b, except that the interconnect (516) does not pass through either of the source / drain regions (505). Instead, the interconnect (516) is a fourth transistor (520 D ) and the second transistor (520 B Wraps around one or more outer surfaces of one or both of the source / drain zones (505) of the ).

[0045] In FIGS. 4a through 5e, examples of gate electrode (413) interconnects (415) between layers (e.g., FIGS. 4a and 4b) or source / drain region (505) interconnects (516) between layers (e.g., FIGS. 5a through 5e) are illustrated. However, in some embodiments, it will be recognized that a semiconductor device having stacked fork sheet transistors may include both source / drain region interconnects (516) and gate electrode interconnects (415) between layers.

[0046] In addition to providing interconnections between stacked layers of a semiconductor device, embodiments also include providing interconnections for contacts below fork sheet transistors. In this way, the embedded fork sheet transistors (i.e., transistors of the first layer) can be contacted without needing to pass through the transistors placed above. Examples of such configurations are provided in FIGS. 6 and 7.

[0047] Now, referring to FIG. 6, a cross-sectional example of a semiconductor device (600) according to an embodiment is shown. In the embodiment, the semiconductor device (600) comprises a substrate (601) and fork sheet transistors (620) on the substrate (601). A-D It may include ). The backbone (610) is the first transistor (620 A ) the second transistor (620 B Separated from ) and the third transistor (620 C ) is the fourth transistor (620 D It can be separated from ). The plane of the cross section is through the source / drain regions (605) of the transistors (620). In an embodiment, an insulating layer (603) may surround the transistors (620).

[0048] In an embodiment, conductive features may be provided on the substrate (601). For example, a buried line (618) may be located adjacent to the stacked transistors (620). Conductive pads (619) may be located below the stacked transistors (620) and connected to the buried line (618) (outside the plane of FIG. 6). In an embodiment, an interconnect (617) extends from the pad (619) to the first transistor (620 A It can be extended to the source / drain region (605) of ). In other embodiments, the first transistor (620 A ) and the second transistor (620 BBoth of them can be connected to the pads (619) placed underneath by the interconnects (617). The architecture of the conductive features of FIG. 6 is actually exemplary, and the transistors (620 A and 620 B It will be recognized that any rear-side interconnect architecture may be used to contact the source / drain zones (605) of the. For example, the rear-side interconnect architecture may include any number of layers of routing, vias, pads, etc.

[0049] Now, referring to FIG. 7, a cross-sectional example of a semiconductor device (700) according to an embodiment is shown. The illustrated plane of FIG. 7 is through the channel region. As shown, the semiconductor device (700) comprises a substrate (701) and a plurality of stacked fork sheet transistors (720 A-D Each of the transistors (720) includes semiconductor channels (706) that extend away from the backbone (710). A gate stack comprising a gate electrode (713) and a gate dielectric (708) surrounds portions of the semiconductor channels (706). An insulating layer (703) surrounds the transistors (720).

[0050] In an embodiment, conductive features may be provided on the substrate (701). For example, a buried line (718) may be located adjacent to the stacked transistors (720). Conductive pads (719) may be located below the stacked transistors (720) and connected to the buried line (718) (outside the plane of FIG. 7). In an embodiment, an interconnect (717) extends from the pad (719) to the first transistor (720 A It can be extended to the gate electrode (713) of ). In other embodiments, the first transistor (720 A ) and the second transistor (720 BBoth can be connected to the pads (719) placed underneath by the interconnects (717). The architecture of the conductive features of FIG. 7 is actually exemplary, and the transistors (720 A and 720 B It will be recognized that any rear-side interconnect architecture may be used to contact the gate electrodes (713) of the. For example, the rear-side interconnect architecture may include any number of layers of routing, vias, pads, etc.

[0051] As mentioned above, conventional forksheet transistors are not true GAA devices. This is because the semiconductor channels are in direct contact with the surface of the backbone. Therefore, the surface in contact with the backbone cannot be gated. Accordingly, the embodiments disclosed herein include forksheet transistor architectures that allow true GAA control of the semiconductor channels.

[0052] Now, referring to FIG. 8a, an example perspective view of a semiconductor device (800) according to an embodiment is shown. The semiconductor device (800) illustrated in FIG. 8a includes a first transistor (820 A ), second transistor (820 B ), and the third transistor (820 C Includes ). The first transistor (820 A ) is a second transistor (820) by means of a backbone (810) B Separated from ) and the second transistor (820 B ) is a third transistor (820) by means of a backbone (810) C It is separated from ). In the embodiment, the first transistor (820 A ) and the third transistor (820 C ) is a first conductivity type (e.g., P-type), and a second transistor (820 B ) is a second conductive type (e.g., N-type). In an embodiment, transistors (820) are placed on a substrate (801).

[0053] As illustrated in FIG. 8a, each transistor (820) comprises a pair of source / drain regions (805) separated from one another by a gate electrode (813). The gate electrode (813) may be separated from the source / drain regions (805) by a spacer (811), as is known to those skilled in the art. A portion of the gate dielectric (808) is also visible between the spacer (811) and the gate electrode (813).

[0054] To provide a GAA architecture, a liner (821) is provided around portions of the backbones (810). The liner (821) is visible adjacent to the source / drain regions (805). However, portions of the liner (821) are removed from the channel region (i.e., along the gate electrode (813)). The liner (821) has a thickness (T). In some embodiments, the thickness (T) may be approximately 3 nm or greater, or approximately 3 nm to 6 nm.

[0055] Now, referring to FIG. 8b, a cross-sectional example of the semiconductor device (800) of FIG. 8a along the line (B-B') according to an embodiment is shown. As illustrated, each of the semiconductor channels (806) has a perimeter that is completely surrounded by a gate dielectric (808) and a gate electrode (813). A work function metal (not shown) is also placed on the gate dielectric (808). The ability to provide such a GAA architecture is provided by removing a liner (821) from the channel region. Removing the liner (821) leaves a gap (T) between the edge of the semiconductor channel (806) and the backbone (810) equal to the thickness (T) of the liner (821). The space (T) is sufficient to allow the deposition of the gate dielectric (808) and the work function metal between the edge of the semiconductor channel (806) and the edge of the backbone (810). In some embodiments, portions of the gate dielectric (808) may also be deposited along the sidewalls of the backbone (810) during the conformal deposition process.

[0056] In the embodiment, the entire liner (821) is not removed from the channel area. For example, a remaining portion of the liner (821) may exist along the lowest surface of the backbone (810). That is, the backbone (810) may be separated from the substrate (801) by the liner (821).

[0057] Now, referring to FIG. 8c, a cross-sectional example of the semiconductor device (800) of FIG. 8a along the line (C-C') according to an embodiment is shown. As shown, semiconductor channels (806) pass through spacers (811) to contact source / drain regions (805). A gate dielectric (808) may cover the surfaces of the channel regions within the spacers (811). A portion of the gate dielectric (808) may also be placed over the inner surfaces of the spacers (811).

[0058] Now, referring to FIG. 8d, an example of a cross-section of the semiconductor device (800) of FIG. 8a along the line (D-D') according to an embodiment is shown. This cross-sectional plane clearly illustrates portions of the liner (821). As illustrated, portions of the liner (821) may wrap around the sidewalls and bottom of the backbone (810) adjacent to the source / drain area (805). That is, in some embodiments, the liner (821) may have a substantially U-shaped cross-section. In other embodiments, the liner (821) may be removed only from the area adjacent to the substrate material (801) through dry etching or a similar process, resulting in the backbone material (810) that is no longer separated from the substrate (801).

[0059] Now, referring to FIGS. 9a and 9b, cross-sectional examples of a semiconductor device (900) according to an additional embodiment are illustrated. The semiconductor device (900) comprises a substrate (901) and a plurality of fork sheet transistors (920) on the substrate (901). A-C ) may include. The transistors (920) may include semiconductor channels (906) that are completely surrounded by a gate dielectric (908) and a gate electrode (913) (Fig. 9a). The transistors (920) may also include source / drain regions (905) (Fig. 9b).

[0060] The semiconductor device (900) of FIGS. 9a and 9b may be substantially similar to the semiconductor device (800) of FIGS. 8a through 8d. Specifically, the cross-section of FIG. 9a is similar to the cross-section of FIG. 8b, and the cross-section of FIG. 9b is similar to the cross-section of FIG. 8d. The difference between the semiconductor device (900) and the semiconductor device (800) is that the liner (921) is removed from the lowest surfaces of the backbone (910). As shown in FIG. 9a, no residual portion of the liner (921) exists in the channel region. Similarly, in FIG. 9b, the lowest portion of the liner (921) between the backbone (910) and the substrate (901) is removed. Thus, the liner (921) is no longer substantially U-shaped and instead comprises a pair of distinct layers on both sidewalls of the backbone (910).

[0061] Now, referring to FIGS. 10a through 10l, a series of examples illustrating a process for forming semiconductor devices having fork sheet transistors including GAA architectures using a liner according to an embodiment are shown.

[0062] Now, referring to FIG. 10a, an example perspective view of a semiconductor device (1000) according to an embodiment is shown. In the embodiment, the semiconductor device (1000) comprises a substrate (1001) and a plurality of layers (1093, 1094) on the substrate (1001). In the embodiment, the layers (1093, 1094) are patterned into pins. The layers (1093) may be a semiconductor material to be used in the channels of the semiconductor device (1000), and the layers (1094) may be sacrificial layers. For example, the layers (1093) may be silicon, and the layers (1094) may be silicon germanium.

[0063] Now, referring to FIG. 10b, there is an example of a perspective view of a semiconductor device (1000) after the backbone trench (1095) is patterned on the layers (1093, 1094). The backbone trench (1095) is a first transistor (1020 A) and the second transistor (1020 B ) can be defined. The backbone trench (1095) can be patterned with any suitable etching process or processes.

[0064] Now, referring to FIG. 10c, an example perspective view of a semiconductor device (1000) is shown after a backbone liner (1021) is placed on exposed surfaces according to an embodiment. In the embodiment, the backbone liner (1021) may be placed by an conformal deposition process, and accordingly, the backbone liner (1021) is a first transistor (1020 A ) and the second transistor (1020 B The sidewall surfaces of the backbone liner (1021) are lined. In some embodiments, the flat surfaces of the backbone liner (1021) (e.g., on the substrate (1001) and on the top surfaces of the transistors (1020)) are etched and removed so that only the backbone liner (1021) on the vertical surfaces is left behind. Such an etching process can be used to form a device similar to those described in relation to FIGS. 9a and 9b.

[0065] Now, referring to FIG. 10d, an example perspective view of a semiconductor device (1000) is shown after the backbone (1010) is placed on the backbone liner (1021) according to an embodiment. The backbone (1010) may be an insulating material that is etch-selective with respect to the backbone liner (1021).

[0066] Now, referring to FIG. 10e, an example perspective view of a semiconductor device (1000) is shown after the portions of the backbone (1010) and backbone liner (1021) outside the backbone trench (1095) according to an embodiment have been removed. The portions outside the backbone trench (1095) can be removed by an etching process using a mask layer (not shown) that protects the backbone trench (1095).

[0067] Now, referring to FIG. 10f, an example perspective view of a semiconductor device (1000) is shown after a gate structure is placed over transistors (1020) according to an embodiment. The gate structure may include a dummy gate electrode (1013') having spacers (1011) on both sides. The gate structure may cross over the uppermost surface of the backbone (1010).

[0068] Now, referring to FIG. 10g, an example perspective view of a semiconductor device (1000) after source / drain depressions have been formed according to an embodiment is shown. In the embodiment, the depressions are formed by removing portions of the layers (1093, 1094) outside the spacers (1011). The surfaces of the semiconductor channels (1006) passing through the spacers (1011) are shown in FIG. 10g.

[0069] Now, referring to FIG. 10h, an example perspective view of a semiconductor device (1000) after source / drain regions (1005) have been formed according to an embodiment is shown. In the embodiment, the source / drain regions (1005) can be grown by an epitaxial growth process.

[0070] Now, referring to FIG. 10i, an example perspective view of a portion of a semiconductor device (1000) after the dummy gate electrode (1013') has been removed according to an embodiment is shown. In the embodiment, an insulating layer (1003) may be placed over the source / drain regions (1005). As illustrated, the removal of the dummy gate electrode (1013') exposes the semiconductor channels (1006), the backbone liner (1021), and the backbone (1010).

[0071] Now, referring to FIG. 10j, a cross-sectional example of the semiconductor device (1000) of FIG. 10i according to an embodiment is shown. As shown, the semiconductor channels (1006) are in direct contact with the backbone liner (1021). The backbone liner (1021) may cover the sidewall surfaces of the backbone (1010) and the bottom surface of the backbone (1010). In other embodiments, the backbone liner (1021) may not be present on the bottom surface of the backbone (1010).

[0072] Now, referring to FIG. 10k, a cross-sectional example of a semiconductor device (1000) after portions of the backbone liner (1021) have been removed according to an embodiment is shown. As illustrated, removing the backbone liner (1021) provides a gap (1097) between the surface of the semiconductor channel (1006) and the surface of the backbone (1010). The gap (1097) provides sufficient space to form a gate dielectric and a gate electrode around the entire perimeter of the semiconductor channel (1006).

[0073] Now, referring to FIG. 10L, a cross-sectional example of a semiconductor device (1000) is shown after a gate stack is placed over semiconductor channels (1006) according to an embodiment. In the embodiment, the gate stack includes a gate dielectric (1008) that surrounds the entire perimeter of the semiconductor channels (1006). Parts of the gate dielectric (1008) may be placed on the backbone (1010) and on the substrate (1001) due to an conformal deposition process. In the embodiment, a gate electrode (1013) is placed over the gate dielectric (1008). This provides GAA control of the fork sheet transistors of the semiconductor device (1000).

[0074] Now, referring to FIG. 11a, a cross-sectional example of a semiconductor device (1100) according to an additional embodiment is shown. The plane of the cross-section in FIG. 11a is through the channel region. The semiconductor device (1100) comprises a substrate (1101) and a plurality of fork sheet transistors (1120) on the substrate (1101). A-C It may include ). Each transistor (1120) may include a plurality of semiconductor channels (1106). The semiconductor channels (1106) have perimeters that are completely surrounded by a gate dielectric (1108) and a gate electrode (1113).

[0075] Each of the transistors (1120) can be separated from the adjacent transistor (1120) by the backbone (1110). Unlike the above embodiments of FIGS. 8a through 9b, a liner (1121) may be present in the channel region between the backbone (1110) and the semiconductor channels (1106). This is possible because the liner (1121) may contain a catalytic oxidizing agent material. For example, the liner (1121) may contain alumina. When a structure having a catalytic oxidizing agent is adjacent to a semiconductor material, such as a channel (1106), the application of heat causes a portion of the channel (1106) and a portion of the liner (1121) to be oxidized. Subsequently, an etchant selective for oxides rather than the semiconductor channel (e.g., a wet etching or atomic layer etching (ALE) approach) may be applied to the channel region to remove the oxides and create a gap between the remainder of the channel (1106) and the remainder of the liner (1121). The gap allows sufficient space to deposit the gate dielectric (1108) and gate electrode (1113) completely around the perimeter of the channel (1106).

[0076] Additionally, since the oxidation reaction is localized to a region of the liner (1121) adjacent to the channels (1106), a pattern of depressions (1124) may exist on the surface of the liner (1121) facing the gate electrode (1113). In an embodiment, the depressions (1124) are aligned with the channels (1106). However, in other embodiments, the liner (1121) may be completely removed.

[0077] In FIG. 11a, the depressions (1124) are depicted as having substantially rectangular outlines. It will be recognized that in some embodiments, the depressions (1124) may have shapes more characteristic of the diffusion event. FIG. 11b is a zoomed-in example of zone (1123) that more clearly illustrates what a typical depression might look like. For example, the depressions (1124) may have a vessel shape or otherwise have non-vertical surfaces. FIG. 11b also illustrates the consumed portion (1106') of the channel (indicated by dashed lines). As illustrated, the channel (1106) is originally coplanar with the surface of the liner (1121) prior to the oxidation and etching process.

[0078] Now, referring to FIG. 11c, an example of another embodiment of the zoomed-in area (1123) is illustrated. In FIG. 11c, the gate electrode (1113) (or work function metal (not illustrated)) does not completely cover all surfaces of the gate dielectric (1108) around the channel (1106). That is, there may be gaps (1125) at some locations. The gaps (1125) may block GAA control of the channel (1106). However, in some embodiments, a portion of the surface of the channel (1106) facing the backbone (1110) may still be gated to provide at least some additional control of the channel (1106).

[0079] Now, referring to FIGS. 12a through 12d, a series of examples illustrating a process for forming GAA fork sheet architectures using a liner having a catalytic oxidizing agent according to an embodiment are shown.

[0080] Now, referring to FIG. 12a, a cross-sectional example of a semiconductor device (1200) according to an embodiment is shown. The cross-sectional view shows a cross-section of a channel region in which backbones (1210) separate individual transistors. In an embodiment, a liner (1221) is disposed along the sidewalls of the backbones (1210). In some embodiments, the liner (1221) may also be on the lowest surface of the backbones (1210) on the substrate (1201). In an embodiment, the liners (1221) may include a catalytic oxidizing agent material. For example, the liners (1221) may include alumina. In an embodiment, the semiconductor channels (1206) are in direct contact with the liners (1221).

[0081] Now, referring to FIG. 12b, a cross-sectional example of a semiconductor device (1200) after heat treatment according to an embodiment is shown. In the embodiment, the heat treatment causes localized oxidation of the liner (1221). For example, only parts of the liner (1221) adjacent to the semiconductor channels (1206) are oxidized. The oxidized parts (1221') of the liner (1221) are shown in different shades in FIG. 12b. In the embodiment, parts of the semiconductor channels (1206') may also be oxidized during the heat treatment.

[0082] Now, referring to FIG. 12c, a cross-sectional example of a semiconductor device (1200) after the oxidized portions (1206' and 1221') have been removed according to an embodiment is shown. In the embodiment, the oxidized portions (1206' and 1221') may be removed by one or more optional etching processes for the semiconductor channels (1206) and / or the liner (1221). This forms depressions (1224) within the liner (1221).

[0083] Now, referring to FIG. 12d, a cross-sectional example of a semiconductor device (1200) is shown after a gate stack is placed over semiconductor channels (1206) according to an embodiment. In the embodiment, the gate stack may include a gate dielectric (1208) and a gate electrode (1213). A recess (1224) provides sufficient space for the gate dielectric (1208) and the gate electrode (1213) to completely surround the perimeter of the semiconductor channels (1206). Thus, GAA control is provided in the semiconductor device (1200).

[0084] Now, referring to FIGS. 13a through 13c, a series of cross-sectional examples illustrating a process for forming an interconnection between the gate electrodes of two fork sheet transistors passing across a backbone according to an embodiment are shown.

[0085] Now, referring to FIG. 13a, a cross-sectional example of a semiconductor device (1300) according to an embodiment is shown. In the embodiment, the semiconductor device (1300) comprises a substrate (1301) and a first transistor (1320) on the substrate (1301). A ) and the second transistor (1320 B Includes ). The first transistor (1320 A ) is a second transistor (1320) by means of a backbone (1310) B It can be separated from ). In the illustrated embodiment, the semiconductor channels (1306) of the transistors (1320) extend outward from the backbone (1310). In other embodiments, the semiconductor channels (1306) may have a GAA architecture similar to the architectures described above in relation to FIGS. 8a through 9b or FIGS. 11a through 11c. The channels (1306) may be surrounded by a gate electrode (1313), and an insulator (1303) may surround the transistors (1320). In the embodiment, the first transistor (1320 A ) may be a first conductivity type (e.g., P-type), and a second transistor (1320B ) may be a second conductivity type (e.g., N-type). In other embodiments, the first transistor (1320 A ) and the second transistor (1320 B ) can be of the same conductive type.

[0086] Now, referring to FIG. 13b, a cross-sectional example of a semiconductor device (1300) after the backbone (1310) has been etched back according to an embodiment is shown. In an embodiment, the backbone (1310) may be etched by a timed etching process. The etching process is timed so that the top surface (1332) of the backbone (1310) is positioned over the top surfaces (1333) of the channels (1306) (in the Z-direction). Maintaining the top surface (1332) of the backbone (1310) over the channels (1306) prevents a short circuit to the channels (1306) when the interconnect is placed in the recess (1331).

[0087] Now, referring to FIG. 13c, a cross-sectional example of a semiconductor device (1300) is shown after the interconnection portion (1334) is placed in the recess (1331) according to an embodiment. The interconnection portion (1334) is a first transistor (1320 A The gate electrode (1313) of the ) and the second transistor (1320 B It provides an electrical connection between the gate electrodes (1313). In an embodiment, the interconnect (1334) is made of the same material as one or both of the gate electrodes (1313). In other embodiments, the interconnect (1334) is made of a different material from the gate electrodes (1313).

[0088] Now, referring to FIG. 13d, an example plan view of the semiconductor device (1300) of FIG. 13c according to an embodiment is shown. In the embodiment, transistors (1320) include source / drains (1305) on opposite sides of the gate electrode (1313). The source / drains (1305) may be separated from the gate electrode (1313) by a spacer (1311). As shown, the interconnection portion (1334) is isolated as a portion of the backbone (1310) between the spacers (1311) to provide only electrical connection through the backbone (1310) within the channel region.

[0089] Now, referring to FIGS. 14a through 14c, a series of cross-sectional examples illustrating a process for forming interconnections between gate electrodes across a backbone using an etching stop layer according to an embodiment are shown.

[0090] Now, referring to FIG. 14a, a cross-sectional example of a semiconductor device (1400) according to an embodiment is shown. In the embodiment, the semiconductor device (1400) comprises a substrate (1401) and a first transistor (1420) on the substrate (1401). A ) and the second transistor (1420 B Includes ). The first transistor (1420 A ) is a second transistor (1420) by means of a backbone (1410) B It can be separated from ). In the illustrated embodiment, the semiconductor channels (1406) of the transistors (1420) extend outward from the backbone (1410). In other embodiments, the semiconductor channels (1406) may have a GAA architecture similar to the architectures described above in relation to FIGS. 8a through 9b or FIGS. 11a through 11c. The channels (1406) may be surrounded by a gate electrode (1413), and an insulator (1403) may surround the transistors (1420). In the embodiment, the first transistor (1420 A) may be a first conductivity type (e.g., P-type) and a second transistor (1420 B ) may be a second conductivity type (e.g., N-type). In other embodiments, the first transistor (1420 A ) and the second transistor (1420 B ) can be of the same conductive type.

[0091] In an embodiment, the backbone (1410) may further include an etch stop layer (1435). The etch stop layer (1435) may have high etch selectivity over the remainder of the backbone (1410). Thus, the portion of the backbone (1410) above the etch stop layer (1435) can be etched and removed without the strict process control required in a timed etching process, such as the process described above in relation to FIGS. 13a through 13c. In an embodiment, the top surface (1436) of the etch stop layer (1435) is above the top surface (1433) of the channels (1406). This prevents short circuits to the channels after deposition of the interconnection between the gate electrodes (1413).

[0092] Now, referring to FIG. 14b, a cross-sectional example of a semiconductor device (1400) is shown after the uppermost portion of the backbone (1410) has been etched back according to an embodiment. Removing the uppermost portion of the backbone (1410) results in the formation of a depression (1431) that terminates at the uppermost surface of the etch stop layer (1435).

[0093] Now, referring to FIG. 14c, a cross-sectional example of a semiconductor device (1400) is shown after the interconnection portion is placed in the recess (1431) according to an embodiment. The interconnection portion (1434) is a first transistor (1420 A The gate electrode (1413) of the ) and the second transistor (1420 BIt provides an electrical connection between the gate electrodes (1413). In an embodiment, the interconnect (1434) is made of the same material as one or both of the gate electrodes (1413). In other embodiments, the interconnect (1434) is made of a different material from the gate electrodes (1413).

[0094] Now, referring to FIGS. 15a through 15d, cross-sectional examples of semiconductor devices (1500) according to various embodiments are illustrated. The illustrated embodiments illustrate different configurations of an etch stop layer that can be used with the backbone to provide interconnects across the backbone.

[0095] Now, referring to FIG. 15a, a cross-sectional example of a semiconductor device (1500) according to an embodiment is shown. In the embodiment, the semiconductor device (1500) comprises a substrate (1501) and a first transistor (1520) on the substrate (1501). A ) and the second transistor (1520 B Includes ). The first transistor (1520 A ) is a second transistor (1520) by means of a backbone (1510) B It can be separated from ). In the illustrated embodiment, the semiconductor channels (1506) of the transistors (1520) extend outward from the backbone (1510). In other embodiments, the semiconductor channels (1506) may have a GAA architecture similar to the architectures described above in relation to FIGS. 8a through 9b or FIGS. 11a through 11c. The channels (1506) may be surrounded by a gate electrode (1513), and an insulator (1503) may surround the transistors (1520). In the embodiment, the first transistor (1520 A ) may be a first conductivity type (e.g., P-type), and a second transistor (1520 B ) may be a second conductivity type (e.g., N-type). In other embodiments, the first transistor (1520 A ) and the second transistor (1520B ) can be of the same conductive type.

[0096] In the embodiment, the backbone (1510) consists of a pair of etch stop layers (1535 A and 1535 B Includes ). The first etching stop layer (1535 A ) has a top surface (1536) on the top surface (1533) of the top channels (1506). The second etching stop layer (1535) B ) has a bottom surface (1537) located below the bottom surface (1538) of the bottom channels (1506). Accordingly, interconnections (not shown) between the gate electrodes (1513) can be formed across the backbone (1510) above and below the channels (1506).

[0097] Now, referring to FIG. 15b, a cross-sectional example of a semiconductor device (1500) according to an additional embodiment is shown. The semiconductor device (1500) of FIG. 15b may be substantially similar to the semiconductor device (1500) of FIG. 15a, except that a single etch stop layer (1535) is used. The uppermost surface (1536) of the etch stop layer (1535) is above the uppermost surface (1533) of the uppermost channels (1506), and the lowermost surface (1537) of the etch stop layer (1535) is below the lowermost surface (1538) of the lowermost channel (1506).

[0098] Now, referring to FIG. 15c, a cross-sectional example of a semiconductor device (1500) according to an additional embodiment is shown. The semiconductor device (1500) of FIG. 15c may be substantially similar to the semiconductor device (1500) of FIG. 15b, except that the lowest surface (1537) of the etching stop layer (1535) extends to the end into the substrate (1501).

[0099] Now, referring to FIG. 15d, a cross-sectional example of a semiconductor device (1500) according to an additional embodiment is shown. The semiconductor device (1500) of FIG. 15d may be substantially similar to the semiconductor device (1500) of FIG. 15a, except that the etch stop layer (1535) is located at the bottom of the backbone (1510). In the embodiment, the bottom surface (1537) of the etch stop layer (1535) is below the bottom surface (1538) of the bottom channel (1506).

[0100] Now, referring to FIGS. 16a through 16d, examples of cross-sections along the length of the backbone (1610) according to the embodiment are illustrated. In the embodiment, semiconductor channels (1606) are illustrated with dashed lines to indicate that they are in and out of the plane of FIGS. 16a through 16d. Additionally, the locations of the source / drains (1605) are highlighted as being on opposite ends of the gate stack (1612).

[0101] Now, referring to FIG. 16a, a cross-sectional example of a backbone (1610) according to an embodiment is shown. As shown, the etch stop layer (1635) extends along the entire length of the backbone (1610). That is, the etch stop layer (1635) is located adjacent to the gate stack (1612) and the source / drain regions (1605). The etch stop layer (1635) is shown in a position (in the Z-direction) similar to the embodiment shown in FIG. 14a through 14c. However, it will be recognized that the etch stop layer (1635) (or a plurality of etch stop layers (1635)) may be located at any position (e.g., at the positions illustrated in FIG. 15a through 15d).

[0102] In FIG. 16b, an example of a cross-section of the backbone (1610) is shown after the interconnection portion (1634) is formed through the backbone (1610) according to an embodiment. As shown, the interconnection portion (1634) is positioned in a recess of the backbone (1610). Additionally, the interconnection portion (1634) is isolated by a gate stack (1612).

[0103] Now, referring to FIGS. 16c through 16d, cross-sectional examples of the backbone (1610) before and after the interconnection portion (1634) is formed across the backbone (1610) according to an embodiment are shown. The backbone (1610) of FIGS. 16c and 16d is similar to that of FIGS. 16a and 16b, except that the etch stop layer (1635) does not extend along the entire length of the backbone (1610). For example, the etch stop layer (1635) may be located close to the gate stack (1612). In some embodiments, the etch stop layer (1635) may extend beyond the gate stack (1612) without extending along the entire length of the backbone (1610).

[0104] Now, referring to FIG. 17a, a cross-sectional example of a semiconductor device (1700) according to an embodiment is shown. In the embodiment, the semiconductor device (1700) comprises a substrate (1701) and a pair of fork sheet transistors (1720) on the substrate (1701). A and 1720 B Includes ). The fork sheet transistors (1720) may be separated from each other by the backbone (1710). The plane of the illustrated embodiment is through the source / drain region (1705). The locations of the channels (1706) are shown with dashed lines to indicate that they are outside the plane shown in FIG. 17a. In the embodiment, the first transistor (1720 A ) may be a first conductivity type (e.g., P-type), and a second transistor (1720 B ) may be a second conductivity type (e.g., N-type). In other embodiments, the first transistor (1720A ) and the second transistor (1720 B ) may be of the same conductive type. As illustrated, the interconnect (1741) is the first transistor (1720 A The source / drain region (1705) of the second transistor (1720) B It is positioned through the backbone (1710) to be electrically coupled to the source / drain area (1705) of the ).

[0105] Referring to FIG. 17b, an example plan view of the semiconductor device (1700) of FIG. 17a according to an embodiment is shown. In FIG. 17b, a gate electrode (1713) and spacers (1711) are shown between the source / drain regions (1705) of each transistor (1720). Additionally, it is shown that an interconnection (1741) is isolated to a single side of the transistors (1720). For example, the first transistor (1720 A The lowest source / drain region (1705) of ) (as shown in FIG. 17b) is the second transistor (1720 B It is electrically coupled to the lowest source / drain region (1705) of the (as shown in FIG. 17b).

[0106] Now, referring to FIG. 18, an example plan view of a semiconductor device (1800) according to an additional embodiment is shown. The semiconductor device (1800) comprises a first fork sheet transistor (1820) separated by a backbone (1810). A ) and the second fork sheet transistor (1820 B Each transistor (1820) includes source / drain regions (1805) on opposite ends of the gate electrode (1813) and spacers (1811). Semiconductor channels connecting the source / drain regions (1805) are hidden by the gate electrode (1813). In an embodiment, the first transistor (1820 A) may be a first conductivity type (e.g., P-type), and a second transistor (1820 B ) may be a second conductivity type (e.g., N-type). In other embodiments, the first transistor (1820 A ) and the second transistor (1820 B ) can be of the same conductive type.

[0107] As illustrated, the semiconductor device (1800) includes a first interconnect (1834) and a second interconnect (1841). The first interconnect (1834) is a first transistor (1820 A ) and the second transistor (1820 B The gate electrodes (1813) of the ) are electrically coupled. The first interconnect (1834) may be similar to the interconnects described above in relation to FIGS. 13a through 16d. The second interconnect (1841) is the first transistor (1820 A ) and the second transistor (1820 B The source / drain regions (1805) of the ) are electrically coupled. The second interconnect (1841) may be similar to the interconnects described above in relation to FIG. 17a and FIG. 17b. In an embodiment, providing interconnects (1834 and 1841) may allow the semiconductor device (1800) to be wired as an inverter. Other circuit elements may also be formed by providing various interconnects through the backbone (1810) to connect the source / drain regions (1805) and / or gate electrodes (1813).

[0108] Now, referring to FIG. 19a, a cross-sectional example of a semiconductor device (1900) according to an embodiment is shown. In the embodiment, the semiconductor device (1900) comprises a substrate (1901) and fork sheet transistors (1920) on the substrate (1901). A and 1920 B ...includes ). The backbone (1910) is the first transistor (1920 A) the second transistor (1920 B Separated from ). The plane of the illustrated embodiment is through the source / drain region (1905). The locations of the channels (1906) are shown with dashed lines to indicate that they are outside the plane shown in FIG. 19a. In the embodiment, the first transistor (1920 A ) can be a first conductivity type (e.g., P-type) and a second transistor (1920 B ) may be a second conductivity type (e.g., N-type). In other embodiments, the first transistor (1920 A ) and the second transistor (1920 B ) can be of the same conductive type.

[0109] In an embodiment, conductive features may be provided on the substrate (1901). For example, a buried line (1918) may be located adjacent to the transistors (1920). Conductive pads (1919) may be located below the transistors (1920) and connected to the buried line (1918) (outside the plane of FIG. 19a). It will be recognized that the architecture of the conductive features of FIG. 19a is exemplary in nature and any back-side interconnection architecture may be used. For example, a back-side interconnection architecture may include any number of layers of routing, vias, pads, etc.

[0110] In an embodiment, etch-selective layers (1943) may be located between source / drain zones (1905) and pads (1919). In a specific embodiment, the etch-selective layers (1943) may be aligned with the channels (1906) placed over them. For example, the distance between the backbone (1910) and the surface (1942) of the channels (1906) facing away from the backbone (1910) may be equal to the distance between the backbone (1910) and the surface (1944) of the etch-selective layers (1943) facing away from the backbone (1910). In some examples, the etch-selective layers (1943) may be referred to as being self-aligned with the channels (1906) placed over them. Self-alignment may be attributed to the patterning of channels (1906) and etch-selective layers (1943) using the same lithography process (e.g., a single mask). In an embodiment, the etch-selective layer (1943) may be a material that is etch-selective with respect to surrounding materials. In a specific embodiment, the etch-selective layers comprise titanium nitride, but other materials may also be used.

[0111] Now, referring to FIG. 19b, a cross-sectional example of a semiconductor device (1900) is shown after the interconnection portion (1941) is placed across the backbone (1910) according to an embodiment. In the illustrated embodiment, the etch-selective layers (1943) are not etched and removed. That is, the etch-selective layers (1943) serve as an etch stop that prevents the interconnection portion (1941) from coming into contact with the pads (1919) placed underneath.

[0112] Now, referring to FIG. 19c, a cross-sectional example of a semiconductor device (1900) having an interconnect (1941) passing through etch-selective layers (1943) according to an embodiment is shown. In some embodiments, a residual portion (1943') of the etch-selective layers (1943) may remain adjacent to the interconnect (1941). The interconnect (1941) may come into contact with the pads (1919) placed underneath. As will be recognized by those skilled in the art, in a single semiconductor die, in addition to examples where the etch-selective layers (1943) remain to prevent connection to the pads (1919) placed underneath (e.g., similar to FIG. 19b), there may be examples where only the residual portion (1943') of the etch-selective layers (1943) remains. In another embodiment, the entire etching optional layer (1943) under each individual transistor of the transistors (1920) can be removed.

[0113] Now, referring to FIG. 20a, a cross-sectional example of a semiconductor device (2000) according to an embodiment is shown. The semiconductor device (2000) has a first etching selective layer (2043 A ) is the second etching optional layer (2043 B It may be substantially similar to a semiconductor device (1900), except that it includes a material different from ). For example, a first etchable optional layer (2043 A ) is the second etchable optional layer (2043 B It can have an etch selectivity for ). Thus, the first etch selective layer (2043 A ) or second etching optional layer (2043 B ) one of the other etchable optional layer (2043 A or 2043 B It can be removed without removing ).

[0114] In an embodiment, the semiconductor device (2000) comprises a substrate (2001) and fork sheet transistors (2020) on the substrate (2001). A and 2020 B ...includes ). The backbone (2010) includes the first transistor (2020 A ) the second transistor (2020 B Separated from ). The plane of the illustrated embodiment is through the source / drain regions (2005). The locations of the channels (2006) are shown with dashed lines to indicate that they are outside the plane shown in FIG. 20a. In the embodiment, the first transistor (2020 A ) may be a first conductivity type (e.g., P-type), and a second transistor (2020 B ) may be a second conductivity type (e.g., N-type). In other embodiments, the first transistor (2020 A ) and the second transistor (2020 B ) can be of the same conductive type.

[0115] In an embodiment, conductive features may be provided on a substrate (2001). For example, a buried line (2018) may be located adjacent to transistors (2020). Conductive pads (2019) may be located below transistors (2020) and connected to the buried line (2018) (outside the plane of FIG. 20a). It will be recognized that the architecture of the conductive features of FIG. 20a is exemplary in nature and any back-side interconnection architecture may be used. For example, a back-side interconnection architecture may include any number of layers of routing, vias, pads, etc.

[0116] Now, referring to FIG. 20b, a cross-sectional example of a semiconductor device (2000) is shown after an interconnection portion (2041) across a backbone (2010) is provided according to an embodiment. As shown, the first etching selective layer (2043 A Only ) is etched, so the first remaining portion (2043 A') is left behind. Second etching optional layer (2043 B ) remains substantially unchanged. Thus, the interconnect portion (2041) is the first transistor (2020 A It contacts only the pad (2019) below, and the second transistor (2020 B The pad (2019) below is electrically isolated from the interconnect (2041). This provides additional refinement and control of the interconnect layouts when multiple etch selective layers (2043) having different etch selectivities are used.

[0117] FIG. 21 illustrates a computing device (2100) according to one embodiment of the present disclosure. The computing device (2100) houses a board (2102). The board (2102) may include a plurality of components, including but not limited to a processor (2104) and at least one communication chip (2106). The processor (2104) is physically and electrically coupled to the board (2102). In some embodiments, at least one communication chip (2106) is also physically and electrically coupled to the board (2102). In additional embodiments, the communication chip (2106) is part of the processor (2104).

[0118] Depending on its applications, the computing device (2100) may include other components that may or may not be physically and electrically coupled to the board (2102). These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a satellite navigation system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., a hard disk drive, a compact disc (CD), a digital multifunction disc (DVD), etc.).

[0119] The communication chip (2106) enables wireless communications for the transmission of data to and from the computing device (2100). The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., capable of communicating data through the use of modulated electromagnetic radiation over a non-solid medium. Although the term does not imply that the associated devices do not include any wires, this may not be the case in some embodiments. The communication chip (2106) may implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 group), WiMAX (IEEE 802.16 group), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols designated as 3G, 4G, 5G and above. The computing device (2100) may include a plurality of communication chips (2106). For example, the first communication chip (2106) may be dedicated to shorter-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip (2106) may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0120] The processor (2104) of the computing device (2100) includes an integrated circuit die packaged within the processor (2104). In an embodiment, the integrated circuit die of the processor (2104) may include fork sheet transistors such as those described herein. The term “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts said electronic data into other electronic data that can be stored in registers and / or memory.

[0121] The communication chip (2106) also includes an integrated circuit die packaged within the communication chip (2106). In an embodiment, the integrated circuit die of the communication chip (2106) may include fork sheet transistors such as those described herein.

[0122] In additional implementations, other components housed within the computing device (2100) may include fork sheet transistors such as those described herein.

[0123] In various implementations, the computing device (2100) may be a laptop, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In additional implementations, the computing device (2100) may be any other electronic device that processes data.

[0124] FIG. 22 illustrates an interposer (2200) comprising one or more embodiments of the present disclosure. The interposer (2200) is an interposing substrate used to bridge a first substrate (2202) to a second substrate (2204). The first substrate (2202) may be, for example, an integrated circuit die. The second substrate (2204) may be, for example, a memory module, a computer motherboard, or another integrated circuit die. In an embodiment, one or both of the first substrate (2202) and the second substrate (2204) may include fork sheet transistors according to the embodiments described herein. Generally, the purpose of the interposer (2200) is to extend connections to a wider pitch or to re-route connections to different connections. For example, the interposer (2200) can combine an integrated circuit die to a ball grid array (BGA) (2206), and the BGA can subsequently be combined to a second substrate (2204). In some embodiments, the first and second substrates (2202 / 2204) are attached to opposite sides of the interposer (2200). In other embodiments, the first and second substrates (2202 / 2204) are attached to the same side of the interposer (2200). And in additional embodiments, three or more substrates are interconnected by the interposer (2200).

[0125] The interposer (2200) may be formed of an epoxy resin, a glass fiber-reinforced epoxy resin, a ceramic material, or a polymer material, such as polyimide. In additional embodiments, the interposer (2200) may be formed of alternative rigid or flexible materials that may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials.

[0126] The interposer (2200) may include metal interconnects (2208) and vias (2210), including but not limited to silicon through-vias (2212). The interposer (2200) may further include embedded devices (2214), including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer (2200). According to embodiments of the present disclosure, the devices and processes disclosed herein may be used in the manufacture of the interposer (2200).

[0127] Accordingly, embodiments of the present disclosure may include fork sheet transistors and resulting structures.

[0128] The foregoing description of the illustrated embodiments of the invention, including those described in the abstract, is not intended to be comprehensive or to limit the invention to the exact forms disclosed. While specific embodiments and examples of the invention are described herein for illustrative purposes, as will be recognized by those skilled in the art, various equivalent modifications are possible within the scope of the invention.

[0129] Such modifications may be made to the invention in consideration of the detailed description above. The terms used in the following claims should not be interpreted as limiting the invention to the specific embodiments disclosed in this specification and claims. Rather, the scope of the invention should be determined entirely by the following claims, which are to be interpreted in accordance with the established principles of claim interpretation.

[0130] Example 1: A semiconductor device comprises first transistor layers and second transistor layers above the first transistor layers, wherein the first transistor layers comprise a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone, and the second transistor layers comprise a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

[0131] Example 2: In the semiconductor device of Example 1, the individual transistors of the first transistor, the second transistor, the third transistor, and the fourth transistor each include a source, a drain, a semiconductor channel between the source and the drain, a gate dielectric surrounding portions of the semiconductor channel, and a gate electrode on the gate dielectric.

[0132] Example 3: In the semiconductor device of Example 2, the surface of the semiconductor channel is in direct contact with the first backbone or the second backbone.

[0133] Example 4: In the semiconductor device of Example 2, the semiconductor channel includes a plurality of semiconductor channels that are vertically stacked between the source and the drain.

[0134] Example 5: In the semiconductor devices of Examples 1 to 4, the first edge of the first backbone is offset from the first edge of the second backbone.

[0135] Example 6: In the semiconductor devices of Examples 1 to 5, the first edge of the first backbone is aligned with the first edge of the second backbone.

[0136] Example 7: In the semiconductor device of Example 6, the first backbone is connected to the second backbone.

[0137] Example 8: In the semiconductor devices of Examples 1 through 7, the first transistor and the second transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors.

[0138] Example 9: In the semiconductor devices of Examples 1 through 8, the first transistor and the third transistor are P-type transistors, and the second transistor and the fourth transistor are N-type transistors.

[0139] Example 10: The semiconductor devices of Examples 1 through 9 further include an insulating layer between the first transistor layers and the second transistor layers.

[0140] Example 11: The semiconductor device of Example 10 further includes an interconnection through an insulating layer for electrically coupling the gate electrode of the first transistor to the gate electrode of the third transistor.

[0141] Example 12: The semiconductor device of Example 10 further includes an interconnection through an insulating layer for electrically coupling the source or drain of the first transistor to the source or drain of the third transistor.

[0142] Example 13: In the semiconductor device of Example 12, the interconnection extends through the source or drain of the third transistor.

[0143] Example 14: In the semiconductor device of Example 13, the interconnect passes into the source or drain of the first transistor.

[0144] Example 15: In the semiconductor device of Example 12, the interconnection contacts the circumference of the source or drain of the third transistor, and the interconnection contacts the circumference of the source or drain of the first transistor.

[0145] Example 16: The semiconductor device of Examples 1 through 15 further comprises a contact portion below the first transistor layers — the contact portion is separated from the first transistor layers by an insulating layer — and an interconnect portion through the insulating layer — the interconnect portion electrically couples the contact portion to the first transistor —.

[0146] Example 17: In the semiconductor device of Example 16, the interconnection electrically couples the contact to the source or drain of the first transistor.

[0147] Example 18: In the semiconductor device of Example 16, the interconnection portion electrically couples the contact portion to the gate electrode of the first transistor.

[0148] Example 19: A semiconductor device comprises a backbone having a first edge and a second edge — the backbone is an insulating material — a first transistor adjacent to the first edge of the backbone, and a second transistor adjacent to the second edge of the backbone, and each of the first and second transistors comprises a source, a drain, a semiconductor channel between the source and the drain — the edge of the semiconductor channel closest to the backbone is spaced apart from the first edge of the backbone or the second edge of the backbone — a gate dielectric completely surrounding the perimeter of the semiconductor channel, and a gate electrode completely surrounding the gate dielectric.

[0149] Example 20: In the semiconductor device of Example 19, the edge of the semiconductor channel closest to the backbone is spaced from the first edge of the backbone or the second edge of the backbone by approximately 6 nm or less.

[0150] Example 21: The semiconductor device of Example 19 or Example 20 further comprises a liner under the backbone, the liner being a material having etch selectivity for the material of the backbone.

[0151] Example 22: The semiconductor devices of Examples 19 to 21 further include a liner on a portion of the first edge of the backbone and on a portion of the second edge of the backbone.

[0152] Example 23: In the semiconductor device of Example 22, the liner is between the source of the first transistor and the backbone, between the source of the second transistor and the backbone, between the drain of the first transistor and the backbone, and between the drain of the second transistor and the backbone.

[0153] Example 24: In the semiconductor device of Example 23, the portion of the first edge of the backbone adjacent to the gate electrode and the portion of the second edge of the backbone are not covered by a liner.

[0154] Example 25: In the semiconductor device of Example 24, the gap between the backbone and the edge of the semiconductor channel closest to the backbone is substantially equal to the thickness of the liner.

[0155] Example 26: In the semiconductor device of Example 24, a portion of the first edge of the backbone adjacent to the gate electrode and a portion of the second edge of the backbone are separated from the gate electrodes by a gate dielectric.

[0156] Example 27: The semiconductor devices of Examples 19 to 25 further comprise a liner on the first edge of the backbone and on the second edge of the backbone, and the liner comprises a catalytic oxidizing agent.

[0157] Example 28: In the semiconductor device of Example 27, the catalytic oxidizing agent includes aluminum and oxygen.

[0158] Example 29: In the semiconductor device of Example 27 or Example 28, the surface of the liner facing the semiconductor channel includes a concave portion.

[0159] Example 30: In the semiconductor device of Example 29, the recess is aligned with the semiconductor channel.

[0160] Example 31: The semiconductor devices of Examples 19 to 30 further include an air gap between the semiconductor channel and the backbone.

[0161] Example 32: In the semiconductor devices of Examples 19 to 31, the first transistor is an N-type transistor and the second transistor is a P-type transistor.

[0162] Example 33: In the semiconductor devices of Examples 19 to 32, the semiconductor channel comprises a plurality of semiconductor channels arranged in a vertical stack between the source and the drain.

[0163] Example 34: A semiconductor device comprises a backbone having a first edge and a second edge — the backbone is an insulating material — a first transistor adjacent to the first edge of the backbone, a second transistor adjacent to the second edge of the backbone — individual transistors of the first transistor and the second transistor include a source, a drain, a semiconductor channel between the source and the drain, a gate dielectric surrounding at least a portion of the perimeter of the semiconductor channel, and a gate electrode on the gate dielectric — and an interconnection for electrically coupling the first transistor to the second transistor — the interconnection passes through the backbone —.

[0164] Example 35: In the semiconductor device of Example 34, the interconnection connects the gate electrode of the first transistor to the gate electrode of the second transistor.

[0165] Example 36: In the semiconductor device of Example 35, the backbone includes a first layer and a second layer, and the first layer has an etch selectivity for the second layer.

[0166] Example 37: In the semiconductor device of Example 36, the uppermost surface of the first layer is on the uppermost surface of the semiconductor channel of the first transistor and the uppermost surface of the semiconductor channel of the second transistor, and the second layer is adjacent to the semiconductor channel of the first transistor and the semiconductor channel of the second transistor.

[0167] Example 38: In the semiconductor device of Example 37, the interconnection contacts the uppermost surface on the second layer.

[0168] Example 39: In the semiconductor devices of Examples 36 to 38, the lowest surface of the first layer is below the lowest surface of the semiconductor channel of the first transistor and the lowest surface of the semiconductor channel of the second transistor, and the second layer is adjacent to the semiconductor channel of the first transistor and the semiconductor channel of the second transistor.

[0169] Example 40: In the semiconductor device of Example 39, the interconnection portion contacts the lowest surface of the first layer.

[0170] Example 41: In the semiconductor devices of Examples 36 to 40, the uppermost surface of the first layer is on the uppermost surface of the semiconductor channel of the first transistor and the uppermost surface of the semiconductor channel of the second transistor, and the second layer is on the first layer.

[0171] Example 42: In the semiconductor devices of Examples 36 to 41, both the second layer and the first layer extend along the entire length of the backbone.

[0172] Example 43: In the semiconductor devices of Examples 36 to 41, the length of the first layer is smaller than the length of the second layer.

[0173] Example 44: In the semiconductor device of Example 43, the first layer is aligned with the gate electrode of the first transistor and the gate electrode of the second transistor.

[0174] Example 45: In the semiconductor devices of Examples 34 to 44, the interconnection unit connects the source or drain of the first transistor to the source or drain of the second transistor.

[0175] Example 46: The semiconductor device of Example 45 further includes a first etch-selective layer under a first transistor and a second etch-selective layer under a second transistor.

[0176] Example 47: In the semiconductor device of Example 46, the first etch-selective layer is the same material as the second etch-selective layer.

[0177] Example 48: In the semiconductor device of Example 46, the first etch selective layer has an etch selectivity for the second etch selective layer.

[0178] Example 49: In the semiconductor device of Example 46, the first edge of the first etching selective layer facing away from the backbone is spaced apart from the backbone by a first spacing equal to the second spacing between the second edge of the semiconductor channel of the first transistor facing away from the backbone and the backbone, and the third edge of the second etching selective layer facing away from the backbone is spaced apart from the backbone by a third spacing equal to the fourth spacing between the fourth edge of the semiconductor channel of the second transistor facing away from the backbone and the backbone.

[0179] Example 50: In the semiconductor device of Example 49, the width of one or both of the first etch-selective layer and the second etch-selective layer is smaller than the width of the semiconductor channel placed over it.

[0180] Example 51: In the semiconductor device of Example 46, in order to electrically couple one or both of the source or drain of the first transistor to the contacts below the first transistor and the second transistor, the lowest interconnect passes adjacent to one or both of the first etch-selective layer and the second etch-selective layer.

[0181] Example 52: In the semiconductor device of Examples 34 to 51, the interconnection comprises a first interconnection passing through the backbone — the first interconnection electrically couples the gate electrode of the first transistor to the gate electrode of the second transistor — and a second interconnection passing through the backbone — the second interconnection electrically couples the source or drain of the first transistor to the source or drain of the second transistor —.

[0182] Example 53: In the semiconductor devices of Examples 34 to 52, the semiconductor device is an inverter.

[0183] Example 54: In the semiconductor devices of Examples 34 to 53, the first transistor is an N-type transistor and the second transistor is a P-type transistor.

[0184] Example 55: In the semiconductor devices of Examples 34 to 53, the semiconductor channel comprises a plurality of semiconductor channels arranged in a vertical stack between the source and the drain.

[0185] Example 56: An electronic system comprises a board, an electronic package connected to the board, and a die electrically coupled to the electronic package, wherein the die comprises a backbone having a first edge and a second edge — the backbone is an insulating material — a first transistor adjacent to the first edge of the backbone, a second transistor adjacent to the second edge of the backbone, and an interconnection for electrically coupling the first transistor to the second transistor — the interconnection passes through the backbone —.

[0186] Example 57: In the electronic system of Example 56, individual transistors of the first transistor and the second transistor include a source, a drain, a semiconductor channel between the source and the drain, a gate dielectric surrounding at least a portion of the perimeter of the semiconductor channel, and a gate electrode on the gate dielectric.

[0187] Example 58: In the electronic system of Example 57, the gate dielectric completely surrounds the perimeter of the semiconductor channel.

[0188] Example 59: The electronic systems of Examples 56 through 58 further include a third transistor above the first transistor, a fourth transistor above the second transistor, and a second backbone between the third transistor and the fourth transistor.

[0189] Example 60: In the electronic system of Example 59, the third transistor is electrically coupled to the first transistor, the fourth transistor is electrically coupled to the second transistor, or the third transistor is electrically coupled to the first transistor and the fourth transistor is electrically coupled to the second transistor.

Claims

Claim 1 A semiconductor device comprising: first transistor layers; and second transistor layers above the first transistor layers, wherein the first transistor layers comprise a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone, and the second transistor layers comprise a second backbone — wherein the second backbone is distinct from the first backbone and separated from the first backbone, and the second backbone overlaps at least partially perpendicularly with the first backbone — a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone. Claim 2 A semiconductor device according to claim 1, wherein each transistor of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises: a source; a drain; a semiconductor channel between the source and the drain; a gate dielectric surrounding portions of the semiconductor channel; and a gate electrode on the gate dielectric. Claim 3 A semiconductor device according to paragraph 2, wherein the surface of the semiconductor channel is in direct contact with the first backbone or the second backbone. Claim 4 In paragraph 2, the semiconductor device comprises a plurality of semiconductor channels arranged in a vertical stack between the source and the drain. Claim 5 A semiconductor device according to claim 1, wherein the first edge of the first backbone is offset from the first edge of the second backbone. Claim 6 A semiconductor device according to claim 1, wherein the first edge of the first backbone is aligned with the first edge of the second backbone. Claim 7 In paragraph 6, the semiconductor device, wherein the first backbone is connected to the second backbone. Claim 8 A semiconductor device according to claim 1, wherein the first transistor and the second transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors. Claim 9 A semiconductor device according to claim 1, wherein the first transistor and the third transistor are P-type transistors, and the second transistor and the fourth transistor are N-type transistors. Claim 10 A semiconductor device according to claim 1, further comprising an insulating layer between the first transistor layers and the second transistor layers. Claim 11 A semiconductor device according to claim 10, further comprising an interconnection portion through the insulating layer for electrically coupling the gate electrode of the first transistor to the gate electrode of the third transistor. Claim 12 A semiconductor device according to claim 10, further comprising an interconnection portion through the insulating layer for electrically coupling the source or drain of the first transistor to the source or drain of the third transistor. Claim 13 In claim 12, the semiconductor device, wherein the interconnection extends through the source or drain of the third transistor. Claim 14 In paragraph 13, the semiconductor device, wherein the interconnection passes into the source or drain of the first transistor. Claim 15 A semiconductor device according to claim 12, wherein the interconnection portion contacts the circumference of the source or drain of the third transistor, and the interconnection portion contacts the circumference of the source or drain of the first transistor. Claim 16 A semiconductor device according to claim 1, further comprising: a contact portion below the first transistor layers — said contact portion is separated from the first transistor layers by an insulating layer — and an interconnect portion through the insulating layer — said interconnect portion electrically couples the contact portion to the first transistor —. Claim 17 In claim 16, the semiconductor device wherein the interconnection portion electrically couples the contact portion to the source or drain of the first transistor. Claim 18 A semiconductor device according to claim 16, wherein the interconnection portion electrically couples the contact portion to the gate electrode of the first transistor. Claim 19 A semiconductor device comprising: a backbone having a first edge and a second edge — said backbone is an insulating material and has a liner on a portion of said first edge of the backbone and on a portion of said second edge of the backbone —; a first transistor adjacent to the first edge of the backbone; and a second transistor adjacent to the second edge of the backbone, wherein each of the first transistor and the second transistor comprises a source, a drain, a semiconductor channel between said source and said drain — the edge of said semiconductor channel closest to the backbone is spaced apart from said first edge of the backbone or said second edge of the backbone — a gate dielectric completely surrounding the perimeter of said semiconductor channel, and a gate electrode completely surrounding said gate dielectric. Claim 20 A semiconductor device according to claim 19, wherein the edge of the semiconductor channel closest to the backbone is spaced from the first edge of the backbone or the second edge of the backbone by 6 nm or less. Claim 21 A semiconductor device comprising: a backbone having a first edge and a second edge — said backbone is an insulating material —; a liner below said backbone — said liner is a material having etch selectivity for the material of said backbone —; a first transistor adjacent to the first edge of said backbone; and a second transistor adjacent to the second edge of said backbone, wherein each of said transistors of said first transistor and said second transistor comprises a source, a drain, a semiconductor channel between said source and said drain — said edge of said semiconductor channel closest to said backbone is spaced apart from said first edge of said backbone or said second edge of said backbone — a gate dielectric completely surrounding the perimeter of said semiconductor channel, and a gate electrode completely surrounding said gate dielectric. Claim 22 delete Claim 23 An electronic system comprising: a board; an electronic package connected to the board; and a die electrically coupled to the electronic package, wherein the die comprises: a backbone having a first edge and a second edge — said backbone is an insulating material —; a first transistor adjacent to the first edge of the backbone, a second transistor adjacent to the second edge of the backbone, and an interconnection for electrically coupling the first transistor to the second transistor — said interconnection passes through the backbone —. Claim 24 An electronic system according to claim 23, wherein individual transistors of the first transistor and the second transistor comprise: a source; a drain; a semiconductor channel between the source and the drain; a gate dielectric surrounding at least a portion of the perimeter of the semiconductor channel; and a gate electrode on the gate dielectric. Claim 25 In claim 24, the electronic system wherein the gate dielectric completely surrounds the perimeter of the semiconductor channel.

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