Semiconductor device

Abstract

A semiconductor device comprises a semiconductor substrate having a first surface and a second surface facing each other, a transistor on the first surface of the semiconductor substrate, a power rail disposed on the first surface of the semiconductor substrate and electrically connected to the transistor, lower wirings on the second surface of the semiconductor substrate, a through via penetrating the semiconductor substrate and connecting a corresponding lower wiring among the lower wirings to the power rail, and a capacitor disposed on the second surface of the semiconductor substrate and disposed between the lower wirings. The lower wirings include a pair of lower wirings spaced apart from each other in a first direction perpendicular to the second surface of the semiconductor substrate, and the capacitor is disposed between the pair of lower wirings and electrically connected to the pair of lower wirings.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device comprising field-effect transistors. Background Technology

[0002] Semiconductor devices include integrated circuits composed of MOS (Metal Oxide Semiconductor) FETs. As the size and design rules of semiconductor devices gradually shrink, the scale-down of MOS FETs is also accelerating. The operating characteristics of semiconductor devices may degrade as the size of MOS FETs is reduced. Accordingly, various methods are being studied to form semiconductor devices with superior performance while overcoming the limitations associated with high integration of semiconductor devices. The problem to be solved

[0003] The technical problem to be solved by the present invention is to provide a semiconductor device with improved integration density and electrical characteristics. means of solving the problem

[0004] A semiconductor device according to the present invention may include: a semiconductor substrate having a first surface and a second surface facing each other; a transistor on the first surface of the semiconductor substrate; a power rail disposed on the first surface of the semiconductor substrate and electrically connected to the transistor; lower wirings on the second surface of the semiconductor substrate; a through-via penetrating the semiconductor substrate and connecting a corresponding lower wiring among the lower wirings to the power rail; and a capacitor disposed on the second surface of the semiconductor substrate and disposed between the lower wirings. The lower wirings may include a pair of lower wirings spaced apart from each other in a first direction perpendicular to the second surface of the semiconductor substrate. The capacitor may be disposed between the pair of lower wirings and electrically connected to the pair of lower wirings.

[0005] A semiconductor device according to the present invention may include: a semiconductor substrate having a first surface and a second surface facing each other; active patterns on the first surface of the semiconductor substrate; gate electrodes disposed on the first surface of the semiconductor substrate and crossing the active patterns; a power rail disposed on the first surface of the semiconductor substrate and electrically connected to a source / drain region of a corresponding active pattern among the active patterns; lower wirings on the second surface of the semiconductor substrate; through vias penetrating the semiconductor substrate and connecting a corresponding lower wiring among the lower wirings to the power rail; and a capacitor disposed on the second surface of the semiconductor substrate and disposed between the lower wirings. The lower wirings may be spaced apart from each other in a first direction perpendicular to the second surface of the semiconductor substrate and may extend in a second direction parallel to the second surface of the semiconductor substrate. The capacitor may be disposed between a pair of lower wirings spaced apart from each other in the first direction among the lower wirings and may be electrically connected to the pair of lower wirings. Effects of the invention

[0006] According to the concept of the present invention, a power transmission network may be disposed on a second surface of a semiconductor substrate and may be electrically connected to a power rail disposed on a first surface of the semiconductor substrate through a through-via. Accordingly, it is easy to increase the integration density of the semiconductor device. In addition, the power transmission network may include at least one capacitor disposed between vertically spaced lower wires. The capacitor may function as a decoupling capacitor, and accordingly, the power integrity characteristics of the power transmission network may be improved. Thus, a semiconductor device with improved integration density and electrical characteristics may be provided. Brief explanation of the drawing

[0007] FIG. 1 is a plan view of a semiconductor device according to some embodiments of the present invention. FIGS. 2a, FIGS. 2b, FIGS. 2c, and FIGS. 2d are cross-sectional views along the lines A-A', B-B', C-C', and D-D' of FIG. 1, respectively. FIGS. 3a to 3d and FIGS. 4a to 4d are cross-sectional views illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. FIG. 5 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. Figure 6 is an enlarged view of section P in Figure 5. FIG. 7 is a drawing showing a method for manufacturing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to line A-A' of FIG. 1. FIG. 8 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. FIGS. 9 and FIGS. 10 are drawings illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention, and are cross-sectional views corresponding to line A-A' of FIG. 1. FIG. 11 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. FIG. 12 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. FIG. 13 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. FIG. 14 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. Specific details for implementing the invention

[0008] The present invention will be described in detail below by explaining embodiments of the present invention with reference to the attached drawings.

[0009] FIG. 1 is a plan view of a semiconductor device according to some embodiments of the present invention. FIG. 2a, FIG. 2b, FIG. 2c and FIG. 2d are cross-sectional views along the lines A-A', B-B', C-C' and D-D' of FIG. 1, respectively.

[0010] Referring to FIGS. 1, 2a to 2d, a semiconductor substrate (100) having a first surface (100a) and a second surface (100b) facing each other may be provided. The semiconductor substrate (100) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0011] A device isolation film (ST) may be disposed adjacent to the first surface (100a) within the semiconductor substrate (100) and may define active regions (AR). The semiconductor substrate (100) may include the active regions (AR) defined by the device isolation film (ST), and the first surface (100a) of the semiconductor substrate (100) may correspond to the upper surfaces of the active regions (AR). The active regions (AR) may protrude from the semiconductor substrate (100) along a first direction (D1) perpendicular to the second surface (100b) of the semiconductor substrate (100), and the device isolation film (ST) may be interposed between the active regions (AR). The active regions (AR) may be spaced apart from each other in a second direction (D2) with the device isolation film (ST) in between and may extend in a third direction (D3). The second direction (D2) and the third direction (D3) may be parallel to the second surface (100b) of the semiconductor substrate (100) and may intersect each other. The active regions (AR) may be PMOSFET regions or NMOSFET regions. The device isolation film (ST) may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0012] A plurality of active patterns (AP) may protrude along the first direction (D1) from each upper surface of the active regions (AR) (i.e., the first surface (100a) of the semiconductor substrate (100). The plurality of active patterns (AP) may be spaced apart from each other in the second direction (D2) on each active region (AR) and may extend in the third direction (D3). The device isolation film (ST) may extend over each upper surface of the active regions (AR) and may cover the sides of the plurality of active patterns (AP). The plurality of active patterns (AP) may be spaced apart from each other in the second direction (D2) with the device isolation film (ST) in between. The plurality of active patterns (AP) may be a part of the semiconductor substrate (100) protruding from each of the upper surfaces of the active regions (AR) (i.e., the first surface (100a) of the semiconductor substrate (100)).

[0013] Each of the plurality of active patterns (AP) may include an active pin (AF) protruding over the device isolation film (ST). The active pin (AF) may not be covered by the device isolation film (ST). That is, the device isolation film (ST) may expose the active pin (AF). Each of the active pins (AF) of the plurality of active patterns (AP) may include a channel region (CH) and source / drain regions (SD). The channel region (CH) may be interposed between the source / drain regions (SD). The source / drain regions (SD) may be epitaxial patterns formed by an optional epitaxial growth process using each active pattern (AP) as a seed. The source / drain regions (SD) may include, for example, at least one of silicon, silicon-germanium, and silicon carbide. The channel region (CH) may be part of each active pattern (AP) extended between the source / drain regions (SD).

[0014] Gate structures (GS) may be disposed on the first surface (100a) of the semiconductor substrate (100) and may traverse the plurality of active patterns (AP). The gate structures (GS) may extend in the second direction (D2) and may be spaced apart from each other in the third direction (D3). Each of the gate structures (GS) may overlap perpendicularly (e.g., in the first direction (D1)) the channel region (CH) of each of the active pins (AF) of the plurality of active patterns (AP). Each of the gate structures (GS) may cover the upper surface of the channel region (CH) and may cover the sides facing each other in the second direction (D2) of the channel region (CH). The source / drain regions (SD) may be disposed on each side of the gate structures (GS).

[0015] Each of the gate structures (GS) may include a gate electrode (GE), a gate insulation pattern (GI) between the gate electrode (GE) and the channel region (CH), gate spacers (GSP) on the sides of the gate electrode (GE), and a gate capping pattern (GC) on the top surface of the gate electrode (GE). The gate insulation pattern (GI) may extend between the gate electrode (GE) and the gate spacers (GSP), and the top surface of the gate insulation pattern (GI) may be substantially co-plane with the top surface of the gate electrode (GE). The gate electrode (GE) may cover the top surface of the channel region (CH) and the sides facing each other in the second direction (D2) of the channel region (CH), and may extend onto the top surface of the device isolation film (ST). The gate insulation pattern (GI) may be interposed between the upper surface of the channel region (CH) and each of the sides facing each other in the second direction (D2) of the channel region (CH) and the gate electrode (GE), and may extend between the upper surface of the device isolation film (ST) and the gate electrode (GE).

[0016] According to some embodiments, the gate electrode (GE), the channel region (CH), and the source / drain regions (SD) may constitute a Fin Field Effect Transistor. According to other embodiments, unlike what is illustrated, the channel region (CH) may include a plurality of semiconductor patterns spaced apart from each other in the first direction (D1), in which case the gate electrode (GE), the channel region (CH), and the source / drain regions (SD) may constitute a Multi Bridge Channel Field Effect Transistor.

[0017] The gate electrode (GE) may comprise a doped semiconductor, a conductive metal nitride, and / or a metal. The gate insulating pattern (GI) may comprise at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a high dielectric film. The high dielectric film may comprise a material having a dielectric constant greater than that of a silicon oxide film, such as a hafnium oxide film (HfO), an aluminum oxide film (AlO), or a tantalum oxide film (TaO). Each of the gate spacers (GSP) and the gate capping pattern (GC) may comprise at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0018] A first upper interlayer insulating film (110) may be disposed on the first surface (100a) of the semiconductor substrate (100) and may cover the gate structure (GS) and the source / drain regions (SD). The first upper interlayer insulating film (110) may cover the upper surface of the device isolation film (ST). The upper surface of the first upper interlayer insulating film (110) may be substantially co-planar with the upper surface of the gate capping pattern (GC). The gate spacer (GSP) may be interposed between the gate capping pattern (GC) and the first upper interlayer insulating film (110). A second upper interlayer insulating film (120) may be disposed on the first upper interlayer insulating film (110). The second upper interlayer insulating film (120) may cover the upper surface of the gate capping pattern (GC). The first and second upper interlayer insulating films (110, 120) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or low dielectric films.

[0019] Source / drain contacts (CT1) can be electrically connected to source / drain regions (SD) by penetrating the first upper interlayer insulating film (110) and the second upper interlayer insulating film (120). The source / drain contacts (CT1) can be positioned on both sides of each gate structure (GS) and may have a bar shape extending in the second direction (D2). Each of the source / drain contacts (CT1) can be connected to a plurality of source / drain regions (SD) spaced apart from each other in the second direction (D2).

[0020] Gate contacts (CT2) may be disposed within the second interlayer insulating film (120). Each of the gate contacts (CT2) may be connected to the gate electrode (GE) by penetrating the second upper interlayer insulating film (120) and the gate capping pattern (GC). The upper surfaces of the source / drain contacts (CT1) and the gate contacts (CT2) may be substantially co-plane with the upper surface of the second upper interlayer insulating film (120). For example, the upper surfaces of the source / drain contacts (CT1) and the gate contacts (CT2) may be at substantially the same height as the upper surface of the second upper interlayer insulating film (120) with respect to the first surface (100a) of the semiconductor substrate (100). The source / drain contacts (CT1) and the gate contacts (CT2) may contain the same conductive material. The source / drain contacts (CT1) and the gate contacts (CT2) may include a metallic material, and, for example, may include at least one of aluminum, copper, tungsten, molybdenum, and cobalt.

[0021] A third upper interlayer insulating film (130) may be disposed on the second upper interlayer insulating film (120) and may cover the upper surfaces of the source / drain contacts (CT1) and the gate contacts (CT2). First upper wirings (132) and first upper vias (134) may be disposed within the third upper interlayer insulating film (130). The first upper wirings (132) may penetrate the upper surface of the third upper interlayer insulating film (130), and the upper surfaces of the first upper wirings (132) may be substantially co-planes with the upper surface of the third upper interlayer insulating film (130). That is, the upper surfaces of the first upper wirings (132) may be at substantially the same height as the upper surface of the third upper interlayer insulating film (130) with respect to the first surface (100a) of the semiconductor substrate (100). The first upper vias (134) may be positioned between the source / drain contacts (CT1) and the first upper wires (132), and between the gate contacts (CT2) and the first upper wires (132), and may penetrate the lower portion of the third upper interlayer insulating film (130). Each of the source / drain contacts (CT1) and the gate contacts (CT2) may be electrically connected to a corresponding first upper wire (132) among the first upper wires (132) through a corresponding first upper via (134) among the first upper vias (134).

[0022] According to some embodiments, the power rail (POR) may be disposed within the third upper interlayer insulating film (130). The power rail (POR) may be located at substantially the same height as the first upper wirings (132) from the first surface (100a) of the semiconductor substrate (100). The power rail (POR) may cross the gate structures (GS) and may have a line shape extending in the third direction (D3). The first upper vias (134) may be disposed between the source / drain contacts (CT1) and the power rail (POR), and at least one of the source / drain contacts (CT1) may be electrically connected to the power rail (POR) through the corresponding first upper via (134) among the first upper vias (134). According to other embodiments, unlike illustrated, the power rail (POR) may be embedded within the device isolation film (ST). In this case, at least one of the source / drain contacts (CT1) may include an extension extending into the device isolation layer (ST) and may be electrically connected to the power rail (POR) through the extension.

[0023] A fourth upper interlayer insulating film (140) may be disposed on the third upper interlayer insulating film (130) and may cover the upper surfaces of the first upper wirings (132) and the power rail (POR). Second upper wirings (142) and second upper vias (144) may be disposed within the fourth upper interlayer insulating film (140). The second upper wirings (142) may penetrate the upper surface of the fourth upper interlayer insulating film (140), and the upper surfaces of the second upper wirings (142) may be substantially co-planes with the upper surface of the fourth upper interlayer insulating film (140). That is, the upper surfaces of the second upper wirings (142) may be at substantially the same height as the upper surface of the fourth upper interlayer insulating film (140) with respect to the first surface (100a) of the semiconductor substrate (100). The second upper vias (144) may be positioned between the first upper wires (132) and the second upper wires (142), and between the power rail (POR) and the second upper wires (142), and may penetrate the lower portion of the fourth upper interlayer insulating film (140). Each of the first upper wires (132) and the power rail (POR) may be electrically connected to a corresponding second upper wire (142) among the second upper wires (142) through a corresponding second upper via (144) among the second upper vias (144).

[0024] The third and fourth upper interlayer insulating films may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or low dielectric films. The first and second upper wirings (132, 142), the power rail (POR), and the first and second upper vias (134, 144) may include at least one of metal and conductive metal nitride.

[0025] A through-via (200) may penetrate the semiconductor substrate (100) and be connected to the power rail (POR). According to some embodiments, the through-via (200) may penetrate the device isolation layer (ST), the first upper interlayer insulating layer (110), and the second upper interlayer insulating layer (120), and penetrate the bottom of the third upper interlayer insulating layer (130) to be connected (or contacted) to the bottom surface of the power rail (POR). According to other embodiments, the power rail (POR) may be embedded within the device isolation layer (ST), in which case the through-via (200) may penetrate the semiconductor substrate (100) to be connected (or contacted) to the bottom surface of the power rail (POR). The through-via (200) may include a conductive material, and, for example, may include a metal and / or a conductive metal nitride.

[0026] A power delivery network (PDN) may be disposed on the second surface (100b) of the semiconductor substrate (100). The power delivery network (PDN) may include lower contacts (152), first lower wires (162), first lower vias (168), second lower wires (182), second lower vias (188), and third lower wires (192) disposed on the second surface (100b) of the semiconductor substrate (100).

[0027] The first lower wiring (162) may be spaced apart from the second surface (100b) of the semiconductor substrate (100) along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (for example, the first direction (D1)), and the lower contacts (152) may be positioned between the second surface (100b) of the semiconductor substrate (100) and the first lower wiring (162). The lower contacts (152) may be electrically connected to the first lower wiring (162). The power transmission network (PDN) may further include a lower insulating film (150) positioned on the second surface (100b) of the semiconductor substrate (100) and covering the lower contacts (152). The first lower wiring (162) may be disposed on the lower insulating film (150) and may extend in a direction parallel to the second surface (100b) of the semiconductor substrate (100) (for example, the second direction (D2)). Each of the lower contacts (152) may penetrate the lower insulating film (150) and may be electrically connected to a corresponding one of the first lower wirings (162).

[0028] The second lower wirings (182) may be spaced apart from the first lower wirings (162) along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (for example, the first direction (D1)), and the first lower vias (168) may be disposed between the first lower wirings (162) and the second lower wirings (182). The first lower vias (168) may electrically connect the first lower wirings (162) and the second lower wirings (182) to each other. The power transmission network (PDN) may further include a first lower interlayer insulating film (160) and a second lower interlayer insulating film (180) stacked sequentially on the lower insulating film (150). The first lower interlayer insulating film (160) may be disposed between the lower insulating film (150) and the second lower interlayer insulating film (180) and may cover the first lower wirings (162). The second lower wirings (182) may be disposed on the second lower interlayer insulating film (180) and may extend in a direction parallel to the second surface (100b) of the semiconductor substrate (100) (e.g., the second direction (D2)). Each of the first lower vias (168) may penetrate the first lower interlayer insulating film (160) and the second lower interlayer insulating film (180) and may extend in a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (e.g., the first direction (D1)). Each of the first lower vias (168) can be electrically connected to a corresponding one of the first lower wires (162) and a corresponding one of the second lower wires (182).

[0029] The third lower wirings (192) may be spaced apart from the second lower wirings (182) along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (e.g., the first direction (D1)), and the second lower vias (188) may be positioned between the second lower wirings (182) and the third lower wirings (192). The second lower vias (188) may electrically connect the second lower wirings (182) and the third lower wirings (192) to each other. The power transmission network (PDN) may further include a third lower interlayer insulating film (190) positioned on the second lower interlayer insulating film (180) and covering the second lower wirings (182), the second lower vias (188), and the third lower wirings (192). The third dissecting wires (192) may extend in a direction parallel to the second surface (100b) of the semiconductor substrate (100) (e.g., the second direction (D2)). Each of the second lower vias (188) may penetrate the third lower interlayer insulating film (190) and may extend in a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (e.g., the first direction (D1)). Each of the second lower vias (188) may be electrically connected to a corresponding one of the second lower wires (182) and a corresponding one of the third lower wires (192).

[0030] The lower contacts (152), the first lower wiring (162), the first lower vias (168), the second lower wiring (182), the second lower vias (188), and the third lower wiring (192) may comprise a conductive material (e.g., a metal (e.g., copper) and / or a conductive metal nitride). The lower insulating film (150) and the first to third lower interlayer insulating films (160, 180, 190) may comprise at least one of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a low dielectric film.

[0031] Although not illustrated, the power transmission network (PDN) may further include additional lower wires spaced apart from the third lower wires (192) along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (e.g., the first direction (D1)), and additional lower vias between the third lower wires (192) and the additional lower wires.

[0032] The power transmission network (PDN) may further include at least one capacitor (170) disposed between the first lower wires (162) and the second lower wires (182), between the second lower wires (182) and the third lower wires (192), and / or between the first lower wires (162) and the third lower wires (192). According to some embodiments, as shown in FIG. 2a, the at least one capacitor (170) may be disposed between the first lower wires (162) and the second lower wires (182).

[0033] According to some embodiments, the capacitor (170) may be positioned between a corresponding first lower wire (162) among the first lower wires (162) and a corresponding second lower wire (182) among the second lower wires (182), and may be electrically connected to the corresponding first lower wire (162) and the corresponding second lower wire (182). The capacitor (170) may be positioned on the first lower interlayer insulating film (160), and the second lower interlayer insulating film (180) may cover the capacitor (170).

[0034] The capacitor (170) may include a first electrode (172), a second electrode (176), and a dielectric (174) between them. The first electrode (172), the dielectric (174), and the second electrode (174) may be stacked sequentially along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) on the first lower interlayer insulating film (160) (e.g., the first direction (D1)) and may extend in a direction parallel to the second surface (100b) of the semiconductor substrate (100) (e.g., the second direction (D2)). Accordingly, the capacitor (170) may have a plate shape extending in a direction parallel to the second surface (100b) of the semiconductor substrate (100) (e.g., the second direction (D2)). The corresponding first lower wiring (162), the capacitor (170), and the corresponding second lower wiring (182) may be extended parallel along a direction parallel to the second surface (100b) of the semiconductor substrate (100) (e.g., the second direction (D2)). Each of the first electrode (172) and the second electrode (176) may include a conductive material (e.g., a metal), and the dielectric (174) may include a dielectric material such as ceramic.

[0035] The power transmission network (PDN) may further include a first electrode contact (164) between the first electrode (172) of the capacitor (170) and the corresponding first lower wiring (162), and a second electrode contact (166) between the second electrode (176) of the capacitor and the corresponding second lower wiring (182). The first electrode contact (164) may penetrate the first lower interlayer insulating film (160) and electrically connect the first electrode (172) of the capacitor (170) and the corresponding first lower wiring (162). The second electrode contact (166) may penetrate the second lower interlayer insulating film (180) and electrically connect the second electrode (176) of the capacitor and the corresponding second lower wiring (182). The first electrode contact (164) and the second electrode contact (166) may include a conductive material (e.g., a metal and / or a conductive metal nitride).

[0036] The through-via (200) may penetrate the semiconductor substrate (100) and may be connected to the power rail (POR) and the power transmission network (150). The through-via (200) may be connected to one of the corresponding lower contacts (152) of the power transmission network (PDN) and may be connected to the bottom surface of the power rail (POR) by extending vertically along the first direction (D1). The power transmission network (PDN) may apply a power voltage (VDD) or a ground voltage (VSS) to the power rail (POR) through the through-via (200). The power rail (POR) may apply a power voltage (VDD) or a ground voltage (VSS) to a corresponding source / drain contact (CT1) among the source / drain contacts (CT1).

[0037] According to the concept of the present invention, the power transmission network (PDN) may be disposed on the second surface (100b) of the semiconductor substrate (100) and may be electrically connected to the power rail (POR) disposed on the first surface (100a) of the semiconductor substrate (100) through the through via (200). Accordingly, the integration density of the semiconductor device may be easily increased. Additionally, the power transmission network (PDN) may include the at least one capacitor (170) disposed between the first lower wiring (162) and the second lower wiring (182), between the second lower wiring (182) and the third lower wiring (192), and / or between the first lower wiring (162) and the third lower wiring (192). The capacitor (170) can function as a decoupling capacitor, and accordingly, the power integrity characteristics of the power transmission network (PDN) can be improved. Thus, a semiconductor device with improved integration density and electrical characteristics can be provided.

[0038] FIGS. 3a to 3d and FIGS. 4a to 4d are drawings illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention, FIGS. 3a and 4a are cross-sectional views corresponding to line A-A' of FIG. 1, FIGS. 3b and 4b are cross-sectional views corresponding to line B-B' of FIG. 1, FIGS. 3c and 4c are cross-sectional views corresponding to line C-C' of FIG. 1, and FIGS. 3d and 4d are cross-sectional views corresponding to line D-D' of FIG. 1. For the sake of simplicity in explanation, Descriptions that overlap with the semiconductor device described with reference to FIGS. 1, 2a to 2d are omitted.

[0039] Referring to FIGS. 1 and FIGS. 3a through 3d, a semiconductor substrate (100) may be provided. First trenches (T1) may be formed by patterning the upper surface of the semiconductor substrate (100). The first trenches (T1) may define a plurality of active patterns (AP) on the upper surface of the semiconductor substrate (100). The plurality of active patterns (AP) may extend in the third direction (D3) and may be spaced apart from each other in the second direction (D2).

[0040] Second trenches (T2) can be formed by patterning the upper surface of the semiconductor substrate (100). The second trenches (T2) can be formed deeper into the semiconductor substrate (100) than the first trenches (T1). The second trenches (T2) can define active regions (AR) on the upper surface of the semiconductor substrate (100). The active regions (AR) can extend in the third direction (D3) and can be spaced apart from each other in the second direction (D2). The plurality of active patterns (AP) can be placed on the active regions (AR). Each of the plurality of active patterns (AP) can protrude in the first direction (D1) from the upper surface of the corresponding active region (AR) among the active regions (AR) (i.e., the first surface (100a) of the semiconductor substrate (100)).

[0041] A device isolation layer (ST) may be formed to cover the active patterns (AP) and the active regions (AR), and may fill the first and second trenches (T1, T2). The device isolation layer (ST) may be recessed until the upper portions of the active patterns (AP) are exposed. The upper portions of each active pattern (AP) exposed by the device isolation layer (ST) may be referred to as active pins (AF). Channel regions (CH) and source / drain regions (SD) may be formed within the active pins (AF). Forming the source / drain regions (SD) may include, for example, recessing portions of the active pins (AF) on both sides of the channel region (CH), and performing an epitaxial growth process on the recessed portions of the active pins (AF). The channel region (CH) may be part of the active pin (AF) interposed between the source / drain regions (SD).

[0042] A first upper interlayer insulating film (110) may be formed to cover the source / drain regions (SD), and gate structures (GS) may be formed within the first upper interlayer insulating film (110). The gate structures (GS) may be formed to cross the active patterns (AP). Each gate structure (GS) may cross the active pin (AF) of the corresponding active pattern (AP) among the active patterns (AP) and may be formed to overlap vertically with the channel region (CH). Each of the gate structures (GS) may cover the upper surface of the channel region (CH) and may cover the sides facing each other in the second direction (D2) of the channel region (CH). The source / drain regions (SD) may be placed on each side of the gate structures (GS).

[0043] Forming the gate structures (GS) may, for example, include forming a void region that exposes the channel region (CH) within the first upper interlayer insulating film (110), and forming a gate insulating pattern (GI), a gate electrode (GE), a gate capping pattern (GC), and gate spacers (GSP) within the void region. A second upper interlayer insulating film (120) may be formed on the first upper interlayer insulating film (110) and may cover the gate structures (GS).

[0044] Source / drain contacts (CT1) may be formed within the first upper interlayer insulating film (110) and the second upper interlayer insulating film (120). The source / drain contacts (CT1) may be electrically connected to the source / drain regions (SD) by penetrating the first upper interlayer insulating film (110) and the second upper interlayer insulating film (120). Gate contacts (CT2) may be formed within the second upper interlayer insulating film (120). Each of the gate contacts (CT2) may be electrically connected to the gate electrode (GE) by penetrating the second upper interlayer insulating film (120) and the gate capping pattern (GC). Forming the source / drain contacts (CT1) and the gate contacts (CT2) may, for example, include forming source / drain contact holes that penetrate the first upper interlayer insulating film (110) and the second upper interlayer insulating film (120) and expose the source / drain regions (SD); forming gate contact holes that penetrate the second upper interlayer insulating film (120) and the gate capping pattern (GC) and expose the gate electrode (GE); forming a conductive film that fills the source / drain contact holes and the gate contact holes; and flattening the conductive film until the upper surface of the second upper interlayer insulating film (120) is exposed.

[0045] A third upper interlayer insulating film (130) may be formed on the second upper interlayer insulating film (120), and first upper wirings (132) and first upper vias (134) may be formed within the third upper interlayer insulating film (130). According to some embodiments, a power rail (POR) may be formed within the third upper interlayer insulating film (130) and may be formed at substantially the same height as the first upper wirings (132) from the first surface (100a) of the semiconductor substrate (100). A fourth upper interlayer insulating film (140) may be formed on the third upper interlayer insulating film (130), and second upper wirings (142) and second upper vias (144) may be formed within the fourth upper interlayer insulating film (140). Although not shown, additional upper interlayer insulating films, additional upper wiring, and additional upper vias may be formed on the fourth interlayer insulating film (140).

[0046] The semiconductor substrate (100) may have a second surface (100b) facing the upper surfaces of the active regions (AR) (i.e., the first surface (100a) of the semiconductor substrate (100). As an etching process is performed on the second surface (100b) of the semiconductor substrate (100), the lower portion of the semiconductor substrate (100) may be removed. The etching process may be performed until the semiconductor substrate (100) has a required thickness (i.e., thickness along the first direction (D1) between the first surface (100a) and the second surface (100b).

[0047] Referring to FIG. 1 and FIG. 4a to 4d, a through-via (200) may be formed to penetrate the lower portion of the semiconductor substrate (200), the device isolation film (ST), the first and second upper interlayer insulating films (110, 120), and the third upper interlayer insulating film (130), and may be connected to the bottom surface of the power rail (POR). Forming the through-via (200) may include, for example, forming a mask pattern (for example, a photoresist pattern) that defines an area where the through-via (200) is to be formed on the second surface (100b) of the semiconductor substrate (100); forming a through-hole by etching the lower portion of the semiconductor substrate (100), the device isolation film (ST), the first and second upper interlayer insulating films (110, 120), and the third upper interlayer insulating film (130) using the mask pattern as an etching mask; forming a conductive film that fills the through-hole on the second surface (100b) of the semiconductor substrate (100); and flattening the conductive film until the second surface (100b) of the semiconductor substrate (100) is exposed.

[0048] A lower insulating film (150) may be formed to cover the second surface (100b) of the semiconductor substrate (100), and lower contacts (152) may be formed within the lower insulating film (150). The through-via (200) may be electrically connected to a corresponding lower contact (152) among the lower contacts (152).

[0049] First lower wirings (162) may be formed on the lower insulating film (150) and may be electrically connected to the lower contacts (152). A first lower interlayer insulating film (160) may be formed on the lower insulating film (150) and may cover the first lower wirings (162).

[0050] According to some embodiments, at least one capacitor (170) may be formed on the first lower interlayer insulating film (160). The capacitor (170) may include a first electrode (172), a dielectric (174), and a second electrode (176) stacked in sequence on the first lower interlayer insulating film (160). Forming the capacitor (170) may, for example, include depositing a first electrode layer, a dielectric layer, and a second electrode layer in sequence on the first lower interlayer insulating film (160), and forming the first electrode (172), the dielectric (174), and the second electrode (176) by patterning the first electrode layer, the dielectric layer, and the second electrode layer.

[0051] A first electrode contact (164) may be formed within the first lower interlayer insulating film (160) and may be formed between the first electrode (172) of the capacitor (170) and a corresponding first lower wiring (162) among the first lower wirings (162). The first electrode (172) of the capacitor (170) may be electrically connected to the corresponding first lower wiring (162) through the first electrode contact (164).

[0052] Referring again to FIGS. 1, 2a through 2d, a second lower interlayer insulating film (180) may be formed on the first lower interlayer insulating film (160) and may cover the capacitor (170). Second lower wiring (182) may be formed on the second lower interlayer insulating film (180). A second electrode contact (166) may be formed within the second lower interlayer insulating film (180) and may be formed between the second electrode (176) of the capacitor (170) and the corresponding second lower wiring (182) among the second lower wirings (182). The second electrode (176) of the capacitor (170) may be electrically connected to the corresponding second lower wiring (182) through the second electrode contact (166).

[0053] First lower vias (168) may be formed within the first and second lower interlayer insulating films (160, 180) and between the first lower wirings (162) and the second lower wirings (182). Each of the first lower vias (168) may penetrate the first lower interlayer insulating film (160) and the second lower interlayer insulating film (180) and may be electrically connected to a corresponding one of the first lower wirings (162) and a corresponding one of the second lower wirings (182).

[0054] A third lower interlayer insulating film (190) may be formed on the second lower interlayer insulating film (180) and may cover the second lower wirings (182). Second lower vias (188) and third lower wirings (192) may be formed within the third lower interlayer insulating film (190). The second lower vias (188) may be formed between the second lower wirings (182) and the third lower wirings (192). Each of the second lower vias (188) may be electrically connected to a corresponding one of the second lower wirings (182) and a corresponding one of the third lower wirings (192).

[0055] The lower contacts (152), the first lower wiring (162), the first lower vias (168), the second lower wiring (182), the second lower vias (188), the third lower wiring (192), the at least one capacitor (170), the first and second electrode contacts (164, 166), the lower insulating film (150), and the first to third lower interlayer insulating films (160, 180, 190) can form a power transmission network (PDN).

[0056] FIG. 5 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. FIG. 6 is an enlarged view of portion P of FIG. 5. For the sake of simplicity, the differences between the semiconductor devices described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0057] Referring to FIGS. 5 and 6, according to some embodiments, the at least one capacitor (170) may be positioned between the first lower wirings (162) and the second lower wirings (182). The capacitor (170) may be positioned between the corresponding first lower wiring (162) among the first lower wirings (162) and the corresponding second lower wiring (182) among the second lower wirings (182), and may be electrically connected to the corresponding first lower wiring (162) and the corresponding second lower wiring (182). The capacitor (170) may be positioned on the first lower interlayer insulating film (160), and the second lower interlayer insulating film (180) may cover the capacitor (170).

[0058] The capacitor (170) may include a plurality of first electrodes (172) and a plurality of second electrodes (176) alternately stacked along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) on the first lower interlayer insulating film (160) (for example, the first direction (D1)), and a dielectric (174) interposed between the plurality of first electrodes (172) and the plurality of second electrodes (176). The plurality of first electrodes (172), the plurality of second electrodes (176), and the dielectric (174) may be extended on the first lower interlayer insulating film (160) in a direction parallel to the second surface (100b) of the semiconductor substrate (100) (e.g., the second direction (D2)), and accordingly, the capacitor (170) may have a plate shape that extends in a direction parallel to the second surface (100b) of the semiconductor substrate (100) (e.g., the second direction (D2)). The corresponding first lower wiring (162), the capacitor (170), and the corresponding second lower wiring (182) may be extended parallel along a direction parallel to the second surface (100b) of the semiconductor substrate (100) (e.g., the second direction (D2)). The plurality of first electrodes (172) can be electrically connected to the corresponding first lower wiring (162), and the plurality of second electrodes (176) can be electrically connected to the corresponding second lower wiring (182).

[0059] The power transmission network (PDN) may further include a first electrode contact (164) electrically connected to the ends of the plurality of first electrodes (172) on one side of the capacitor (170), and a second electrode contact (166) electrically connected to the ends of the plurality of second electrodes (176) on the other side of the capacitor (170). The first electrode contact (164) may extend in a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) on the one side of the capacitor (170) (e.g., the first direction (D1)). The ends of the plurality of first electrodes (172) may come into contact with the side of the first electrode contact (164). The first electrode contact (164) may penetrate portions of the first and second lower interlayer insulating films (160, 180) and may be electrically connected to the corresponding first lower wiring (162). The second electrode contact (166) may extend from the other side of the capacitor (170) in a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (e.g., the first direction (D1)). The ends of the plurality of second electrodes (176) may come into contact with the side of the second electrode contact (166). The second electrode contact (166) may penetrate the second lower interlayer insulating film (180) and may be electrically connected to the corresponding second lower wiring (182).

[0060] According to the embodiments, the power transmission network (PDN) may include the capacitor (170) with increased capacitance.

[0061] FIG. 7 is a drawing showing a method for manufacturing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to line A-A' of FIG. 1. For the sake of simplicity, the differences from the method of manufacturing a semiconductor device described with reference to FIGS. 1, FIGS. 2a to 2d, FIGS. 3a to 3d, and FIGS. 4a to 4d will be mainly explained.

[0062] Referring to FIGS. 6 and 7, the lower insulating film (150), the lower contacts (152), the first lower wiring (162), and the first lower interlayer insulating film (160) may be formed on the second surface (100b) of the semiconductor substrate (100).

[0063] According to some embodiments, at least one capacitor (170) may be formed on the first lower interlayer insulating film (160). The capacitor (170) may include a plurality of first electrodes (172) and a plurality of second electrodes (176) alternately stacked along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (for example, the first direction (D1)), and a dielectric (174) interposed between the plurality of first electrodes (172) and the plurality of second electrodes (176). Forming the capacitor (170) may, for example, include alternately depositing a plurality of first electrode layers, a plurality of second electrode layers, and a plurality of dielectric layers on the first lower interlayer insulating film (160), and forming the plurality of first electrodes (172), the plurality of second electrodes (176), and the dielectric layer (174) between them by patterning the plurality of first electrode layers, the plurality of dielectric layers, and the plurality of second electrode layers.

[0064] A first sub-insulating film (180a) may be formed on the first lower interlayer insulating film (160) and may cover the capacitor. A first electrode contact (164) may be formed to penetrate the first sub-insulating film (180a) and the first lower interlayer insulating film (160) on one side of the capacitor (170). The first electrode contact (164) may extend in a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (for example, the first direction (D1)) and may be connected to the ends of the plurality of first electrodes (172). The ends of the plurality of first electrodes (172) may be in contact with the side of the first electrode contact (164). The first electrode contact (164) can be electrically connected to a corresponding first lower wire (162) among the first lower wires (162).

[0065] A second sub-insulating film (180b) may be formed on the first sub-insulating film (180a) and may cover the capacitor (170) and the first electrode contact (164). The first sub-insulating film (180a) and the second sub-insulating film (180b) may constitute a second lower interlayer insulating film (180).

[0066] Referring again to FIGS. 5 and 6, a second electrode contact (166) may be formed to penetrate the second lower interlayer insulating film (180) on the other side of the capacitor (170). The second electrode contact (166) may extend in a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (for example, the first direction (D1)) and may be connected to the ends of the plurality of second electrodes (176). The ends of the plurality of second electrodes (176) may come into contact with the side of the second electrode contact (166).

[0067] Second lower wirings (182) may be formed on the second lower interlayer insulating film (180). The second electrode contact (166) may be electrically connected to a corresponding second lower wiring (182) among the second lower wirings (182).

[0068] Except for the differences described above, the method for manufacturing a semiconductor device according to the embodiments is substantially the same as the method for manufacturing a semiconductor device described with reference to FIGS. 1, FIGS. 2a to 2d, FIGS. 3a to 3d, and FIGS. 4a to 4d.

[0069] FIG. 8 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. For the sake of simplicity, the differences between the semiconductor devices described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0070] Referring to FIG. 8, according to some embodiments, the at least one capacitor (170) may be positioned between the first lower wiring (162) and the second lower wiring (182). The capacitor (170) may be positioned between the corresponding first lower wiring (162) among the first lower wirings (162) and the corresponding second lower wiring (182) among the second lower wirings (182), and may be electrically connected to the corresponding first lower wiring (162) and the corresponding second lower wiring (182). The capacitor (170) may be positioned on the first lower interlayer insulating film (160), and the second lower interlayer insulating film (180) may cover the capacitor (170).

[0071] The power transmission network (PDN) may further include a molded film (182) disposed between the first lower wirings (162) and the second lower wirings (182). The molded film (182) may be interposed between the first lower interlayer insulating film (160) and the second lower interlayer insulating film (180). The molded film (182) may include, for example, at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a low dielectric film.

[0072] The capacitor (170) may be disposed within a vertical hole (170H) that penetrates the mold film (182) and extends in a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (e.g., the first direction (D1)). The capacitor (170) may include a first electrode (172) conformally covering the inner surface of the vertical hole (170H), a second electrode (176) disposed within the vertical hole (170H) and spaced apart from the first electrode (172), and a dielectric (174) disposed within the vertical hole (170H) and interposed between the first electrode (172) and the second electrode (176). For example, the first electrode (172) may conformally cover the inner surface of the vertical hole (170H) and may extend onto one surface of the first lower interlayer insulating film (160) exposed by the vertical hole (170H). The first electrode (172) may extend between the mold film (182) and the second lower interlayer insulating film (180) along a direction parallel to the second surface (100b) of the semiconductor substrate (100) (for example, the second direction (D2)). The second electrode (176) may be extended in a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) within the vertical hole (170H) (e.g., the first direction (D1)), and may be extended on the first electrode (172) along a direction parallel to the second surface (100b) of the semiconductor substrate (100) between the mold film (182) and the second lower layer insulating film (180) (e.g., the second direction (D2)).The dielectric (174) may be interposed between the first electrode (172) and the second electrode (176) within the vertical hole (170H), and may extend between the first electrode (172) and the second electrode (176) along a direction parallel to the second surface (100b) of the semiconductor substrate (100) (e.g., the second direction (D2)) between the mold film (182) and the second lower interlayer insulating film (180).

[0073] The power transmission network (PDN) may further include a first electrode contact (164) between the first electrode (172) of the capacitor (170) and the corresponding first lower wiring (162), and a second electrode contact (166) between the second electrode (176) of the capacitor and the corresponding second lower wiring (182). The first electrode contact (164) may penetrate the first lower interlayer insulating film (160) and electrically connect the first electrode (172) of the capacitor (170) and the corresponding first lower wiring (162). The second electrode contact (166) may penetrate the second lower interlayer insulating film (180) and electrically connect the second electrode (176) of the capacitor and the corresponding second lower wiring (182).

[0074] According to the embodiments, the power transmission network (PDN) may include the capacitor (170) with increased capacitance.

[0075] FIGS. 9 and FIGS. 10 are drawings illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention, and are cross-sectional views corresponding to line A-A' of FIG. 1. For the sake of simplicity, the differences from the method of manufacturing a semiconductor device described with reference to FIGS. 1, FIGS. 2a to 2d, FIGS. 3a to 3d, and FIGS. 4a to 4d will be mainly explained.

[0076] Referring to FIG. 9, the lower insulating film (150), the lower contacts (152), the first lower wiring (162), and the first lower interlayer insulating film (160) may be formed on the second surface (100b) of the semiconductor substrate (100). The first electrode contact (164) may be formed within the first lower interlayer insulating film (160) and may be electrically connected to a corresponding first lower wiring (162) among the first lower wirings (162).

[0077] According to some embodiments, a mold film (182) may be formed on the first lower interlayer insulating film (160), and a vertical hole (170H) may be formed within the mold film (182). The vertical hole (170H) may penetrate the mold film (182) along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (for example, the first direction (D1)) and may expose the first electrode contact (164). Forming the vertical hole (170H) may include, for example, forming a mask pattern that defines an area on the mold film (182) where the vertical hole (170H) is to be formed, and etching the mold film (182) using the mask pattern as an etching mask.

[0078] Referring to FIG. 10, a capacitor (170) may be formed within the vertical hole (170H). The capacitor (170) may include a first electrode (172) conformally covering the inner surface of the vertical hole (170H), a second electrode (176) disposed within the vertical hole (170H) and spaced apart from the first electrode (172), and a dielectric (174) disposed within the vertical hole (170H) and interposed between the first electrode (172) and the second electrode (176). Forming the capacitor (170) may include, for example, forming a first electrode film conformally covering the inner surface of the vertical hole (170H) on the mold film (182), forming a dielectric film filling a portion of the vertical hole (170H) on the first electrode film, forming a second electrode film filling the remainder of the vertical hole (170H) on the dielectric film, and removing (for example, etching) the first electrode film, the dielectric film, and the second electrode film on the mold film (182). The first electrode (172) of the capacitor (170) may be connected (or contacted) to the first electrode contact (164) and may be electrically connected to the corresponding first lower wiring (162) through the first electrode contact (164).

[0079] Referring again to FIG. 8, a second lower interlayer insulating film (180) may be formed on the mold film (182) and may cover the capacitor (170). Second lower wiring (182) may be formed on the second lower interlayer insulating film (180). A second electrode contact (166) may be formed within the second lower interlayer insulating film (180) and may be connected (or contacted) to the second electrode (176) of the capacitor (170). The second electrode contact (166) may be electrically connected to the corresponding second lower wiring (182) among the second lower wiring (182). The second electrode (176) of the capacitor (170) may be electrically connected to the corresponding second lower wiring (182) through the second electrode contact (166).

[0080] Except for the differences described above, the method for manufacturing a semiconductor device according to the embodiments is substantially the same as the method for manufacturing a semiconductor device described with reference to FIGS. 1, FIGS. 2a to 2d, FIGS. 3a to 3d, and FIGS. 4a to 4d.

[0081] FIG. 11 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. For the sake of simplicity, the differences between the semiconductor devices described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0082] Referring to FIG. 11, the first lower wiring (162) can be placed on the lower insulating film (150) and electrically connected to the lower contacts (152).

[0083] The second lower wirings (182) may be spaced apart from the first lower wirings (162) along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (e.g., the first direction (D1)), and the first lower vias (168) may be positioned between the first lower wirings (162) and the second lower wirings (182). The first lower vias (168) may electrically connect the first lower wirings (162) and the second lower wirings (182) to each other. The power transmission network (PDN) may include a first lower interlayer insulating film (160) positioned on the lower insulating film (150) and covering the first lower wirings (162) and the first lower vias (168). The second lower wiring (182) may be disposed on the first lower interlayer insulating film (160). Each of the first lower vias (168) may penetrate the first lower interlayer insulating film (160) and may be electrically connected to a corresponding one of the first lower wirings (162) and a corresponding one of the second lower wirings (182).

[0084] The power transmission network (PDN) may further include a second lower interlayer insulating film (180) disposed on the first lower interlayer insulating film (160) and covering the second lower wirings (182). The third lower wirings (192) may be disposed within the second lower interlayer insulating film (180) and may be spaced apart from the second lower wirings (182) along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (for example, the first direction (D1)).

[0085] According to some embodiments, the at least one capacitor (170) may be disposed between the second lower wirings (182) and the third lower wirings (192), and within the second lower interlayer insulating film (180). The capacitor (170) may be disposed between the corresponding second lower wiring (182) among the second lower wirings (182) and the corresponding third lower wiring (192) among the third lower wirings (192), and may be electrically connected to the corresponding second lower wiring (182) and the corresponding third lower wiring (192).

[0086] The capacitor (170) may include the first electrode (172), the dielectric (174), and the second electrode (176) which are sequentially stacked along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) between the corresponding second lower wiring (182) and the corresponding third lower wiring (192) (e.g., the first direction (D1)). The first electrode (172), the dielectric (174), and the second electrode (174) may extend in a direction parallel to the second surface (100b) of the semiconductor substrate (100) (e.g., the second direction (D2)). The corresponding second lower wiring (182), the capacitor (170), and the corresponding third lower wiring (192) may be extended parallel to the second surface (100b) of the semiconductor substrate (100) (for example, the second direction (D2)).

[0087] The power transmission network (PDN) may further include a first electrode contact (164) between the first electrode (172) of the capacitor (170) and the corresponding second lower wiring (182), and a second electrode contact (166) between the second electrode (176) of the capacitor and the corresponding third lower wiring (192). The first electrode contact (164) may electrically connect the first electrode (172) of the capacitor (170) and the corresponding second lower wiring (182), and the second electrode contact (166) may electrically connect the second electrode (176) of the capacitor and the corresponding third lower wiring (192).

[0088] Except for the arrangement of the capacitor (170), the first electrode contact (164), and the second electrode contact (166), the semiconductor device according to the embodiments is substantially the same as the semiconductor device described with reference to FIGS. 1, 2a to 2d. According to some embodiments, the capacitor (170), the first electrode contact (164), and the second electrode contact (166) may be configured substantially the same as the capacitor (170), the first electrode contact (164), and the second electrode contact (166) described with reference to FIGS. 5 and 6, or may be configured substantially the same as the capacitor (170), the first electrode contact (164), and the second electrode contact (166) described with reference to FIG. 8.

[0089] FIG. 12 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. For the sake of simplicity, the differences between the semiconductor devices described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0090] Referring to FIG. 12, the power transmission network (PDN) may include the capacitor (170) positioned between the first lower wires (162) and the second lower wires (182), and may further include an additional capacitor (170) positioned between the second lower wires (182) and the third lower wires (192).

[0091] According to some embodiments, the capacitor (170) may be positioned between a corresponding first lower wire (162) among the first lower wires (162) and a corresponding second lower wire (182) among the second lower wires (182), and may be electrically connected to the corresponding first lower wire (162) and the corresponding second lower wire (182). The first electrode contact (164) may penetrate the first lower interlayer insulating film (160) and may electrically connect the first electrode (172) of the capacitor (170) and the corresponding first lower wire (162). The second electrode contact (166) may penetrate the second lower interlayer insulating film (180) and may electrically connect the second electrode (176) of the capacitor (170) and the corresponding second lower wire (182).

[0092] The additional capacitor (170) may be disposed between the corresponding second lower wire (182) among the second lower wires (182) and the corresponding third lower wire (192) among the third lower wires (192), and may be electrically connected to the corresponding second lower wire (182) and the corresponding third lower wire (192). The additional capacitor (170) may be disposed within the third lower interlayer insulating film (190) and may be configured substantially identically to the capacitor (170). That is, the additional capacitor (170) may include the first electrode (172), the dielectric (174), and the second electrode (176), which are stacked sequentially along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) between the corresponding second lower wiring (182) and the corresponding third lower wiring (192) (for example, the first direction (D1)). The additional capacitor (170) may be a capacitor of the same type as the capacitor (170).

[0093] The power transmission network (PDN) may further include an additional first electrode contact (164) between the first electrode (172) of the additional capacitor (170) and the corresponding second lower wire (182), and an additional second electrode contact (166) between the second electrode (176) of the additional capacitor (170) and the corresponding third lower wire (192). The additional first electrode contact (164) may electrically connect the first electrode (172) of the additional capacitor (170) and the corresponding second lower wire (182), and the additional second electrode contact (166) may electrically connect the second electrode (176) of the additional capacitor (170) and the corresponding third lower wire (192). The additional first electrode contact (164) and the additional second electrode contact (166) may comprise a conductive material (e.g., a metal and / or a conductive metal nitride).

[0094] According to some embodiments, the capacitor (170), the first electrode contact (164), and the second electrode contact (166) may be configured substantially identically to the capacitor (170), the first electrode contact (164), and the second electrode contact (166) described with reference to FIG. 5 and FIG. 6, or may be configured substantially identically to the capacitor (170), the first electrode contact (164), and the second electrode contact (166) described with reference to FIG. 8. Additionally, the additional capacitor (170), the additional first electrode contact (164), and the additional second electrode contact (166) may be configured substantially identically to the capacitor (170), the first electrode contact (164), and the second electrode contact (166) described with reference to FIG. 5 and FIG. 6, or may be configured substantially identically to the capacitor (170), the first electrode contact (164), and the second electrode contact (166) described with reference to FIG. 8.

[0095] FIG. 13 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. For the sake of simplicity, the differences between the semiconductor devices described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0096] Referring to FIG. 13, the first lower wiring (162) can be placed on the lower insulating film (150) and electrically connected to the lower contacts (152).

[0097] The second lower wirings (182) may be spaced apart from the first lower wirings (162) along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (e.g., the first direction (D1)), and the first lower vias (168) may be positioned between the first lower wirings (162) and the second lower wirings (182). The first lower vias (168) may electrically connect the first lower wirings (162) and the second lower wirings (182) to each other. The power transmission network (PDN) may include a first lower interlayer insulating film (160) positioned on the lower insulating film (150) and covering the first lower wirings (162) and the first lower vias (168). The second lower wiring (182) may be disposed on the first lower interlayer insulating film (160). Each of the first lower vias (168) may penetrate the first lower interlayer insulating film (160) and may be electrically connected to a corresponding one of the first lower wirings (162) and a corresponding one of the second lower wirings (182).

[0098] The power transmission network (PDN) may further include a second lower interlayer insulating film (180) disposed on the first lower interlayer insulating film (160) and covering the second lower wirings (182). The third lower wirings (192) may be disposed within the second lower interlayer insulating film (180) and may be spaced apart from the second lower wirings (182) along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) (for example, the first direction (D1)). The second lower vias (188) may be disposed within the second lower interlayer insulating film (180) and between the second lower wirings (182) and the third lower wirings (192). The second lower vias (188) can electrically connect the second lower wires (182) and the third lower wires (192) to each other.

[0099] According to some embodiments, the power transmission network (PDN) may include at least one capacitor (170) disposed between the first lower wires (162) and the third lower wires (192). The capacitor (170) may be disposed on the first lower interlayer insulating film (160). The second lower interlayer insulating film (180) may cover the capacitor (170). The capacitor (170) may be disposed between the corresponding first lower wire (162) among the first lower wires (162) and the corresponding third lower wire (192) among the third lower wires (192), and may be electrically connected to the corresponding first lower wire (162) and the corresponding third lower wire (192).

[0100] The capacitor (170) may include the first electrode (172), the dielectric (174), and the second electrode (176) which are sequentially stacked along a direction perpendicular to the second surface (100b) of the semiconductor substrate (100) between the corresponding first lower wiring (162) and the corresponding third lower wiring (192) (e.g., the first direction (D1)). The first electrode (172), the dielectric (174), and the second electrode (176) may extend in a direction parallel to the second surface (100b) of the semiconductor substrate (100) (e.g., the second direction (D2)). The corresponding first lower wiring (162), the capacitor (170), and the corresponding third lower wiring (192) may be extended parallel to the second surface (100b) of the semiconductor substrate (100) (for example, the second direction (D2)).

[0101] The power transmission network (PDN) may further include a first electrode contact (164) between the first electrode (172) of the capacitor (170) and the corresponding first lower wiring (162), and a second electrode contact (166) between the second electrode (176) of the capacitor and the corresponding third lower wiring (192). The first electrode contact (164) may penetrate the first lower interlayer insulating film (160) and electrically connect the first electrode (172) of the capacitor (170) and the corresponding first lower wiring (162). The second electrode contact (166) may penetrate the second lower interlayer insulating film (180) and electrically connect the second electrode (176) of the capacitor (170) and the corresponding third lower wiring (192).

[0102] Except for the arrangement of the capacitor (170), the first electrode contact (164), and the second electrode contact (166), the semiconductor device according to the embodiments is substantially the same as the semiconductor device described with reference to FIGS. 1, 2a to 2d. According to some embodiments, the capacitor (170), the first electrode contact (164), and the second electrode contact (166) may be configured substantially the same as the capacitor (170), the first electrode contact (164), and the second electrode contact (166) described with reference to FIGS. 5 and 6, or may be configured substantially the same as the capacitor (170), the first electrode contact (164), and the second electrode contact (166) described with reference to FIG. 8.

[0103] FIG. 14 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along A-A' of FIG. 1. For the sake of simplicity, the differences between the semiconductor devices described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0104] Referring to FIG. 14, the power transmission network (PDN) may include a plurality of capacitors (170) disposed between the first lower wires (162) and the second lower wires (182), and between the second lower wires (182) and the third lower wires (192). Although not illustrated, at least one of the plurality of capacitors (170) may be disposed between the first lower wires (162) and the third lower wires (192), as described with reference to FIG. 13.

[0105] According to some embodiments, the plurality of capacitors (170) may be capacitors of different types. For example, one of the plurality of capacitors (170) may be configured substantially identically to the capacitor (170) described with reference to FIG. 2a, FIG. 11, FIG. 12 and FIG. 13, another of the plurality of capacitors (170) may be configured substantially identically to the capacitor (170) described with reference to FIG. 5 and FIG. 6, and yet another of the plurality of capacitors (170) may be configured substantially identically to the capacitor (170) described with reference to FIG. 8.

[0106] The above description of the embodiments of the present invention provides examples for explaining the present invention. Accordingly, the present invention is not limited to the above embodiments, and it is evident that many modifications and changes are possible within the technical scope of the present invention, such as combining the above embodiments by those skilled in the art.

Claims

Claim 1 A semiconductor substrate having a first surface and a second surface facing each other; a transistor on the first surface of the semiconductor substrate; a power rail disposed on the first surface of the semiconductor substrate and electrically connected to the transistor; lower wirings disposed on the second surface of the semiconductor substrate and spaced apart from the second surface along a first direction perpendicular to the second surface; a lower interlayer insulating film disposed on the second surface of the semiconductor substrate and covering the lower wirings; a through-via penetrating the semiconductor substrate and connecting a corresponding lower wiring among the lower wirings and the power rail; A semiconductor device comprising a capacitor disposed on the second surface of the semiconductor substrate and disposed between the lower wires, wherein the capacitor comprises a first electrode, a second electrode and a dielectric between them, and the lower wires comprise a pair of lower wires spaced apart from each other in the first direction, and the first electrode, the second electrode and the dielectric of the capacitor are disposed within the lower interlayer insulating film between the pair of lower wires, the first electrode is electrically connected to one of the pair of lower wires, and the second electrode is electrically connected to the other of the pair of lower wires. Claim 2 delete Claim 3 A semiconductor device according to claim 1, wherein the pair of lower wires extend in a second direction parallel to the second surface of the semiconductor substrate and further comprises: a first electrode contact electrically connecting one of the pair of lower wires and the first electrode; and a second electrode contact electrically connecting the other of the pair of lower wires and the second electrode, wherein the first electrode contact and the second contact are disposed within the lower interlayer insulating film between the pair of lower wires. Claim 4 In claim 3, each of the first electrode contact and the second electrode contact is a semiconductor device extending in the first direction. Claim 5 In claim 4, the first electrode, the second electrode, and the dielectric are a semiconductor device extending in the second direction between the first electrode contact and the second electrode contact. Claim 6 A semiconductor device according to claim 1, wherein each of the first electrode and the second electrode is provided in a plurality, and the capacitor comprises: the plurality of first electrodes and the plurality of second electrodes alternately stacked along the first direction; and the dielectric interposed between the plurality of first electrodes and the plurality of second electrodes, wherein the plurality of first electrodes, the plurality of second electrodes, and the dielectric of the capacitor are disposed within the lower interlayer insulating film between the pair of lower wirings, and the plurality of first electrodes are electrically connected to one of the pair of lower wirings, and the plurality of second electrodes are electrically connected to the other of the pair of lower wirings. Claim 7 A semiconductor device according to claim 6, wherein the pair of lower wires extend in a second direction parallel to the second plane of the semiconductor substrate and is electrically connected to the ends of the plurality of first electrodes on one side of the capacitor and is connected to one of the pair of lower wires; and further comprising a first electrode contact electrically connected to the ends of the plurality of second electrodes on the other side of the capacitor and is connected to the other of the pair of lower wires, wherein the first electrode contact and the second contact are disposed within the lower interlayer insulating film between the pair of lower wires. Claim 8 In claim 7, each of the first electrode contact and the second electrode contact is a semiconductor device extending in the first direction. Claim 9 A semiconductor device according to claim 1, further comprising a mold film disposed within the lower interlayer insulating film between the pair of lower wires, wherein the mold film comprises a vertical hole penetrating the mold film along the first direction, and the first electrode, the second electrode, and the dielectric of the capacitor extend along the inner surface of the vertical hole. Claim 10 A semiconductor substrate having a first surface and a second surface facing each other; active patterns on the first surface of the semiconductor substrate; gate electrodes disposed on the first surface of the semiconductor substrate and traversing the active patterns; a power rail disposed on the first surface of the semiconductor substrate and electrically connected to a source / drain region of a corresponding active pattern among the active patterns; lower wirings disposed on the second surface of the semiconductor substrate and spaced apart from the second surface along a first direction perpendicular to the second surface; a lower interlayer insulating film disposed on the second surface of the semiconductor substrate and covering the lower wirings; a through-via penetrating the semiconductor substrate and connecting a corresponding lower wiring among the lower wirings and the power rail; A semiconductor device comprising a capacitor disposed on the second surface of the semiconductor substrate and disposed between the lower wires, wherein the capacitor comprises a first electrode, a second electrode and a dielectric between them, and the lower wires comprise a pair of lower wires spaced apart from each other in the first direction, and the first electrode, the second electrode and the dielectric of the capacitor are disposed within the lower interlayer insulating film between the pair of lower wires, the first electrode is electrically connected to one of the pair of lower wires, and the second electrode is electrically connected to the other of the pair of lower wires.

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