Image sensor and method for fabricating the same

Abstract

An image sensor with reduced Gate Induced Drain Leakage (GIDL) current and a method for manufacturing the same are provided. The image sensor comprises a substrate, a photoelectric conversion region within the substrate, a substrate trench formed within the substrate on the photoelectric conversion region, a floating diffusion region adjacent to the side of the substrate trench within the substrate, a gate dielectric film extending along the side and bottom of the substrate trench, and a transmission gate electrode comprising a lower gate having a first width that fills a portion of the substrate trench on the gate dielectric film, and an upper gate having a second width smaller than the first width on the lower gate, wherein the gate dielectric film comprises a lower dielectric film having a first thickness interposed between the substrate and the lower gate, and an upper dielectric film having a second thickness larger than the first thickness adjacent to the floating diffusion region.

Description

Technology Field

[0001] The present invention relates to an image sensor and a method for manufacturing the same. More specifically, the present invention relates to a CMOS-type image sensor comprising a vertical transfer gate and a method for manufacturing the same. Background Technology

[0002] An image sensor is a semiconductor device that converts optical information into an electrical signal. Such image sensors may include Charge Coupled Device (CCD) image sensors and Complementary Metal-Oxide Semiconductor (CMOS) image sensors.

[0003] The image sensor can be configured in the form of a package, wherein the package can be structured to protect the image sensor while allowing light to be incident on the photo-receiving surface or sensing area of ​​the image sensor. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide an image sensor with reduced Gate Induced Drain Leakage (GIDL) current.

[0005] Another technical problem that the present invention aims to solve is to provide a method for manufacturing an image sensor with reduced gate-induced leakage (GIDL) current.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] An image sensor according to some embodiments for achieving the above technical problem comprises a substrate, a photoelectric conversion region within the substrate, a substrate trench formed within the substrate on the photoelectric conversion region, a floating diffusion region adjacent to the side of the substrate trench within the substrate, a gate dielectric film extending along the side and bottom surface of the substrate trench, and a transmission gate electrode comprising a lower gate having a first width that fills a portion of the substrate trench on the gate dielectric film, and an upper gate having a second width smaller than the first width on the lower gate, wherein the gate dielectric film comprises a lower dielectric film having a first thickness interposed between the substrate and the lower gate, and an upper dielectric film having a second thickness greater than the first thickness adjacent to the floating diffusion region.

[0008] An image sensor according to some embodiments for achieving the above technical problem comprises: a substrate; a photoelectric conversion region within the substrate; a substrate trench formed within the substrate on the photoelectric conversion region; a floating diffusion region adjacent to the side of the substrate trench within the substrate; a gate dielectric film extending along the side and bottom surface of the substrate trench; a lower gate filling a portion of the substrate trench on the gate dielectric film; a transmission gate electrode comprising an upper gate spaced apart from the side of the gate dielectric film on the lower gate; and a residual gate film extending along the gate dielectric film on the lower gate; and a gate spacer interposed between the upper gate and the residual gate film on the lower gate, wherein the gate dielectric film comprises a lower dielectric film interposed between the substrate and the lower gate and having a first thickness, and an upper dielectric film interposed between the floating diffusion region and the residual gate film and having a second thickness greater than the first thickness.

[0009] An image sensor according to some embodiments for achieving the above technical problem comprises: a first substrate including a first surface and a second surface opposite to each other; a photoelectric conversion region within the first substrate; a transmission gate electrode on a first surface of the first substrate, at least a portion of which is embedded within the first substrate; a gate dielectric film interposed between the first substrate and the transmission gate electrode; a floating diffusion region adjacent to a side of the transmission gate electrode within the first substrate; a first wiring structure electrically connected to the transmission gate electrode or the floating diffusion region on a first surface of the first substrate; and a microlens on a second surface of the first substrate, wherein the transmission gate electrode comprises a lower gate adjacent to the photoelectric conversion region and an upper gate spaced apart from a side of the gate dielectric film on the lower gate, and the gate dielectric film comprises a lower dielectric film interposed between the first substrate and the lower gate and having a first thickness, and an upper dielectric film adjacent to the floating diffusion region and having a second thickness greater than the first thickness.

[0010] A method for manufacturing an image sensor according to some embodiments for achieving the above other technical objectives comprises providing a substrate including a photoelectric conversion region, forming a floating diffusion region within the substrate, forming a substrate trench adjacent to the floating diffusion region within the substrate, forming a gate dielectric film extending along the side and bottom surface of the substrate trench, performing a fluorine ion implantation process on the gate dielectric film adjacent to the floating diffusion region, forming a pre-electrode film that fills the substrate trench on the gate dielectric film, and patterning the pre-electrode film to form a transmission gate electrode, wherein the transmission gate electrode includes a lower gate that fills a portion of the substrate trench, and an upper gate spaced apart from the side of the gate dielectric film on the lower gate.

[0011] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0012] FIG. 1 is an exemplary block diagram for illustrating an image sensor according to some embodiments. FIG. 2 is an exemplary circuit diagram for illustrating an image sensor according to some embodiments. FIG. 3 is a schematic layout diagram illustrating a unit pixel of an image sensor according to some embodiments. Figure 4 is a schematic cross-sectional view taken along AA of Figure 3. Figure 5 is an enlarged view to explain the S region of Figure 4. Figure 6 is an enlarged view to explain the E1 region of Figure 5. Figure 7 is an enlarged view to explain the E2 region of Figure 5. FIGS. 8 to 11 are various schematic cross-sectional views for illustrating image sensors according to some embodiments. FIG. 12 is an exemplary circuit diagram for illustrating an image sensor according to some embodiments. FIGS. 13 and FIGS. 14 are various schematic layout diagrams for illustrating image sensors according to some embodiments. FIG. 15 is an exemplary layout diagram for illustrating an image sensor according to some embodiments. FIG. 16 is a schematic cross-sectional view illustrating the image sensor of FIG. 15. FIGS. 17 to 26 are intermediate step drawings for explaining a method of manufacturing an image sensor according to some embodiments. Specific details for implementing the invention

[0013] Hereinafter, an image sensor according to exemplary embodiments is described with reference to FIGS. 1 to 16.

[0014] FIG. 1 is an exemplary block diagram for illustrating an image sensor according to some embodiments.

[0015] Referring to FIG. 1, an image sensor according to some embodiments includes an active pixel sensor array (1; APS, active pixel sensor array), a row decoder (2; Row Decoder), a row driver (3; Row Driver), a column decoder (4; Column Decoder), a timing generator (5; Timing Generator), a correlated double sampler (6; CDS, correlated double sampler), an analog to digital converter (7; ADS, analog to digital converter), and an input / output buffer (8; I / O Buffer).

[0016] The active pixel sensor array (1) includes a plurality of unit pixels arranged in two dimensions and can convert an optical signal into an electrical signal. The active pixel sensor array (1) can be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, from a row driver (3). Additionally, the electrical signal converted by the active pixel sensor array (1) can be provided to a correlation double sampler (6).

[0017] The row driver (3) can provide a plurality of driving signals to the active pixel sensor array (1) to drive a plurality of unit pixels according to the result decoded by the row decoder (2). If the unit pixels are arranged in a matrix form, driving signals can be provided for each row.

[0018] The timing generator (5) can provide timing signals and control signals to the row decoder (2) and the column decoder (4).

[0019] The correlation double sampler (CDS; 6) can receive, hold, and sample electrical signals generated from the active pixel sensor array (1). The correlation double sampler (6) can double-sample a specific noise level and a signal level from an electrical signal, and output a difference level corresponding to the difference between the noise level and the signal level.

[0020] The analog-to-digital converter (ADC; 7) can convert the analog signal corresponding to the difference level output from the correlated double sampler (6) into a digital signal and output it.

[0021] The input / output buffer (8) latches a digital signal, and the latched signal can sequentially output the digital signal to a video signal processing unit (not shown) according to the decoding result in the column decoder (4).

[0022] FIG. 2 is an exemplary circuit diagram for illustrating an image sensor according to some embodiments.

[0023] Referring to FIG. 2, a unit pixel of an image sensor according to some embodiments may include a photoelectric conversion element (PD), a transfer transistor (TG), a floating diffusion region (FD), a reset transistor (RG), a source follower transistor (SF), and a select transistor (SEL).

[0024] A photoelectric conversion device (PD) can generate charge in proportion to the amount of light incident from the outside. The photoelectric conversion device (PD) can be coupled with a transfer transistor (TG) that transfers the generated and accumulated charge to a floating diffusion region (FD). The floating diffusion region (FD) is a region that converts charge into voltage, and because it has parasitic capacitance, charge can be accumulated and stored.

[0025] One end of the transfer transistor (TG) is connected to the photoelectric conversion element (PD), and the other end of the transfer transistor (TG) can be connected to the floating diffusion region (FD). The transfer transistor (TG) can be formed as a transistor driven by a predetermined bias (e.g., a transfer signal (TX)). That is, the transfer transistor (TG) can transfer the charge generated from the photoelectric conversion element (PD) to the floating diffusion region (FD) according to the transfer signal (TX).

[0026] The source follower transistor (SF) amplifies the change in electrical potential of the floating diffusion region (FD), which receives charge from the photoelectric conversion element (PD), and outputs it to the output line (V OUT It can output as ). When the source follower transistor (SF) is turned on, a predetermined electrical potential provided to the drain of the source follower transistor (SF), e.g., power supply voltage (V DD ) can be transferred to the drain region of the select transistor (SEL).

[0027] The select transistor (SEL) can select unit pixels to be read row by row. The select transistor (SEL) may be composed of a transistor driven by a select line that applies a predetermined bias (e.g., row select signal (SX)).

[0028] The reset transistor (RG) can periodically reset the floating diffusion region (FD). The reset transistor (RG) may consist of a transistor driven by a reset line that applies a predetermined bias (e.g., a reset signal (RX)). When the reset transistor (RG) is turned on by the reset signal (RX), a predetermined electrical potential, e.g., a power supply voltage (V), is provided at the drain of the reset transistor (RG). DD ) can be transferred to the floating diffusion zone (FD).

[0029] FIG. 3 is a schematic layout diagram illustrating a unit pixel of an image sensor according to some embodiments. FIG. 4 is a schematic cross-sectional view cut along AA of FIG. 3. FIG. 5 is an enlarged view illustrating region S of FIG. 4. FIG. 6 is an enlarged view illustrating region E1 of FIG. 5. FIG. 7 is an enlarged view illustrating region E2 of FIG. 5.

[0030] An image sensor according to some embodiments may include a plurality of unit pixels. The plurality of unit pixels may be arranged two-dimensionally (e.g., in a matrix form) in a plane including a first direction (X) and a second direction (Y), for example. For convenience of explanation, FIGS. 3 to 7 will focus on a single unit pixel (hereinafter, the first unit pixel (UP1)).

[0031] Referring to FIGS. 3 through 7, an image sensor according to some embodiments includes a first substrate (100), a photoelectric conversion region (101), a device isolation pattern (110), a gate dielectric film (130), a first transmission gate electrode (140A), a gate spacer (150), a first wiring structure (160), a surface insulating film (170), a grid pattern (172, 174), a color filter (180), and a micro lens (190).

[0032] The first substrate (100) may be a semiconductor substrate. For example, the first substrate (100) may be bulk silicon or a silicon-on-insulator (SOI). The first substrate (100) may be a silicon substrate, or may include other materials, for example, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first substrate (100) may be a base substrate on which an epitaxial layer is formed.

[0033] The first substrate (100) may include a first surface (100a) and a second surface (100b) that are opposite to each other. In the embodiments described below, the first surface (100a) may be referred to as the front side of the first substrate (100), and the second surface (100b) may be referred to as the back side of the first substrate (100). In some embodiments, the second surface (100b) of the first substrate (100) may be a light-receiving surface to which light is incident. That is, the image sensor according to some embodiments may be a back-illuminated (BSI) image sensor.

[0034] In some embodiments, the first substrate (100) may have a first conductivity type. For example, the first substrate (100) may contain p-type impurities (e.g., boron (B), aluminum (Al), indium (In), or gallium (Ga)). In the following embodiments, the first conductivity type is described as p-type, but this is merely illustrative, and the first conductivity type may be n-type.

[0035] The photoelectric conversion region (101) can be formed within the first substrate (100) of the first unit pixel (UP1). The photoelectric conversion region (101) can correspond to the photoelectric conversion element (PD) of FIG. 2. That is, the photoelectric conversion region (101) can generate a charge in proportion to the amount of light incident from the outside.

[0036] The photoelectric conversion region (101) may have a second conductivity type different from the first conductivity type. For example, the photoelectric conversion region (101) may be formed by ion implanting n-type impurities into a first substrate (100) that is p-type.

[0037] A device isolation pattern (110) may be formed within a first substrate (100). The device isolation pattern (110) may extend from a first surface (100a) of the first substrate (100) toward a second surface (100b) of the first substrate (100). For example, the device isolation pattern (110) may be formed by embedding an insulating material within a shallow trench formed by patterning the first substrate (100) including the first surface (100a). The device isolation pattern (110) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto.

[0038] The device isolation pattern (110) can define a plurality of unit pixels within the first substrate (100). For example, at least a portion of the device isolation pattern (110) can be formed within the first substrate (100) to surround the first unit pixel (UP1).

[0039] Additionally, the device isolation pattern (110) can define a plurality of active regions (e.g., first to third active regions (AR1 to AR3)) within the first unit pixel (UP1). For example, the device isolation pattern (110) can surround the first to third active regions (AR1 to AR3) respectively from a planar perspective.

[0040] The first active region (AR1) may include a first floating diffusion region (FD1) and a first channel region (CH1).

[0041] A first floating diffusion region (FD1) may be formed within the first substrate (100) of the first active region (AR1). The first floating diffusion region (FD1) may have the second conductivity type. For example, the first floating diffusion region (FD1) may be a first impurity region (102) formed by ion implanting n-type impurities within the first substrate (100) which is p-type. In some embodiments, the first floating diffusion region (FD1) may have the second conductivity type with a higher impurity concentration than the photoelectric conversion region (101). For example, the first floating diffusion region (FD1) may be formed by ion implanting a high concentration of n-type impurities (n+) within the first substrate (100) which is p-type.

[0042] A first channel region (CH1) may be formed within the first substrate (100) of the first active region (AR1). The first channel region (CH1) may be formed between the photoelectric conversion region (101) and the first floating diffusion region (FD1). The first channel region (CH1) may have the first conductivity type. For example, the first channel region (CH1) may be part of the first substrate (100) which is p-type.

[0043] The second active region (AR2) may be separated from the first active region (AR1) by a device isolation pattern (110). In some embodiments, the second active region (AR2) may include a ground region (GND) to which a ground voltage is applied.

[0044] A ground region (GND) may be formed within the first substrate (100) of the second active region (AR2). The ground region (GND) may have the first conductivity type. For example, the ground region (GND) may be a second impurity region (103) formed by ion implanting a high concentration of p-type impurities (p+) within the first substrate (100), which is p-type.

[0045] The third active region (AR3) may be separated from the first active region (AR1) and the second active region (AR2) by a device isolation pattern (110). In some embodiments, the third active region (AR3) may include first source / drain regions (SD1) and a second channel region (CH2).

[0046] First source / drain regions (SD1) may be formed within the first substrate (100) of the third active region (AR3). The first source / drain regions (SD1) may have the second conductivity type. For example, the first source / drain regions (SD1) may each be a first impurity region (102) formed by ion implanting n-type impurities into the first substrate (100), which is p-type.

[0047] A second channel region (CH2) may be formed within the first substrate (100) of the third active region (AR3). The second channel region (CH2) may be formed between the first source / drain regions (SD1). The second channel region (CH2) may have the first conductivity type. For example, the second channel region (CH2) may be part of the first substrate (100) which is p-type.

[0048] In some embodiments, a pixel separation pattern (120) may be formed within the first substrate (100). The pixel separation pattern (120) may extend from the lower surface of the device separation pattern (110) toward the second surface (100b) of the first substrate (100). For example, the pixel separation pattern (120) may be formed by embedding an insulating material within a deep trench formed by patterning the first substrate (100). The pixel separation pattern (120) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto.

[0049] The pixel separation pattern (120) can define a plurality of unit pixels within the first substrate (100). For example, the pixel separation pattern (120) can be formed within the first substrate (100) to surround the first unit pixel (UP1).

[0050] The width of the pixel separation pattern (120) is shown as constant, but this is merely illustrative. Unlike what is shown, in some other embodiments, the width of the pixel separation pattern (120) may decrease as it faces the second surface (100b) of the first substrate (100). In some other embodiments, the width of the pixel separation pattern (120) may increase as it faces the second surface (100b) of the first substrate (100).

[0051] In some embodiments, the pixel separation pattern (120) may completely penetrate the first substrate (100). For example, the lower surface of the pixel separation pattern (120) may be exposed on the second surface (100b) of the first substrate (100).

[0052] In some embodiments, the pixel separation pattern (120) may include a filling pattern (122) and a spacer film (124).

[0053] The filling pattern (122) may extend from the lower surface of the device isolation pattern (110) toward the second surface (100b) of the first substrate (100). The filling pattern (122) may include a conductive material, for example, polysilicon (poly Si), but is not limited thereto. In some embodiments, a ground voltage or a negative voltage may be applied to the filling pattern (122). Such a filling pattern (122) can effectively prevent ESD bruise defects by preventing charges generated by ESD (electrostatic discharge), etc., from accumulating on the surface of the first substrate (100) (e.g., the second surface (100b)).

[0054] The spacer film (124) may extend along the side of the filling pattern (122). The spacer film (124) may comprise at least one of an insulating material, for example, silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof, but is not limited thereto. Such a spacer film (124) may be interposed between the filling pattern (122) and the first substrate (100) to electrically separate the filling pattern (122) and the first substrate (100).

[0055] A first transmission gate electrode (140A) may be formed on a first surface (100a) of a first substrate (100). The first transmission gate electrode (140A) may be formed on the first substrate (100) between the photoelectric conversion region (101) and the first floating diffusion region (FD1). For example, the first transmission gate electrode (140A) may be formed on a first channel region (CH1) of a first active region (AR1). That is, the first channel region (CH1) may be defined within the first active region (AR1) below the first transmission gate electrode (140A).

[0056] When the first transmission gate electrode (140A) is turned on, a channel can be formed within the first channel region (CH1) between the photoelectric conversion region (101) and the first floating diffusion region (FD1). For example, the first transmission gate electrode (140A) can form a channel of the second conductivity type (e.g., n-type) within the first channel region (CH1).

[0057] The first transmission gate electrode (140A) may correspond to the gate electrode of a transmission transistor (e.g., TG of FIG. 2). For example, when the first transmission gate electrode (140A) is turned on, the charge generated from the photoelectric conversion region (101) may be transferred to the first floating diffusion region (FD1) through the first channel region (CH1).

[0058] The first transfer gate electrode (140A) may be a vertical transfer gate. That is, at least a portion of the first transfer gate electrode (140A) may be embedded within the first substrate (100). For example, a substrate trench (100t) may be formed within the first substrate (100) that overlaps at least a portion with the first active region (AR1). At least a portion of the first transfer gate electrode (140A) may be formed to fill this substrate trench (100t). The substrate trench (100t) may extend from the first surface (100a) of the first substrate (100). Accordingly, the lower surface of the first transfer gate electrode (140A) may be formed lower than the first surface (100a) of the first substrate (100).

[0059] In some embodiments, the width of the substrate trench (100t) may decrease as it moves away from the first surface (100a) of the first substrate (100). This may be due to the characteristics of the etching process for forming the substrate trench (100t).

[0060] In some embodiments, the substrate trench (100t) may overlap with both the first active region (AR1) and the device isolation pattern (110). For example, the substrate trench (100t) may be a trench formed by patterning both the first substrate (100) containing the first active region (AR1) and the device isolation pattern (110). In this case, as illustrated in FIGS. 4 and 5, a portion of the side of the substrate trench (100t) may be defined by the device isolation pattern (110).

[0061] The first transmission gate electrode (140A) may include, for example, impurity-doped polysilicon (poly Si), metal silicides such as cobalt silicide, metal nitrides such as titanium nitride, and at least one of metals such as tungsten, copper, and aluminum, but is not limited thereto. For example, the first transmission gate electrode (140A) may include a polysilicon film.

[0062] The first transmission gate electrode (140A) may include a lower gate (142) and an upper gate (144).

[0063] The lower gate (142) can fill a portion of the substrate trench (100t). In some embodiments, the upper surface of the lower gate (142) may be formed lower than the first surface (100a) of the first substrate (100). For example, the lower gate (142) can fill the lower portion of the substrate trench (100t).

[0064] An upper gate (144) may be placed on a lower gate (142). The upper gate (144) may have a shape that protrudes from the upper surface of the lower gate (142). In some embodiments, the upper surface of the upper gate (144) may be formed higher than the first surface (100a) of the first substrate (100). For example, the upper part of the upper gate (144) may protrude above the first surface (100a) of the first substrate (100).

[0065] In some embodiments, the second width (W2) of the upper gate (144) may be smaller than the first width (W1) of the lower gate (142). These lower gate (142) and upper gate (144) may be formed, for example, by patterning the upper portion of the first transmission gate electrode (140A). For example, as shown in FIG. 5, a first gate trench (140t1) and a second gate trench (140t2) may be formed within the upper portion of the first transmission gate electrode (140A). The first gate trench (140t1) and the second gate trench (140t2) may be defined by the upper surface of the lower gate (142) and the side surface of the upper gate (144), respectively.

[0066] In some embodiments, the first gate trench (140t1) may be defined between the upper gate (144) and the first floating diffusion region (FD1). In some embodiments, the second gate trench (140t2) may be defined between the upper gate (144) and the device isolation pattern (110).

[0067] With respect to the surface of the first substrate (100) (e.g., the first surface (100a)), the depth at which the first gate trench (140t1) is formed and the depth at which the second gate trench (140t2) is formed are shown to be the same, but this is merely illustrative. In other examples, the depth at which the first gate trench (140t1) is formed and the depth at which the second gate trench (140t2) is formed may, of course, be different from each other.

[0068] In some embodiments, the first transmission gate electrode (140A) may further include a residual gate film (146). This residual gate film (146) may be, for example, a residual film remaining during the patterning process of the upper part of the first transmission gate electrode (140A). For example, as shown in FIG. 5, the first gate trench (140t1) may be defined by the upper surface of the lower gate (142), the side of the upper gate (144), and the side of the residual gate film (146).

[0069] In some embodiments, the lower gate (142), the upper gate (144), and the remaining gate film (146) may be formed integrally.

[0070] A gate dielectric film (130) may be interposed between a first transmission gate electrode (140A) and a first substrate (100). For example, the gate dielectric film (130) may extend along the profile of the side and bottom surface of the substrate trench (100t). The first transmission gate electrode (140A) may be formed on the gate dielectric film (130) to fill at least a portion of the substrate trench (100t). In some embodiments, the gate dielectric film (130) may not extend along the first surface (100a) of the first substrate (100).

[0071] The gate dielectric film (130) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric (low-k) material with a dielectric constant lower than that of silicon oxide, but is not limited thereto. The low-dielectric material may include, for example, FOX (Flowable Oxide), TOSZ (Torene SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, and at least one combination thereof. For example, the gate dielectric film (130) may include a silicon oxide film.

[0072] The gate dielectric film (130) may include a lower dielectric film (132) and an upper dielectric film (134).

[0073] At least a portion of the lower dielectric film (132) may be interposed between the first substrate (100) and the lower gate (142). For example, the lower dielectric film (132) may extend conformally along a portion of the side of the substrate trench (100t) and the profile of the lower surface.

[0074] The upper dielectric film (134) may extend from the upper portion of the lower dielectric film (132). At least a portion of the upper dielectric film (134) may be adjacent to the first floating diffusion region (FD1). For example, at least a portion of the upper dielectric film (134) may be interposed between the first floating diffusion region (FD1) and the upper gate (144). In some embodiments, at least a portion of the upper dielectric film (134) may be interposed between the first floating diffusion region (FD1) and the remaining gate film (146). For example, the remaining gate film (146) may extend along the profile of the side of the upper dielectric film (134).

[0075] The residual gate film (146) is shown extending only to the top of the upper dielectric film (134), but this is merely illustrative. As another example, the residual gate film (146) may extend along the profile of a portion of the side of the upper dielectric film (134) (e.g., lower). In this case, another portion of the side of the upper dielectric film (134) (e.g., upper) may be exposed from the residual gate film (146).

[0076] In some embodiments, the upper dielectric film (134) may extend from the lower dielectric film (132) to the surface of the first substrate (100) (e.g., the first surface (100a)). For example, the upper surface of the upper dielectric film (134) may be exposed at the first surface (100a) of the first substrate (100).

[0077] In some embodiments, with respect to the surface of the first substrate (100) (e.g., the first surface (100a)), the depth (D2) at which the upper dielectric film (134) is formed may be greater than the depth (D1) at which the first floating diffusion region (FD1) is formed. For example, the depth (D2) at which the upper dielectric film (134) is formed may be about 0.1 Å to about 2000 Å, and preferably about 1 Å to about 1100 Å. Within this range, the upper dielectric film (134) is positioned in an overlapping area between the first transmission gate electrode (140A) and the first floating diffusion region (FD1) to effectively reduce gate-induced drain leakage.

[0078] With respect to the surface of the first substrate (100) (e.g., the first surface (100a)), the depth at which the first gate trench (140t1) is formed is shown to be the same as the depth (D2) at which the upper dielectric film (134) is formed, but this is merely illustrative. In other examples, the depth at which the first gate trench (140t1) is formed and the depth (D2) at which the upper dielectric film (134) is formed may, of course, be different from each other.

[0079] The upper dielectric film (134) may have an increased thickness compared to the lower dielectric film (132). For example, as shown in FIGS. 5 to 7, the lower dielectric film (132) may have a first thickness (T1), and the upper dielectric film (134) may have a second thickness (T2) greater than the first thickness (T1).

[0080] In some embodiments, the second thickness (T2) of the upper dielectric film (134) may increase as it moves away from the lower dielectric film (132), or increase as it moves away from the lower dielectric film (132) and then become constant.

[0081] In some embodiments, as shown in FIG. 7, a boundary film (100f) may be formed within the first substrate (100) adjacent to the upper dielectric film (134). The boundary film (100f) may extend along the profile of the side of the upper dielectric film (134). The upper dielectric film (134) may be interposed between the remaining gate film (146) and the boundary film (100f).

[0082] A boundary film (100f) can be formed by injecting impurity atoms into a first substrate (100) adjacent to an upper dielectric film (134). The impurity atoms may include, for example, fluorine (F). For example, if the first substrate (100) is a silicon (Si) substrate, the boundary film (100f) may include silicon-fluorine (Si-F) bonds. The impurity concentration of the boundary film (100f) (e.g., fluorine concentration) is, for example, about 2 E15 at / cm 3 Up to about 4 E15 at / cm 3 It may be possible. In the above range, the upper dielectric film (134) is positioned in an overlapping area between the first transmission gate electrode (140A) and the first floating diffusion region (FD1) to effectively reduce gate-induced drain leakage.

[0083] As the impurity atoms are injected into the first substrate (100) to form a boundary film (100f), the thickness of the gate dielectric film (130) adjacent to the boundary film (100f) can be increased. Accordingly, a gate dielectric film (130) including the upper dielectric film (134) described above can be formed. This will be described in more detail later in the description of FIG. 21.

[0084] A gate spacer (150) may be formed on the first transmission gate electrode (140A). The gate spacer (150) may be formed on the upper surface of the lower gate (142) and on the side surface of the upper gate (144). For example, as shown in FIG. 5, the gate spacer (150) may fill at least a portion of the first gate trench (140t1) and / or at least a portion of the second gate trench (140t2).

[0085] The gate spacer (150) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto. For example, the gate spacer (150) may include a silicon nitride film.

[0086] A gate spacer (150) formed within the first gate trench (140t1) may be interposed between the upper gate (144) and the upper dielectric film (134). That is, the upper gate (144) may be separated from the upper dielectric film (134) by the gate spacer (150). In some embodiments, the upper gate (144) may be separated from the remaining gate film (146) by the gate spacer (150).

[0087] A gate spacer (150) formed within the second gate trench (140t2) may be interposed between the upper gate (144) and the device isolation pattern (110). That is, the upper gate (144) may be separated from the device isolation pattern (110) by the gate spacer (150). In some embodiments, a portion of the second gate trench (140t2) may be defined within a portion of the device isolation pattern (110). In this case, a portion of the gate spacer (150) may overlap with a portion of the device isolation pattern (110).

[0088] In some embodiments, a first operating gate electrode (G1) may be formed on a first surface (100a) of a first substrate (100). For example, as shown in FIG. 3, the first operating gate electrode (G1) may be formed on a second channel region (CH2) of a third active region (AR3). That is, the second channel region (CH2) may be defined within the third active region (AR3) below the first operating gate electrode (G1). First source / drain regions (SD1) may be defined within the third active region (AR3) adjacent to both sides of the first operating gate electrode (G1).

[0089] When the first transmission gate electrode (140A) is turned on, a channel can be formed within the second channel region (CH2) between the first source / drain regions (SD1). For example, the first transmission gate electrode (140A) can form a channel of the second conductivity type (e.g., n-type) within the second channel region (CH2).

[0090] In some embodiments, the first operating gate electrode (G1) may be a planar gate. For example, the lower surface of the first operating gate electrode (G1) may extend along the first surface (100a) of the first substrate (100).

[0091] In some embodiments, the first operating gate electrode (G1) may correspond to one of the gate electrode of a reset transistor (e.g., RG in FIG. 2), the gate electrode of a source follower transistor (e.g., SF in FIG. 2) and the gate electrode of a select transistor (e.g., SEL in FIG. 2).

[0092] Although it is illustrated that only one first operating gate electrode (G1) is disposed within the first unit pixel (UP1), this is merely exemplary, and it is obvious that multiple operating gate electrodes having different functions may be disposed within the first unit pixel (UP1). For example, at least two gate electrodes among the gate electrode of a reset transistor (e.g., RG in FIG. 2), the gate electrode of a source follower transistor (e.g., SF in FIG. 2), and the gate electrode of a select transistor (e.g., SEL in FIG. 2) may be disposed within the first unit pixel (UP1).

[0093] A first wiring structure (160) may be formed on a first surface (100a) of a first substrate (100). The first wiring structure (160) may include a plurality of wiring patterns. For example, the first wiring structure (160) may include a first inter-wiring insulating film (162) on the first surface (100a) and a first wiring pattern (164) within the first inter-wiring insulating film (162). In FIG. 4, the number of layers and arrangement of the first wiring pattern (164) are merely exemplary and are not limited thereto.

[0094] The first wiring structure (160) may be electrically connected to the first transmission gate electrode (140A) and / or the first operation gate electrode (G1). For example, gate contacts (165a, 165b) connecting the first transmission gate electrode (140A) or the first operation gate electrode (G1) and the first wiring pattern (164) may be formed within the first wiring inter-insulating film (162).

[0095] Additionally, the first wiring structure (160) may be electrically connected to active regions (e.g., first to third active regions (AR1 to AR3)). For example, source / drain contacts (167a to 167d) connecting the first impurity region (102) or the second impurity region (103) and the first wiring pattern (164) may be formed within the first wiring inter-insulating film (162).

[0096] A surface insulating film (170) may be formed on a second surface (100b) of a first substrate (100). The surface insulating film (170) may extend along the second surface (100b) of the first substrate (100). The surface insulating film (170) may comprise at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof, but is not limited thereto.

[0097] In some embodiments, the surface insulating film (170) may be formed as a multilayer film. For example, unlike what is illustrated, the surface insulating film (170) may include an aluminum oxide film, a hafnium oxide film, a silicon oxide film, a silicon nitride film, and a hafnium oxide film that are sequentially stacked on the second surface (100b) of the first substrate (100).

[0098] The surface insulating film (170) functions as an anti-reflection film to prevent the reflection of light incident on the second surface (100b) of the first substrate (100). Through this, the light reception rate of the photoelectric conversion region (101) can be improved. In addition, the surface insulating film (170) functions as a flattening film to contribute to the formation of the color filter (180) and micro lens (190), which will be described later, at a uniform height.

[0099] A color filter (180) can be formed on a surface insulating film (170). The color filter (180) can be arranged to correspond to each unit pixel (e.g., a first unit pixel (UP1)). That is, a plurality of color filters (180) can be arranged two-dimensionally (e.g., in a matrix form) in a plane including a first direction (X) and a second direction (Y).

[0100] The color filter (180) may have various colors depending on the unit pixels. For example, the color filter (180) may include a red color filter, a green color filter, a blue color filter, a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter.

[0101] In some embodiments, a grid pattern (172, 174) may be formed on the surface insulating film (170). The grid pattern (172, 174) may be formed in a grid shape in a planar view and interposed between the color filters (180). In some embodiments, the grid pattern (172, 174) may be positioned to overlap with the pixel separation pattern (120).

[0102] In some embodiments, the grid pattern (172, 174) may include a metal pattern (172) and a low refractive index pattern (174). The metal pattern (172) and the low refractive index pattern (174) may be stacked sequentially, for example, on a surface insulating film (170).

[0103] The metal pattern (172) may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof, but is not limited thereto. The metal pattern (172) prevents charges generated by electrostatic discharge (ESD), etc., from accumulating on the surface of the first substrate (100) (e.g., the second surface (100b)), thereby effectively preventing ESD defects.

[0104] The low refractive index pattern (174) may include a low refractive index material that has a lower refractive index than silicon (Si). For example, the low refractive index pattern (174) may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof, but is not limited thereto. The low refractive index pattern (174) can improve light collection efficiency by refracting or reflecting light incident at an angle.

[0105] In some embodiments, a first protective layer (176) may be formed on the surface insulating layer (170) and the grid pattern (172, 174). For example, the first protective layer (176) may extend conformally along the profile of the surface insulating layer (170) and the grid pattern (172, 174). The first protective layer (176) may include, for example, aluminum oxide, but is not limited thereto. Such a first protective layer (176) can prevent damage to the surface insulating layer (170) and the grid pattern (172, 174).

[0106] Micro lenses (190) can be formed on a color filter (180). Micro lenses (190) can be arranged to correspond to each unit pixel (e.g., a first unit pixel (UP1)). For example, a plurality of micro lenses (190) can be arranged two-dimensionally (e.g., in a matrix form) in a plane including a first direction (X) and a second direction (Y).

[0107] The micro lens (190) has a convex shape and may have a predetermined radius of curvature. Accordingly, the micro lens (190) can concentrate light incident on the photoelectric conversion region (101). The micro lens (190) may include, for example, a light-transmitting resin, but is not limited thereto.

[0108] In some embodiments, a second protective film (195) may be formed on the microlens (190). The second protective film (195) may extend along the surface of the microlens (190). The second protective film (195) may, for example, comprise an inorganic oxide film. For example, the second protective film (195) may comprise at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof, but is not limited thereto. In some embodiments, the second protective film (195) may comprise a low temperature oxide (LTO).

[0109] This second protective layer (195) can protect the micro-lens (190) from the outside. For example, the second protective layer (195) can protect the micro-lens (190) containing organic material by including an inorganic oxide film. Additionally, the second protective layer (195) can improve the quality of the image sensor by improving the light gathering efficiency of the micro-lens (190). For example, the second protective layer (195) can reduce the reflection, refraction, scattering, etc. of incident light reaching the space between the micro-lenses (190) by filling the space between the micro-lenses (190).

[0110] When the gate electrode and the drain region are placed adjacent to each other, direct tunneling can occur due to the strong electric field generated between them, and the resulting leakage current is called Gate Induced Drain Leakage (GIDL). As image sensors with miniaturized unit pixels are required to miniaturize electronic devices and improve the quality of image sensors, the impact of leakage currents such as Gate Induced Drain Leakage is increasing.

[0111] In particular, in image sensors using a vertical transfer gate, it is important to control gate-induced drain leakage due to the overlapping region between the vertical transfer gate and the floating diffusion region. To reduce such gate-induced drain leakage, the gate electrode of the vertical transfer gate can be patterned to separate the upper part of the gate electrode (e.g., upper gate (144)) from the floating diffusion region; however, residual material remaining during the gate electrode patterning process (e.g., residual gate film (146)) still causes gate-induced drain leakage.

[0112] An image sensor according to some embodiments may reduce the gate-induced drain leakage described above by having a structure in which the thickness of the gate dielectric film (130) adjacent to the residual gate film (146) is selectively increased. Specifically, as described above, the upper dielectric film (134) of the gate dielectric film (130) adjacent to the residual gate film (146) may have an increased thickness compared to the lower dielectric film (132). This upper dielectric film (134) is placed in an overlapping area between the residual gate film (146) and the first floating diffusion region (FD1) so as to effectively reduce the gate-induced drain leakage caused by the residual gate film (146).

[0113] FIGS. 8 to 11 are various schematic cross-sectional views for illustrating image sensors according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 7 are briefly described or omitted.

[0114] Referring to FIG. 8, in an image sensor according to some embodiments, the device isolation pattern (110) is formed as a multilayer film.

[0115] For example, the device isolation pattern (110) may include an insulating liner (112), an etch-stopping liner (114), and a gap-fill insulating film (116) that are sequentially stacked on a first substrate (100). The insulating liner (112) may be conformally extended along the side and bottom profiles of a shallow trench formed by patterning the first substrate (100). The etch-stopping liner (114) may be formed on the insulating liner (112). The etch-stopping liner (114) may be conformally extended along the profile of the insulating liner (112). The gap-fill insulating film (116) may be formed on the etch-stopping liner (114). The gap-fill insulating film (116) may fill the area of ​​the shallow trench remaining after the insulating liner (112) and the etch-stopping liner (114) are formed.

[0116] The insulating liner (112), the etching stop liner (114), and the gap-fill insulating film (116) may each include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but are not limited thereto.

[0117] In some embodiments, the etch-stop liner (114) may comprise a material having an etch selectivity ratio with respect to the insulating liner (112) and the gap-fill insulating film (116). For example, where the insulating liner (112) and the gap-fill insulating film (116) comprise silicon oxide, the etch-stop liner (114) may comprise at least one of silicon nitride, silicon carbonitride, silicon oxycarbonitride, and combinations thereof. For example, the insulating liner (112) and the gap-fill insulating film (116) may comprise silicon oxide, and the etch-stop liner (114) may comprise silicon nitride.

[0118] Referring to FIG. 9, in an image sensor according to some embodiments, the first transmission gate electrode (140A) includes a concave surface (140t3).

[0119] A concave surface (140t3) may be formed on the upper surface of the upper gate (144). The concave surface (140t3) may have a shape that is concave toward the first substrate (100). This may be due to the characteristics of the deposition process for forming the first transmission gate electrode (140A). For example, in the process of forming the first transmission gate electrode (140A), the electrode film (e.g., the preliminary electrode film (140L) of FIG. 22) filling the substrate trench (100t) may form a concave surface (140t3).

[0120] Referring to FIG. 10, in an image sensor according to some embodiments, the width of the upper gate (144) decreases as it moves away from the lower gate (142).

[0121] For example, the width of the first gate trench (140t1) and / or the width of the second gate trench (140t2) may decrease as it is adjacent to the lower gate (142). This may be due to the characteristics of the etching process for forming the first gate trench (140t1) and / or the second gate trench (140t2).

[0122] Referring to FIG. 11, an image sensor according to some embodiments further includes a first insulating film (152) and a second insulating film (154).

[0123] The first insulating film (152) may extend along the surface of the first transmission gate electrode (140A). For example, the first insulating film (152) may extend conformally along the upper surface of the lower gate (142), the side and upper surface of the upper gate (144), and the side of the remaining gate film (146). In some embodiments, the first insulating film (152) may be an oxide film formed by oxidizing the surface of the first transmission gate electrode (140A). For example, if the first transmission gate electrode (140A) comprises polysilicon, the first insulating film (152) may comprise a silicon oxide film.

[0124] A second insulating film (154) may be formed on the first insulating film (152). For example, the second insulating film (154) may extend conformally along the surface of the first insulating film (152), the surface of the first substrate (100), and the surface of the device isolation pattern (110). The second insulating film (154) may comprise, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric (low-k) material with a dielectric constant lower than that of silicon oxide, but is not limited thereto. For example, the second insulating film (154) may comprise USG (Undoped Silicate Glass).

[0125] In some embodiments, the gate contacts (165a, 165b) may be connected to the first transmission gate electrode (140A) or the first operation gate electrode (G1) by penetrating the first insulating film (152) and the second insulating film (154).

[0126] In some embodiments, source / drain contacts (167a–167d) may penetrate the second insulating film (154) and be connected to the first impurity region (102) or the second impurity region (103).

[0127] FIG. 12 is an exemplary circuit diagram for illustrating an image sensor according to some embodiments. FIG. 13 and FIG. 14 are various schematic layout diagrams for illustrating an image sensor according to some embodiments.

[0128] Referring to FIG. 12, an image sensor according to some embodiments may include a first photoelectric conversion element (PD1) and a second photoelectric conversion element (PD2) that share a floating diffusion region (FD).

[0129] The first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) can each generate a charge in proportion to the amount of light incident from the outside. The first photoelectric conversion element (PD1) can be coupled with a first transfer transistor (TG1) that transfers the generated and accumulated charge to a floating diffusion region (FD). The second photoelectric conversion element (PD2) can be coupled with a second transfer transistor (TG2) that transfers the generated and accumulated charge to a floating diffusion region (FD).

[0130] One end of the first transmission transistor (TG1) is connected to the first photoelectric conversion element (PD1), and the other end of the first transmission transistor (TG1) can be connected to the floating diffusion region (FD). The first transmission transistor (TG1) can be formed as a transistor driven by a predetermined bias (e.g., the first transmission signal (TX1)). One end of the second transmission transistor (TG2) is connected to the second photoelectric conversion element (PD2), and the other end of the second transmission transistor (TG2) can be connected to the floating diffusion region (FD). The second transmission transistor (TG2) can be formed as a transistor driven by a predetermined bias (e.g., the second transmission signal (TX2)).

[0131] Referring to FIG. 13, an image sensor according to some embodiments includes a first unit pixel (UP1) and a second unit pixel (UP2) adjacent to each other.

[0132] For example, the first unit pixel (UP1) and the second unit pixel (UP2) may be arranged adjacently in the first direction (X). The first unit pixel (UP1) and the second unit pixel (UP2) may each be defined by an element isolation pattern (110). For example, the element isolation pattern (110) may surround the first unit pixel (UP1) and the second unit pixel (UP2), respectively.

[0133] In the first unit pixel (UP1), the first to third active regions (AR1~AR3), the first transmission gate electrode (140A), and the first operation gate electrode (G1) described above using FIGS. 3 to 7 may be formed. Therefore, a detailed description of the first unit pixel (UP1) is omitted.

[0134] In the second unit pixel (UP2), the fourth to sixth active regions (AR4~AR6), the second transmission gate electrode (140B), the second operation gate electrode (G2), and the third operation gate electrode (G3) may be formed.

[0135] The fourth active region (AR4) may include a second floating diffusion region (FD2) and a third channel region (CH3). Except for being formed in the second unit pixel (UP2), the fourth active region (AR4) may be similar to the first active region (AR1), so a detailed description is omitted below.

[0136] The fifth active region (AR5) may be separated from the first active region (AR1) by a device isolation pattern (110). In some embodiments, the fifth active region (AR5) may include a ground region to which a ground voltage is applied. Except for being formed in the second unit pixel (UP2), the fifth active region (AR5) may be similar to the second active region (AR2), so a detailed description is omitted below.

[0137] The sixth active region (AR6) may be separated from the fourth active region (AR4) and the fifth active region (AR5) by a device isolation pattern (110). In some embodiments, the sixth active region (AR6) may include second source / drain regions (SD2) and a fourth channel region (CH4). Except for being formed in the second unit pixel (UP2), the sixth active region (AR6) may be similar to the third active region (AR3), so a detailed description is omitted below.

[0138] In some embodiments, as illustrated, the first to third active regions (AR1 to AR3) and the fourth to sixth active regions (AR4 to AR6) may be formed symmetrically with respect to a plane crossing the first unit pixel (UP1) and the second unit pixel (UP2).

[0139] The second transmission gate electrode (140B) may be formed on the third channel region (CH3) of the fourth active region (AR4). Except for being formed on the second unit pixel (UP2), the second transmission gate electrode (140B) may be similar to the first transmission gate electrode (140A), so a detailed description is omitted below.

[0140] In some embodiments, as illustrated, the first transmission gate electrode (140A) and the second transmission gate electrode (140B) may be formed symmetrically with respect to a plane crossing the first unit pixel (UP1) and the second unit pixel (UP2).

[0141] The first transmission gate electrode (140A) may correspond to the gate electrode of the first transmission transistor (e.g., TG1 in FIG. 12), and the second transmission gate electrode (140B) may correspond to the gate electrode of the second transmission transistor (e.g., TG2 in FIG. 12).

[0142] In some embodiments, the first floating diffusion region (FD1) and the second floating diffusion region (FD2) may be electrically connected. For example, as illustrated, a connecting wire (CW) connecting the first floating diffusion region (FD1) and the second floating diffusion region (FD2) may be formed. Through this, the first unit pixel (UP1) and the second unit pixel (UP2) may share a floating diffusion region (e.g., FD in FIG. 6).

[0143] The second operating gate electrode (G2) and the third operating gate electrode (G3) may each be formed on the fourth channel region (CH4) of the sixth active region (AR6). That is, the fourth channel region (CH4) may be defined within the sixth active region (AR6) below the second operating gate electrode (G2) and the third operating gate electrode (G3). The second source / drain regions (SD2) may be defined within the sixth active region (AR6) adjacent to both sides of the second operating gate electrode (G2) and both sides of the third operating gate electrode (G3).

[0144] In some embodiments, the first operating gate electrode (G1) may correspond to the gate electrode of a reset transistor (e.g., RG in FIG. 12). For example, a connecting wire (CW) may connect the first floating diffusion region (FD1) and the second floating diffusion region (FD2) to the first source / drain region (SD1). By doing so, the first operating gate electrode (G1) can periodically reset the first floating diffusion region (FD1) and the second floating diffusion region (FD2).

[0145] In some embodiments, the second operating gate electrode (G2) may correspond to the gate electrode of a source follower transistor (e.g., SF in FIG. 12). For example, a connecting wire (CW) may connect the first floating diffusion region (FD1) and the second floating diffusion region (FD2) to the second operating gate electrode (G2). The second operating gate electrode (G2) amplifies the change in electrical potential of the first floating diffusion region (FD1) and the second floating diffusion region (FD2) and transmits it to an output line (e.g., V in FIG. 12). OUT It can be output as ).

[0146] In some embodiments, the third operating gate electrode (G3) may correspond to the gate electrode of a selection transistor (e.g., SEL of FIG. 12).

[0147] Referring to FIG. 14, an image sensor according to some embodiments includes first to fourth unit pixels (UP1 to UP4) adjacent to each other.

[0148] For example, the first unit pixel (UP1) and the second unit pixel (UP2) may be arranged adjacently in the first direction (X). The third unit pixel (UP3) and the fourth unit pixel (UP4) may be arranged adjacently in the first direction (X). Additionally, the first unit pixel (UP1) and the third unit pixel (UP2) may be arranged adjacently in the second direction (Y), and the second unit pixel (UP2) and the fourth unit pixel (UP4) may be arranged adjacently in the second direction (Y). The first to fourth unit pixels (UP1 to UP4) may each be defined by an element isolation pattern (110). For example, the element isolation pattern (110) may surround the first to fourth unit pixels (UP1 to UP4) respectively.

[0149] The first unit pixel (UP1) and the second unit pixel (UP2) are identical to those described above using FIG. 13, so a detailed description is omitted below.

[0150] The third unit pixel (UP3) may be similar to the first unit pixel (UP1). In some embodiments, as illustrated, the first unit pixel (UP1) and the third unit pixel (UP3) may be formed symmetrically with respect to a plane crossing them.

[0151] The fourth unit pixel (UP4) may be similar to the second unit pixel (UP2). In some embodiments, as illustrated, the second unit pixel (UP2) and the fourth unit pixel (UP4) may be formed symmetrically with respect to a plane crossing them.

[0152] FIG. 15 is an exemplary layout diagram for illustrating an image sensor according to some embodiments. FIG. 16 is a schematic cross-sectional view for illustrating the image sensor of FIG. 15. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 14 are briefly described or omitted.

[0153] Referring to FIGS. 15 and 16, an image sensor according to some embodiments includes a sensor array region (SAR), a connection region (CR), and a pad region (PR).

[0154] The sensor array region (SAR) may include a region corresponding to the active pixel sensor array (1) of FIG. 1. For example, a plurality of unit pixels arranged two-dimensionally (e.g., in the form of a matrix) may be formed within the sensor array region (SAR).

[0155] The sensor array area (SAR) may include an receiving area (APS) and a blocking area (OB). Active pixels that receive light and generate an active signal may be arranged in the receiving area (APS). Optical black pixels that block light and generate an optical black signal may be arranged in the blocking area (OB). The blocking area (OB) may be formed, for example, along the periphery of the receiving area (APS), but this is merely illustrative.

[0156] In some embodiments, a photoelectric conversion region (101) may not be formed within a portion of the light-blocking region (OB). For example, the photoelectric conversion region (101) may be formed within the first substrate (100) of the light-blocking region (OB) adjacent to the light-receiving region (APS), but may not be formed within the first substrate (100) of the light-blocking region (OB) spaced apart from the light-receiving region (APS).

[0157] In some embodiments, dummy pixels (not shown) may be formed in a light-receiving area (APS) adjacent to a light-blocking area (OB).

[0158] A connection area (CR) may be formed around the sensor array area (SAR). The connection area (CR) may be formed on one side of the sensor array area (SAR), but this is merely an example. Wiring may be formed in the connection area (CR) to transmit and receive electrical signals from the sensor array area (SAR).

[0159] A pad region (PR) may be formed around a sensor array region (SAR). The pad region (PR) may be formed adjacent to the edge of an image sensor according to some embodiments, but this is merely exemplary. The pad region (PR) may be connected to an external device, etc., and configured to transmit and receive electrical signals between the image sensor and the external device according to some embodiments.

[0160] The connection area (CR) is depicted as being interposed between the sensor array area (SAR) and the pad area (PR), but this is merely illustrative. It goes without saying that the arrangement of the sensor array area (SAR), connection area (CR), and pad area (PR) can vary as needed.

[0161] The first wiring structure (160) may include a first wiring pattern (164) within a sensor array area (SAR) and a second wiring pattern (163) within a connection area (CR). The first wiring pattern (164) may be electrically connected to unit pixels of the sensor array area (SAR). At least a portion of the second wiring pattern (163) may be electrically connected to at least a portion of the first wiring pattern (164). Through this, the second wiring pattern (163) may be electrically connected to unit pixels of the sensor array area (SAR).

[0162] An image sensor according to some embodiments may include a second substrate (200) and a second wiring structure (240).

[0163] The second substrate (200) may be bulk silicon or SOI (silicon-on-insulator). The second substrate (200) may be a silicon substrate, or may include other materials, for example, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the second substrate (200) may be an epitaxial layer formed on a base substrate.

[0164] The second substrate (200) may include a third surface (200a) and a fourth surface (200b) that are opposite to each other. The third surface (200a) of the second substrate (200) may face the first surface (100a) of the first substrate (100).

[0165] A peripheral circuit element (PC) may be formed on the third surface (200a) of the second substrate (200). The peripheral circuit element (PC) is electrically connected to the sensor array area (SAR) and can transmit and receive electrical signals to and from each unit pixel of the sensor array area (SAR). For example, the peripheral circuit element (PC) may include electronic components constituting the row decoder (2), row driver (3), column decoder (4), timing generator (5), correlation double sampler (6), analog-to-digital converter (7), or input / output buffer (8) of FIG. 1.

[0166] The second wiring structure (240) may be formed on the third surface (200a) of the second substrate (200). For example, the second wiring structure (240) may include a second inter-wiring insulating film (242) and various wiring patterns (244, 234, 236) within the second inter-wiring insulating film (242). In FIG. 9, the number of layers and arrangement of the wiring patterns (244, 234, 236) are merely exemplary and are not limited thereto.

[0167] At least some of the wiring patterns (244, 234, 236) of the second wiring structure (240) may be connected to a peripheral circuit element (PC). In some embodiments, the second wiring structure (240) may include a third wiring pattern (244) in a sensor array area (SAR), a fourth wiring pattern (234) in a connection area (CR), and a fifth wiring pattern (236) in a pad area (PR). In some embodiments, the fourth wiring pattern (234) may be the uppermost wiring among a plurality of wirings in the connection area (CR), and the fifth wiring pattern (236) may be the uppermost wiring among a plurality of wirings in the pad area (PR).

[0168] The first wiring structure (160) and the second wiring structure (240) can be bonded to each other. For example, as shown in FIG. 16, the upper surface of the second wiring structure (240) can be attached to the lower surface of the first wiring structure (160). The first wiring structure (160) and the second wiring structure (240) can be bonded, for example, by a wafer bonding process, but are not limited thereto.

[0169] An image sensor according to some embodiments may include a first connection structure (350), a second connection structure (450), and a third connection structure (550).

[0170] A first connection structure (350) may be formed within a light-shielding area (OB). A first connection structure (350) may be formed on a surface insulating film (170) of the light-shielding area (OB). The first connection structure (350) may come into contact with a portion of a pixel separation pattern (120). For example, a first trench (355t) exposing the pixel separation pattern (120) may be formed within the first substrate (100) and the surface insulating film (170) of the light-shielding area (OB). The first connection structure (350) may be formed within the first trench (355t) to come into contact with the pixel separation pattern (120) within the light-shielding area (OB). In some embodiments, the first connection structure (350) may extend along the profile of the side and bottom surface of the first trench (355t).

[0171] The first connecting structure (350) may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu) and combinations thereof, but is not limited thereto.

[0172] In some embodiments, the first connection structure (350) is electrically connected to the pixel separation pattern (120) to apply a ground voltage or a negative voltage to the pixel separation pattern (120). Accordingly, charges generated by ESD, etc., can be discharged to the first connection structure (350) through the pixel separation pattern (120). Through this, ESD defects can be effectively prevented.

[0173] In some embodiments, a first pad (355) that fills a first trench (355t) may be formed on the first connecting structure (350). The first pad (355) may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, but is not limited thereto.

[0174] In some embodiments, the first protective layer (176) may cover the first connecting structure (350) and the first pad (355). For example, the first protective layer (176) may extend along the profile of the first connecting structure (350) and the first pad (355).

[0175] A second connection structure (450) may be formed within a connection area (CR). The second connection structure (450) may be formed on a surface insulating film (170) of the connection area (CR). The second connection structure (450) may electrically connect the first wiring structure (160) and the second wiring structure (240). For example, a second trench (455t) may be formed within the connection area (CR) to expose a second wiring pattern (163) and a fourth wiring pattern (234). The second connection structure (450) may be formed within the second trench (455t) to connect the second wiring pattern (163) and the fourth wiring pattern (234). In some embodiments, the second connection structure (450) may extend along the profiles of the side and bottom surfaces of the second trench (455t).

[0176] The second connecting structure (450) may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof, but is not limited thereto. In some embodiments, the second connecting structure (450) may be formed at the same level as the first connecting structure (350).

[0177] In some embodiments, the first protective layer (176) may cover the second connecting structure (450). For example, the first protective layer (176) may extend along the profile of the second connecting structure (450).

[0178] In some embodiments, a first filling insulating film (460) that fills the second trench (455t) may be formed on the second connecting structure (450). The first filling insulating film (460) may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof, but is not limited thereto.

[0179] A third connection structure (550) may be formed within the pad area (PR). The third connection structure (550) may be formed on the surface insulating film (170) of the pad area (PR). The third connection structure (550) may electrically connect the second wiring structure (240) and an external device, etc. For example, a third trench (550t) that exposes the fifth wiring pattern (236) may be formed within the pad area (PR). The third connection structure (550) may be formed within the third trench (550t) and contact the fifth wiring pattern (236). Additionally, a fourth trench (555t) may be formed within the first substrate (100) of the pad area (PR). The third connection structure (550) may be formed within the fourth trench (555t) and exposed. In some embodiments, the third connecting structure (550) may extend along the side and bottom profiles of the third trench (550t) and the fourth trench (555t).

[0180] The third connecting structure (550) may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof, but is not limited thereto. In some embodiments, the third connecting structure (550) may be formed at the same level as the first connecting structure (350) and the second connecting structure (450).

[0181] In some embodiments, a second filling insulating film (560) that fills the third trench (550t) may be formed on the third connecting structure (550). The second filling insulating film (560) may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof, but is not limited thereto. In some embodiments, the second filling insulating film (560) may be formed at the same level as the first filling insulating film (460).

[0182] In some embodiments, a second pad (555) filling a fourth trench (555t) may be formed on the third connecting structure (550). The second pad (555) may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof, but is not limited thereto. In some embodiments, the second pad (555) may be formed at the same level as the first pad (355).

[0183] In some embodiments, the first protective layer (176) may cover the third connection structure (550). For example, the first protective layer (176) may extend along the profile of the third connection structure (550). In some embodiments, the first protective layer (176) may expose the second pad (555).

[0184] In some embodiments, an isolation pattern (115) may be formed within the first substrate (100). Although the isolation pattern (115) is illustrated as being formed only around the second connection structure (450) and the third connection structure (550), this is merely exemplary. For example, the isolation pattern (115) may also be formed around the first connection structure (350). The isolation pattern (115) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof, but is not limited thereto.

[0185] In some embodiments, the width of the isolation pattern (115) may decrease as it extends from the second surface (102b) of the first substrate (100) toward the first surface (100a) of the first substrate (100). This may be due to the characteristics of the etching process for forming the isolation pattern (115). For example, the isolation pattern (115) may be a backside deep trench isolation (BDTI) formed by a deep trench isolation (DTI) process on the back side of the first substrate (100). In some embodiments, the isolation pattern (115) may be spaced apart from the first surface (100a) of the first substrate (100).

[0186] In some embodiments, a light-blocking color filter (170C) may be formed on the first connection structure (350) and the second connection structure (450). For example, the light-blocking color filter (170C) may be formed to cover a portion of the first protective film (176) within the light-blocking region (OB) and the connection region (CR). The light-blocking color filter (170C) may block light incident on the first substrate (100).

[0187] In some embodiments, a third protective film (380) may be formed on the light-blocking color filter (170C). For example, the third protective film (380) may be formed to cover a portion of the first protective film (176) within the light-blocking area (OB), the connection area (CR), and the pad area (PR). In some embodiments, the second protective film (185) may extend along the surface of the third protective film (380). The third protective film (380) may, for example, comprise a light-transmitting resin, but is not limited thereto. In some embodiments, the third protective film (380) may be formed at the same level as the microlens (190).

[0188] In some embodiments, the second protective layer (185) and the third protective layer (380) may expose the second pad (555). For example, an exposure opening (ER) that exposes the second pad (555) may be formed within the second protective layer (185) and the third protective layer (380). Accordingly, the second pad (555) may be connected to an external device, etc., and configured to transmit and receive electrical signals between the image sensor and the external device according to some embodiments. That is, the second pad (555) may be an input / output pad of the image sensor according to some embodiments.

[0189] Hereinafter, a method for manufacturing an image sensor according to exemplary embodiments is described with reference to FIGS. 1 to 26.

[0190] FIGS. 17 to 26 are intermediate step drawings for explaining a method of manufacturing an image sensor according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 16 are briefly explained or omitted.

[0191] Referring to FIG. 17, a first substrate (100) including a photoelectric conversion region (101) is provided.

[0192] The first substrate (100) may include a first surface (100a) and a second surface (100b) opposite each other. In some embodiments, the first substrate (100) may have a first conductivity type (e.g., p-type).

[0193] A photoelectric conversion region (101) may be formed within the first substrate (100). The photoelectric conversion region (101) may have a second conductivity type (e.g., n-type) different from the first conductivity type.

[0194] A plurality of active regions (e.g., first to third active regions (AR1 to AR3)) separated by a device isolation pattern (110) may be formed within the first substrate (100). In some embodiments, the device isolation pattern (110) may be formed as a multilayer film. For example, the device isolation pattern (110) may include an insulating liner (112), an etching stop liner (114), and a gap-fill insulating film (116) as described above using FIG. 8.

[0195] Additionally, a first floating diffusion region (FD1) may be formed within the first substrate (100). For example, the first floating diffusion region (FD1) may be a first impurity region (102) formed by ion implanting n-type impurities into the first substrate (100), which is p-type.

[0196] In some embodiments, a ground region (GND) may be formed within the first substrate (100). For example, the ground region (GND) may be a second impurity region (103) formed by ion implanting a high concentration of p-type impurities (p+) within the first substrate (100), which is p-type.

[0197] Referring to FIG. 18, a substrate trench (100t) is formed within the first substrate (100).

[0198] A substrate trench (100t) may extend from a first surface (100a) of a first substrate (100). A substrate trench (100t) may be formed within the first substrate (100) between a photoelectric conversion region (101) and a first floating diffusion region (FD1). In some embodiments, the substrate trench (100t) may overlap with a first active region (AR1) and a device isolation pattern (110).

[0199] In some embodiments, the width of the substrate trench (100t) may decrease as it moves away from the first surface (100a) of the first substrate (100). This may be due to the characteristics of the etching process for forming the substrate trench (100t).

[0200] Referring to FIG. 19, a first surface treatment process (P1) is performed on a substrate trench (100t).

[0201] As the first surface treatment process (P1) is performed, the surface of the first substrate (100) exposed from the substrate trench (100t) can be cured. For example, dangling bonds on the surface of the first substrate (100) formed in the etching process for forming the substrate trench (100t) can be cured by the first surface treatment process (P1).

[0202] In some embodiments, the first surface treatment process (P1) may include an ion implantation (IIP) process. For example, the first surface treatment process (P1) may include a boron ion implantation (B-IIP) process.

[0203] In some embodiments, the first surface treatment process (P1) may include a tilt ion implantation (tilt IIP) process. The angle of inclination of the tilt ion implantation process with respect to the vertical plane may be, for example, about 1° to about 10°, but is not limited thereto. Through the tilt ion implantation process, the curing efficiency for the substrate trench (100t) may be increased.

[0204] In some embodiments, the first surface treatment process (P1) may include a gradient ion implantation process performed multiple times. For example, the first surface treatment process (P1) may include a first gradient ion implantation process and a second gradient ion implantation process performed after the first gradient ion implantation process. By performing the gradient ion implantation process multiple times, the curing efficiency for the substrate trench (100t) may be increased. In some embodiments, the gradient angle of the first gradient ion implantation process and the gradient angle of the second gradient ion implantation process may be different from each other. For example, the gradient angle of the first gradient ion implantation process may be about 5° to about 10°, and the gradient angle of the second gradient ion implantation process may be about 1° to about 5°.

[0205] Referring to FIG. 20, a gate dielectric film (130) is formed within a substrate trench (100t).

[0206] For example, a preliminary dielectric film may be deposited on the first substrate (100) and the device isolation pattern (110). Subsequently, the preliminary dielectric film on the first surface (100a) of the first substrate (100) and the upper surface of the device isolation pattern (110) may be removed. Through this, a gate dielectric film (130) that conformally extends along the profiles of the side and lower surfaces of the substrate trench (100t) may be formed.

[0207] The gate dielectric film (130) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric (low-k) material with a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0208] Referring to FIG. 21, a second surface treatment process (P2) is optionally performed on a gate dielectric film (130) adjacent to a first floating diffusion region (FD1).

[0209] The second surface treatment process (P2) may include an ion implantation (IIP) process. In some embodiments, the second surface treatment process (P2) may include a fluorine ion implantation (F-IIP) process.

[0210] As the second surface treatment process (P2) is performed, the thickness of the gate dielectric film (130) adjacent to the first floating diffusion region (FD1) can be optionally increased. For example, fluoride ions optionally injected into the gate dielectric film (130) adjacent to the first floating diffusion region (FD1) can replace oxygen (O) atoms of the relatively weak silicon-oxygen (Si-O) bond at the boundary between the gate dielectric film (130) and the first substrate (100). At this time, the excess oxygen (O) atoms that are detached can bond with silicon (Si) atoms to increase the thickness of the gate dielectric film (130). Through this, a gate dielectric film (130) including a lower dielectric film (132) and an upper dielectric film (134) can be formed. Additionally, as described above with respect to FIG. 7, a boundary film (100f) including silicon-fluorine (Si-F) bonds can be formed within the first substrate (100).

[0211] In some embodiments, the second surface treatment process (P2) may include a tilt ion implantation (tilt IIP) process. The tilt angle (θ) of the tilt ion implantation process with respect to the vertical plane may, for example, be about 1° to about 10°, and preferably about 3° to about 7°. Through the tilt ion implantation process, fluoride ions may be selectively implanted onto the upper surface of the gate dielectric film (130) adjacent to the first floating diffusion region (FD1). For example, the tilt ion implantation process may be performed in quad mode at an energy of about 9 kEV to about 13 keV, but is not limited thereto. The ion implantation concentration according to the tilt ion implantation process is about 2 E15 at / cm² 3 Up to about 4 E15 at / cm 3It may be, but is not limited to this.

[0212] Referring to FIG. 22, a preliminary electrode film (140L) is formed on the gate dielectric film (130).

[0213] The preliminary electrode film (140L) can be formed to fill the substrate trench (100t). Accordingly, the lower surface of the preliminary electrode film (140L) can be formed lower than the first surface (100a) of the first substrate (100). The preliminary electrode film (140L) may include, for example, impurity-doped polysilicon (poly Si), metal silicides such as cobalt silicide, metal nitrides such as titanium nitride, and at least one of metals such as tungsten, copper, and aluminum, but is not limited thereto.

[0214] Referring to FIGS. 22 and 23, a patterning process is performed on a preliminary electrode film (140L).

[0215] For example, a first gate trench (140t1) and a second gate trench (140t2) may be formed within the upper portion of the pre-electrode film (140L). Through this, a first transmission gate electrode (140A) including a lower gate (142) and an upper gate (144) may be formed.

[0216] In some embodiments, the first transmission gate electrode (140A) may further include a residual gate film (146). The residual gate film (146) may be a residual film remaining from the preliminary electrode film (140L) during the process of forming the first gate trench (140t1).

[0217] In some embodiments, a portion of the second gate trench (140t2) may overlap with a portion of the device isolation pattern (110). In this case, the pre-electrode film (140L) may not remain during the process of forming the second gate trench (140t2).

[0218] Referring to FIG. 24, a gate spacer (150) is formed within the first gate trench (140t1) and the second gate trench (140t2).

[0219] The upper gate (144) may be separated from the upper dielectric film (134) by a gate spacer (150). In some embodiments, the upper gate (144) may be separated from the remaining gate film (146) by a gate spacer (150).

[0220] The upper gate (144) can be separated from the device isolation pattern (110) by a gate spacer (150). In some embodiments, a portion of the gate spacer (150) may overlap with a portion of the device isolation pattern (110).

[0221] The gate spacer (150) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto. For example, the gate spacer (150) may include a silicon nitride film.

[0222] Referring to FIG. 25, a first wiring structure (160) is formed.

[0223] A first wiring structure (160) may be formed on a first surface (100a) of a first substrate (100). The first wiring structure (160) may include a plurality of wiring patterns. For example, the first wiring structure (160) may include a first inter-wiring insulating film (162) and a first wiring pattern (164) within the first inter-wiring insulating film (162).

[0224] Next, referring to FIG. 4, a surface insulating film (170), a grid pattern (172, 174), a color filter (180), and a micro lens (190) are formed sequentially on the second surface (100b) of the first substrate (100). Through this, the image sensor described above can be manufactured using FIG. 3 to FIG. 7.

[0225] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0226] 100: First substrate 100a: First surface 100b: Second side 100t: Substrate trench 101: Photoelectric conversion region 102: First impurity region 103: Second impurity region 130: Gate dielectric 140A: First transmission gate electrode 140t1: First gate trench 140t2: 2nd Gate Trench 142: Lower Gate 144: Upper gate 146: Remaining gate membrane 150: Gate spacer 160: First wiring structure AR1: First active area AR2: Second active area CH1: Channel 1 Area CH2: Channel 2 Area FD1: 1st floating diffusion zone GND: Ground zone SD1: 1st Source / Drain Area UP1: 1st Unit Pixel

Claims

Claim 1 An image sensor comprising: a substrate; a photoelectric conversion region within the substrate; a substrate trench formed within the substrate on the photoelectric conversion region; a floating diffusion region adjacent to the side of the substrate trench within the substrate; a gate dielectric film extending along the side and bottom surface of the substrate trench; and a transmission gate electrode comprising a lower gate having a first width that fills a portion of the substrate trench on the gate dielectric film, and an upper gate having a second width smaller than the first width on the lower gate, wherein the gate dielectric film comprises a lower dielectric film interposed between the substrate and the lower gate and having a first thickness, and an upper dielectric film adjacent to the floating diffusion region and having a second thickness greater than the first thickness, and further comprising a first gate trench defined by the upper surface of the lower gate, the first side of the upper gate, and a device isolation pattern, and a second gate trench defined by the upper surface of the lower gate, the second side of the upper gate, and the upper dielectric film. Claim 2 An image sensor according to claim 1, wherein the photoelectric conversion region and the floating diffusion region contain impurities of the same conductivity type. Claim 3 An image sensor according to claim 1, wherein the upper dielectric film extends from the lower dielectric film to the surface of the substrate. Claim 4 An image sensor according to claim 1, further comprising a boundary film containing fluorine (F) atoms within the substrate adjacent to the upper dielectric film. Claim 5 An image sensor according to claim 1, wherein the transmission gate electrode further comprises a residual gate film extending along the profile of the upper dielectric film and spaced apart from the upper gate on the lower gate. Claim 6 A substrate; a photoelectric conversion region within the substrate; a substrate trench formed within the substrate on the photoelectric conversion region; a floating diffusion region within the substrate adjacent to the side of the substrate trench; a gate dielectric film extending along the side and bottom surface of the substrate trench; and a transmission gate electrode comprising a lower gate filling a portion of the substrate trench on the gate dielectric film, an upper gate spaced apart from the side of the gate dielectric film on the lower gate, and a residual gate film extending along the gate dielectric film on the lower gate. An image sensor comprising a gate spacer interposed between the upper gate and the residual gate film on the lower gate, wherein the gate dielectric film comprises a lower dielectric film interposed between the substrate and the lower gate and having a first thickness, and an upper dielectric film interposed between the floating diffusion region and the residual gate film and having a second thickness greater than the first thickness, and further comprising a first gate trench defined by the upper surface of the lower gate, a first side of the upper gate, and a device isolation pattern, and a second gate trench defined by the upper surface of the lower gate, a second side of the upper gate, and the upper dielectric film, wherein the gate spacer fills at least a portion of the first gate trench. Claim 7 In claim 6, the image sensor wherein the lower gate, the upper gate, and the remaining gate film are integrally formed. Claim 8 In claim 6, the image sensor, wherein the gate spacer fills at least a portion of the second gate trench. Claim 9 A first substrate comprising a first surface and a second surface opposite to each other; a photoelectric conversion region within the first substrate; a transmission gate electrode on the first surface of the first substrate, at least a portion of which is embedded within the first substrate; a gate dielectric film interposed between the first substrate and the transmission gate electrode; a floating diffusion region within the first substrate adjacent to a side of the transmission gate electrode; and a first wiring structure on the first surface of the first substrate, electrically connected to the transmission gate electrode or the floating diffusion region. An image sensor comprising a microlens on the second surface of the first substrate, wherein the transmission gate electrode comprises a lower gate adjacent to the photoelectric conversion region and an upper gate spaced apart from the side of the gate dielectric film on the lower gate, and the gate dielectric film comprises a lower dielectric film interposed between the first substrate and the lower gate and having a first thickness, and an upper dielectric film adjacent to the floating diffusion region and having a second thickness greater than the first thickness, and further comprising a first gate trench defined by the upper surface of the lower gate, the first side of the upper gate, and a device isolation pattern, and a second gate trench defined by the upper surface of the lower gate, the second side of the upper gate, and the upper dielectric film. Claim 10 A method for manufacturing an image sensor, comprising providing a substrate including a photoelectric conversion region, forming a floating diffusion region within the substrate, forming a substrate trench adjacent to the floating diffusion region within the substrate, forming a gate dielectric film extending along the side and bottom surfaces of the substrate trench and including a first region adjacent to the floating diffusion region and a second region which is the remaining region excluding the first region, performing a fluorine ion implantation process on the first region of the gate dielectric film, forming a pre-electrode film that fills the substrate trench on the gate dielectric film, and patterning the pre-electrode film to form a transmission gate electrode, wherein the transmission gate electrode includes a lower gate that fills a portion of the substrate trench, and an upper gate on the lower gate that is spaced apart from the side surface of the gate dielectric film.

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