Semiconductor device including select cutting structure, method for manufacturing the same and electronic system including the same

Abstract

A semiconductor device of the present disclosure comprises: a peripheral circuit structure including a peripheral transistor; a semiconductor layer on the peripheral circuit structure; a source structure on the semiconductor layer; a gate stacking structure disposed on the source structure and comprising a word line, a gate upper line, and a step structure; a memory channel structure and a dummy channel structure penetrating the gate stacking structure; a selective cutting structure penetrating the gate upper line; and a bit line overlapping the memory channel structure. The selective cutting structure comprises a narrow portion and a wide portion disposed closer to the step structure than the narrow portion. The width of the narrow portion is smaller than the width of the wide portion.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing the same, and an electronic system including the same. More specifically, the present disclosure relates to a semiconductor device including a selective cutting structure, a method for manufacturing the same, and an electronic system including the same. Background Technology

[0002] In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing high-capacity data. Accordingly, methods to increase the data storage capacity of semiconductor devices are being studied. For example, as one method to increase the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. The problem to be solved

[0003] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics.

[0004] One of the technical problems that the technical concept of the present invention aims to solve is to provide an electronic system including a semiconductor device with improved electrical characteristics. means of solving the problem

[0005] A semiconductor device according to some embodiments of the present disclosure comprises: a peripheral circuit structure including a peripheral transistor; a semiconductor layer on the peripheral circuit structure; a source structure on the semiconductor layer; a gate stacking structure disposed on the source structure and including a word line, a gate upper line, and a step structure; a memory channel structure and a dummy channel structure penetrating the gate stacking structure; a selective cutting structure penetrating the gate upper line; and a bit line overlapping with the memory channel structure, wherein the selective cutting structure includes a narrow portion and a wide portion disposed closer to the step structure than the narrow portion, and the width of the narrow portion may be smaller than the width of the wide portion.

[0006] A semiconductor device according to some embodiments of the present disclosure may include a gate stacking structure comprising a word line and a gate upper line; memory channel structures and dummy channel structures penetrating the gate stacking structure; and a selective cutting structure penetrating the gate upper line, wherein the selective cutting structure comprises a narrow portion and a wide portion having a width greater than that of the narrow portion, the memory channel structures may include a first memory channel structure in contact with the narrow portion, and the dummy channel structures may include a first dummy channel structure in contact with the wide portion.

[0007] An electronic system according to some embodiments of the present disclosure comprises a main board; a semiconductor device on the main board; and a controller electrically connected to the semiconductor device on the main board, wherein the semiconductor device comprises a gate stacking structure including a word line and a gate upper line; a memory channel structure and a support structure penetrating the gate stacking structure; and a selective cutting structure penetrating the gate upper line, wherein the selective cutting structure comprises a narrow portion adjacent to the memory channel structure and a wide portion adjacent to the support structure, and the width of the narrow portion may be smaller than the width of the wide portion.

[0008] A method for manufacturing a semiconductor device according to some embodiments of the present disclosure comprises: forming a gate stacked structure comprising stacked insulating films and stacked sacrificial films that are alternately stacked; forming a step structure in the gate stacked structure; forming a cover insulating film that covers the step structure; forming a selective cutting trench that penetrates the topmost stacked sacrificial film among the cover insulating film and the stacked sacrificial films; and forming a selective cutting structure that fills the selective cutting trench, wherein the width of the selective cutting trench may increase as it approaches the step structure. Effects of the invention

[0009] A semiconductor device according to the embodiments of the present disclosure may have its electrical characteristics improved by including a selective cutting structure that becomes wider as it extends toward an extended region.

[0010] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0011] FIG. 1 is a schematic diagram showing an electronic system including a semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a schematic perspective view of an electronic system including a semiconductor device according to some embodiments of the present disclosure. FIGS. 3 and FIGS. 4 are cross-sectional views schematically illustrating semiconductor packages according to some embodiments of the present disclosure. FIG. 5a is a plan view of a semiconductor device according to some embodiments of the present disclosure. Figure 5b is a cross-sectional view along the line A1-A1' of Figure 5a. Figure 5c is a cross-sectional view along the line B1-B1' of Figure 5a. FIG. 5d is a cross-sectional view along the line C1-C1' of FIG. 5a. Figure 5e is an enlarged view of area D of Figure 5a. FIGS. 6 and 7a are drawings for illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 7b is a cross-sectional view along the line A2-A2' of Figure 7a. Figure 7c is a cross-sectional view along the line B2-B2' of Figure 7a. FIG. 7d is a cross-sectional view along the line C2-C2' of FIG. 7a. FIG. 8 is a plan view of a semiconductor device according to some embodiments of the present disclosure. FIG. 9 is a plan view of a semiconductor device according to some embodiments of the present disclosure. FIG. 10 is a plan view of a semiconductor device according to some embodiments of the present disclosure. FIG. 11 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Specific details for implementing the invention

[0012] Hereinafter, embodiments of the present invention will be described as follows with reference to the attached drawings.

[0013] FIG. 1 is a schematic diagram showing an electronic system including a semiconductor device according to some embodiments of the present disclosure.

[0014] Referring to FIG. 1, an electronic system (1000) according to some embodiments of the present disclosure may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor devices (1100). For example, the electronic system (1000) may be a solid state drive device (SSD) comprising one or more semiconductor devices (1100), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device.

[0015] The semiconductor device (1100) may be a non-volatile memory device, for example, a NAND flash memory device described later with reference to FIGS. 5a through 5e. The semiconductor device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). In some embodiments, the first structure (1100F) may be placed next to the second structure (1100S). The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure comprising a bit line (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings (CESR) between the bit line (BL) and the common source line (CSL).

[0016] In the second structure (1100S), each memory cell string (CESR) may include lower transistors (LT1, LT2) adjacent to a common source line (CSL), upper transistors (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments.

[0017] In some embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The gate lower lines (LL1, LL2) may each be the gate electrodes of the lower transistors (LT1, LT2). The word lines (WL) may be the gate electrodes of the memory cell transistors (MCT), and the gate upper lines (UL1, UL2) may each be the gate electrodes of the upper transistors (UT1, UT2).

[0018] The common source line (CSL), the first and second gate lower lines (LL1, LL2), the word lines (WL), and the first and second gate upper lines (UL1, UL2) can be electrically connected to the decoder circuit (1110) through first connecting wires (1115) extending from the first structure (1100F) to the second structure (1100S). The bit lines (BL) can be electrically connected to the page buffer (1120) through second connecting wires (1125) extending from the first structure (1100F) to the second structure (1100S).

[0019] In the first structure (1100F), the decoder circuit (1110) and the page buffer (1120) can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit (1110) and the page buffer (1120) can be controlled by the logic circuit (1130). The semiconductor device (1100) can communicate with the controller (1200) through an input / output pad (1101) that is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first structure (1100F) to the second structure (1100S).

[0020] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). According to some embodiments, the electronic system (1000) may include a plurality of semiconductor devices (1100), in which case the controller (1200) may control the plurality of semiconductor devices (1100).

[0021] The processor (1210) can control the operation of the entire electronic system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the semiconductor device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the semiconductor device (1100). Through the NAND interface (1221), control commands for controlling the semiconductor device (1100), data to be written to the memory cell transistors (MCT) of the semiconductor device (1100), data to be read from the memory cell transistors (MCT) of the semiconductor device (1100), etc., may be transmitted. The host interface (1230) may provide communication functions between the electronic system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the semiconductor device (1100) in response to the control command.

[0023] FIG. 2 is a schematic perspective view of an electronic system including a semiconductor device according to some embodiments of the present disclosure.

[0024] Referring to FIG. 2, an electronic system (2000) according to some embodiments of the present disclosure may include a main board (2001), a controller (2002) mounted on the main board (2001), one or more semiconductor packages (2003), and a DRAM (2004). The semiconductor package (2003) and the DRAM (2004) may be connected to the controller (2002) by wiring patterns (2005) formed on the main board (2001).

[0025] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the electronic system (2000) and the external host. In some embodiments, the electronic system (2000) may communicate with the external host according to any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In some embodiments, the electronic system (2000) may operate by power supplied from the external host through the connector (2006). The electronic system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2002) and a semiconductor package (2003).

[0026] The controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the electronic system (2000).

[0027] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the electronic system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (2003). When the electronic system (2000) includes the DRAM (2004), the controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the semiconductor package (2003).

[0028] A semiconductor package (2003) may include first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). Each of the first and second semiconductor packages (2003a, 2003b) may include a package substrate (2100), semiconductor chips (2200) on the package substrate (2100), adhesive layers (2300) disposed on the lower surface of each of the semiconductor chips (2200), a connecting structure (2400) electrically connecting the semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0029] The package substrate (2100) may be a printed circuit board including package upper pads (2130). Each semiconductor chip (2200) may include an input / output pad (2210). The input / output pad (2210) may correspond to the input / output pad (1101) of FIG. 1. Each of the semiconductor chips (2200) may include gate stacking structures (3210) and memory channel structures (3220). Each of the semiconductor chips (2200) may include a semiconductor device described later with reference to FIGS. 5a to 5e.

[0030] In some embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pads (2130). Accordingly, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (2130) of the package substrate (2100). According to embodiments, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0031] In some embodiments, the controller (2002) and the semiconductor chips (2200) may be included in a single package. In some embodiments, the controller (2002) and the semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0033] FIGS. 3 and 4 are cross-sectional views schematically illustrating semiconductor packages according to some embodiments of the present disclosure. FIGS. 3 and 4 each describe an embodiment of the semiconductor package (2003) of FIG. 2 and conceptually show a region of the semiconductor package (2003) of FIG. 2 cut along the cutting line I-I'.

[0034] Referring to FIG. 3, in a semiconductor package (2003), the package substrate (2100) may be a printed circuit board. The package substrate (2100) may include a package substrate body portion (2120), package upper pads (2130) disposed on the upper surface of the package substrate body portion (2120), lower pads (2125) disposed on the lower surface of the package substrate body portion (2120) or exposed through the lower surface, and internal wiring (2135) electrically connecting the upper pads (2130) and the lower pads (2125) inside the package substrate body portion (2120). The upper pads (2130) may be electrically connected to connection structures (2400). The lower pads (2125) may be connected to wiring patterns (2005) of the main board (2001) of the electronic system (2000) as in FIG. 2 through conductive connection portions (2800).

[0035] Each of the semiconductor chips (2200) may include a semiconductor substrate (3010) and a first structure (3100) and a second structure (3200) that are sequentially stacked on the semiconductor substrate (3010). The first structure (3100) may include a peripheral circuit region including peripheral wiring (3110). The second structure (3200) may include a common source line (3205), a gate stacking structure (3210) on the common source line (3205), memory channel structures (3220) and separation structures (3230) penetrating the gate stacking structure (3210), bit lines (3240) electrically connected to the memory channel structures (3220), and gate connection wiring electrically connected to the word lines (WL in FIG. 1) of the gate stacking structure (3210).

[0036] Each of the semiconductor chips (2200) may include a through-wire (3245) that is electrically connected to the peripheral wiring (3110) of the first structure (3100) and extends into the second structure (3200). The through-wire (3245) may penetrate the gate stacking structure (3210) and may be further disposed outside the gate stacking structure (3210). Each of the semiconductor chips (2200) may further include an input / output connection wiring (3265) that is electrically connected to the peripheral wiring (3110) of the first structure (3100) and extends into the second structure (3200), and an input / output pad (2210) that is electrically connected to the input / output connection wiring (3265).

[0038] Referring to FIG. 4, in a semiconductor package (2003A), each of the semiconductor chips (2200a) may include a semiconductor substrate (4010), a first structure (4100) on the semiconductor substrate (4010), and a second structure (4200) bonded to the first structure (4100) by a wafer bonding method on the first structure (4100).

[0039] The first structure (4100) may include a peripheral circuit region comprising peripheral wiring (4110) and first junction structures (4150). The second structure (4200) may include a common source line (4205), a gate stacking structure (4210) between the common source line (4205) and the first structure (4100), memory channel structures (4220) penetrating the gate stacking structure (4210) and a separation structure (4230), and second junction structures (4250) electrically connected to the word lines (WL in FIG. 1) of the memory channel structures (4220) and the gate stacking structure (4210), respectively. For example, the second bonding structures (4250) may be electrically connected to the memory channel structures (4220) and the word lines (WL in FIG. 1) respectively through bit lines (4240) electrically connected to the memory channel structures (4220) and gate connection wiring electrically connected to the word lines (WL in FIG. 1). The first bonding structures (4150) of the first structure (4100) and the second bonding structures (4250) of the second structure (4200) may be bonded while in contact with each other. The bonded portions of the first bonding structures (4150) and the second bonding structures (4250) may be formed of, for example, copper (Cu).

[0040] Each of the semiconductor chips (2200a) may further include an input / output pad (2210) and an input / output connection wiring (4265) below the input / output pad (2210). The input / output connection wiring (4265) may be electrically connected to some of the second junction structures (4250).

[0041] The semiconductor chips (2200) of FIG. 3 and the semiconductor chips (2200a) of FIG. 4 may be electrically connected to each other by connection structures (2400) in the form of bonding wires. However, in some embodiments, semiconductor chips within a single semiconductor package, such as the semiconductor chips (2200) of FIG. 3 and the semiconductor chips (2200a) of FIG. 4, may be electrically connected to each other by a connection structure including a through-hole electrode (TSV).

[0043] FIG. 5a is a plan view of a semiconductor device according to some embodiments of the present disclosure. FIG. 5b is a cross-sectional view along the line A1-A1' of FIG. 5a. FIG. 5c is a cross-sectional view along the line B1-B1' of FIG. 5a. FIG. 5d is a cross-sectional view along the line C1-C1' of FIG. 5a. FIG. 5e is an enlarged view of region D of FIG. 5a.

[0044] Referring to FIGS. 5a, 5b, 5c and 5d, a semiconductor device according to some embodiments of the present disclosure may include a peripheral circuit structure (PCS) and a memory cell structure (CES). A memory cell structure (CES) may be provided on a peripheral circuit structure (PCS).

[0045] A semiconductor device may include a cell region (CR) and an extension region (ER). The cell region (CR) and the extension region (ER) may be regions distinguished in a planar view defined by a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) may intersect each other. For example, the first direction (D1) and the second direction (D2) may be orthogonal to each other.

[0046] The peripheral circuit structure (PCS) may include a substrate (100). The substrate (100) may have the form of a plate extending along a plane defined by a first direction (D1) and a second direction (D2). In some embodiments, the substrate (100) may be a semiconductor substrate. For example, the substrate (100) may be a silicon substrate. In some embodiments, the substrate (100) may be a silicon-on-insulator (SOI) substrate.

[0047] The peripheral circuit structure (PCS) may further include a first insulating film (110) covering the substrate (100). The first insulating film (110) may cover the upper surface of the substrate (100). The first insulating film (110) may include an insulating material. For example, the first insulating film (110) may include an oxide. In some embodiments, the first insulating film (110) may be a multiple insulating film.

[0048] The peripheral circuit structure (PCS) may further include peripheral transistors (PTR). The peripheral transistors (PTR) may be provided between the substrate (100) and the first insulating film (110). The peripheral transistors (PTR) may include source / drain regions (SD), a gate electrode (GE), and a gate insulating film (GI). The gate electrode (GE) and the gate insulating film (GI) may be provided between the source / drain regions (SD). The gate electrode (GE) may be separated from the substrate (100) by the gate insulating film (GI). The source / drain regions (SD) may be formed by doping the substrate (100) with impurities. The gate electrode (GE) may include a conductive material. The gate insulating film (GI) may include an insulating material.

[0049] The peripheral circuit structure (PCS) may further include device isolation layers (STI). The device isolation layers (STI) may be provided within the substrate (100). The device isolation layers (STI) may be positioned between peripheral transistors (PTR) to electrically isolate the peripheral transistors (PTR). The device isolation layers (STI) may include an insulating material.

[0050] The peripheral circuit structure (PCS) may further include peripheral contacts (PCT) and peripheral wiring (PML). The peripheral contacts (PCT) may be connected to a peripheral transistor (PTR), and the peripheral wiring (PML) may be connected to the peripheral contacts (PCT). The peripheral contacts (PCT) and peripheral wiring (PML) may be provided within the first insulating film (110). The peripheral contacts (PCT) and peripheral wiring (PML) may include a conductive material.

[0051] The memory cell structure (CES) may include a semiconductor layer (200), a source structure (SOS), a gate stacking structure (GSS), memory channel structures (MCS), dummy channel structures (DCS), support structures (SUS), and a bitline structure (BLS).

[0052] A semiconductor layer (200) may be disposed on a first insulating film (110) of a peripheral circuit structure (PCS). The semiconductor layer (200) may comprise an extrinsic semiconductor material doped with impurities and / or an intrinsic semiconductor material not doped with impurities. For example, the semiconductor layer (200) may comprise at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof.

[0053] A source structure (SOS) may be provided on a semiconductor layer (200). The source structure (SOS) may include a lower source film (LSL), an upper source film (USL), a first dummy film (DL1), a second dummy film (DL2), and a third dummy film (DL3).

[0054] A lower source film (LSL) may be provided on a semiconductor layer (200). The lower source film (LSL) may be placed in a cell region (CR). The lower source film (LSL) may be a common source line. The lower source film (LSL) may include a conductive material. For example, the lower source film (LSL) may include impurity-doped polysilicon.

[0055] The first dummy film (DL1), the second dummy film (DL2), and the third dummy film (DL3) may be provided sequentially along a third direction (D3) on the semiconductor layer (200). The third direction (D3) may intersect the first direction (D1) and the second direction (D2). For example, the third direction (D3) may be orthogonal to the first direction (D1) and the second direction (D2).

[0056] The first to third dummy films (DL1, DL2, DL3) may be placed in an extended region (ER). The first to third dummy films (DL1, DL2, DL3) may be placed at the same level as the lower source film (LSL). The first to third dummy films (DL1, DL2, DL3) may comprise an insulating material. In some embodiments, the first and third dummy films (DL1, DL3) may comprise the same insulating material, and the second dummy film (DL2) may comprise an insulating material different from that of the first and third dummy films (DL1, DL3). For example, the second dummy film (DL2) may comprise silicon nitride, and the first and third dummy films (DL1, DL3) may comprise silicon oxide.

[0057] The upper source film (USL) may cover the lower source film (LSL) and the first to third dummy films (DL1, DL2, DL3). The upper source film (USL) may extend from the cell region (CR) to the extension region (ER). The upper source film (USL) may include a semiconductor material. For example, the upper source film (USL) may include impurity-doped or impurity-undoped polysilicon.

[0058] In some embodiments, the source structure (SOS) may further include a buried insulating film (BI) on the upper source membrane (USL). The buried insulating film (BI) may be provided between the cell region (CR) and the extension region (ER). The buried insulating film (BI) may be provided between the lower source membrane (LSL) and the first to third dummy membranes (DL1, DL2, DL3). The lower source membrane (LSL) and the first to third dummy membranes (DL1, DL2, DL3) may be spaced apart from each other in a second direction (D2) with the buried insulating film (BI) and a portion of the upper source membrane (USL) surrounding the buried insulating film (BI) in between. The buried insulating film (BI) may extend in a first direction (D1). The buried insulating film (BI) may include an insulating material.

[0059] A gate stack structure (GSS) may be provided on a source structure (SOS). The gate stack structure (GSS) may include insulating patterns (IP) and conductive patterns (CP) that are alternately stacked along a third direction (D3). The insulating patterns (IP) may include an insulating material. For example, the insulating patterns (IP) may include an oxide. The conductive patterns (CP) may include a conductive material.

[0060] The conduction patterns (CP) may include gate lower lines (GLL), word lines (WOL), and gate upper lines (GUL). Some of the conduction patterns (CP) adjacent to the source structure (SOS) may be gate lower lines (GLL). Some of the conduction patterns (CP) adjacent to the bit line structure (BLS) may be gate upper lines (GUL). Some of the conduction patterns (CP) positioned between the gate upper lines (GUL) and the gate lower lines (GLL) may be word lines (WOL). The number of gate lower lines (GLL), gate upper lines (GUL), and word lines (WOL) is not limited to that illustrated.

[0061] In some embodiments, the bottom insulation pattern (IP) can be integrally combined with the buried insulation film (BIL).

[0062] The gate stack structure (GSS) may further include a step structure (STE). The step structure (STE) may be placed in an extension region (ER). The step structure (STE) may be defined by insulating patterns (IP) and conductive patterns (CP) being configured in the form of steps. The surface of the step structure (STE) may include step sidewalls (STE_S) and step top surfaces (STE_T). The step sidewalls (STE_S) may be defined by the sidewalls of the insulating pattern (IP) and the conductive pattern (CP) that are co-planar with each other. The portion of the top surface of the conductive pattern (CP) that is not covered by the insulating pattern (IP) may be defined as the step top surface (STE_T). The step sidewalls (STE_S) and the step top surfaces (STE_T) may be connected to each other. Each step sidewall (STE_S) may have a lower level as it moves away from the cell region (CR). Each stair surface (STE_T) can have a lower level as it moves further away from the cell area (CR).

[0063] The gate stack structure (GSS) may further include a cover insulating film (CIL). The cover insulating film (CIL) may cover the step structure (STE). The cover insulating film (CIL) may cover the step sidewalls (STE_S) and step top surfaces (STE_T) of the step structure (STE). The cover insulating film (CIL) may cover the top surface of the top conductive pattern (CP). The cover insulating film (CIL) may include an insulating material. For example, the cover insulating film (CIL) may include an oxide.

[0064] Memory channel structures (MCS) can be placed in a cell region (CR). Memory channel structures (MCS) can extend in a third direction (D3) to penetrate the cover insulating film (CIL), conductive patterns (CP) and insulating patterns (IP) of the gate stack structure (GSS), and the upper source film (USL) and lower source film (LSL) of the source structure (SOS). Memory channel structures (MCS) can be surrounded by the insulating patterns (IP) and conductive patterns (CP) of the gate stack structure (GSS). The bottom portion of the memory channel structure (MCS) can be placed within the semiconductor layer (200).

[0065] Each memory channel structure (MCS) may include a core insulating layer (CI), a pad (PA), a channel layer (CH), and a memory layer (ML). The core insulating layer (CI) may extend in a third direction (D3) to penetrate the conductive patterns (CP) and insulating patterns (IP) of the gate stacked structure (GSS), and the upper source layer (USL) and lower source layer (LSL) of the source structure (SOS). The core insulating layer (CI) may include an insulating material. For example, the core insulating layer (CI) may include an oxide.

[0066] A pad (PA) can be provided on a core insulating film (CI). The pad (PA) may include a conductive material.

[0067] The channel film (CH) may surround the core insulating film (CI) and the pad (PA). The channel film (CH) may extend in a third direction (D3) to penetrate the conductive patterns (CP) and insulating patterns (IP) of the gate stacking structure (GSS), and the upper source film (USL) and lower source film (LSL) of the source structure (SOS). The channel film (CH) may cover the sidewalls and bottom surface of the core insulating film (CI). The channel film (CH) may be in contact with the lower source film (LSL) of the source structure (SOS). The memory channel structure (MCS) may be electrically connected to the source structure (SOS). The channel film (CH) of the memory channel structure (MCS) may be electrically connected to the lower source film (LSL) of the source structure (SOS). The channel film (CH) may comprise a semiconductor material. For example, the channel film (CH) may comprise polysilicon.

[0068] The memory film (ML) can surround the channel film (CH). The memory film (ML) can extend in a third direction (D3) and penetrate the conductive patterns (CP) and insulating patterns (IP) of the gate stacked structure (GSS). The memory film (ML) can be surrounded by the conductive patterns (CP) and insulating patterns (IP) of the gate stacked structure (GSS).

[0069] The memory film (ML) may include a tunnel insulating film (TU) surrounding a channel film (CH), a charge storage film (DA) surrounding the tunnel insulating film (TU), and a blocking film (BLK) surrounding the charge storage film (DA). Each of the tunnel insulating film (TU), the charge storage film (DA), and the blocking film (BLK) may penetrate the conduction patterns (CP) and insulation patterns (IP) of the gate stacked structure (GSS). The lower source film (LSL) of the source structure (SOS) may be connected to the channel film (CH) by penetrating the tunnel insulating film (TU), the charge storage film (DA), and the blocking film (BLK) of the memory film (ML). The tunnel insulating film (TU) may include a material through which charge can be tunneled. As an example, the tunnel insulating film (TU) may include silicon oxide. The charge storage film (DA) may include a material through which charge can be stored. For example, the charge storage film (DA) may include silicon nitride. The blocking film (BLK) may include a material capable of blocking the movement of charge. For example, the blocking film (BLK) may include silicon oxide.

[0070] Dummy channel structures (DCS) can be placed in the cell region (CR). Dummy channel structures (DCS) can extend in a third direction (D3) to penetrate the cover insulating film (CIL), conduction patterns (CP) and insulating patterns (IP) of the gate stacking structure (GSS), and the upper source film (USL) and lower source film (LSL) of the source structure (SOS). Dummy channel structures (DCS) can be placed closer to the extension region (ER) than to the memory channel structures (MCS). Dummy channel structures (DCS) can be placed closer to the step structure (STE) than to the memory channel structures (MCS). The memory channel structures (MCS) can overlap with the bit line (300) described later, and the dummy channel structures (DCS) may not overlap with the bit line (300) described later.

[0071] Each dummy channel structure (DCS) may include a core insulating layer (CI), a pad (PA), a channel layer (CH), and a memory layer (ML). The core insulating layer (CI), pad (PA), channel layer (CH), and memory layer (ML) of the dummy channel structure (DCS) may be similar to the core insulating layer (CI), pad (PA), channel layer (CH), and memory layer (ML) of the memory channel structure (MCS). The memory layer (ML) of the dummy channel structure (DCS) may include a tunnel insulating layer (TU), a charge storage layer (DA), and a blocking layer (BLK), similar to the memory layer (ML) of the memory channel structure (MCS).

[0072] Support structures (SUS) may be placed in an extended region (ER). Support structures (SUS) may extend in a third direction (D3) and penetrate the cover insulating film (CIL), conductive patterns (CP) and insulating patterns (IP) of the gate stack structure (GSS), and the upper source film (USL) and first to third dummy films (DL1, DL2, DL3) of the source structure (SOS). At least one of the support structures (SUS) may penetrate the upper surface of the steps (STE_T) of the step structure (STE). Support structures (SUS) may be surrounded by the conductive patterns (CP) and insulating patterns (IP) of the gate stack structure (GSS). The bottom portion of the support structures (SUS) may be placed within the semiconductor layer (200). Support structures (SUS) may support the gate stack structure (GSS) in the extended region (ER).

[0073] The memory cell structure (CES) may further include a selective cutting structure (SCS). The selective cutting structure (SCS) may extend from the cell region (CR) to the extension region (ER). The selective cutting structure (SCS) may extend in a second direction (D2). The selective cutting structure (SCS) may penetrate the gate upper lines (GUL). The selective cutting structure (SCS) may penetrate some of the insulation patterns (IP). The bottom of the selective cutting structure (SCS) may be placed at a level higher than the top word line (WOL). The bottom of the selective cutting structure (SCS) may be placed within an insulation pattern (IP) covering the upper surface of the top word line (WOL). The selective cutting structure (SCS) may include an insulating material. For example, the selective cutting structure (SCS) may include an oxide.

[0074] The Selective Cutting Structure (SCS) may include a narrow portion (NA) and a wide portion (WD). The narrow portion (NA) may be a portion adjacent to the memory channel structures (MCS). The wide portion (WD) may be a portion adjacent to the dummy channel structures (DCS) and support structures (SUS). The wide portion (WD) may be positioned closer to the step structure (STE) than the narrow portion (NA). The wide portion (WD) may be positioned closer to the support structure (SUS) than the narrow portion (NA). The narrow portion (NA) may be positioned between the memory channel structures (MCS). The wide portion (WD) may be positioned between the dummy channel structures (DCS) and between the support structures (SUS). The narrow portion (NA) may be positioned in the area where the memory channel structures (MCS) are positioned, and the wide portion (WD) may be positioned in the area where the dummy channel structures (DCS) and support structures (SUS) are positioned. The narrow portion (NA) can be placed in the cell region (CR). The wide portion (WD) can extend from the cell region (CR) to the extended region (ER).

[0075] In some embodiments, the level of the lower surface (WD_B) of the wide portion (WD) may be the same as the level of the lower surface (NA_B) of the narrow portion (NA). That is, the depth of the wide portion (WD) and the depth of the narrow portion (NA) may be the same. In some embodiments, the level of the lower surface (WD_B) of the wide portion (WD) may be lower than the level of the lower surface (NA_B) of the narrow portion (NA). That is, the depth of the wide portion (WD) may be deeper than the depth of the narrow portion (NA).

[0076] The narrow (NA) and wide (WD) sections of the Selective Cutting Structure (SCS) are described in detail below.

[0077] The memory cell structure (CES) may further include isolation structures (DS). The isolation structures (DS) may extend in a second direction (D2). The isolation structures (DS) may penetrate the conductive patterns (CP) and insulating patterns (IP) of the gate stack structure (GSS). Memory channel structures (MCS), dummy channel structures (DCS), support structures (SUS), and selective cutting structures (SCS) may be disposed between the isolation structures (DS). In some embodiments, the isolation structures (DS) may include an insulating material.

[0078] A bitline structure (BLS) may be provided on a gate stack structure (GSS). The bitline structure (BLS) may include a second insulating film (120), bitline contacts (BCT), a third insulating film (130), and bitlines (300).

[0079] The second insulating film (120) can cover the gate stacking structure (GSS), memory channel structures (MCS), dummy channel structures (DCS), support structures (SUS), and selective cutting structure (SCS). The second insulating film (120) may include an insulating material.

[0080] Bitline contacts (BCTs) may be provided within the second insulating film (120). The bitline contacts (BCTs) may penetrate the second insulating film (120) and contact the pads (PA) of the memory channel structures (MCS). Dummy channel structures (DCS) may not contact the bitline contacts (BCTs). The bitline contacts (BCTs) may include a conductive material.

[0081] A third insulating film (130) covering the second insulating film (120) and the bitline contacts (BCT) may be provided. The third insulating film (130) may include an insulating material.

[0082] Bit lines (300) may be provided within the third insulating film (130). The bit lines (300) may extend in a first direction (D1). The bit lines (300) may be spaced apart from each other in a second direction (D2). The bit lines (300) may be electrically connected to a memory channel structure (MCS) through bit line contacts (BCT). The bit lines (300) may include a conductive material.

[0083] Referring to FIG. 5e, the boundary (BO) between the narrow portion (NA) and the wide portion (WD) may be positioned between memory channel structures (MCS) and dummy channel structures (DCS). The boundary (BO) between the narrow portion (NA) and the wide portion (WD) may be positioned between the memory channel structure (MCS) closest to the dummy channel structures (DCS) and the dummy channel structure (DCS) closest to the memory channel structures (MCS). In some embodiments, the boundary (BO) between the narrow portion (NA) and the wide portion (WD) may be positioned between the dummy channel structures (DCS).

[0084] The width of the narrow section (NA) in the first direction (D1) can be defined as the first width (W1). The width of the wide section (WD) in the first direction (D1) can be defined as the second width (W2). The width of the narrow section (NA) may be smaller than the width of the wide section (WD). For example, the first width (W1) may be smaller than the second width (W2). The width of the narrow section (NA) may be constant. For example, the first width (W1) may be constant. The width of the wide section (WD) may increase as it moves away from the narrow section (NA). For example, the second width (W2) may increase as it moves away from the narrow section (NA). The width of the wide section (WD) may increase as it approaches the stair structure (STE). The width of the wide section (WD) may increase as it approaches the support structure (SUS). The width of the wide region (WD) can increase as it moves away from the memory channel structures (MCS). The width of the wide region (WD) can increase as it moves from the cell region (CR) to the extension region (ER).

[0085] The maximum width of the narrow portion (NA) may be smaller than the minimum width of the wide portion (WD). For example, the maximum value of the first width (W1) may be smaller than the minimum value of the second width (W2). In some embodiments, the first width (W1) may be 70 nm to 90 nm, and the minimum value of the second width (W2) may be 110 nm to 130 nm.

[0086] The narrow portion (NA) may include a first side wall (NA_S1) and a second side wall (NA_S2). The first and second side walls (NA_S1, NA_S2) of the narrow portion (NA) may extend in a second direction (D2). The distance between the first and second side walls (NA_S1, NA_S2) of the narrow portion (NA) may be constant. The wide portion (WD) may include a first side wall (WD_S1) and a second side wall (WD_S2). The first and second side walls (WD_S1, WD_S2) of the wide portion (WD) may have an inclination with respect to the second direction (D2). The distance between the first and second side walls (WD_S1, WD_S2) of the wide portion (WD) may increase as it moves further away from the narrow portion (NA).

[0087] The wide section (WD) may include a first connecting surface (COS1) and a second connecting surface (COS2). The first connecting surface (COS1) may connect the first side wall (WD_S1) of the wide section (WD) and the first side wall (NA_S1) of the narrow section (NA). The first connecting surface (COS1) may intersect the first side wall (WD_S1) of the wide section (WD) and the first side wall (NA_S1) of the narrow section (NA). The second connecting surface (COS2) may connect the second side wall (WD_S2) of the wide section (WD) and the second side wall (NA_S2) of the narrow section (NA). The second connecting surface (COS2) may intersect the second side wall (WD_S2) of the wide section (WD) and the second side wall (NA_S2) of the narrow section (NA). The first and second connecting surfaces (COS1, COS2) may intersect in the second direction (D2). The first and second connecting surfaces (COS1, COS2) may be positioned between memory channel structures (MCS) and dummy channel structures (DCS). A boundary (BO) between the narrow portion (NA) and the wide portion (WD) may be defined between the first and second connecting surfaces (COS1, COS2).

[0088] At least one of the memory channel structures (MCS) may be in contact with the narrow portion (NA) of the selection cutting structure (SCS). For example, among the memory channel structures (MCS), a first memory channel structure (MCS1) may be in contact with the narrow portion (NA). A second memory channel structure (MCS2) adjacent to the first memory channel structure (MCS1) in a fourth direction (D4) may be defined. The fourth direction (D4) may intersect the first and second directions (D1, D2). The fourth direction (D4) may be orthogonal to the third direction (D3). A third memory channel structure (MCS3) adjacent to the first memory channel structure (MCS1) in a fifth direction (D5) may be defined. The fifth direction (D5) may intersect the first, second, and fourth directions (D1, D2, D4). The fifth direction (D5) may be orthogonal to the third direction (D3). The second and third memory channel structures (MCS2, MCS3) can be spaced apart from the narrow portion (NA).

[0089] At least one of the dummy channel structures (DCS) may overlap with the first memory channel structure (MCS1) in the second direction (D2). First and second dummy channel structures (DCS1, DCS2) that overlap with the first memory channel structure (MCS1) in the second direction (D2) may be defined. The first memory channel structure (MCS1), the first dummy channel structure (DCS1), and the second dummy channel structure (DCS2) may be arranged on the same line extending in the second direction (D2).

[0090] The first and second dummy channel structures (DCS1, DCS2) may be in contact with the wide section (WD). The first dummy channel structure (DCS1) may be positioned closer to the narrow section (NA) than the second dummy channel structure (DCS2). The first dummy channel structure (DCS1) may penetrate the first side wall (WD_S1) and the second side wall (WD_S2) of the wide section (WD). The second dummy channel structure (DCS2) may be surrounded by the wide section (WD). A third dummy channel structure (DCS3) adjacent to the first dummy channel structure (DCS1) in the fourth direction (D4) may be defined, a fourth dummy channel structure (DCS4) adjacent to the first dummy channel structure (DCS1) in the fifth direction (D5) may be defined, a fifth dummy channel structure (DCS5) adjacent to the second dummy channel structure (DCS2) in the fourth direction (D4) may be defined, and a sixth dummy channel structure (DCS6) adjacent to the second dummy channel structure (DCS2) in the fifth direction (D5) may be defined. The third to sixth dummy channel structures (DCS3, DCS4, DCS5, DCS6) may be in contact with the wide section (WD). The third and fifth dummy channel structures (DCS3, DCS5) may penetrate the first side wall (WD_S1) of the wide section (WD). The fourth and sixth dummy channel structures (DCS4, DSC6) can penetrate the second side wall (WD_S2) of the wide section (WD).

[0091] The structure of the wide portion (WD) and dummy channel structures (DCS) of the selective cutting structure (SCS) is not limited to that shown in FIG. 5e. In some embodiments, the first dummy channel structure (DCS1) may be surrounded by the wide portion (WD). In some embodiments, the third to sixth dummy channel structures (DCS3, DCS4, DCS5, DCS6) may be spaced apart from the wide portion (WD). In some embodiments, the second dummy channel structure (DCS2) may penetrate the first and second side walls (WD_S1, WD_S2) of the wide portion (WD).

[0093] FIGS. 6 and 7a are drawings for illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 7b is a cross-sectional view along the line A2-A2' of FIG. 7a. FIG. 7c is a cross-sectional view along the line B2-B2' of FIG. 7a. FIG. 7d is a cross-sectional view along the line C2-C2' of FIG. 7a.

[0094] Referring to FIG. 6, a peripheral circuit structure (PCS) can be formed. Forming the peripheral circuit structure (PCS) may include forming peripheral transistors (PTR), device isolation layers (STI), peripheral contacts (PCT), peripheral wiring (PML), and a first insulating film (110) on a substrate (100).

[0095] A semiconductor layer (200) can be formed on a peripheral circuit structure (PCS).

[0096] A source structure (SOS) can be formed on a semiconductor layer (200). The source structure (SOS) may include first to third dummy films (DL1, DL2, DL3) of a cell region (CR), first to third dummy films (DL1, DL2, DL3) of an extension region (ER), an upper source film (USL) covering the first to third dummy films (DL1, DL2, DL3), and a buried insulating film (BI) on the upper source film (USL).

[0097] In some embodiments, a process of separating the first to third dummy films (DL1, DL2, DL3) of the cell region (CR) and the first to third dummy films (DL1, DL2, DL3) of the extension region (ER) may be performed before forming the upper source film (USL). In some embodiments, the buried insulating film (BI) may be formed simultaneously with the lowest stacked insulating film (IL) among the stacked insulating films (IL) described below.

[0098] A gate stacked structure (GSS) comprising stacked insulating films (IL) and stacked sacrificial films (SL) can be formed. The gate stacked structure (GSS) can be formed by alternately stacking the stacked insulating films (IL) and the stacked sacrificial films (SL) along a third direction (D3). The stacked sacrificial films (SL) and the stacked insulating films (IL) may comprise materials having an etch selectivity ratio with respect to each other. For example, the stacked sacrificial film (SL) may comprise a nitride, and the stacked insulating film (IL) may comprise an oxide.

[0099] A step structure (STE) can be formed on a gate stack structure (GSS). Forming the step structure (STE) may include etching the stacked sacrificial films (SL) and stacked insulating films (IL) in a step-like manner.

[0100] A cover insulating film (CIL) can be formed. The cover insulating film (CIL) can cover the stair structure (STE). The cover insulating film (CIL) can cover the stair top surfaces (STE_T) and stair side walls (STE_S) of the stair structure (STE). The cover insulating film (CIL) can cover the top surface of the uppermost stacked sacrificial film (SL) among the stacked sacrificial films (SL).

[0101] The level of the upper surface (CIL_T) of the cover insulating film (CIL) may increase as it extends from the cell region (CR) to the extension region (ER). The level of the upper surface (CIL_T) of the cover insulating film (CIL) may increase as it approaches the stepped structure (STE). The thickness of the cover insulating film (CIL) (i.e., the width in the third direction (D3)) may increase as it extends from the cell region (CR) to the extension region (ER).

[0102] Referring to FIGS. 7a, 7b, 7c, and 7d, a selective cutting trench (SCT) can be formed. The selective cutting trench (SCT) can be formed by etching a cover insulating layer (CIL), some of the stacked sacrificial layers (SL), and some of the stacked insulating layers (IL). The selective cutting trench (SCT) can penetrate the cover insulating layer (CIL). The selective cutting trench (SCT) can penetrate the uppermost stacked sacrificial layer (SL) among the stacked sacrificial layers (SL). The width of the selective cutting trench (SCT) can increase as it approaches the step structure (STE). The width of the selective cutting trench (SCT) can increase as it moves from the cell region (CR) to the extension region (ER).

[0103] Selective Cutting Trench (SCT) may include interconnected narrow trenches (NT) and wide trenches (WT). The narrow trench (NT) may be formed in the cell area (CR). The wide trench (WT) may extend from the cell area (CR) to the extension area (ER). The wide trench (WT) may be positioned closer to the stair structure (STE) than the narrow trench (NT).

[0104] The narrow trench (NT) may have a constant width. For example, the width of the narrow trench (NT) in the first direction (D1) may be constant. The width of the wide trench (WT) may increase as it moves away from the narrow trench (NT). For example, the width of the wide trench (WT) in the first direction (D1) may increase as it moves away from the narrow trench (NT). The width of the wide trench (WT) may increase as it approaches the stair structure (STE). The width of the narrow trench (NT) may be smaller than the width of the wide trench (WT). The maximum width of the narrow trench (NT) may be smaller than the minimum width of the wide trench (WT).

[0105] In some embodiments, the level of the lower surface (WT_B) of the wide trench (WT) may be the same as the level of the lower surface (NT_B) of the narrow trench (NT). That is, the depth of the wide trench (WT) and the depth of the narrow trench (NT) may be the same. In some embodiments, the level of the lower surface (WT_B) of the wide trench (WT) may be lower than the level of the lower surface (NT_B) of the narrow trench (NT). That is, the depth of the wide trench (WT) may be deeper than the depth of the narrow trench (NT).

[0106] Referring to FIGS. 5a, 5b, 5c and 5d, a selective cutting structure (SCS) can be formed to fill a selective cutting trench (SCT). In some embodiments, forming the selective cutting structure (SCS) may include filling the selective cutting trench (SCT) with an insulating material and performing a polishing process to polish the upper surface (CIL_T) of the cover insulating film (CIL). A narrow portion (NA) can be formed to fill a narrow trench (NT), and a wide portion (WD) can be formed to fill a wide trench (WT).

[0107] Memory channel structures (MCS), dummy channel structures (DCS), and support structures (SUS) can be formed. Forming memory channel structures (MCS) may include forming memory channel holes penetrating a gate stack structure (GSS) and forming each memory channel structure (MCS) in each memory channel hole. Forming dummy channel structures (DCS) may include forming dummy channel holes penetrating a gate stack structure (GSS) and forming each dummy channel structure (DCS) in each dummy channel hole. Stacked insulating films (IL) penetrating by memory channel holes and dummy channel holes may be defined as insulating patterns (IP) and may be defined as sacrificial patterns of stacked sacrificial films (SL) penetrating by memory channel holes and dummy channel holes. In some embodiments, memory channel holes and dummy channel holes may be formed simultaneously, and memory channel structures (MCS) and dummy channel structures (DCS) may be formed simultaneously.

[0108] Some of the memory channel holes may penetrate the narrow portion (NA) of the selective cutting structure (SCS). Some of the dummy channel holes may penetrate the wide portion (WD) of the selective cutting structure (SCS). Some of the dummy channel holes may be surrounded by the wide portion (WD) of the selective cutting structure (SCS).

[0109] A bitline structure (BLS) can be formed on a gate stacked structure (GSS).

[0110] The sacrifice patterns can be replaced with conduction patterns (CP), and the first to third dummy membranes (DL1, DL2, DL3) of the cell region (CR) can be replaced with a lower source membrane (LSL). After forming the conduction patterns (CP) and the lower source membrane (LSL), a separation structure (DS) can be formed.

[0111] In a semiconductor device according to the embodiments of the present disclosure, the difficulty of the process for forming a memory channel hole can be improved as the narrow portion of the selective cutting structure has a relatively small width. Specifically, the difficulty of the process for forming a memory channel hole penetrating the narrow portion of the selective cutting structure can be improved.

[0112] A semiconductor device according to the embodiments of the present disclosure can form a wide portion to a desired depth even if the thickness of the cover insulating film is relatively large at the location where the wide portion is formed, as the wide portion of the selective cutting structure is formed to have a relatively large width.

[0114] FIG. 8 is a plan view of a semiconductor device according to some embodiments of the present disclosure.

[0115] Referring to FIG. 8, the semiconductor device may include memory channel structures (MCSa) and dummy channel structures (DCSa) disposed in a cell region (CRa), and support structures (SUSa) disposed in an extension region (ERa).

[0116] The semiconductor device may further include a selective cutting structure (SCSa) extending from a cell region (CRa) to an extension region (ERa). The selective cutting structure (SCSa) may include a narrow portion (NAa) and a wide portion (WDa). The boundary between the wide portion (WDa) and the narrow portion (NAa) may be positioned between memory channel structures (MCSa) and dummy channel structures (DCSa). The minimum width of the wide portion (WDa) may be equal to the width of the narrow portion (NAa). For example, the minimum width of the wide portion (WDa) in a first direction (D1) may be equal to the width of the narrow portion (NAa) in a first direction (D1).

[0118] FIG. 9 is a plan view of a semiconductor device according to some embodiments of the present disclosure.

[0119] Referring to FIG. 9, the semiconductor device may include memory channel structures (MCSb) and dummy channel structures (DCSb) disposed in a cell region (CRb), and support structures (SUSb) disposed in an extension region (ERb).

[0120] The semiconductor device may further include a selective cutting structure (SCSb) extending from a cell region (CRb) to an extension region (ERb). The selective cutting structure (SCSb) may include a narrow portion (NAb) and a wide portion (WDb). The boundary between the narrow portion (NAb) and the wide portion (WDb) may be positioned between memory channel structures (MCSb) and dummy channel structures (DCSb). The wide portion (WDb) and the narrow portion (NAb) may have a constant width. For example, the width of the wide portion (WDb) and the narrow portion (NAb) in a first direction (D1) may be constant. The width of the wide portion (WDb) may be greater than the width of the narrow portion (NAb). For example, the width of the wide portion (WDb) in a first direction (D1) may be greater than the width of the narrow portion (NAb) in a first direction (D1).

[0122] FIG. 10 is a plan view of a semiconductor device according to some embodiments of the present disclosure.

[0123] Referring to FIG. 10, the semiconductor device may include memory channel structures (MCSc) and dummy channel structures (DCSc) disposed in a cell region (CRc), and support structures (SUSc) disposed in an extension region (ERc).

[0124] The semiconductor device may further include a selective cutting structure (SCSc) extending from a cell region (CRc) to an extension region (ERc). The selective cutting structure (SCSc) may include a narrow portion (NAc) and a wide portion (WDc). The boundary between the narrow portion (NAc) and the wide portion (WDc) may be positioned between memory channel structures (MCSc) and dummy channel structures (DCSc).

[0125] The semiconductor device may further include first separation structures (DS1) and second separation structures (DS2). The first and second separation structures (DS1, DS2) may extend in a second direction (D2). The first separation structures (DS1) may be spaced apart from each other in a first direction (D1). Memory channel structures (MCSc), dummy channel structures (DCSc), support structures (SUSc), selective cutting structures (SCSc), and second separation structures (DS2) may be disposed between the first separation structures (DS1).

[0126] The second separation structure (DS2) may be placed between the support structures (SUSc). The second separation structure (DS2) may be connected to the wide portion (WDc) of the selective cutting structure (SCSc). The second separation structure (DS2) and the wide portion (WDc) may be connected in an extension area (ERc). The second separation structure (DS2) and the selective cutting structure (SCSc) may be placed on the same line extending in the second direction (D2). The second separation structure (DS2) and the selective cutting structure (SCSc) may overlap in the second direction (D2). The second separation structure (DS2) may be in contact with the portion where the width of the wide portion (WDc) is maximum. The width of the second separation structure (DS2) may be greater than the maximum width of the wide portion (WDc). For example, the width of the second separation structure (DS2) in the first direction (D1) may be greater than the maximum width of the wide portion (WDc) in the first direction (D1).

[0128] FIG. 11 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0129] Referring to FIG. 11, the semiconductor device may include memory channel structures (MCSd) and dummy channel structures (DCSd) placed in a cell region (CRd).

[0130] The semiconductor device may further include a selective cutting structure (SCSd) extending from a cell region (CRd) to an extension region (ERd). The selective cutting structure (SCSd) may include a narrow portion (NAd) and a wide portion (WDd). A boundary (BOd) between the narrow portion (NAd) and the wide portion (WDd) may be positioned between memory channel structures (MCSd) and dummy channel structures (DCSd).

[0131] The width of the narrow portion (NAd) in the third direction (D3) can be defined as the third width (W3). The third width (W3) of the narrow portion (NAd) can be constant. The level of the lower surface (NAd_B) of the narrow portion (NAd) can be constant. The width of the wide portion (WDd) in the third direction (D3) can be defined as the fourth width (W4). The fourth width (W4) of the wide portion (WDd) can increase as it moves away from the narrow portion (NAd). The fourth width (W4) of the wide portion (WDd) can increase as it moves away from the memory channel structures (MCSd). The level of the lower surface (WDd_B) of the wide portion (WDd) can decrease as it moves away from the narrow portion (NAd). The level of the lower surface (WDd_B) of the wide portion (WDd) can decrease as it moves away from the memory channel structures (MCSd). As the width of the wide section (WDd) in the first direction (D1) increases as it moves further away from the narrow section (NAd), the fourth width (W4) of the wide section (WDd) can increase as it moves further away from the narrow section (NAd) during the manufacturing process.

[0132] Among the word lines, the one adjacent to the upper line of the gate may be defined as a dummy word line (DWL). A wide portion (WDd) may penetrate the dummy word line (DWL). A wide portion (WDd) may be in contact with the dummy word line (DWL). Although the wide portion (WDd) is depicted as penetrating one dummy word line (DWL), the present disclosure is not limited thereto, and the wide portion (WDd) may penetrate two or more dummy word lines.

[0133] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0134] PCS: Peripheral circuit structure CES: Memory cell structure MCS: Memory Channel Structure DCS: Dummy Channel Structure SUS: Support structure SCS: Selective Cutting Structure

Claims

Claim 1 A semiconductor device comprising: a peripheral circuit structure including a peripheral transistor; a semiconductor layer on the peripheral circuit structure; a source structure on the semiconductor layer; a gate stacking structure disposed on the source structure and including a word line, a gate upper line, and a step structure; a memory channel structure and a dummy channel structure penetrating the gate stacking structure; a selective cutting structure penetrating the gate upper line but not penetrating the word line; and a bit line overlapping with the memory channel structure, wherein the selective cutting structure includes a narrow portion and a wide portion disposed closer to the step structure than the narrow portion, and the width of the narrow portion is smaller than the width of the wide portion. Claim 2 In claim 1, the boundary between the narrow portion and the wide portion is a semiconductor device disposed between the memory channel structure and the dummy channel structure. Claim 3 A semiconductor device in which, in claim 1, the width of the wide portion increases as it moves away from the memory channel structure. Claim 4 A semiconductor device according to claim 1, wherein the minimum width of the wide portion is greater than the maximum width of the narrow portion. Claim 5 A semiconductor device according to claim 1, wherein the dummy channel structure comprises a plurality of dummy channel structures, and the plurality of dummy channel structures comprise a first dummy channel structure surrounded by the wide portion. Claim 6 In claim 5, the plurality of dummy channel structures include a second dummy channel structure adjacent to the first dummy channel structure, and the second dummy channel structure is a semiconductor device in contact with the wide portion. Claim 7 A semiconductor device according to claim 1, wherein the wide portion includes a connecting surface connecting the side wall of the wide portion and the side wall of the narrow portion. Claim 8 A semiconductor device comprising: a gate stacking structure including a word line and a gate upper line; memory channel structures and dummy channel structures penetrating the gate stacking structure; and a selection cutting structure penetrating the gate upper line, wherein the selection cutting structure includes a narrow portion and a wide portion having a width greater than that of the narrow portion, the memory channel structures include a first memory channel structure in contact with the narrow portion, the dummy channel structures include a first dummy channel structure in contact with the wide portion, and the lower surface of the narrow portion and the lower surface of the wide portion are located at the same level. Claim 9 A semiconductor device according to claim 8, wherein the wide portion comprises a connecting surface connecting the side wall of the narrow portion and the side wall of the wide portion. Claim 10 In claim 9, the connecting surface is a semiconductor device disposed between the memory channel structures and the dummy channel structures.

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