Semiconductor devices

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a substrate having an active region extending in a first direction; a gate structure extending in a second direction intersecting the active region on the substrate and including a gate dielectric layer and a gate electrode; channel layers spaced apart from each other along a third direction perpendicular to the upper surface of the substrate on the active region and arranged to be surrounded by the gate structure; side structures disposed on the inner surfaces of the gate dielectric layer and in contact with the gate dielectric layer and the gate electrode; and source / drain regions disposed on both sides of the gate structure in regions where the active region is recessed and connected to the channel layers, wherein the level of the lower surfaces of the side structures is higher than the level of the lower surface of the gate electrode.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the integration density of semiconductor devices is increasing. In manufacturing semiconductor devices with fine patterns to meet the trend of high integration, it is required to implement patterns with fine widths or fine spacing. In addition, efforts are being made to develop semiconductor devices equipped with a channel of a three-dimensional structure to overcome the limitations of operating characteristics resulting from the size reduction of planar MOSFETs (metal oxide semiconductor FETs). The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and reliability. means of solving the problem

[0007] A semiconductor device according to exemplary embodiments comprises: a substrate having first and second regions and active regions extending in a first direction; a first gate structure having a first gate dielectric layer, a first electrode layer, and a second electrode layer sequentially stacked and extending in a second direction intersecting the active region on the first region; a second gate structure having a second gate dielectric layer, a third electrode layer, and a fourth electrode layer sequentially stacked and extending in the second direction intersecting the active region on the second region; channel layers spaced apart from each other along a third direction perpendicular to the upper surface of the substrate on the active regions and arranged to be surrounded by each of the first and second gate structures; source / drain regions connected to the channel layers, disposed in regions where the active regions are recessed on both sides of the first and second gate structures; first gate spacer layers covering both sides of the first gate structure; second gate spacer layers covering both sides of the second gate structure; and the second On the inner walls of the gate spacer layers, side structures interposed between the second gate dielectric layer and the third electrode layer are included, and the third electrode layer can extend horizontally below the side structures and come into contact with the lower surfaces of the side structures.

[0008] A semiconductor device according to exemplary embodiments comprises: a substrate having an active region extending in a first direction; a gate structure extending in a second direction intersecting the active region on the substrate and including a gate dielectric layer and a gate electrode; channel layers spaced apart from each other along a third direction perpendicular to the upper surface of the substrate on the active region and arranged to be surrounded by the gate structure; side structures disposed on the inner surfaces of the gate dielectric layer and in contact with the gate dielectric layer and the gate electrode; and source / drain regions disposed in regions where the active region is recessed on both sides of the gate structure and connected to the channel layers, wherein the level of the lower surfaces of the side structures may be higher than the level of the lower surface of the gate electrode.

[0009] A semiconductor device according to exemplary embodiments comprises: a substrate having first and second regions, and an active region extending in a first direction in each of the first and second regions; a first gate structure extending in a second direction intersecting the active region on the first region and comprising a first gate dielectric layer and a first electrode layer; a second gate structure extending in the second direction intersecting the active region on the second region and comprising a second gate dielectric layer and a second electrode layer; channel layers spaced apart from each other along a third direction perpendicular to the upper surface of the substrate on each of the active regions and arranged to be surrounded by each of the first and second gate structures; first gate spacer layers covering both sides of the first gate structure; second gate spacer layers covering both sides of the second gate structure; and side structures interposed within the second gate structure and comprising an insulating layer, wherein the first electrode layer has a first length between the first gate spacer layers, and the second between the second gate spacer layers The electrode layer may include a region having a second length smaller than the first length. Effects of the invention

[0011] By using a side protection layer that protects the side of the mask layer, a semiconductor device with improved electrical characteristics and reliability can be provided.

[0012] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0014] FIG. 1 is a layout diagram illustrating a semiconductor device according to exemplary embodiments. FIGS. 2a and FIGS. 2b are schematic cross-sectional views illustrating semiconductor devices according to exemplary embodiments. FIG. 3 is a partial enlarged view illustrating a part of a semiconductor device according to exemplary embodiments. FIGS. 4a and FIGS. 4b are magnified views illustrating semiconductor devices according to exemplary embodiments. FIGS. 5a and 5b are a schematic cross-sectional view and a partial enlarged view illustrating a semiconductor device according to exemplary embodiments. FIGS. 6a and 6b are a schematic cross-sectional view and a partial enlarged view illustrating a semiconductor device according to exemplary embodiments. FIGS. 7a and 7b are a schematic cross-sectional view and a partial enlarged view illustrating a semiconductor device according to exemplary embodiments. FIG. 8 is a schematic cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIGS. 9a and 9b are flowcharts for illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 10a to 22b are drawings illustrated in the order of process to explain a method for manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0015] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0017] FIG. 1 is a layout diagram illustrating a semiconductor device according to exemplary embodiments. For convenience of explanation, only some components of the semiconductor device are shown in FIG. 1.

[0018] FIGS. 2a and 2b are schematic cross-sectional views illustrating semiconductor devices according to exemplary embodiments. FIG. 2a illustrates cross-sections along the cutting lines II' and II-II' of FIG. 1, and FIG. 2b illustrates a cross-section along the cutting line III-III' of FIG. 1.

[0019] FIG. 3 is a partial enlarged view illustrating a portion of a semiconductor device according to exemplary embodiments. FIG. 3 illustrates an enlarged view of region 'A' of FIG. 2a.

[0020] Referring to FIGS. 1 to 3, a semiconductor device (100) may include a substrate (101) having first and second regions (R1, R2) and active regions (105), channel structures (140) having first to third channel layers (141, 142, 143) spaced apart perpendicularly from each other on the active regions (105), first and second gate structures (GS1, GS2) extending intersecting the active regions (105) and each having first and second gate electrodes (170A, 170B), side structures (LS) located within the second gate structure (GS2), source / drain regions (150) in contact with the channel structures (140), and contact plugs (195) connected to the source / drain regions (150). The semiconductor device (100) may further include a device isolation layer (110), internal spacer layers (130), and an interlayer insulating layer (190). The first and second gate structures (GS1, GS2) may further include, in addition to the first and second gate electrodes (170A, 170B), first and second gate dielectric layers (162A, 162B) and first and second gate spacer layers (164A, 164B), respectively.

[0021] In the semiconductor device (100), active regions (105) have a fin shape, and first and second gate electrodes (170A, 170B) may be disposed between the active regions (105) and the channel structures (140), between the first to third channel layers (141, 142, 143) of the channel structures (140), and on the channel structures (140). Accordingly, the semiconductor device (100) is a gate-all-around type field-effect transistor, such as an MBCFET. TMIt may include a transistor with a (Multi-Bridge Channel FET) structure.

[0023] The substrate (101) may have an upper surface extending in the x and y directions. The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may be provided as a bulk wafer, an epitaxial layer, a Silicon On Insulator (SOI) layer, or a Semiconductor On Insulator (SeOI) layer, etc.

[0024] The first and second regions (R1, R2) of the substrate (101) may be regions adjacent to each other along the extension direction of the first and second gate structures (GS1, GS2), for example, the y direction.

[0025] The substrate (101) may include active regions (105) disposed on the upper side. The active regions (105) are defined by a device isolation layer (110) within the substrate (101) and may be disposed to extend in a first direction, e.g., the x-direction. However, depending on the method of description, it may also be possible to describe the active regions (105) as a separate configuration from the substrate (101). The active regions (105) may have a structure protruding upward. The active regions (105) may be formed as part of the substrate (101) or may include an epitaxial layer grown from the substrate (101). However, on both sides of the first and second gate structures (GS1, GS2), the active regions (105) may be partially recessed to form recessed regions, and source / drain regions (150) may be disposed in said recessed regions.

[0026] In exemplary embodiments, the active regions (105) may or may not include a well region containing impurities. For example, in the case of a p-type transistor (pFET), the well region may include n-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb), and in the case of an n-type transistor (nFET), the well region may include p-type impurities such as boron (B), gallium (Ga), or aluminum (Al). If the well region is included, the well region may be located at a predetermined depth from the upper surface of the active region (105). In one embodiment, the active region (105) of the first region (R1) may include the n-type impurities, and the active region (105) of the second region (R2) may include the p-type impurities, but is not limited thereto.

[0028] The device isolation layer (110) may define active regions (105) on the substrate (101). The device isolation layer (110) may be formed, for example, by a shallow trench isolation (STI) process. In some embodiments, the device isolation layer (110) may further include a region that extends deeper and has a step below the substrate (101). The device isolation layer (110) may expose the upper surface of the active regions (105) and may expose a portion of the upper surface. In exemplary embodiments, the device isolation layer (110) may have a curved upper surface having a higher level as it is adjacent to the active regions (105). The device isolation layer (110) may be made of an insulating material. The device isolation layer (110) may be, for example, an oxide, a nitride, or a combination thereof.

[0030] Channel structures (140) may be disposed on the active regions (105) in regions where the active regions (105) intersect with the first and second gate structures (GS1, GS2). Each of the channel structures (140) may include first to third channel layers (141, 142, 143), which are two or more channel layers spaced apart from each other in the z direction. The channel structures (140) may be connected to source / drain regions (150). The channel structures (140) may have a width equal to or smaller than that of the active regions (105) in the y direction and a width equal to or similar to that of the first and second gate structures (GS1, GS2) in the x direction. In some embodiments, the channel structures (140) may have a reduced width such that their sides are located below the first and second gate structures (GS1, GS2) in the x direction.

[0031] The channel structures (140) may be made of a semiconductor material and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The channel structures (140) may be made of, for example, the same material as the substrate (101). In some embodiments, the channel structures (140) may include an impurity region located in a region adjacent to the source / drain regions (150). The number and shape of the channel layers forming a channel structure (140) may vary in the embodiments. For example, in some embodiments, the channel structures (140) may further include a channel layer positioned below the first and second gate electrodes (170A, 170B) at the bottom.

[0033] Source / drain regions (150) may be disposed in recessed regions that partially recess the upper portion of the active regions (105) on both sides of the first and second gate structures (GS1, GS2). Source / drain regions (150) may be disposed to cover the sides of each of the first to third channel layers (141, 142, 143) of the channel structures (140). The upper surfaces of the source / drain regions (150) may be located at the same or similar height as the lower surfaces of the regions disposed at the top of the first and second gate electrodes (170A, 170B), and said height may be varied in the embodiments. According to embodiments, on each of the first and second regions (R1, R2), source / drain regions (150) may be connected to or merged with each other on two or more active regions (105) adjacent along the y direction to form a single source / drain region (150). The source / drain regions (150) may contain impurities. In one embodiment, the source / drain regions (150) on both sides of the first gate electrode (170A) may contain p-type impurities, and the source / drain regions (150) on both sides of the second gate electrodes (170A) may contain n-type impurities, but are not limited thereto.

[0035] The first and second gate structures (GS1, GS2) may be arranged to extend in a second direction, e.g., in the y direction, intersecting the active regions (105) and channel structures (140). The first gate structure (GS1) may be placed in the first region (R1), and the second gate structure (GS2) may be placed in the first region (R2). The first and second gate structures (GS1, GS2) may be arranged in a straight line along the y direction. Channel regions of transistors may be formed in the channel structures (140) intersecting the first and second gate electrodes (170A, 170B) of the first and second gate structures (GS1, GS2).

[0036] The first gate structure (GS1) may include a first gate electrode (170A), first gate dielectric layers (162A) between the first gate electrode (170A) and the channel structure (140), and first gate spacer layers (164A) on the sides of the first gate electrode (170A). The second gate structure (GS2) may include a second gate electrode (170B), second gate dielectric layers (162B) between the second gate electrode (170B) and the channel structure (140), and second gate spacer layers (164B) on the sides of the second gate electrode (170B). In some embodiments, the first and second gate structures (GS1, GS2) may further include a capping layer on the upper surface of each of the first and second gate electrodes (170A, 170B). Alternatively, a portion of the interlayer insulating layer (190) on the first and second gate structures (GS1, GS2) may be referred to as a gate capping layer.

[0038] The first and second gate dielectric layers (162A, 162B) may be disposed between the active regions (105) and the first and second gate electrodes (170A, 170B) and between the channel structures (140) and the first and second gate electrodes (170A, 170B), and may be disposed to cover at least some of the faces of the first and second gate electrodes (170A, 170B). For example, the first and second gate dielectric layers (162A, 162B) may be disposed to surround all faces of the first and second gate electrodes (170A, 170B) except for the top face. The first and second gate dielectric layers (162A, 162B) may extend between the first and second gate electrodes (170A, 170B) and the gate spacer layers (164), but are not limited thereto. On the channel structures (140), the first gate dielectric layer (162A) may be in contact with the first electrode layer (172), and the second gate dielectric layer (162B) may be in contact with the second electrode layer (174) and the side conductive layer (172R). The first and second gate dielectric layers (162A, 162B) may have the same or different thicknesses.

[0039] The first and second gate dielectric layers (162A, 162B) may be made of the same material or may include different materials. The first and second gate dielectric layers (162A, 162B) may include oxides, nitrides, or high-k materials. The high-k material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). The high-k material is, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi2). x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x Oy ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y It may be any one of ), and praseodymium oxide (Pr2O3). In some embodiments, the first and second gate dielectric layers (162A, 162B) may each be made of a multilayer film.

[0041] The first and second gate spacer layers (164A, 164B) may be disposed on each side of the first and second gate electrodes (170A, 170B), respectively. The first and second gate spacer layers (164A, 164B) may insulate the source / drain regions (150) from the first and second gate electrodes (170A, 170B). The first gate spacer layers (164A) and the second gate spacer layers (164B) may be in contact with and connected to each other at the boundary between the first region (R1) and the second region (R2). The first length (L1) between the first gate spacer layers (164A) along the x direction may be substantially the same as the second length (L2) between the second gate spacer layers (164B).

[0042] The first and second gate spacer layers (164A, 164B) can be formed together in the same process step and thus can be made of the same material. In some embodiments, the first and second gate spacer layers (164A, 164B) may each be made of a multilayer structure. The first and second gate spacer layers (164A, 164B) may be made of oxides, nitrides, and oxynitrides, and in particular, may be made of low dielectric constant films.

[0044] The first and second gate electrodes (170A, 170B) may be disposed to extend above the channel structures (140) and fill the space between the channel structures (140) on the active regions (105). The first and second gate electrodes (170A, 170B) may be spaced apart from the channel structures (140) by the first and second gate dielectric layers (162A, 162B), respectively. The first gate electrode (170A) may include first and third electrode layers (172, 176) sequentially stacked from the first gate dielectric layers (162A). The second gate electrode (170B) may include second and third electrode layers (174, 176) sequentially stacked from the second gate dielectric layers (162B). The first and second gate electrodes (170A, 170B) each include different first and second electrode layers (172, 174) and may further include third electrode layers (176) identically. The first and second gate electrodes (170A, 170B) may be separated from each other by a gate separation layer (180) at the boundary between the first region (R1) and the second region (R2).

[0045] In the second gate electrode (170B), the second electrode layer (174) may cover the inner and lower surfaces of the side structures (LS) and may include a region extending horizontally below the side structures (LS). Accordingly, the fourth length (L4) of the second gate electrode (170B) along the x direction may be smaller than the third length (L3) of the first gate electrode (170A). The third length (L3) and the fourth length (L4) may refer to lengths at the same level excluding the extended lower portion of the second electrode layer (174), or may refer to minimum lengths. In some embodiments, the second electrode layer (174) may include an air-gap inside below the side structures (LS).

[0046] The first and second electrode layers (172, 174) may have the same or different thicknesses. In the embodiments, the relative thicknesses of the first to third electrode layers (172, 174, 176) may vary. The first to third electrode layers (172, 174, 176) may comprise a conductive material and may comprise, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. The first to third electrode layers (172, 174, 176) may comprise different materials. The first electrode layer (172) and the second electrode layer (174) may comprise materials with different work functions. For example, the first electrode layer (172) may include TiN, the second electrode layer (174) may include aluminum (Al), for example, TiAlC or TiAlN, and the third electrode layer (176) may include tungsten (W) or molybdenum (Mo).

[0048] Side structures (LS) may be located within the second gate structure (GS2) in the second region (R2). Side structures (LS) may extend in the y-direction along the second gate structure (GS2) and may come into contact with the gate separation layer (180) at one end, as illustrated in FIG. 1. In this embodiment, side structures (LS) may not be placed in the first region (R1).

[0049] Side structures (LS) are located on the inner surfaces of the second gate dielectric layer (162B), particularly on the inner surfaces of the vertical portions, at the top of the channel structure (140), and may be interposed between the second gate dielectric layer (162B) and the second electrode layer (174). The vertical portions may refer to regions extending in the z-direction on the inner surfaces of the second gate spacer layers (164B) as a region of the second gate dielectric layer (162B). The side structures (LS) are each located on the inner surfaces of the vertical portions and may be spaced apart from each other along the x-direction.

[0050] The lower surfaces of the side structures (LS) may be spaced upward from the horizontal portion of the channel structure (140) and the second gate dielectric layer (162B). The horizontal portion may refer to a region of the second gate dielectric layer (162B) that extends in the x and y directions on the upper surface of the third channel layer (143). The lower surfaces of the side structures (LS) may be covered by the second electrode layer (174) and may be in contact with the second electrode layer (174). The outer surfaces of the side structures (LS) may be in contact with the second gate dielectric layer (162B), and the inner surfaces may be in contact with the second electrode layer (174). The level of the lower surfaces of the side structures (LS) may be higher than the level of the lower surface of the second gate spacer layers (164B) and higher than the level of the lower surface of the second electrode layer (174). The length (H1) along the z-direction of the side structures (LS) may be smaller than the length (H2) of the second gate spacer layers (164B).

[0051] As illustrated in FIG. 3, each of the side structures (LS) may include a side conductive layer (172R), an etch protection layer (166), and a side protection layer (168) sequentially stacked on the vertical portion of the second gate dielectric layer (162B). In FIG. 3 and others, the relative thicknesses of the side conductive layer (172R), the etch protection layer (166), the side protection layer (168), and the second electrode layer (174) are exemplary and may vary in the embodiments. The levels of the lower surfaces of the side conductive layer (172R), the etch protection layer (166), and the side protection layer (168) may differ from one another. The level of the lower surface of the side protection layer (168) may be the lowest, the level of the lower surface of the etch protection layer (166) may be higher than that, and the level of the lower surface of the side conductive layer (172R) may be the highest. For example, the lower surface of the side protection layer (168) may be spaced apart by a first dimension (D1) from the upper surface of the horizontal portion of the second gate dielectric layer (162B). The first dimension (D1) may be equal to or similar to the sum of the thickness of the side conductive layer (172R) and the thickness of the etching protection layer (166). However, in the embodiments, the relationship between the levels of the lower surfaces of the side conductive layer (172R), the etching protection layer (166), and the side protection layer (168) is not limited thereto. In some embodiments, the profiles of the lower surfaces of the side conductive layer (172R), the etching protection layer (166), and the side protection layer (168) may be changed into various curved shapes depending on the etching process in which the side structure (LS) is formed.

[0052] The side conductive layer (172R) may be a layer remaining after being formed together with the first electrode layer (172) of the first gate electrode (170A). Accordingly, the side conductive layer (172R) may include the same material as the first electrode layer (172) and may include a conductive material.

[0053] The etch protection layer (166) may be a layer used for patterning the first electrode layer (172) during the manufacturing process of the semiconductor device (100) described below with reference to FIGS. 14a and 14b. The etch protection layer (166) may be a layer containing, for example, titanium (Ti). The etch protection layer (166) may include, for example, TiAlN or TiN, and may include a material different from the first electrode layer (172). The etch protection layer (166) may be a conductive layer, but is not limited thereto, and may be an insulating layer according to the embodiments.

[0054] The side protection layer (168) may be a layer used to reinforce the side of the mask layer during the manufacturing process of the semiconductor device (100) described below with reference to FIGS. 17a and FIGS. 17. The top of the side protection layer (168) may have a shape in which the width decreases toward the outer surface, but is not limited thereto. The side protection layer (168) may be an insulating layer, particularly an inorganic insulating layer, and may be, for example, at least one of titanium oxide (TiO2), aluminum oxide (Al2O3), silicon nitride (SiN), and silicon oxide (SiO2). The side protection layer (168) may include a material different from the second gate dielectric layer (162B) and the second gate spacer layers (164B). The side protection layer (168) may also include a material different from the etch protection layer (166) and the first electrode layer (172).

[0056] The internal spacer layers (130) may be arranged parallel to the first and second gate electrodes (170A, 170B) between the channel structures (140). The first and second gate electrodes (170A, 170B) may be electrically isolated by being stably spaced apart from the source / drain regions (150) by the internal spacer layers (130). The internal spacer layers (130) may have a shape in which the side facing the first and second gate electrodes (170A, 170B) is rounded inwardly convex toward the first and second gate electrodes (170A, 170B), but is not limited thereto. The internal spacer layers (130) may be made of oxides, nitrides, and oxynitrides, and in particular may be made of low dielectric constant films. However, in some embodiments, the internal spacer layers (130) may be omitted.

[0058] A gate separation layer (180) may be positioned to separate the first and second gate electrodes (170A, 170B) and the first and second gate dielectric layers (162A, 162B) between the first and second gate electrodes (170A, 170B). The lower surface of the gate separation layer (180) may be in contact with the device separation layer (110). The sides of the gate separation layer (180) may be perpendicular to the upper surface of the substrate (101) or inclined so that the width narrows toward the bottom. The gate separation layer (180) may be positioned between a pair of first and second gate spacer layers (164A, 164B), as shown in FIG. 1. However, in some embodiments, the gate separation layer (180) may have a shape that extends in the x-direction through the first and second gate spacer layers (164A, 164B).

[0059] The gate isolation layer (180) may include an insulating material. The gate isolation layer (180) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. The gate isolation layer (180) may be composed of a single insulating layer or may be composed of a structure in which a plurality of insulating layers are stacked.

[0061] The interlayer insulating layer (190) covers the source / drain regions (150) and the first and second gate structures (GS1, GS2) and may be positioned to cover the device isolation layer (110). The interlayer insulating layer (190) may include at least one of an oxide, a nitride, and an oxynitride, and may include, for example, a low dielectric constant material. In some embodiments, the interlayer insulating layer (190) may include a plurality of insulating layers.

[0063] Contact plugs (195) can penetrate the interlayer insulation layer (190) and be connected to source / drain regions (150), and can apply an electrical signal to the source / drain regions (150). The contact plugs (195) may have inclined sides such that the width of the lower portion is narrower than the width of the upper portion according to the aspect ratio, but are not limited thereto. The contact plugs (195) may extend from the top, for example, below the lower portion of the third channel layer (143), but are not limited thereto. In exemplary embodiments, the contact plugs (195) may be positioned to make contact along the upper surface of the source / drain regions (150) without recessing the source / drain regions (150).

[0064] The contact plugs (195) may include a metal silicide layer located at the bottom including a lower surface, and may further include a barrier layer disposed on the upper surface and sidewalls of the metal silicide layer. The barrier layer may include a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The contact plugs (195) may include a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo). In exemplary embodiments, the number and arrangement of the conductive layers constituting the contact plugs (195) may vary.

[0066] FIGS. 4a and FIGS. 4b are magnified views illustrating semiconductor devices according to exemplary embodiments.

[0067] Referring to FIG. 4a, in the semiconductor device (100a), the shape of the side structures (LSa) and the second electrode layer (174) may differ from that of the embodiments of FIG. 2a and FIG. 3. In the side structures (LSa) of the present embodiment, the side conductive layer (172R) and the etch protection layer (166) may have a shape that is partially recessed from the upper surfaces. The recessed area of ​​the side conductive layer (172R) and the etch protection layer (166) may be filled with the second electrode layer (174). Accordingly, the upper surfaces of the side conductive layer (172R) and the etch protection layer (166) may come into contact with the second electrode layer (174). In the embodiments, the depth of the recessed side conductive layer (172R) and the etch protection layer (166), the shape of the recessed upper surface, etc., may be varied.

[0068] This shape of the side conductive layer (172R) and the etch protection layer (166) can be formed during the manufacturing process as the side conductive layer (172R) and the etch protection layer (166) are partially removed from the upper surface.

[0070] Referring to FIG. 4b, in the semiconductor device (100b), the shape of the side structures (LSb) and the second electrode layer (174) may differ from that of FIG. 2a and FIG. 3. In the side structures (LSb) of the present embodiment, the etch protection layer (166) may have a shape that is folded to cover the lower surface of the side protection layer (168), and the side conductive layer (172R) may have a shape that is folded to cover the lower surface of the etch protection layer (166). Accordingly, the second electrode layer (174) may be placed only between the inner surfaces of the side structures (LSb) and may not include a region that extends horizontally from the bottom. In some embodiments, the second electrode layer (174) may have a shape that partially recesses the lower part of the side structures (LSb) and partially extends horizontally below the side structures (LSb).

[0071] As in the embodiments of FIG. 3, FIG. 4a and FIG. 4b, the degree to which the side structures (LSa, LSb) are recessed from the top and bottom surfaces can be varied in the embodiments.

[0073] FIGS. 5a and 5b are a schematic cross-sectional view and a partial enlarged view illustrating a semiconductor device according to exemplary embodiments.

[0074] Referring to FIGS. 5a and 5b, in the semiconductor device (100c), the side structures (LSc) may not include a side protection layer (168), unlike in the embodiment of FIGS. 2a and 3. The side structures (LSc) may each include only a side conductive layer (172R) and an etch protection layer (166). The inner surface of the etch protection layer (166) may be in contact with the second electrode layer (174). Even in this case, the lower surfaces of the side conductive layer (172R) and the etch protection layer (166) may be located at a higher level than the lower surface of the second electrode layer (174).

[0075] The structure of such side structures (LSc) can be formed by removing the side protective layer (168) through a separate process.

[0077] FIGS. 6a and 6b are a schematic cross-sectional view and a partial enlarged view illustrating a semiconductor device according to exemplary embodiments.

[0078] Referring to FIGS. 6a and 6b, in the semiconductor device (100d), the side structures (LSd) may not include a side conductive layer (172R) and an etch protection layer (166), unlike in the embodiment of FIGS. 2a and 3. Each side structure (LSd) may include only a side protection layer (168). The outer surface of the side protection layer (168) may be in contact with a second gate dielectric layer (162B).

[0079] The structure of such side structures (LSd) can be formed by removing the side conductive layer (172R) and the etch protection layer (166) from the top of the channel structures (140) through a separate process.

[0081] FIGS. 7a and 7b are a schematic cross-sectional view and a partial enlarged view illustrating a semiconductor device according to exemplary embodiments.

[0082] Referring to FIGS. 7a and 7b, the semiconductor device (100e) may include first side structures (LSe) interposed between first gate structures (GS1) in a first region (R1), and second side structures (LS) interposed between second gate structures (GS2) in a second region (R2). That is, unlike the embodiment of FIGS. 2a and 3, the semiconductor device (100e) may further include first side structures (LSe). In this embodiment, to distinguish them from the first side structures (LSe), the side structures of the second region (R2) are referred to as second side structures (LS). The same description of the side structures (LS) with reference to FIGS. 1 to 3 may apply to the second side structures (LS).

[0083] The first side structures (LSe) may extend in the y direction along the first gate structure (GS1) and may come into contact with the gate separation layer (180) (see FIG. 1) at one end. The first side structures (LSe) may be located on the inner sides of the first electrode layer (172), particularly on the inner sides of the vertical sections, above the channel structure (140), and may be interposed between the first electrode layer (172) and the third electrode layer (176). The vertical sections may refer to regions extending in the z direction on the inner sides of the first gate spacer layers (164A) as a region of the first electrode layer (172). The first side structures (LSe) may be located on each of the vertical sections and may be spaced apart from each other along the x direction.

[0084] The lower surfaces of the first side structures (LSe) may be spaced upward from the horizontal portion of the channel structure (140) and the first gate dielectric layer (162A). The lower surfaces of the first side structures (LSe) may be covered by a third electrode layer (176) and may be in contact with the third electrode layer (176). The outer surfaces of the first side structures (LSe) may be in contact with the first electrode layer (172), and the inner surfaces may be in contact with the third electrode layer (176). The level of the lower surfaces of the first side structures (LSe) may be higher than the level of the lower surface of the first gate spacer layers (164A) and higher than the level of the lower surface of the first electrode layer (172). The length along the z-direction of the first side structures (LSe) may be smaller than the length along the z-direction of the first gate spacer layers (164A).

[0086] As illustrated in FIG. 7b, each of the first side structures (LSe) may include a side conductive layer (174R), an etch protection layer (166), and a side protection layer (168) sequentially stacked on the vertical portion of the first electrode layer (172). The levels of the lower surfaces of the side conductive layer (174R), the etch protection layer (166), and the side protection layer (168) may differ from one another. The level of the lower surface of the side protection layer (168) may be the lowest, the level of the lower surface of the etch protection layer (166) may be higher than that, and the level of the lower surface of the side conductive layer (174R) may be the highest, but is not limited thereto. For example, the lower surface of the side protection layer (168) may be positioned upward from the upper surface of the horizontal portion of the first electrode layer (172) by the sum of the thickness of the side conductive layer (174R) and the thickness of the etch protection layer (166). In some embodiments, the profiles of the side conductive layer (174R), etch protection layer (166), and side protection layer (168) can be changed into various curved shapes.

[0087] The side conductive layer (174R) may be a layer remaining after being formed together with the second electrode layer (174) of the second gate electrode (170B). Accordingly, the side conductive layer (174R) may include the same material as the second electrode layer (174) and may include a conductive material.

[0088] For the etch protection layer (166) and the side protection layer (168), the description with reference to FIGS. 1 through 3 may apply in the same way unless otherwise described. The side protection layer (168) may include a material different from the first gate dielectric layer (162A) and the first gate spacer layers (164A). The side protection layer (168) may also include a material different from the etch protection layer (166) and the second electrode layer (174). In exemplary embodiments, the etch protection layers (166) of the first and second side structures (LSe, LS) may be the same or different materials, and the side protection layers (168) of the first and second side structures (LSe, LS) may be the same or different materials.

[0089] In exemplary embodiments, the semiconductor device may include at least one of the first and second side structures (LSe, LS).

[0091] FIG. 8 is a schematic cross-sectional view illustrating a semiconductor device according to exemplary embodiments.

[0092] Referring to FIG. 8, unlike the embodiments of FIG. 2 and 3, the semiconductor device (100f) may not have an internal spacer layer (130) disposed in the first region (R1). In this case, the source / drain regions (150) may have a shape that extends into the region where the internal spacer layers (130) are omitted. Additionally, the first gate electrode (170A) may be spaced apart from the source / drain regions (150) by the first gate dielectric layers (162A). In another embodiment, the source / drain regions (150) may not extend into the region where the internal spacer layers (130) are omitted, and the first gate electrode (170A) may be disposed extended along the x direction.

[0093] According to such a structure, the internal spacer layer (130) is omitted in the first region (R1), so that the source / drain regions (150) may have improved crystallinity during the growth of the source / drain regions (150). For example, if the source / drain regions (150) of the first region (R1) contain SiGe, the internal spacer layer (130) may be selectively omitted in this way only in the first region (R1) to improve the crystallinity of SiGe. However, in exemplary embodiments, the internal spacer layer (130) may be omitted in at least one of the first region (R1) and the second region (R2).

[0095] FIGS. 9a and 9b are flowcharts for illustrating a method for manufacturing a semiconductor device according to exemplary embodiments.

[0096] FIGS. 10a to 22b are drawings illustrated in the order of process to explain a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 10a to 22b describe an example of a method for manufacturing a semiconductor device of FIGS. 1 to 3.

[0097] Referring to FIGS. 9a, 10a, and 10b, sacrificial layers (120) and first to third channel layers (141, 142, 143) can be alternately stacked on a substrate (101) (S110), and active structures can be formed (S120).

[0098] The sacrificial layers (120) may be layers that are replaced by the first and second gate dielectric layers (162A, 162B) and the first and second gate electrodes (170A, 170B) below the third channel layer (143) through a subsequent process, as shown in FIG. 2a and 2b. The sacrificial layers (120) may be made of a material having etch selectivity with respect to each of the first to third channel layers (141, 142, 143). The first to third channel layers (141, 142, 143) may include a material different from the sacrificial layers (120). The sacrificial layers (120) and the first to third channel layers (141, 142, 143) may comprise a semiconductor material including, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may include different materials and may or may not include impurities. For example, the sacrificial layers (120) may include silicon germanium (SiGe), and the first to third channel layers (141, 142, 143) may include silicon (Si).

[0099] Sacrificial layers (120) and first to third channel layers (141, 142, 143) can be formed by performing an epitaxial growth process from a substrate (101). Each of the sacrificial layers (120) and the first to third channel layers (141, 142, 143) may have a thickness in the range of about 1 Å to about 100 nm. The number of layers of channel layers (141, 142, 143) alternately stacked with the sacrificial layers (120) may vary in the embodiments.

[0100] Next, the active structures may include sacrificial layers (120) and first to third channel layers (141, 142, 143) that are alternately stacked with one another, and may further include active regions (105) formed so as to protrude from the substrate (101) by removing a portion of the substrate (101). The active structures may be formed in a line shape extending in one direction, for example, in the x direction, and may be formed spaced apart from each other in the y direction.

[0101] In the area where a portion of the substrate (101) has been removed, an insulating material is buried, and then a portion of the insulating material is removed so that an active region (105) protrudes, thereby forming a device isolation layer (110). The upper surface of the device isolation layer (110) may be formed lower than the upper surface of the active region (105).

[0103] Referring to FIGS. 9a, FIGS. 11a, and FIGS. 11b, a sacrificial gate structure (200) and first and second gate spacer layers (164A, 164B) can be formed on the active structures (S130).

[0104] The sacrificial gate structure (200) may be a sacrificial structure formed in an area where the first and second gate dielectric layers (162A, 162B) and the first and second gate electrodes (170A, 170B) are disposed on the upper part of the channel structure (140) through a subsequent process as shown in FIG. 2a and 2b. The sacrificial gate structure (200) may include first and second sacrificial gate layers (202, 205) and a mask pattern layer (206) that are sequentially stacked. The first and second sacrificial gate layers (202, 205) may be patterned using the mask pattern layer (206). The first and second sacrificial gate layers (202, 205) may each be an insulating layer and a conductive layer, but are not limited thereto, and the first and second sacrificial gate layers (202, 205) may be formed as a single layer. For example, the first sacrificial gate layer (202) may comprise silicon oxide, and the second sacrificial gate layer (205) may comprise polysilicon. The mask pattern layer (206) may comprise silicon oxide and / or silicon nitride. The sacrificial gate structure (200) may have a line shape extending in one direction intersecting the active structures. The sacrificial gate structure (200) may extend in the y direction, for example, and be spaced apart from an adjacent sacrificial gate structure (200) in the x direction.

[0105] The first and second gate spacer layers (164A, 164B) may be formed on both side walls of the sacrificial gate structure (200). The first and second gate spacer layers (164A, 164B) may be formed together and have a shape connected to each other along the y direction. The first and second gate spacer layers (164A, 164B) may be made of a low dielectric constant material and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0107] Referring to FIG. 9a, FIG. 12a, and FIG. 12b, on the outside of the sacrificial gate structure (200), the exposed sacrificial layers (120) and the first to third channel layers (141, 142, 143) can be partially removed to form recessed regions, internal spacer layers (130) can be formed, and source / drain regions (150) that fill the recessed regions can be formed (S140).

[0108] First, using the sacrificial gate structure (200) and the first and second gate spacer layers (164A, 164B) as a mask, the exposed sacrificial layers (120) and the first to third channel layers (141, 142, 143) can be removed to form recessed regions. By doing so, the first to third channel layers (141, 142, 143) can form a channel structure (140) having a limited length along the x direction.

[0109] Next, the sacrificial layers (120) can be partially removed. The sacrificial layers (120) can be selectively etched with respect to the channel structure (140) by, for example, a wet etching process, and removed to a predetermined depth from the side along the x direction. The sacrificial layers (120) may have inwardly concave sides by such side etching. However, the shape of the side of the sacrificial layers (120) is not limited to that illustrated.

[0110] Next, internal spacer layers (130) can be formed in the region where the sacrificial layers (120) have been partially removed. The internal spacer layers (130) may be formed of the same material as the first and second gate spacer layers (164A, 164B), but are not limited thereto. For example, the internal spacer layers (130) may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN.

[0111] Next, source / drain regions (150) may be formed by growing from the upper surface of the active regions (105) and the sides of the channel structures (140), for example, by a selective epitaxial process. The source / drain regions (150) may contain impurities by in-situ doping and may include multiple layers having different doping elements and / or doping concentrations.

[0113] Referring to FIGS. 9a, FIGS. 13a, and FIGS. 13b, after forming an interlayer insulating layer (190), the sacrificial layers (120) and the sacrificial gate structure (200) can be removed (S150).

[0114] The interlayer insulating layer (190) can be formed by forming an insulating film covering the sacrificial gate structure (200) and source / drain regions (150) and performing a flattening process.

[0115] The sacrificial layers (120) and the sacrificial gate structure (200) can be selectively removed with respect to the first and second gate spacer layers (164A, 164B), the interlayer insulating layer (190), and the channel structures (140). First, the sacrificial gate structure (200) can be removed to form an upper gap region (UR), and then the sacrificial layers (120) exposed through the upper gap region (UR) can be removed to form lower gap regions (LR). For example, if the sacrificial layers (120) contain silicon germanium (SiGe) and the channel structures (140) contain silicon (Si), the sacrificial layers (120) can be selectively removed by performing a wet etching process using peracetic acid as an etchant. During the above removal process, the source / drain regions (150) can be protected by an interlayer insulating layer (190) and internal spacer layers (130).

[0117] Hereinafter, with reference to FIG. 9b and FIG. 14a to FIG. 22b, the step (S160) of forming first and second gate structures (GS1, GS2) is described.

[0118] First, referring to FIG. 9b, FIG. 14a, and FIG. 14b, first and second gate dielectric layers (162A, 162B), a first electrode layer (172), and an etching protection layer (166) can be formed (S161).

[0119] The first and second gate dielectric layers (162A, 162B) may be formed to conformally cover the inner surfaces of the upper gap region (UR) and the lower gap regions (LR). In some embodiments, at this stage, the entire first gate dielectric layer (162A) may be formed in the first region (R1), and a portion of the second gate dielectric layer (162B) may be formed in the second region (R2). In this case, another portion of the second gate dielectric layer (162B) may be further formed before the subsequent formation of the second electrode layer (174).

[0120] The first electrode layer (172) can be formed to fill the lower gap regions (LR) and conformally cover the first and second gate dielectric layers (162A, 162B) in the upper gap region (UR). For example, the first electrode layer (172) can be formed with a uniform thickness using Atomic Layer Deposition (ALD).

[0121] The etch protection layer (166) may be formed to conformally cover the first electrode layer (172) in the upper gap region (UR). The etch protection layer (166) may be a layer to prevent the mask layer (ML) (see FIG. 15a and FIG. 15b) from filling between the channel structures (140) in a subsequent process and to allow it to be easily removed between the channel structures (140). The etch protection layer (166) may include a material that can be easily and selectively removed by a wet etching process during a subsequent process. For example, the etch protection layer (166) may include TiAlN or TiN.

[0123] Referring to FIG. 9b, FIG. 15a, and FIG. 15b, a mask layer (ML) covering the first and second regions (R1, R2) can be formed (S162).

[0124] A mask layer (ML) may be formed on an interlayer insulating layer (190). The mask layer (ML) may be a layer for removing the first electrode layer (172) from the second region (R2) by patterning it in a subsequent process to expose the second region (R2). The mask layer (ML) may be, for example, a bottom anti-reflective coating layer and may include organic materials or inorganic materials such as carbides, but is not limited thereto.

[0126] Referring to FIG. 9b, FIG. 16a, and FIG. 16b, the mask layer (ML) can be partially removed so that the height of the mask layer (ML) in the second region (R2) is lowered (S163).

[0127] First, a second region (R2) can be exposed using a separate patterning layer formed on the mask layer (ML). Next, the exposed mask layer (ML) can be etched first to remove the upper portion of the mask layer (ML) so that the height of the mask layer (ML) is reduced. The mask layer (ML) can be removed until the upper surface of the etch protection layer (166) on the third channel layer (143) is exposed in the cross-section of FIG. 16b, or it can be removed so that a portion remains on the upper surface of the etch protection layer (166). In the second region (R2), the upper surface of the mask layer (ML) can be located at the same or a higher level as the upper surface of the etch protection layer (166). In some embodiments, at this step, the etch protection layer (166) can be used as an etch stop layer.

[0128] In this step, in a cross-section along the x-direction of FIG. 16a, an etch protection layer (166) may be exposed through an upper gap region (UR) between the second gate spacer layers (164B) of the second region (R2). In this step, depending on the level of the upper surface of the mask layer (ML) after partial removal, the level of the lower surface of the side protection layer (168) of the side structure (LS) (see FIG. 2a and FIG. 2b) subsequently formed may be changed. For example, if the level of the upper surface of the mask layer (ML) is relatively high, the level of the lower surface of the side protection layer (168) may also be higher.

[0129] In the case of the embodiments of FIGS. 6a and 6b, at this step, the etching protection layer (166) and the first conductive layer (172) exposed through the upper gap region (UR) in the second region (R2) can be manufactured.

[0131] Referring to FIG. 9b and FIG. 17a to FIG. 18b, a side protective layer (168) can be formed on the side of the mask layer (ML) (S164).

[0132] First, referring to FIGS. 17a and 17b, a side protection layer (168) can be deposited over the entire first and second regions (R1, R2). The side protection layer (168) may be a layer for reinforcing the side of the mask layer (ML) by protecting the side of the mask layer (ML) at the boundary of the first and second regions (R1, R2). The side protection layer (168) may be made of an inorganic material, for example, a TiO2 layer. The side protection layer (168) may also be formed on the etching protection layer (166) in the upper gap region (UR) of the second region (R2).

[0133] Next, referring to FIGS. 18a and 18b, the side protection layer (168) can be partially removed so that the side protection layer (168) remains on the side of the mask layer (ML). For example, the side protection layer (168) can be partially removed on the upper surface of the mask layer (ML) using an etch-back process. By this step, the side protection layer (168) may remain on the side of the mask layer (ML) at the boundary of the first and second regions (R1, R2). Additionally, the side protection layers (168) may also remain on the inner walls of the upper gap region (UR) of the second region (R2) in a cross-section along the x-direction. The side protection layer (168) may have a thickness of, for example, about 1 nm to about 10 nm, but is not limited thereto.

[0135] Referring to FIG. 9b, FIG. 19a, and FIG. 19b, the mask layer (ML) can be completely removed in the second region (R2) (S165).

[0136] The exposed mask layer (ML) can be etched a second time to completely remove the mask layer (ML) in the second region (R2). Since the upper part of the side of the mask layer (ML) is protected and reinforced by the side protection layer (168), a vertical side profile can be maintained from the bottom to the area where the second etching takes place.

[0137] In this way, in the present embodiment, by first etching the upper part of the mask layer (ML), forming a side protection layer (168), and then secondarily etching the remainder, defects such as the tail of the mask layer (ML) remaining in the second region (R2) can be prevented, and defects such as the first electrode layer (172) remaining in the second region (R2) can also be prevented. Accordingly, the electrical characteristics and reliability of the semiconductor device (100) can be improved.

[0139] Referring to FIG. 9b, FIG. 20a, and FIG. 20b, the etching protection layer (166) and the first electrode layer (172) can be removed in the second region (R2) (S166).

[0140] The etch protection layer (166) and the first electrode layer (172) can be removed sequentially. The etch protection layer (166) and the first electrode layer (172) can be removed by a wet etching process and / or a dry etching process.

[0141] In this step, in a cross-section along the x direction, since side protection layers (168) are formed on the inner walls of the upper gap region (UR) of the second region (R2), the etching protection layer (166) and the first electrode layer (172) on the inner walls may be covered by the side protection layers (168) and at least some of them may remain unremoved. For example, in the upper gap region (UR), the horizontal regions of the etching protection layer (166) and the first electrode layer (172) exposed to the top may be removed, and some of them may be removed from the bottom and / or top between the second gate spacer layers (164B) and the side protection layers (168). Alternatively, the etching protection layer (166) and the first electrode layer (172) may not be removed between the second gate spacer layers (164B) and the side protection layers (168). Accordingly, a side structure (LS) including a side conductive layer (172R), an etch protection layer (166), and a side protection layer (168) sequentially stacked from the second gate dielectric layer (162B) can be formed.

[0142] In some embodiments, a process of removing the side protection layer (168) may be added before removing the etch protection layer (166) and the first electrode layer (172). In this case, the side structure (LS) may not be formed on the inner walls of the upper gap region (UR) of the second region (R2). Alternatively, the side structure (LS) may not be formed even if the side protection layer (168) is removed together with the etch protection layer (166).

[0143] In the case of the embodiments of FIG. 5a and FIG. 5b, the etching protection layer (166) and the first electrode layer (172) can be manufactured by adding a process of removing the side protection layer (168).

[0145] Referring to FIG. 9b, FIG. 21a, and FIG. 21b, after removing the mask layer (ML) from the first region (R1) (S167) and removing the etching protection layer (166), a second electrode layer (174) can be formed in the first and second regions (R1, R2) (S168).

[0146] First, the mask layer (ML) can be removed from the first region (R1), and the exposed etch protection layer (166) can be removed. When removing the mask layer (ML), the side protection layer (168) on the side of the mask layer (ML) can also be removed together. Next, a second electrode layer (174) can be formed over the entire region. By doing so, a second electrode layer (174) can be formed on the second gate dielectric layers (162B) in the second region (R2). In a cross-section along the x direction, the second electrode layer (174) can be formed in the upper gap region (UR) of the second region (R2) to cover the inner and lower sides of the side structure (LS).

[0148] Referring to FIG. 9a, FIG. 22a, and FIG. 22b, a third electrode layer (176) can be formed in the first and second regions (R1, R2) to form first and second gate electrodes (170A, 170B) and first and second gate structures (GS1, GS2) including the same (S160).

[0149] First, a process of removing the second electrode layer (174) from the first region (R1) may be performed. The specific method of the process of removing the second electrode layer (174) is not limited. For example, in the case of the embodiment of FIGS. 7a and 7b, the second electrode layer (174) may be removed by forming a mask layer (ML) and a side protective layer (168) in the same manner as described above with reference to FIGS. 15a to 20b. That is, the process of removing the second electrode layer (174) from the first region (R1) may be performed similarly to the process of removing the first conductive layer (172) from the second region (R2). In this case, a side structure (LSe) may also be formed in the first region (R1).

[0150] Next, a third electrode layer (176) can be formed in the first and second regions (R1, R2). In the first region (R1), the third electrode layer (176) is formed on the first electrode layer (172) in the upper gap region (UR) and can be formed to completely fill the upper gap region (UR). In the second region (R2), the third electrode layer (176) is formed on the second electrode layer (174) in the upper gap region (UR) and can be formed to completely fill the upper gap region (UR). Next, a planarization process can be performed. By doing so, first and second gate electrodes (170A, 170B) and first and second gate structures (GS1, GS2) including the same can be formed.

[0151] In some embodiments, the third electrode layer (176) may include a plurality of conductive layers. Depending on the thickness of the upper portion of the first and second gate electrodes (170A, 170B) removed during the planarization process, the upper shape of the side structure (LS) may be changed. For example, if the thickness of the first and second gate electrodes (170A, 170B) and the side structure (LS) removed during the planarization process is relatively large, the side protection layer (168) of the side structure (LS) may have a flat upper surface.

[0152] Subsequently, a gate separation layer (180) can be formed. The gate separation layer (180) can be formed by creating an opening at the boundary between the first region (R1) and the second region (R2) to penetrate the first and second gate electrodes (170A, 170B) and the first and second gate dielectric layers (162A, 162B) from the top, and then filling the opening with an insulating material.

[0154] Next, referring to FIG. 2a and FIG. 2b together, contact plugs (195) can be formed (S170).

[0155] First, an interlayer insulating layer (190) can be further formed on the first and second gate structures (GS1, GS2). Next, the interlayer insulating layer (190) can be patterned to form contact holes that expose source / drain regions (150). Contact plugs (195) can be formed by filling the contact holes with a conductive material. Specifically, after depositing a barrier layer material within the contact holes, a silicide process can be performed to form a metal-semiconductor compound layer, such as a silicide layer, at the bottom. Next, a conductive material can be deposited to fill the contact holes to form contact plugs (195). By doing so, the semiconductor device (100) of FIGS. 1 to 3 can be manufactured.

[0157] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0159] 101: Substrate 105: Active region 110: Device isolation layer 120: Sacrificial layer 130: Internal spacer layer 140: Channel structure 150: Source / Drain region 162A, 162B: Gate dielectric layer 164A, 164B: Gate spacer layer 166: Etching protection layer 168: Side protection layer 170A, 170B: Gate electrode 172: First electrode layer 172R: Remaining electrode layer 174: Second electrode layer 176: Third electrode layer 180: Gate separation layer 190: Interlayer insulation layer 195: Contact Plug GS1, GS2: Gate Structure LS: Side structure

Claims

Claim 1 A substrate having first and second regions and active regions extending in a first direction; a first gate structure having a first gate dielectric layer, a first electrode layer, and a third electrode layer sequentially stacked, extending in a second direction intersecting the active region on the first region; a second gate structure having a second gate dielectric layer, a second electrode layer, and the third electrode layer sequentially stacked, extending in the second direction intersecting the active region on the second region; channel layers spaced apart from each other along a third direction perpendicular to the upper surface of the substrate on the active regions and arranged to be surrounded by each of the first and second gate structures; source / drain regions disposed in regions where the active regions are recessed on both sides of the first and second gate structures and connected to the channel layers; first gate spacer layers covering both sides of the first gate structure; and second gate spacer layers covering both sides of the second gate structure. A semiconductor device comprising side structures interposed between the second gate dielectric layer and the second electrode layer on the inner walls of the second gate spacer layers, wherein the second electrode layer extends horizontally below the side structures and contacts the lower surfaces of the side structures, and the side structures are spaced apart from each other in the first direction with the second electrode layer and the third electrode layer in between. Claim 2 A semiconductor device according to claim 1, wherein the lower surfaces of the side structures are located at a higher level than the lower surfaces of the second gate spacer layers. Claim 3 In claim 1, each of the above-mentioned side structures comprises a side protective layer made of an insulating material. Claim 4 In claim 3, the side protective layer comprises a semiconductor device including titanium. Claim 5 A substrate having first and second regions and active regions extending in a first direction; a first gate structure having a first gate dielectric layer, a first electrode layer, and a third electrode layer sequentially stacked, extending in a second direction intersecting the active region on the first region; a second gate structure having a second gate dielectric layer, a second electrode layer, and the third electrode layer sequentially stacked, extending in the second direction intersecting the active region on the second region; channel layers spaced apart from each other along a third direction perpendicular to the upper surface of the substrate on the active regions and arranged to be surrounded by each of the first and second gate structures; source / drain regions disposed in regions where the active regions are recessed on both sides of the first and second gate structures and connected to the channel layers; first gate spacer layers covering both sides of the first gate structure; and second gate spacer layers covering both sides of the second gate structure. A semiconductor device comprising side structures interposed between the second gate dielectric layer and the second electrode layer on the inner walls of the second gate spacer layers, wherein the second electrode layer extends horizontally below the side structures and contacts the lower surfaces of the side structures, and each of the side structures comprises a side conductive layer, an etching protection layer, and a side protection layer sequentially disposed from the inner surface of the second gate dielectric layer, and at least one of the etching protection layer and the side protection layer is an insulating layer. Claim 6 In claim 5, the semiconductor device wherein the lateral conductive layer comprises the same material as the first electrode layer. Claim 7 A semiconductor device comprising: a substrate including an active region extending in a first direction; a gate structure extending in a second direction intersecting the active region on the substrate and including a gate dielectric layer and a gate electrode; channel layers spaced apart from each other along a third direction perpendicular to the upper surface of the substrate on the active region and arranged to be surrounded by the gate structure; side structures disposed on the inner surfaces of the gate dielectric layer and in contact with the gate dielectric layer and the gate electrode; and source / drain regions disposed in recessed regions of the active region on both sides of the gate structure and connected to the channel layers, wherein the level of the lower surfaces of the side structures is higher than the level of the lower surface of the gate electrode, and the side structures are spaced apart from each other in the first direction with the gate electrode in between. Claim 8 In claim 7, the side structures are semiconductor devices disposed on the uppermost channel layer among the channel layers. Claim 9 A semiconductor device according to claim 7, further comprising gate spacer layers covering both sides of the gate structure, wherein the side structures have a first length along the third direction and the gate spacer layers have a second length along the third direction that is longer than the first length. Claim 10 A substrate having first and second regions, and an active region extending in a first direction in each of the first and second regions; a first gate structure extending in a second direction intersecting the active region on the first region and including a first gate dielectric layer and an electrode layer; a second gate structure extending in the second direction intersecting the active region on the second region and including a second gate dielectric layer and the electrode layer; channel layers spaced apart from each other along a third direction perpendicular to the upper surface of the substrate on each of the active regions and arranged to be surrounded by each of the first and second gate structures; first gate spacer layers covering both sides of the first gate structure; and second gate spacer layers covering both sides of the second gate structure. A semiconductor device comprising side structures interposed within the second gate structure and including an insulating layer, wherein the electrode layer between the first gate spacer layers has a first length and the electrode layer between the second gate spacer layers has a second length smaller than the first length, and the side structures are spaced apart from each other in the first direction with the electrode layer in between.

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